JNTUK R16 ECE

L T P C
III Year - II Semester
4 0 0 3
MICROPROCESSORS AND MICROCONTROLLERS

UNIT-I:
8086 ARCHITECTURE: Main features, pin diagram/description, 8086 microprocessor family, 8086 internal
architecture, bus interfacing unit, execution unit, interrupts and interrupt responses, 8086 system timing, minimum
mode and maximum mode configuration.

UNIT-II:
8086 PROGRAMMING: Program development steps, instructions, addressing modes, assembler directives,
writing simple programs with an assembler, assembly language program development tools.

UNIT-III:
8086 INTERFACING : Semiconductor memories interfacing (RAM,ROM), 8254 software programmable
timer/counter, Intel 8259 programmable interrupt controller, software and hardware interrupt applications, Intel
8237a DMA controller, Intel 8255 programmable peripheral interface, keyboard interfacing, alphanumeric displays
(LED,7-segment display, multiplexed 7-segment display, LCD), Intel 8279 programmable keyboard/display
controller, stepper motor, A/D and D/A converters.

UNIT-IV:
80386 AND 80486 MICROPROCESSORS: Introduction, programming concepts, special purpose registers,
memory organization, moving to protected mode, virtual mode, memory paging mechanism, architectural
differences between 80386 and 80486 microprocessors.

UNIT-V:
Intel 8051 MICROCONTROLLER: Architecture, hardware concepts, input/output ports and circuits, external
memory, counters/timers, serial data input/output, interrupts.
Assembly language programming: Instructions, addressing modes, simple programs.
Interfacing: keyboard, displays (LED, 7-segment display unit), A/D and D/A converters.
.
UNIT-VI:
PIC MICROCONTROLLER: Introduction, characteristics of PIC microcontroller, PIC microcontroller families,
memory organization, parallel and serial input and output, timers, Interrupts, PIC 16F877 architecture, instruction
set of the PIC 16F877.

Text Books:
1. Microprocessors and Interfacing – Programming and Hard ware by Douglas V Hall, SSSP Rao, Tata McGraw
Hill Education Private Limited, 3rd Edition.
2. The 8051 Microcontroller & Embedded Systems Using Assembly and C by Kenneth J.Ayala, Dhananjay
V.Gadre,Cengage Learninbg , India Edition.

References:
1. The Intel Microprocessors-Architecture, Programming, and Interfacing by Barry B.Brey,
Pearson, Eighth Edition-2012.
2. Microprocessors and Microcontrollers-Architecture, Programming and System Design by Krishna Kant, PHI
Learning Private Limited, Second Edition, 2014.
3. Microprocessors and Microcontrollers by N.Senthil Kumar, M.Saravanan and S.Jeevananthan, Oxford
University Press, Seventh Impression 2013

RCE III-ii 1
 JNTUK R16 ECE

Code No: R1632041 R16 SET - 1

III B. Tech II Semester Supplementary Examinations, November - 2019

MICROPROCESSORS AND MICROCONTROLLERS
(Common to Electronics and Communication Engineering, Electronics and Instrumentation
Engineering, Electronics and Computer Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A (14 Marks)

1. a) What is a microprocessor? State its importance. [2M]
b) List the steps in developing an assembly language program. [2M]
c) Define semiconductor memory. [2M]
d) List out the registers of 80386. [3M]
e) What is the significance of EA pin? [3M]
f) Draw the pin diagram of PIC16F877. [2M]

PART –B (56 Marks)

2. a) What is an interrupt? Explain the classification of interrupts of 8086. [7M]
b) Draw and discuss the maximum mode of 8086 system with relevant read and write [7M]
cycle timing diagram.

3. a) Explain the different logical instructions of 8086 microprocessor. [7M]

b) Write a short note on assembler directives. [7M]

4. a) Explain the important features of 8259 interrupts controller. [7M]

b) Explain the interface of LCD with 8086. [7M]

5. a) Draw and explain the register set of 80386. [7M]

b) Compare the features of 80386 and 80486 processors. [7M]

6. a) Draw and explain the capacities of internal and external program memory and [7M]
internal data memory.
b) Write the process of assembling and running an 8051 program. [7M]

7. a) Explain about the memory organization of PIC microcontroller. [7M]

b) Explain about the interrupts in PIC 16F877. [7M]

*****

RCE III-ii 2
 JNTUK R16 ECE

Code No: R1632041 R16 SET - 1

III B. Tech II Semester Regular Examinations, April/May - 2019

MICROPROCESSORS AND MICROCONTROLLERS
(Common to Electronics and Communication Engineering, Electronics and Instrumentation
Engineering, Electronics and Computer Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) Differentiate between minimum and maximum mode operations of 8086 [2M]
microprocessor.
b) What is immediate addressing mode of 8086? Explain with an example instruction. [2M]
c) List the applications of A/D and D/A converters. [2M]
d) List the salient features of 80386DX microprocessor. [3M]
e) Differentiate between microprocessors and microcontrollers. [3M]
f) What is a Timer? What is its use? [2M]

PART -B
2. a) What are registers? List and discuss the functions of the registers of 8086 [9M]
microprocessor.
b) What is an interrupt? List and explain different interrupts supported by 8086 [5M]
microprocessor.

3. a) Write and discuss different machine language instruction formats supported by 8086 [9M]
microprocessor.
b) Write an assembly language program in 8086 to find the factorial of a given number. [5M]

4. a) Explain the BSR mode of operation of 8255 programmable peripheral interface. [6M]
b) Write an assembly language program in 8086 to generate a symmetrical square wave [8M]
with 1KHz frequency? Give the necessary circuit set up with a DAC.

5. a) Explain the use of segment descriptor register and control registers of 80386. [7M]
b) List and discuss different data types supported by 80386 microprocessor. [7M]

6. a) Discuss the internal memory organization of 8051 microcontroller. [7M]

b) List and explain various addressing modes of 8051 microcontroller. [7M]

7. a) How microcontrollers can be used for automation and control applications? Explain. [6M]
b) Discuss the additional features and applications of PIC 16F877 Microcontrollers. [8M]

*****

RCE III-ii 3
 JNTUK R16 ECE

Code No: R1632041 R16 SET - 2

III B. Tech II Semester Regular Examinations, April/May - 2019

MICROPROCESSORS AND MICROCONTROLLERS
(Common to Electronics and Communication Engineering, Electronics and Instrumentation
Engineering, Electronics and Computer Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) What is the use of memory segmentation in 8086 microprocessor? [2M]
b) What is the use of LOCK prefix in 8086 programming? [2M]
c) Differentiate between static memory and dynamic memory. [2M]
d) What is Paging? Explain its use. [3M]
e) What is a seven segment display? Briefly explain its implementation. [3M]
f) What are the advantages of PIC microcontrollers? [2M]
PART -B
2. a) List the main features of 8086 microprocessor. Draw and explain the internal [10M]
architecture of 8086 microprocessor.
b) Draw the flag register of 8086 and discuss the use of each flag. [4M]

3. a) What are addressing modes? List different addressing modes supported by 8086 [10M]
and explain with suitable examples.
b) What is the purpose of AAA, AAD and DAA instructions of 8086? Explain with [4M]
examples.

4. a) Interface an 8255 with 8086 to work as a peripheral interface. Initialize its port A [12M]
as output port, port B as input port and port C as output port. Port A address should
be 0740H.Writ a program to sense switch positions SW0 –SW7 connected at port
B. The sensed pattern is to be displayed in port A, to which 8 LEDs are connected,
which the port C lower displays number of ‘ON’ switches out of the total eight
switches.
b) What is DMA? What are its advantages? [2M]

5. a) Draw and discuss the register set of 80386 and explain the functions of registers in [11M]
brief.
b) Enlist the additional features of 80486 over 80386 microprocessor. [3M]

6. a) What are Timers? Explain the timers of 8051 microcontroller. Also explain the use [8M]
of TMOD register.
b) What are interrupts? What are various interrupts supported by 8051 [6M]
microcontroller? Specify the priority of these interrupts.

7. a) What is the use of File Selection Register (FSR) in PIC microcontrollers? [7M]
b) Discuss the salient features of PIC microcontrollers. [7M]
*****

RCE III-ii 4
 JNTUK R16 ECE

Code No: R1632041 R16 SET - 3

III B. Tech II Semester Regular Examinations, April/May - 2019

MICROPROCESSORS AND MICROCONTROLLERS
(Common to Electronics and Communication Engineering, Electronics and Instrumentation
Engineering, Electronics and Computer Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) List and explain the machine control flags of 8086 microprocessor. [2M]
b) Explain PUSH and POP inductions with examples. [2M]
c) What is the use of BSR mode of operation of 8255? [2M]
d) What Cache memory? What is its use? [3M]
e) Differentiate between serial communication and parallel communication. [3M]
f) List the applications of PIC microcontrollers. [2M]
PART -B
2. a) What is memory segmentation? What is its use? Explain the memory segmentation [9M]
in 8086 microprocessor.
b) What is the use of operating 8086 in maximum mode? Explain. [5M]

3. a) List different arithmetic instruction of 8086 microprocessor and explain with [7M]
examples.
b) Write a program in 8086 to convert a 16-bit binary number into equivalent BCD [7M]
number.

4. a) Discuss the applications of A-to-D and D-to-A converters. [4M]

b) Draw the schematic diagram of stepper motor interfacing to 8086. Write an [10M]
assembly language program to rotate shaft of a 4-phase, 200 teeth stepper motor
i) 10 rotations in clockwise ii)5 rotations in anticlockwise
iii) Exactly by an angle of 27o in clockwise

5. a) Explain the physical address formation in real address mode of 80386 [8M]
microprocessor.
b) What is meant by paging? What are its advantages and disadvantages? [6M]

6. a) What are various addressing modes supported by 8051? Discuss with example [9M]
instructions.
b) Explain the I/O ports of 8051 microcontroller. [5M]

7. a) Discuss the characteristics of PIC microcontrollers. [7M]

b) Discuss the memory organization of PIC 16F877 microcontroller. [7M]

*****

RCE III-ii 5
 JNTUK R16 ECE

Code No: R1632041 R16 SET - 4

III B. Tech II Semester Regular Examinations, April/May - 2019
MICROPROCESSORS AND MICROCONTROLLERS
(Common to Electronics and Communication Engineering, Electronics and Instrumentation
Engineering, Electronics and Computer Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) Explain the functions of ALE, READY, HOLD, and BHE pins of 8086 [2M]
microprocessor.
b) Discuss the use of EQU, OFFSET, ENDP and LENGTH assembler directives. [2M]
c) Differentiate between LEDs and LCDs. [2M]
d) What is virtual memory? [3M]
e) What are the additional features of microcontrollers over microprocessors? [3M]
f) What is serial data communication? How is it different from parallel communication? [2M]
PART -B
2. a) What is an interrupt? What are different types of interrupt supported by 8086 [4M]
microprocessor?
b) With a neat schematic diagram, discuss the working of 8086 microprocessor in its [10M]
maximum mode. Draw and discuss the timing diagrams for memory read and write
operation.

3. a) Write an assembly language program to find out the number of positive numbers and [7M]
negative numbers from a given list of 16-bit signed numbers.
b) What are assembler directives? Explain any seven assembler directive supported by [7M]
8086.

4. a) What are the main features of 8255? Draw and explain the control word register [5M]
formats of 8255.
b) Interface ADC 0808 with 8086 using 8255 ports. Use port A of 8255 for transferring [9M]
digital data output of ADC to the CPU and port C for control signals. Assume that an
analog input is present at I/P2 of the ADC and a clock input of suitable frequency in
available for ADC. Draw the schematic and write required ALP.

5. a) Draw and discuss the paging mechanism of 80386 in detail. [7M]

b) What is meant by a cache memory? How does it speed up the program execution? [7M]
Explain.

6. a) With a neat diagram, explain the internal architecture of 8051 microcontroller. [10M]
b) List and discuss the applications of 8051 microcontrollers. [4M]

7. a) What is the use of interrupts? Discuss the interrupts in PIC 16F877. [6M]
b) List and discuss the main instructions of the PIC 16F877. [8M]

*****

RCE III-ii 6
 JNTUK R16 ECE

L T P C
III Year - II Semester
4 0 0 3
MICROWAVE ENGINEERING

OBJECTIVES
The student will
• Understand fundamental characteristics of waveguides and Microstrip lines through electromagnetic field
analysis.
• Understand the basic properties of waveguide components and Ferrite materials composition
• Understand the function, design, and integration of the major microwave components oscillators, power
amplifier.
• Understand a Microwave test bench setup for measurements.

UNIT I
MICROWAVE TRANSMISSION LINES: Introduction, Microwave Spectrum and Bands, Applications of
Microwaves. Rectangular Waveguides – TE/TM mode analysis, Expressions for Fields, Characteristic Equation and
Cut-off Frequencies, Filter Characteristics, Dominant and Degenerate Modes, Sketches of TE and TM mode fields
in the cross-section, Mode Characteristics – Phase and Group Velocities, Wavelengths and Impedance Relations;
Power Transmission and Power Losses in Rectangular Guide, Impossibility of TEM mode. Related Problems.

UNIT II
CIRCULAR WAVEGUIDES: Introduction, Nature of Fields, Characteristic Equation, Dominant and Degenerate
Modes.
Cavity Resonators– Introduction, Rectangular and Cylindrical Cavities, Dominant Modes and Resonant
Frequencies, Q factor and Coupling Coefficients, Excitation techniques- waveguides and cavities, Related
Problems.
MICROSTRIP LINES– Introduction, Zo Relations, Effective Dielectric Constant, Losses, Q factor.

UNIT III
MICROWAVE TUBES :Limitations and Losses of conventional tubes at microwave frequencies. Re-entrant
Cavities,Microwave tubes – O type and M type classifications. O-type tubes :2 Cavity Klystrons – Structure,
Velocity Modulation Process and Applegate Diagram, Bunching Process and Small Signal Theory –Expressions for
o/p Power and Efficiency, Applications, Reflex Klystrons – Structure, Applegate Diagram and Principle of working,
Mathematical Theory of Bunching, Power Output, Efficiency, Electronic Admittance; Oscillating Modes and o/p
Characteristics, Electronic and Mechanical Tuning, Applications, Related Problems.

UNIT - IV
HELIX TWTS: Significance, Types and Characteristics of Slow Wave Structures; Structure of TWT and
Suppression of Oscillations, Nature of the four Propagation Constants(Qualitative treatment).
M-type Tubes
Introduction, Cross-field effects, Magnetrons – Different Types, 8-Cavity Cylindrical Travelling Wave Magnetron –
Hull Cut-off Condition, Modes of Resonance and PI-Mode Operation, Separation of PI-Mode, o/p characteristics.

RCE III-ii 7
 JNTUK R16 ECE

UNIT V
WAVEGUIDE COMPONENTS AND APPLICATIONS - I :Coupling Mechanisms – Probe, Loop, Aperture
types. Waveguide Discontinuities – Waveguide irises, Tuning Screws and Posts, Matched Loads. Waveguide
Attenuators – Resistive Card, Rotary Vane types; Waveguide Phase Shifters – Dielectric, Rotary Vane types.
Scattering Matrix– Significance, Formulation and Properties. S-Matrix Calculations for – 2 port Junction, E-plane
and H-plane Tees, Magic Tee, Hybrid Ring; Directional Couplers – 2Hole, Bethe Hole types, Ferrite Components–
Faraday Rotation, S-Matrix Calculations for Gyrator, Isolator, Circulator, Related Problems.

UNIT VI
MICROWAVE SOLID STATE DEVICES: Introduction, Classification, Applications. TEDs – Introduction,
Gunn Diode – Principle, RWH Theory, Characteristics, Basic Modes of Operation, Oscillation Modes. Avalanche
Transit Time Devices – Introduction, IMPATT and TRAPATT Diodes – Principle of Operation and Characteristics.
MICROWAVE MEASUREMENTS: Description of Microwave Bench – Different Blocks and their Features,
Precautions; Microwave Power Measurement – Bolometer Method. Measurement of Attenuation, Frequency, Q-
factor, Phase shift, VSWR, Impedance Measurement.

TEXT BOOKS:

1. Microwave Devices and Circuits – Samuel Y. Liao, PHI, 3rd Edition,1994.

2.Foundations for Microwave Engineering – R.E. Collin, IEEE Press, John Wiley, 2nd Edition, 2002.

REFERENCES:
1. Microwave Principles – Herbert J. Reich, J.G. Skalnik, P.F. Ordung and H.L. Krauss, CBS Publishers and
Distributors, New Delhi, 2004
2. Microwave Engineering- Annapurna Das and Sisir K.Das, Mc Graw Hill Education, 3rd Edition.
3. Microwave and Radar Engineering-M.Kulkarni, Umesh Publications, 3rd Edition.
4. Microwave Engineering – G S N Raju , I K International
5. Microwave and Radar Engineering – G Sasibhushana Rao Pearson

OUTCOMES : After going through this course the student will be able to
• Design different modes in waveguide structures
• Calculate S-matrix for various waveguide components and splitting the microwave energy in a desired
direction
• Distinguish between Microwave tubes and Solid State Devices, calculation of efficiency of devices.
• Measure various microwave parameters using a Microwave test bench

RCE III-ii 8
 JNTUK R16 ECE

Code No: R1632042 R16 SET - 1

III B. Tech II Semester Supplementary Examinations, November – 2019

MICROWAVE ENGINEERING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A (14 Marks)

1. a) Define cut-off frequency of a waveguide and write its significance. [2M]
b) Draw the schematic diagram of a microstrip line. [2M]
c) Define reentrant cavity. [2M]
d) Write the applications of magnetron. [3M]
e) Write short notes on waveguide irises. [3M]
f) Write the performance characteristics of TRAPATT diode. [2M]
PART –B (56 Marks)
2. a) What are the characteristics and advantages of microwaves? Explain. [7M]
b) What are the various power losses in waveguides? Explain. [7M]

3. Discuss about TE modes in circular waveguides. [14M]

4. a) Draw the diagram of two-cavity klystron amplifier and explain its working. [7M]
b) Explain about limitations of conventional tubes at microwave frequencies. [7M]

5. a) What is meant by slow wave structure? List out the various slow wave structures. [7M]
Discuss the properties of Helical slow wave structure.
b) Discuss about power output and efficiency of cylindrical magnetron. [7M]

6. a) What is S-matrix? Explain its significance and write the properties of S-matrix. [7M]
b) Explain the operation of circulator and write its applications. [7M]

7. a) Explain about RWH theory for Gunn effect. [7M]

b) Explain the procedure of measurement of low VSWR. [7M]

******

RCE III-ii 9
 JNTUK R16 ECE

Code No: R1632042 R16 SET - 1

III B. Tech II Semester Regular Examinations, April/May- 2019

MICROWAVE ENGINEERING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) An air filled waveguide with cross section 2 cm x 1 cm transports TE10 mode. Find [2M]
λc?
b) The wave is travelled in circular wave guide of Vp= 5x108 m/sec, find Group [2M]
velocity?
c) Calculate the velocity of an electron beam if Vdc=9 V. [2M]
d) Define π-mode condition in Magnetron? [3M]
e) Find the reflection coefficient if VSWR=3. [3M]
f) Draw the graphs of drift velocity versus E-field and J versus E-field. [2M]

PART -B
2. a) When the dominant mode is propagated in an air-filled standard rectangular [7M]
waveguide, the guide wave length at a frequency of 9 GHz is 4 cm. Calculate width
of the guide.
b) Derive TE Wave field equations. [7M]

3. a) Give the physical structure and field distribution of microstrip line. Why Can a [7M]
pure TEM mode not be propagated in a microstrip line?
b) An air-filled circular waveguide of 2 cm inside radius is operated in the TE01 mode. [7M]
i) Compute the cut-off frequency.
ii) If the guide is to be filled with a dielectric material of εr= 2.25, to what value
must its radius be changed in order to maintain the cut-off frequency at its
original value?

4. a) Explain principle of operation, performance characteristics and applications of [7M]

Two Cavity Klystron.
b) A Reflex Klystron is operated at 9 GHz with DC beam voltage of 600 V and [7M]
1 3 4 mode, repeller space length 1 mm. DC beam current 10 mA. The beam
coupling coefficient is assumed to be 1. Calculate the repeller voltage, electronic
efficiency and output power.

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Code No: R1632042 R16 SET - 1

5. a) Why Magnetron is also called “Extended Interaction tube”? Derive the expression [7M]
for Hull cut-off magnetic flux density in cylindrical Magnetron.
b) A Travelling Wave Tube has the following parameters: [7M]
Beam current, Io=50 mA; Beam voltage, Vo=2.5 kV;
Characteristic impedance of helix, Zo=6.75Ω; Circuit length N=45;
Frequency f= 8 GHz. Determine
i) Gain parameter C
ii) Output power gain in db
iii) All four propagation constants
iv) The wave equations for all four modes in exponential form.

6. a) What is Magic Tee? Why it is called so? Explain the characteristics of the tee [7M]
considering various input/output conditions?
b) What is a precision rotary attenuator? Explain its operation. [7M]

7. a) How is slotted line used for measurement of impedance of an unknown load? [7M]
Explain.
b) Draw the band diagram of GaAs and explain the Gunn effect, where by negative [7M]
resistances and therefore oscillations are obtained under certain conditions from
bulk gallium arsenide.

*****

2 of 2

RCE III-ii 11
 JNTUK R16 ECE

Code No: R1632042 R16 SET - 2

III B. Tech II Semester Regular Examinations, April/May- 2019

MICROWAVE ENGINEERING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) An air-filled waveguide with dimensions 5 cm x 2 cm transports TE01 mode. Find [2M]
λc?
b) The radius of a circular waveguide with air filled is 3 cm. Find the radius if guide is [2M]
filled with εr = 4.
c) Calculate the transit angle of a beam passing through the gap of 1 mm with [2M]
frequency 3 GHz and uniform velocity 2 x 107 m/sec.
d) Calculate angular frequency of a magnetron if B0= 2m/e? [3M]
e) Calculate coupling factor of a directional coupler, if Pin = 100 mW and Coupling [3M]
power is 10 mW.
f) Estimate the fr of an IMPATT diode whose drift velocity is 105 m/sec and Drift [2M]
space is 22 µm.
PART -B
2. a) What is the maximum power that can be transmitted by rectangular guide [7M]
1.5 cm x 0.75 cm at 45 GHz?
b) Prove that TM11 is the lowest TM wave mode in a rectangular WG. [7M]

3. a) Explain the function of a Rectangular Resonator Cavity? [7M]

b) A TE11 wave is propagating through a circular waveguide. The diameter of the [7M]
guide is 10 cm and waveguide is air filled.
i) Find the cutoff frequency.
ii) Find the Wavelength λg in the guide for a frequency of 3 GHz.
iii) Determine the wave impedance in the guide.

4. a) For a Two Cavity Klystron, the voltage applied to cathode is 900 V. The gap in [7M]
input cavity is 1.5 mm and spacing between cavities is 4 cm. The voltage across the
cavity gap is 10 V peak to peak. Calculate the value of bunching parameter for a
beam frequency of 9 GHz.
b) Derive the expression for electron admittance of a Reflex Klystron Oscillator. [7M]

5. a) What are π-mode oscillations? Explain how oscillations are sustained in the Cavity [7M]
Magnetron with suitable sketches, assuming that π-mode oscillations already exist?
b) A helical TWT has a diameter of 2 mm with 50 turns per cm. Calculate axial phase [7M]
velocity and the anode voltage at which the TWT can operate in useful gain.

6. a) Explain the construction and working of Directional Coupler. Under what [7M]
conditions does the coupler give maximum directivity?
b) Discuss various types of Waveguide attenuators. [7M]

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Code No: R1632042 R16 SET - 2

7. a) How VSWR of unknown load is measured with the help of Slotted Wave Carriage [7M]
using microwave bench setup? Draw the block diagram of the setup.
b) What is transferred electron effect? In which type of material it is present. How the [7M]
domain formation is taking place in Gunn devices and what are its various modes
of operation?

*****

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Code No: R1632042 R16 SET - 3

III B. Tech II Semester Regular Examinations, April/May- 2019

MICROWAVE ENGINEERING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) The wave is travelled in a rectangular wave guide with λc is 3λ0. Find Group [2M]
velocity?
b) List out the losses in microstrip lines. [2M]
c) Define velocity modulation. [2M]
d) Write the applications of Travelling wave tubes. [3M]
e) Draw the structure of capacitive Iris and resonant Iris? [3M]
f) By using reflectometer, the measured incident power is 9 times of reflected Power. [2M]
What is the reflection coefficient?
PART -B
2. a) Prove that TE10 is the dominant mode in rectangular wave guide. [7M]
b) Explain the concept of phase velocity and group velocity. [7M]

3. a) Explain the following about microstrip line: [7M]

i) Characteristic impedance
ii) The effective microstrip permittivity and effective relative permittivity.
b) Estimate the quality factor of a cavity resonator at different load conditions. [7M]

4. a) How bunch formation takes place in drift region in Two Cavity Klystron? Explain? [7M]
b) What are the Re-entrant Cavities? Why these are different from Resonant cavities? [7M]
Explain?

5. a) Define mode jumping? Explain the techniques to eliminate mode jumping? [7M]
b) A helix travelling wave tube operates at 4 GHz under a beam voltage Vo=6 kV and [7M]
beam current Io=30mA. If the helix impedance Zo is 100 ohm and circuit length
N=30, find the output power gain.

6. a) Derive the S-Matrix of E-plane tee when power is fed from auxiliary port. Consider [7M]
other ports in the matched condition.
b) What is Circulator? Explain the various applications of Circulator. [7M]
7. a) Show how to measure the frequency of the source without using a wave meter in the [7M]
microwave test bench? Explain.
b) How avalanche effect is utilized to generate microwave signals? Explain The [7M]
operation of IMPATT diode.

*****

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Code No: R1632042 R16 SET - 4

III B. Tech II Semester Regular Examinations, April/May- 2019
MICROWAVE ENGINEERING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) The wave is travelled in a rectangular wave guide with λc is 2λo. Find Phase [2M]
velocity?
b) Calculate the resonant frequency of a Rectangular Cavity Resonator with [2M]
dimensions 2 cm x 1 cm x 3 cm with TE100 wave?
c) Define beam coupling coefficient and draw the graph between angle and beam [2M]
efficiency?
d) Draw the types of slow wave structures used in HTWT? [3M]
e) Estimate the reflected power due to load mismatch with Ѓ=0.1 and Pi= 200W? [3M]
f) Using double minima method, find SWR for λg= π cm and distance between the [2M]
positions of twice minimum power is 0.5 cm.
PART -B
2. a) A rectangular air filled copper waveguide with dimension 2.28 cm and 1.01 cm is [7M]
operated at 9.2 GHz with dominant mode. Find the cut-off frequency, guide wave
length, phase shift, phase velocity and characteristic impedance.
b) Discuss the types of losses exist in Rectangular Wave Guide. [7M]

3. a) Compute the lowest resonant frequency of a Rectangular Cavity Resonator having [7M]
following dimensions: width=2 cm, height=1cm , length=3 cm.
b) Derive TE mode in a Circular Waveguide? [7M]

4. a) Derive the velocity modulation equation of Two Cavity Klystron amplifier? [7M]
b) Prove that the efficiency of a Reflex Klystron Oscillator is only 22%? [7M]

5. a) With the support of a diagram, explain the operation of Eight Cavity Magnetron. [7M]
b) An X-band pulsed Cylindrical Magnetron has Vo=30 kV, Io=80 A, [7M]
Bo=0.01 Wb/m2, a=4 cm, b=8 cm. Calculate
i) Cyclotron angular frequency
ii) Cutoff voltage
iii) Cutoff magnetic flux density
6. a) Explain the working and applications of two types of Waveguide discontinuity. [7M]
b) An Isolator has an insertion loss of 0.5 dB and isolation of 30 dB. Determine the [7M]
scattering matrix of the Isolator if the isolated ports are perfectly matched to
junction.
7. a) What is Reflection meter? How it is used to measure the reflection coefficient and [7M]
VSWR of any unknown load?
b) How avalanche effect is utilized to generate microwave signals? Explain the [7M]
operation of TRAPATT diode.
*****

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L T P C
III Year - II Semester
4 0 0 3
VLSI DESIGN
Objectives:

The main objectives of this course are:

• Basic characteristics of MOS transistor and examines various possibilities for configuring inverter circuits
and aspects of latch-up are considered.
• Design processes are aided by simple concepts such as stick and symbolic diagrams but the key element is a
set of design rules, which are explained clearly.
• Basic circuit concepts are introduced for MOS processes we can set out approximate circuit parameters
which greatly ease the design process.

Outcomes:

At the end of this course the student can able to:

• Understand the properties of MOS active devices and simple circuits configured when using them and the
reason for such encumbrances as ratio rules by which circuits can be interconnected in silicon.
• Know three sets of design rules with which nMOS and CMOS designs may be fabricated.
• Understand the scaling factors determining the characteristics and performance of MOS circuits in silicon.

Syllabus:

UNIT-I:
Introduction and Basic Electrical Properties of MOS Circuits: Introduction to IC technology, Fabrication
process: nMOS, pMOS and CMOS. Ids versus Vds Relationships, Aspects of MOS transistor Threshold Voltage,
MOS transistor Trans, Output Conductance and Figure of Merit. nMOS Inverter, Pull-up to Pull-down Ratio for
nMOS inverter driven by another nMOS inverter, and through one or more pass transistors. Alternative forms of
pull-up, The CMOS Inverter, Latch-up in CMOS circuits, Bi-CMOS Inverter, Comparison between CMOS and
BiCMOS technology.
(Text Book-1)

UNIT-II:
MOS and Bi-CMOS Circuit Design Processes: MOS Layers, Stick Diagrams, Design Rules and Layout, General
observations on the Design rules, 2µm Double Metal, Double Poly, CMOS/BiCMOS rules, 1.2µm Double Metal,
Double Poly CMOS rules, Layout Diagrams of NAND and NOR gates and CMOS inverter, Symbolic Diagrams-
Translation to Mask Form.
(Text Book-1)

UNIT-III:
Basic Circuit Concepts: Sheet Resistance, Sheet Resistance concept applied to MOS transistors and Inverters, Area
Capacitance of Layers, Standard unit of capacitance, Some area Capacitance Calculations, The Delay Unit, Inverter
Delays, Driving large capacitive loads, Propagation Delays, Wiring Capacitances, Choice of layers.

Scaling of MOS Circuits: Scaling models and scaling factors, Scaling factors for device parameters, Limitations of
scaling, Limits due to sub threshold currents, Limits on logic levels and supply voltage due to noise and current
density. Switch logic, Gate logic.
(Text Book-1)

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UNIT-IV:
Chip Input and Output circuits: ESD Protection, Input Circuits, Output Circuits and L(di/dt) Noise, On-Chip
clock Generation and Distribution.

Design for Testability: Fault types and Models, Controllability and Observability, Ad Hoc Testable Design
Techniques, Scan Based Techniques and Built-In Self Test techniques.
(Text Book-2)

UNIT-V:
FPGA Design: FPGA design flow, Basic FPGA architecture, FPGA Technologies, FPGA families- Altera Flex
8000FPGA, Altera Flex 10FPGA, Xilinx XC4000 series FPGA, Xilinx Spartan XL FPGA, Xilinx Spartan II
FPGAs, Xilinx Vertex FPGA. Case studies: FPGA Implementation of Half adder and full adder.

Introduction to synthesis: Logic synthesis, RTL synthesis, High level Synthesis.

(Reference Text Book-1)

UNIT-VI:
Introduction to Low Power VLSI Design: Introduction to Deep submicron digital IC design, Low Power CMOS
Logic Circuits: Over view of power consumption, Low –power design through voltage scaling, Estimation and
optimisation of switching activity, Reduction of switching capacitance. Interconnect Design, Power Grid and Clock
Design.
(Text Book-2)

Text Books:

1. Essentials of VLSI Circuits and Systems - Kamran Eshraghian, Douglas and A. Pucknell and Sholeh
Eshraghian, Prentice-Hall of India Private Limited, 2005 Edition.
2. CMOS Digital Integrated Circuits Analysis and Design- Sung-Mo Kang, Yusuf Leblebici, Tata McGraw-
Hill Education, 2003.

References:

1. Advanced Digital Design with the Verilog HDL, Michael D.Ciletti, Xilinx Design Series, Pearson Education
2. Analysis and Design of Digital Integrated Circuits in Deep submicron Technology, 3’rd edition, David
Hodges.

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Code No: R1632043 R16 SET - 1

III B. Tech II Semester Supplementary Examinations, November - 2019
VLSI DESIGN
(Common to Electronics and Communication Engineering, Electronics
and Computer Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A (14 Marks)

1. a) Why is VLSI design process presented in NMOS only? Justify with an example. [2M]
b) Give the different scaling models and scaling factors. [2M]
c) Explain about Inverter Delays. [2M]
d) Explain about chip output circuit. [3M]
e) What information from the targeted FPGA device is required in RTL synthesis? [3M]
f) Explain about Clock Design. [2M]

PART –B (56 Marks)

2. a) Derive an equation for Ids of an n-channel Enhancement MOSFET operating in [7M]
Saturation region.
b) An nMOS transistor is operating in saturation region with the following [7M]
parameters. VGS = 5V; Vtn = 1.2V; W/L = 110; μnCox = 110 μA/V2. Find
transconductance of the device.

3. a) Explain about double poly CMOS rules. [7M]

b) Design a layout diagram for CMOS 3-input NAND gate. [7M]

4. a) What is meant by sheet resistance Rs? Explain the concept of Rs applied to MOS [7M]
transistors.
b) Calculate on resistance of an inverter from VDD to GND. If n- channel sheet [7M]
resistance Rsn=104 Ω per square and P-channel sheet resistance Rsp = 3.5 × 104 Ω
per square. (Zpu=4:4 and Zpd=2:2).

5. Discuss in detail about Fault types and Models. [14M]

6. a) Write down the step by step approach of FPGA design process on XILINX [7M]
environment.
b) Design a queue and write the dataflow style VHDL program for the same. [7M]

7. Discuss in detail about Low Power CMOS Logic Circuits. [14M]

*****

RCE III-ii 18
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Code No: R1632043 R16 SET - 1

III B. Tech II Semester Regular Examinations, April/May - 2019

VLSI DESIGN
(Common to Electronics and Communication Engineering, Electronics and Instrumentation
Engineering, Electronics and Computer Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) Write down the equations for Ids of an n-channel enhancement MOSFET operating in [2M]
Non-saturated region and saturated region.
b) Define stick diagram and layout diagram. [2M]
c) Explain about the constraints in choice of layers. [2M]
d) Mention the common techniques involved in ad-hoc testing. [3M]
e) What information from the targeted FPGA device is required in RTL synthesis? [3M]
f) Explain about clock skew. [2M]

PART -B
2. a) Explain the nMOS enhancement mode fabrication process for different conditions of [7M]
Vds.
b) Derive an expression for transconductance of an n-channel enhancement MOSFET [7M]
operating in active region.

3. a) Draw a stick diagram and layout for two input CMOS NAND gate indicating all the [7M]
regions and layers.
b) Explain 2 µm Double Metal, Double Poly CMOS / BiCMOS Rules. [7M]

4. a) Explain the issues involved in driving large capacitor loads in VLSI circuit regions. [7M]
b) Calculate the gate capacitance value of 5 mm technology minimum size transistor with [7M]
gate to channel value is 4 x 10-4 pF/mm2.

5. a) Explain about the following types of faults with suitable example: [7M]
(i) stuck at faults (ii) Bridge faults (iii) temporary faults
b) Explain the different categories of DFT techniques. [7M]

6. a) Write down the step by step approach for FPGA design process on XILINX [7M]
environment?
b) Draw and explain the basic architecture of FPGA. [7M]

7. a) Explain about deep submicron processes with suitable schematic diagrams. [7M]
b) Explain about the scaling limitation for low voltage, low power design. Give the effect [7M]
of scaling on various MOSFET parameters with necessary equations.

******

RCE III-ii 19
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Code No: R1632043 R16 SET - 2

III B. Tech II Semester Regular Examinations, April/May - 2019

VLSI DESIGN
(Common to Electronics and Communication Engineering, Electronics and Instrumentation
Engineering, Electronics and Computer Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) Explain the terms SSI, LSI, and VLSI with the number of transistors per chip and [2M]
applications.
b) Draw the stick diagram for CMOS Inverter. [2M]
c) What is sheet resistance? Derive the Expression for RS? [2M]
d) What are the approaches in design for testability? [3M]
e) Explain synthesis process. [3M]
f) What are the different types of power consumption? [2M]

PART -B
2. a) Explain in detail the p-well process for CMOS fabrication indicating the masks used. [7M]
b) Compare the relative merits of three different forms of pull-up for an inverter circuit. [7M]
What is the best choice for realization in nMOS and CMOS technology?

3. a) What are the λ-based design rules? Give them for each layer. [7M]
b) Draw a stick diagram for CMOS logic Y= (A+B+C)Ꞌ. [7M]

4. a) What is inverter delay? How delay is calculated for multiple stages? Explain. [7M]
b) Two nMOS inverters are cascaded to drive a capacitive load C L=16Cg. Calculate pair [7M]
delay Vin to Vout in terms of τ.

5. a) What are the different faults found in combinational circuits? How can they be [7M]
categorized?
b) Briefly discuss about Built-In-Self Test technique with a suitable diagram. [7M]

6. a) Give the steps in FPGA design flow with flow diagram and briefly discuss about each [7M]
step.
b) Explain about the principle and operation of FPGAs. What are its applications? [7M]

7. a) Discuss about the various problems associated with low voltage VLSI circuit design. [7M]
b) Explain about estimation and optimization of switching activity. [7M]

*****

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Code No: R1632043 R16 SET - 3

III B. Tech II Semester Regular Examinations, April/May - 2019

VLSI DESIGN
(Common to Electronics and Communication Engineering, Electronics and Instrumentation
Engineering, Electronics and Computer Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) Define Moore’s law. [2M]
b) Draw a symbolic layout of a two–input NAND gate. [3M]
c) Give the scaling factor for Maximum operating frequency (f0) in terms of different [2M]
scaling models.
d) What is meant by observability? [3M]
e) What are FPGAs? [2M]
f) What is switching activity? [2M]
PART -B
2. a) Compare BiCMOS technology with other Technologies. [7M]
b) Calculate ID and VDS if kn = 100 μA/v2, Vtn = 0.6V and W/L =3 for transistor M1, in [7M]
the circuit shown below:

3. a) Explain with suitable examples how to design the layout of a Gate to maximize [7M]
performance and minimize area.
b) Design a stick diagram for nMOS logic Y= (A+B+C)Ꞌ. [7M]
4. a) How does depletion regions around source and drain are affected due to scaling [7M]
down of device dimensions? Explain.
b) Derive the expression for propagation delay in the case of cascaded pass transistors. [7M]

5. a) Define the terms ‘failure’ and ‘fault’. Discuss the different fault models. [7M]
b) Briefly discuss about On-Chip clock generation and distribution. [7M]
6. a) Explain the following terms: [8M]
(i) LUT (ii) CLB (iii) IOB (iv) Switch matrix
b) List out the various FPGA families. Explain how they are different from each [6M]
other?
7. a) Explain about the design limitations imposed on low power, low voltage circuits [7M]
pertaining to the scaling and inter connect wires.
b) Briefly discuss about the different techniques for reduction of switching [7M]
capacitance.
*****

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Code No: R1632043 R16 SET - 4

III B. Tech II Semester Regular Examinations, April/May - 2019

VLSI DESIGN
(Common to Electronics and Communication Engineering, Electronics and Instrumentation
Engineering, Electronics and Computer Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) Discuss the microelectronics evolution. [3M]
b) What is Vias? How to construct it in layout? [2M]
c) What is the need of scaling in MOS circuits? [2M]
d) Explain how function of system can be tested. [2M]
e) List out the commercially available FPGAs. [3M]
f) What is the need of interconnect? [2M]
PART -B
2. a) What are the additional two layers in BiCMOS technology compared to others? [7M]
With neat sketches explain BiCMOS fabrication process.
b) Show that the switching speed of an enhancement MOSFET varies inversely as [7M]
the square of the channel length.

3. a) Give the design rules for the following cases with neat sketches: [8M]
(i) Polysilicon – polysilicon (ii) n-type diffusion – n-type diffusion
(iii) n-type diffusion – p-type diffusion (iv) metal 1 – metal 2.
b) Design a stick diagram for two input pMOS NAND and NOR gates. [6M]

4. Describe the following briefly [14M]

(i) Cascaded inverters as drivers (ii) Super buffers (iii) BiCMOS drivers

5. a) Explain the terms controllability, observability and fault coverage. [7M]

b) With suitable diagrams, explain the Scan based test techniques. [7M]

6. a) List out the different configuration modes in FPGA. Briefly discuss about it. [7M]
b) How the pass transistors are used to connect wire segments for the purpose of [7M]
FPGA programming? Explain.

7. a) What is the different technical parameter issues connected with VLSI low power [7M]
and low voltage design? Explain.
b) With schematic diagrams explain about deep submicron processes. [7M]

*****

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L T P C
III Year - II Semester
4 0 0 3
DIGITAL SIGNAL PROCESSING

OBJECTIVES
The student will be able to
• Analyze the Discrete Time Signals and Systems
• Know the importance of FFT algorithm for computation of Discrete Fourier Transform
• Understand the various implementations of digital filter structures
• Learn the FIR and IIR Filter design procedures
• Know the need of Multirate Processing
• Learn the concepts of DSP Processors

UNIT I INTRODUCTION: Introduction to Digital Signal Processing: Discrete time signals & sequences,
Classification of Discrete time systems , stability of LTI systems, Invertability, Response of LTI systems to
arbitrary inputs. Solution of Linear constant coefficient difference equations. Frequency domain representation of
discrete time signals and systems. Review of Z-transforms, solution of difference equations using Z-transforms,
System function.

UNIT II DISCRETE FOURIER SERIES & FOURIER TRANSFORMS: Properties of discrete Fourier series,
DFS representation of periodic sequences, Discrete Fourier transforms: Properties of DFT, linear filtering methods
based on DFT, Fast Fourier transforms (FFT) - Radix-2 decimation in time and decimation in frequency FFT
Algorithms, Inverse FFT.

UNIT III. DESIGN OF IIR DIGITAL FILTERS& REALIZATIONS: Analog filter approximations – Butter
worth and Chebyshev, Design of IIR Digital filters from analog filters, Design Examples, Analog and Digital
frequency transformations. Basic structures of IIR systems, Transposed forms.

UNIT IV DESIGN OF FIR DIGITAL FILTERS & REALIZATIONS:

Characteristics of FIR Digital Filters, frequency response. Design of FIR Digital Filters using Window Techniques
and Frequency Sampling technique, Comparison of IIR & FIR filters.
Basic structures of FIR systems, Lattice structures, Lattice-ladder structures

UNIT V MULTIRATE DIGITAL SIGNAL PROCESSING: Introduction, Decimation , Interpolation

Sampling rate conversion ,Implementation of sampling rate converters, Applications – Sub-band Coding of Speech
Signals ,Implementation of Digital Filter Banks, Trans-multiplexers.

UNIT VI INTRODUCTION TO DSP PROCESSORS: Introduction to programmable DSPs: Multiplier and

Multiplier Accumulator, Modified bus structures and memory access schemes in P-DSPs ,Multiple Access Memory,
Multiported memory, VLIW architecture, Pipelining, Special addressing modes, On-Chip Peripherals.
Architecture of TMS320C5X: Introduction, Bus Structure, Central Arithmetic Logic Unit, Auxiliary Register ALU,
Index Register, Block Move Address Register, Parallel Logic Unit, Memory mapped registers, program controller,
some flags in the status registers, On- chip memory, On-chip peripherals.
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TEXT BOOKS:
1. Digital Signal Processing, Principles, Algorithms, and Applications: John G. Proakis, Dimitris
G.Manolakis,Pearson Education / PHI, 2007.
2. Discrete Time Signal Processing – A.V.Oppenheim and R.W. Schaffer, PHI
3. Digital Signal Processors – Architecture, Programming and Applications,, B.Venkataramani, M.Bhaskar, TATA
McGraw Hill, 2002
4. Digital Signal Processing – K Raja Rajeswari, I.K. International Publishing House

Reference Books:
1. Digital Signal Processing: Andreas Antoniou, TATA McGraw Hill , 2006
2. Digital Signal Processing: MH Hayes, Schaum’s Outlines, TATA Mc-Graw Hill, 2007.
3. DSP Primer - C. Britton Rorabaugh, Tata McGraw Hill, 2005.
4. Fundamentals of Digital Signal Processing using Matlab – Robert J. Schilling, Sandra
L. Harris,Thomson, 2007.
5. Digital Signal Processing – Alan V. Oppenheim, Ronald W. Schafer, PHI Ed., 2006
6. Digital Signal Processing – Ramesh babu, Sci Tech publications

OUTCOMES
After going through this course the student will be able to

• Apply the difference equations concept in the anayziation of Discrete time systems
• Use the FFT algorithm for solving the DFT of a given signal
• Design a Digital filter (FIR&IIR) from the given specifications
• Realize the FIR and IIR structures from the designed digital filter.
• Use the Multirate Processing concepts in various applications(eg: Design of phase shifters, Interfacing of
digital systems…)
• Apply the signal processing concepts on DSP Processor.

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Code No: R1632044 R16 SET - 1

III B. Tech II Semester Regular Examinations, April/May - 2019

DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

PART –A
1. a) What is the condition for stability of an LTI system? [2M]
b) What are the number of computations required for the direct computation of 𝑁- [2M]
point DFT?
c) What is the relation between digital and analog frequencies in bilinear [2M]
transformation?
d) What are the characteristics of FIR digital filters? [3M]
e) List the applications of multirate signal processing. [3M]
f) What are the on-chip peripherals of programmable DSP? [2M]
PART -B
2. a) What are the advantages of DSP over ASP? Explain. [7M]
b) Find the impulse response ℎ[𝑛] of the system described by the difference [7M]
equation
8𝑦 𝑛 + 6𝑦 𝑛 − 1 = 𝑥[𝑛]

3. a) Compute the DFT of the three point sequence x(n) = { 2, 1, 2 }. Using the [7M]
same sequence, compute the 6 point DFT and compare the two DFTs.
b) Give the steps involved in implementing Radix –2, DIT FFT algorithm. [7M]

4. a) With an example explain the design procedure for Butterworth filter. [7M]
b) Explain the differences between Direct form-I and Direct form-II structures. [7M]
5. a) What are the characteristics of linear phase FIR digital filters? [7M]
b) Design an FIR digital low pass filter with cutoff frequency 1.2 radian and [7M]
length 𝑁 = 7. Use frequency sampling method.

6. a) What are the basic building blocks of multirate system? Explain. [7M]
b) Describe the multi-stage implementation of a 32-fold decimator. [7M]

7. a) Explain the difference between Von Neumann and Harvard architectures. [7M]
Which architecture is preferred for DSP applications and why?
b) Explain what is meant by instruction pipelining. [7M]

*****

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 JNTUK R16 ECE

Code No: R1632044 R16 SET - 2

III B. Tech II Semester Regular Examinations, April/May - 2019

DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) State the time shifting property of z-transform. [2M]
b) Draw the butterfly structure for computation of 4-point DFT of a DT sequence. [2M]
c) What is meant by frequency warping effect? [2M]
d) Draw the frequency response of digital low pass and high pass filters. [3M]
e) What do you mean by fractional sampling rate conversion? [3M]
f) What is the use of MAC unit in DSP architecture? [2M]
PART -B
2. a) What are the conditions for stability and causality of an LTI system? Explain. [7M]
b) For a system described by 8𝑦 𝑛 + 4𝑦 𝑛 − 1 + 𝑦 𝑛 − 2 = 𝑥[𝑛] [7M]
Find the response to a unit amplitude complex sinusoidal excitation at a DT cyclic
frequency Ω.
3.  [7M]
a) Compute the 4-point DFT of x(n)  Cos n 0 n 3 using Radix–2 DIT FFT
2
algorithm.
b) Compute the circular convolution of the sequences [7M]
𝑥1 𝑛 = { 1, 2, 0, 1 } and 𝑥2 (𝑛) = { 2, 2, 1, 1 }

4. Design a low pass digital filter that will operate on sampled analog data such that [14M]
the analog cutoff frequency is 200 Hz (1 dB acceptable ripple) and at 400 Hz the
attenuation is at least 20 dB with monotonic shape past 400 Hz. The sample rate is
2000 samples/sec. Use impulse invariant transformation.

5. a) Distinguish between IIR and FIR filters. [7M]

b) Explain the frequency-sampling method of FIR filter design with an example. [7M]

6. a) Show that down-sampler is a time-variant system. [7M]

b) What is the need for multi-stage implementation of sampling rate converters? [7M]
Explain with an example.

7. a) What is meant by bit reversed addressing mode? What is the application for which [7M]
this addressing mode is preferred?
b) Draw the pipelined MAC configuration to perform convolution operation and [7M]
explain with neat timing diagrams.

*****

RCE III-ii 26
 JNTUK R16 ECE

Code No: R1632044 R16 SET - 3

III B. Tech II Semester Regular Examinations, April/May - 2019
DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) 𝑧2 [2M]
Draw the pole-zero plot of 𝐻 𝑧 = 1
𝑧−1 𝑧−
4
b) Compute the DFT of 𝑥 𝑛 = [1,0]. [2M]
c) 1 [2M]
Find 𝐻(𝑧) using bilinear transformation transformation, if 𝐻𝑎 𝑠 = 𝑠 .
d) What is Gibb’s phenomenon? [3M]
e) 1 𝑛 [3M]
𝑛 ;0 ≤ 𝑛 ≤ 3
Plot 𝑦 𝑛 = 𝑥 , if 𝑥 𝑛 = 2
2
0 ; 𝑒𝑙𝑠𝑒𝑤ℎ𝑒𝑟𝑒
f) What do you mean by circular buffer? [2M]
PART -B
2. a) State and prove the properties of convolution. [7M]
b) Using the z-transform, find the total solution to the following difference equation [7M]
with initial conditions, for discrete time 𝑛 ≥ 0.
5𝑦 𝑛 + 2 − 3𝑦 𝑛 + 1 + 𝑦 𝑛 = 0.8 𝑛 𝑢 𝑛 , 𝑦 0 = −1, 𝑦 1 = 10

3. a) Compute the DFT of the given sequence 𝑥 𝑛 using DIT FFT algorithm. [7M]
𝑥[𝑛] = {1, −1, 1, − 1, 1, − 1, 1, − 1}
Show the intermediate result on the flow graph.
b) Prove that the convolution in time-domain leads to multiplication in frequency [7M]
domain for discrete time signals.

4. Determine the system function 𝐻(𝑧) of the lowest order Butterworth digital filter [14M]
with the following specification
(i) 3 dB ripple in pass band 0 𝑤  0.2 
(ii) 25 dB attenuation in stop band 0.45  𝑤 .

5. Design a linear phase FIR filter with the magnitude response [14M]
𝜋
𝐻 𝑒 𝑗 Ω = 1 𝑓𝑜𝑟   8
= 0 𝑓𝑜𝑟  8    𝜋

Use Hamming window. The length of the impulse response is limited to 9. Draw the
Direct form structure of the filter.

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Code No: R1632044 R16 SET - 3

6. a) An up-sampler and X (  ) are depicted in the following figure. Draw the spectrum of [7M]
y[ n ].

b) Show that the up-sampler is a time-variant system. [7M]

7. a) What are the architectural features of TMS320C5x DSP? [7M]

b) What are the special addressing modes of DSP? Explain. [7M]

*****

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Code No: R1632044 R16 SET - 4

III B. Tech II Semester Regular Examinations, April/May - 2019

DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A
1. a) What are the limitations of DSP? [2M]
b) Draw the discrete spectrum of the DT sequence 𝑥 𝑛 = 1,1,1,1 . [2M]
c) 1 [2M]
Find 𝐻(𝑧) using impulse invariant transformation, if 𝐻𝑎 𝑠 = 𝑠+1.
d) Draw the spectrum of rectangular window function. [3M]
e) Find 𝑦 𝑛 = 𝑥 3𝑛 , if 𝑥 𝑛 = [1,2,3,4]. [3M]
f) Draw the configuration of a pipelined MAC unit. [2M]
PART -B
2. a) State and prove final-value theorem of z-transform. [7M]
b) What are the basic elements of a DSP system? Explain. [7M]

3. a) 1 1 1 1 [7M]
Compute the DFT of a sequence 𝑥 𝑛 = 2 , 2 , 2 , 2 , 1, 1, 1, 1 using DIF-FFT
b) State and prove convolution property of DFT. [7M]

4. Determine the system function 𝐻(𝑧) of the lowest order Chebyshev digital filter [14M]
with the following specification
(i) 3dB ripple in pass band 0 𝑤  0.25 
(ii) 30 dB attenuation in stop band 0.35  𝑤 .

5. Design a linear phase FIR filter with the magnitude response [14M]
𝜋
𝐻 𝑒 𝑗 Ω = 1 𝑓𝑜𝑟   4
𝜋
= 0 𝑓𝑜𝑟    𝜋
4

Use Rectangular window. The length of the impulse response is limited to 7. Find
the magnitude response of designed filter.

6. a) Explain the frequency-domain characterization of down-sampler with neat sketches. [7M]

b) What are the applications of multirate DSP? Explain briefly. [7M]

7. Write notes on the following:

a) VLIW architecture [7M]
b) Multiported memory [7M]

*****

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Code No: R1632044 R16 SET - 1

III B. Tech II Semester Supplementary Examinations, November -2019

DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Max. Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answer ALL the question in Part-A
3. Answer any FOUR Questions from Part-B
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
PART –A (14 Marks)
1. a) What is BIBO stability? What are the conditions for BIBO stability? [2M]
b) How FFT is more efficient to determine DFT of sequence? [2M]
c) Why IIR filters do not have linear phase? [2M]
d) What conditions are to be satisfied by the impulse response of an FIR system in order [3M]
to have a linear phase?
e) What is the significance of Multirate Signal processing? [3M]
f) What are the advantages of VLIW architecture? [2M]
PART –B (56 Marks)
2. a) Determine the Inverse Z-Transform of: X(Z)=1/(1-Z-1)(1-Z-1)2. [7M]
b) Determine the stability for the following systems: [7M]
i) h(n) = 2n u(n) ii) h(n) = 5n u(3-n) iii) h(n) = e-6|n|.

3. a) Find the DFT of a sequence x(n)={1, 1, 0, 0} and find the IDFT of Y(k)={1, 0, 1, 0}. [7M]
b) Establish the relation between DFT and Z-transform. [7M]

4. a) Determine direct form I and cascade realization of the following system: [7M]
H [z] =
(
2 1 −z −1
)(1 + 2 z + z )
−1 −2

(1 + 0.5 z −1
) (1 − 0.9 z −1+0.81z − 2 )
b) Design a Chebyshev filter with a maximum pass band attenuation of 2.5 dB at a [7M]
frequency of 20 rad/sec and the stop band attenuation of 30 dB at a frequency
50 rad/sec.

5. a) List out the characteristics of FIR digital filters. [7M]

b) Explain the need for the use of window sequence in the design of FIR filter. Describe [7M]
the window sequence generally used and compare the properties.
6. a) Explain the decimation and interpolation processes with an example. [7M]
b) Explain any two applications of Multirate digital signal processing. [7M]

7. a) Explain the following in detail: [7M]

i) Index Register ii) On-chip memory.
b) With neat block diagram, explain about the pipelining. [7M]

*****

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 JNTUK R16 ECE

L T P C
III Year - II Semester
4 0 0 3
OOPS THROUGH JAVA
OPEN ELECTIVE

OBJECTIVES:
• Understanding the OOP’s concepts, classes and objects, threads, files, applets, swings and act.
• This course introduces computer programming using the JAVA programming language with object-
oriented programming principles.
• Emphasis is placed on event-driven programming methods, including creating and manipulating objects,
classes, and using Java for network level programming and middleware development

UNIT-I:
Introduction to OOP, procedural programming language and object oriented language, principles of OOP,
applications of OOP, history of java, java features, JVM, program structure.
Variables, primitive data types, identifiers, literals, operators, expressions, precedence rules and associativity,
primitive type conversion and casting, flow of control.

UNIT-II:
Classes and objects, class declaration, creating objects, methods, constructors and constructor overloading, garbage
collector, importance of static keyword and examples, this keyword, arrays, command line arguments, nested
classes.

UNIT-III:
Inheritance, types of inheritance, super keyword, final keyword, overriding and abstract class.
Interfaces, creating the packages, using packages, importance of CLASSPATH and java.lang package. Exception
handling, importance of try, catch, throw, throws and finally block, user-defined exceptions, Assertions.

UNIT-IV:
Multithreading: introduction, thread life cycle, creation of threads, thread priorities, thread synchronization,
communication between threads. Reading data from files and writing data to files, random access file,

UNIT-V:
Applet class, Applet structure, Applet life cycle, sample Applet programs. Event handling: event delegation model,
sources of event, Event Listeners, adapter classes, inner classes.

UNIT-VI:
AWT: introduction, components and containers, Button, Label, Checkbox, Radio Buttons, List Boxes, Choice
Boxes, Container class, Layouts, Menu and Scrollbar.

OUTCOMES:
• Understand Java programming concepts and utilize Java Graphical User Interface in
Program writing.
• Write, compile, execute and troubleshoot Java programming for networking concepts.
• Build Java Application for distributed environment.
• Design and Develop multi-tier applications.
RCE III-ii 31
 JNTUK R16 ECE

• Identify and Analyze Enterprise applications.

TEXT BOOKS:
1. The complete Reference Java, 8th edition, Herbert Schildt, TMH.
2. Programming in JAVA, Sachin Malhotra, Saurabh Choudary, Oxford.
3. Introduction to java programming, 7th edition by Y Daniel Liang, Pearson.

REFERENCE BOOKS:
1. Swing: Introduction, JFrame, JApplet, JPanel, Componets in Swings, Layout Managers in
2. Swings, JList and JScrollPane, Split Pane, JTabbedPane, JTree, JTable, Dialog Box.

RCE III-ii 32