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This is why different descriptions exist for the hardware functionality. Complex systems
are often described by the behaviour that is observable from the outside. Abstract
behavioural models are used in this case that hide all the implementation details. In this
example the print protocol will be executed whenever a PRINTREQUEST occurs. This
can be either a pressed key or a software command, etc. The description of a basic logic
gate, on the other hand, may consist of only one boolean equation. This is a very short
and precise description.
The language VHDL covers the complete range of applications and can be used to model
(digital) hardware in a general way.
The most evident application is probably the development of a formal model of the
behaviour of a system. With formality, misunderstandings and misinterpretations can be
avoided. Because of the selfdocumenting character of VHDL, a VHDL model can even
serve as system documentation to a certain degree.
The big advantage of hardware description languages is the possibility to actually execute
the code. In principle, they are nothing else than a specialized programming language.
Coding errors of the formal model or conceptual errors of the system can be found by
running simulations. There, the response of the model on stimulation with different input
values can be observed and analysed.
During the development cycle the description has to become more and more precise until
it is actually possible to manufacture the product. The (automatic) transformation of a
less detailed description into a more elaborated one is called synthesis. Existing synthesis
tools are capable of mapping specific constructs of hardware description languages
directly to the standard components of integrated circuits. This way, a formal model of
the hardware system can be used from the early design studies to the final netlist.
Software support is available for the necessary refinement steps.