Dwi Putri Wahyuningsih

2019390004

Computer Architecture & Organization.

Intel x86 & ARM Instruction Set

1. Intel x86 Instruction Set

Instruction Operation Type Description

MOV Data Transfer - General • Move from source to
destination
• Source and destination have
the same size
• No immediate to segment
moves
PUSH Data Transfer - General The push instruction places its
operand onto the top of the
hardware supported stack in
memory
PUSHA Data Transfer - General Pushes the contents of the general-
purpose registers onto the stack.
POP Data Transfer - General • Pop a value from the stack
• Loads the value from the
top of the stack to the
location specified with the
destination operand and
then increments the stack
pointer.
POPA Data Transfer - General • Pop all registers off stack
• Pops from the stack into the
general-purpose registers.
XCHG • Exchange register/memory
with register
• Exchanges the contents of
the destination (first) and
source (second) operands.
XLAT Data Transfer - Address • Table look-up translation
Object • Locates a byte entry in a
table in memory, using the
contents of the AL register
as a table index, then copies
the contents of the table
entry back into the AL
register.
LEA Data Transfer - Address • Load effective address
Object • Used to put a memory
address into the destination.
LDS Data Transfer - Address • Load pointer into D
Object segment register
• Load far pointer
• Loads a far pointer
(segment selector and
offset) from the second
operand (source operand)
into a segment register and
the first operand
(destination operand).
LES Data Transfer - Address • Load pointer into E
Object segment register
• Load far pointer
 • Loads a far pointer
(segment selector and
offset) from the second
operand (source operand)
into a segment register and
the first operand
(destination operand).

LFS Data Transfer - Address • Load pointer into F

Object segment register
• Load far pointer
• Loads a far pointer
(segment selector and
offset) from the second
operand (source operand)
into a segment register and
the first operand
(destination operand).

LGS Data Transfer - Address • Load pointer into G

Object segment register
• Load far pointer
• Loads a far pointer
(segment selector and
offset) from the second
operand (source operand)
into a segment register and
the first operand
(destination operand).
LSS Data Transfer - Address • Load pointer into S (stack)
Object segment register
• Load far pointer
 • Loads a far pointer
(segment selector and
offset) from the second
operand (source operand)
into a segment register and
the first operand
(destination operand).
LAHF Data Transfer - Flag • Load A register from Flags
Manipulation • This instruction executes as
described above in
compatibility mode and
legacy mode.
SAHF Data Transfer - Flag Store A register in Flags
Manipulation
PUSHF Data Transfer - Flag • Push flags onto stack
Manipulation • Decrements the stack
pointer by 4 (if the current
operand-size attribute is 32)
and pushes the entire
contents
POPF Data Transfer - Flag • Pop flags off stack
Manipulation • Pops a doubleword
(POPFD) from the top of
the stack (if the current
operand-size attribute is 32)
PUSHFD Data Transfer - Flag • Push EFLAGS onto stack
Manipulation • Decrements the stack
pointer by 4 (if the current
operand-size attribute is 32)
 and pushes the entire
contents
POPFD Data Transfer - Flag • Pop EFLAGS off stack
Manipulation • Pops a doubleword
(POPFD) from the top of
the stack (if the current
operand-size attribute is 32)
CLC Data Transfer - Flag • Clear Carry Flag
Manipulation • Clears the CF flag in the
EFLAGS register.
CLD Data Transfer - Flag • Clear Direction Flag
Manipulation • Clears the DF flag in the
EFLAGS register. When
the DF flag is set to 0, string
operations increment the
index registers
CMC Data Transfer - Flag • Complement Carry Flag
Manipulation • Complements the CF flag
in the EFLAGS register.
CMC operation is the same
in non-64-bit modes and
64-bit mode.
STC Data Transfer - Flag • Set Carry Flag
Manipulation • Sets the CF flag in the
EFLAGS register.
Operation is the same in all
modes.
STD Data Transfer-Flag • Set Direction Flag
Manipulation • Sets the DF flag in the
EFLAGS register. When
 the DF flag is set to 1, string
operations decrement the
index registers (ESI and/or
EDI). Operation is the same
in all modes.
MOVSX Conversion • Move with sign-extension
• Copies the contents of the
source operand (register or
memory location) to the
destination operand
(register) and sign extends
the value to 16 or 32 bits
MOVZX Conversion • Move with zero-extend
• Copies the contents of the
source operand (register or
memory location) to the
destination operand
(register) and zero extends
the value to 16 or 32 bits.
CBW Conversion • Convert byte to word
• Double the size of the
source operand by means of
sign extension.
CWD Conversion Convert word to doubleword
CWDE Conversion Convert word to doubleword
extended.
CDQ Conversion Convert doubleword to quadword.
IN Input/output • Input operand from I/O
space
 • Copies the value from the
I/O port specified with the
second operand (source
operand) to the destination
operand (first operand).
OUT Input/output • Output operand to I/O
space
• Copies the value from the
second operand (source
operand) to the I/O port
specified with the
destination operand (first
operand).
ADD Arithmetic - Addition • Add operands
• Adds the first operand
(destination operand) and
the second operand (source
operand) and stores the
result in the destination
operand.
ADC Arithmetic - Addition • Add with carry
• Adds the destination
operand (first operand), the
source operand (second
operand), and the carry
(CF) flag and stores the
result in the destination
operand.
INC Arithmetic - Addition • Increment operand by 1
 • Adds 1 to the destination
operand, while preserving
the state of the CF flag.
AAA Arithmetic - Addition • ASCII adjusts for addition
• Adjusts the sum of two
unpacked BCD values to
create an unpacked BCD
result.
DAA Arithmetic - Addition • Decimal adjusts for
addition
• Adjusts the sum of two
packed BCD values to
create a packed BCD result.
SUB Arithmetic - Subtraction • Subtract operands
• Subtracts the second
operand (source operand)
from the first operand
(destination operand) and
stores the result in the
destination operand.
SBB Arithmetic - Subtraction • Subtract with borrow
• Adds the source operand
(second operand) and the
carry (CF) flag, and
subtracts the result from the
destination operand (first
operand).
DEC Arithmetic - Subtraction • Decrement operand by 1
• Subtracts 1 from the
destination operand, while
 preserving the state of the
CF flag.
NEG Arithmetic - Subtraction • Negate operand
• Replaces the value of
operand (the destination
operand) with its two's
complement. (This
operation is equivalent to
subtracting the operand
from 0.)
CMP Arithmetic - Subtraction • Compare operands
• Compares the first source
operand with the second
source operand and sets the
status flags in the EFLAGS
register according to the
results.
DAS Arithmetic - Subtraction • Decimal adjusts for
subtraction
• Adjusts the result of the
subtraction of two packed
BCD values to create a
packed BCD result.
AAS Arithmetic - Subtraction • ASCII adjusts for
subtraction
• Adjusts the result of the
subtraction of two
unpacked BCD values to
create a unpacked BCD
result.
MUL Arithmetic - Multiplication • Multiply Double/Single
Precision
• Performs an unsigned
multiplication of the first
operand (destination
operand) and the second
operand (source operand)
and stores the result in the
destination operand.
IMUL Arithmetic - Multiplication • Integer multiply
• Performs a signed
multiplication of two
operands.
AAM Arithmetic - Multiplication • ASCII adjust after
multiplying
• Adjusts the result of the
multiplication of two
unpacked BCD values to
create a pair of unpacked
(base 10) BCD values.
DIV Arithmetic - Division Divide unsigned
IDIV Arithmetic - Division • Integer Divide
• Signed Divide
AAD Arithmetic - Division • ASCII adjusts before
division
INS String • Input string from I/O space
• Copies the data from the
I/O port specified with the
source operand (second
 operand) to the destination
operand (first operand).
OUTS String • Output string to I/O space
• Copies data from the source
operand (second operand)
to the I/O port specified
with the destination
operand (first operand).
CMPS String • Compare String Operands
• Compares the byte, word,
doubleword, or quadword
specified with the first
source operand with the
byte, word, doubleword, or
quadword specified with
the second source operand
and sets the status flags in
the EFLAGS register
according to the results.
SCAS String • Scan String
• Compares the byte, word,
or double word specified
with the memory operand
with the value
LODS String • Load String
• Loads a byte, word, or
doubleword from the
source operand
STOS String Store String
REP String • Repeat
 • Repeats a string instruction
the number of times
specified in the count
register ((E)CX) or until the
indicated condition of the
ZF flag is no longer met.
REPE/REPZ String • Repeat while equal/zero
• Repeats execution of string
instructions and the Zero
Flag is set.
RENE/REPNZ String Repeat while not equal/not zero
NOT Logical – Logical Operations • “NOT” operands
• One's Complement
Negation
• Performs a bitwise NOT
operation (each 1 is set to 0,
and each 0 is set to 1) on the
destination operand and
stores the result in the
destination operand
location.
AND Logical – Logical Operations • “AND” operands
• Performs a bitwise AND
operation on the destination
(first) and source (second)
operands and stores the
result in the destination
operand location.
OR Logical – Logical Operations • “Inclusive OR” operands
• Logical Inclusive OR
 • Performs a bitwise
inclusive OR operation
between the destination
(first) and source (second)
operands and stores the
result in the destination
operand location.
XOR Logical – Logical Operations • “Exclusive OR” operands
• Performs a bitwise
exclusive OR (XOR)
operation on the destination
(first) and source (second)
operands and stores the
result in the destination
operand location.
TEST Logical – Logical Operations • “Test” operands
• Computes the bit-wise
logical AND of first
operand (source 1 operand)
and the second operand
(source 2 operand)
SHL/SHR Logical – Shifts • Shift logical left or right
• Shifts the bits in the first
operand (destination
operand) to the left or right
by the number of bits
specified in the second
operand (count operand).
SAL/SAR Logical – Shifts • Shift arithmetic left or right
 • Shifts the bits in the first
operand (destination
operand) to the left or right
by the number of bits
specified in the second
operand (count operand).
SHLD/SHRD Logical – Shifts • Double shift left or right
• Double Precision Shift
• SHLD shifts dest to the left
count times and the bit
positions opened are filled
with the most significant
bits
ROL/ROR Logical – Rotates • Rotate left/right
• Shifts (rotates) the bits of
the first operand
(destination operand) the
number of bit positions
specified in the second
operand (count operand)
and stores the result in the
destination operand.
RCL/RCR Logical – Rotates • Rotate through carry
left/right
• Shifts (rotates) the bits of
the first operand
(destination operand) the
number of bit positions
specified in the second
operand (count operand)
 and stores the result in the
destination operand.
BT Bit Manipulation • Bit Test
• Selects the bit in a bit string
(specified with the first
operand, called the bit base)
at the bit-position
designated by the bit offset
(specified by the second
operand) and stores the
value of the bit
BTS Bit Manipulation • Bit Test and Set
• Selects the bit in a bit string
(specified with the first
operand, called the bit base)
at the bit-position
designated by the bit offset
operand (second operand),
stores the value of the bit
and sets the selected bit in
the bit string to 1.
BTR Bit Manipulation • Bit Test and Reset
• Selects the bit in a bit string
(specified with the first
operand, called the bit base)
at the bit-position
designated by the bit offset
operand (second operand),
stores the value of the bit
 and clears the selected bit in
the bit string to 0.
BTC Bit Manipulation • Bit Test and Complement
• Selects the bit in a bit string
(specified with the first
operand, called the bit base)
at the bit-position
designated by the bit offset
operand (second operand),
stores the value of the bit
and complements the
selected bit in the bit string.
BSF Bit Manipulation • Bit Scan Forward
• Searches the source
operand (second operand)
for the least significant set
bit (1 bit).
BSR Bit Manipulation • Bit Scan Reverse
• Searches the source
operand (second operand)
for the most significant set
bit (1 bit).
SETCC Program Control – • Set byte equal to condition
Conditional Transfers code
• Sets the destination operand
to 0 or 1 depending on the
settings of the status flags
JA/JNBE Program Control – Jump if above/not below nor equal
Conditional Transfers
JAE/JNB Program Control – Jump if above or equal/not below
Conditional Transfers
JB/JNAE Program Control – Jump if below/not above nor equal
Conditional Transfers
JBE/JNA Program Control – Jump if below or equal/not above
Conditional Transfers
JC Program Control – Jump if carry
Conditional Transfers
JE/JZ Program Control – Jump if equal/zero
Conditional Transfers
JG/JNLE Program Control – Jump if grater/not less nor equal
Conditional Transfers
JGE/JNL Program Control – Jump if greater or equal/not less
Conditional Transfers
JL/JNGE Program Control – Jump if less/not greater nor equal
Conditional Transfers
JLE/JNG Program Control – Jump if less or equal/not greater
Conditional Transfers
JNC Program Control – Jump if not carry
Conditional Transfers
JNE/JNZ Program Control – Jump if not equal/not zero
Conditional Transfers
JNO Program Control – Jump if not overflow
Conditional Transfers
JNP/JPO Program Control – Jump if not parity/parity odd
Conditional Transfers
JNS Program Control – Jump if not sign
Conditional Transfers
JO Program Control – Jump if overflow
Conditional Transfers
 JP/JPE Program Control –
Conditional Transfers
JS Program Control – Jump if Sign
Conditional Transfers
CALL Program Control –
Unconditional Transfers
RET Program Control –
Unconditional Transfers
JMP Program Control –
Unconditional Transfers
LOOP Program Control – Iteration
Control
LOOPE/LOOPZ Program Control – Iteration
Control
LOOPNE/LOOPNZ Program Control – Iteration
Control
Jump if parity/parity even
• Call procedure/task
• Saves procedure linking
information on the stack
and branches to the
procedure (called
procedure) specified with
the destination (target)
operand.
• Return from procedure
• Transfers program control
to a return address located
on the top of the stack.
• Jump
• Transfers program control
to a different point in the
instruction stream without
recording return
information.
• Loop
• Performs a loop operation
• Loop if equal/zero
• Loop decrements the count
register; the flags register
remains unchanged.
• Loop if not equal/zero
 • Loop decrements the count
register; the flags register
remains unchanged.
JCXZ Program Control – Iteration • Jump if register CXe0
Control • The JCXZ instruction tests
the contents of the CX or
ECX register for 0.
INT Program Control – Interrupts • Interrupt
• Generates a call to the
interrupt or exception
handler specified with the
destination operand
INTO Program Control – Interrupts • Interrupt if overflow
• Generates a call to the
interrupt or exception
handler specified with the
destination operand
IRET Program Control – Interrupts • Return from Interrupt/Task
• Returns program control
from an exception or
interrupt handler to a
program or procedure that
was interrupted by an
exception, an external
interrupt, or a software-
generated interrupt.
CLI Program Control – Interrupts • Clear Interrupt Enable
• If protected-mode virtual
interrupts are not enabled,
STI Program Control – Interrupts • Set Interrupt Enable
 • If protected-mode virtual
interrupts are not enabled
BOUND High Level Language • Check Array Bounds
• BOUND determines if the
first operand (array index)
is within the bounds of an
array specified the second
operand (bounds operand).
ENTER High Level Language • Setup Parameter Block for
Entering Procedure
• Creates a stack frame
(comprising of space for
dynamic storage and 1-32
frame pointer storage) for a
procedure.
LEAVE High Level Language • Leave Procedure
• Releases the stack frame set
up by an earlier ENTER
instruction.
SGDT Protection Model • Store Global Descriptor
Table
• Stores the content of the
global descriptor table
register (GDTR) in the
destination operand.
SIDT Protection Model • Store Interrupt Descriptor
Table
• Stores the content the
interrupt descriptor table
 register (IDTR) in the
destination operand.
STR Protection Model • Store Task Register
• Stores the segment selector
from the task register (TR)
in the destination operand.
SLDT Protection Model • Store Local Descriptor
Table
• Stores the segment selector
from the local descriptor
table register (LDTR) in the
destination operand.
LGDT Protection Model • Load Global Descriptor
Table
• Loads the values in the
source operand into the
global descriptor table
register (GDTR) or the
interrupt descriptor table
register (IDTR).
LIDT Protection Model • Load Interrupt Descriptor
Table
• Loads the values in the
source operand into the
global descriptor table
register (GDTR) or the
interrupt descriptor table
register (IDTR).
LTR Protection Model • Load Task Register
 • Loads the source operand
into the segment selector
field of the task register.
LLDT Protection Model • Load Local descriptor
Table
• Loads the source operand
into the segment selector
field of the local descriptor
table register (LDTR).
ARPL Protection Model • Adjust Requested Privilege
Level
• Compares the RPL fields of
two segment selectors.
LAR Protection Model • Load Access Rights
• Loads the access rights
from the segment descriptor
specified by the second
operand (source operand)
into the first operand
(destination operand)
LSL Protection Model • Load Segment Limit
• Loads the unscrambled
segment limit from the
segment descriptor
specified with the second
operand (source operand)
into the first operand
(destination operand)
VERR/VERW Protection Model Verify Segment for Reading or
Writing
LMSW Protection Model • Load Machine Status Word
• Loads the source operand
into the machine status
word,
SMSW Protection Model • Store Machine Status Word
• Stores the machine status
word (bits 0 through 15 of
control register CR0) into
the destination operand.
HLT Processor Control • Halt
• Stops instruction execution
and places the processor in
a HALT state.
WAIT Processor Control • Wait until BUSY negated
• Causes the processor to
check for and handle
pending, unmasked,
floating-point exceptions
before proceeding.
ESC Processor Control • Escape
• This Instruction uses for
Link with External
Coprocessors
LOCK Processor Control • Lock Bus
• Causes the processor’s
LOCK# signal to be
asserted during execution
of the accompanying
instruction (turns the
 instruction into an atomic
instruction).

2. ARM Instruction Set

Instruction Operation Type Description
LA Load and Store • Load Address
• Loads the destination
register with the effective
32-bit address of the
specified data item.
DLA Load and Store • Load Doubleword
Address
• Loads the destination
register with the effective
64-bit address of the
specified data item
(MIPS3 and above only).
LB Load and Store • Load Byte
• Loads the least-
significant byte of the
destination register with
the contents of the byte
that is at the memory
location specified by the
effective address.
LBU Load and Store • Load Byte Unsigned
• Loads the least-
significant byte of the
destination register with
the contents of the byte
 that is at the memory
location specified by the
effective address
LH Load and Store • Load Halfword (LH)
• Loads the two least-
significant bytes of the
destination register with
the contents of the
halfword that is at the
memory location
specified by the effective
address.
LHU Load and Store • Load Halfword Unsigned
• Loads the least-
significant bits of the
destination register with
the contents of the
halfword that is at the
memory location
specified by the effective
address.
LL Load and Store • Load Linked
• Loads the destination
register with the contents
of the word that is at the
memory location
• This instruction is not
valid in the MIPS1
architectures.
LW Load and Store • Load Word
 • Loads the destination
register with the contents
of the word that is at the
memory location.
LWL Load and Store • Load Word Left
• Loads the sign; that is,
Load Word Left loads the
destination register with
the most-significant bytes
of the word specified by
the effective address.
LWR Load and Store • Load Word Right
• Loads the lowest
precision bytes; that is,
Load Word Right loads
the destination register
with the least-significant
bytes of the word
specified by the effective
address.
LD Load and Store • Load Doubleword (LD)
• LD is a machine
instruction in the MIPS3
architecture.
• This is retained for use
with the -mips1 and -
mips2 options to provide
backward compatibility
only.
ULH Load and Store • Unaligned Load
Halfword
• Loads a halfword into the
destination register from
the specified address and
extends the sign of the
halfword. Unaligned
Load Halfword loads a
halfword regardless of the
halfword's alignment in
memory.
ULHU Load and Store • Unaligned Load
Halfword Unsigned
• Loads a halfword into the
destination register from
the specified address and
zero extends the
halfword. Unaligned
Load Halfword Unsigned
loads a halfword
regardless of the
halfword's alignment in
memory.
ULW Load and Store • Unaligned Load Word
• Loads a word into the
destination register from
the specified address.
Unaligned Load Word
loads a word regardless of
 the word's alignment in
memory.
LI Load and Store • Load Immediate
• Loads the destination
register with the 32-bit
value of an expression
that can be computed at
assembly time.
• Note: Load Immediate
can generate any efficient
code sequence to put a
desired value in the
register.
DLI Load and Store • Load Doubleword
Immediate
• Loads the destination
register with the 64-bit
value of an expression
that can be computed at
assembly time.
• Note: Load Immediate
can generate any efficient
code sequence to put a
desired value in the
register (MIPS3 and
above only).
SDR Load and Store • Store Doubleword Right
• Stores the least-
significant bytes of a
doubleword in the
 memory location
specified by the effective
address. It alters only the
doubleword in memory
which contains the byte
indicated by the effective
address.
USD Load and Store • Unaligned Store
Doubleword
• Stores the contents of the
source register in a
doubleword specified by
the address. The machine
does not require
alignment for the storage
address.
LUI Load and Store • Load Upper Immediate
• Loads the most-
significant half of a
register with the
expression's value. The
system fills the least-
significant half of the
register with zeros. The
expression's value must
be in the range
SB Load and Store • Store Byte
• Stores the contents of the
source register's least-
significant byte in the
 byte specified by the
effective address.
SC Load and Store • Store Conditional
• Stores the contents of a
word from the source
register into the memory
location specified by the
effective address.
• This instruction is not
valid in the MIPS1
architectures.
SD Load and Store • Store Doubleword
• SD is a machine
instruction in the MIPS3
architecture.
• Note: This is retained for
use with the -mips1 and -
mips2 options to provide
backward compatibility
only.
SH Load and Store • Store Halfword
• Stores the two least-
significant bytes of the
source register in the
halfword that is at the
memory location
specified by the effective
address. The effective
address must be divisible
by two; otherwise the
 machine signals an
address error exception.
SWL Load and Store • Store Word Left
• Stores the most-
significant bytes of a
word in the memory
location specified by the
effective address.
SWR Load and Store • Store Word Right
• Stores the least-
significant bytes of a
word in the memory
location specified by the
effective address.
SW Load and Store • Store Word
• Stores the contents of a
word from the source
register in the memory
location specified by the
effective address.
USH Load and Store • Unaligned Store
Halfword
• Stores the contents of the
two least-significant
bytes of the source
register in a halfword that
the address specifies. The
machine does not require
alignment for the storage
address.
USW Load and Store • Unaligned Store Word
• Stores the contents of the
source register in a word
specified by the address.
The machine does not
require alignment for the
storage address.
LD Load and Store • Load Doubleword
• Loads the destination
register with the contents
of the doubleword that is
at the memory location.
LLD Load and Store • Load Linked Doubleword
• Loads the destination
register with the contents
of the doubleword that is
currently in the memory
location.
LWU Load and Store • Load Word Unsigned
• Loads the least-
significant bits of the
destination register with
the contents of the word
(32 bits) that is at the
memory location
specified by the effective
address.
LDL Load and Store • Load Doubleword Left
• Loads the destination
register with the most-
 significant bytes of the
doubleword specified by
the effective address.
LDR Load and Store • Load Doubleword Right
• Loads the destination
register with the least-
significant bytes of the
doubleword specified by
the effective address.
ULD Load and Store • Unaligned Load
Doubleword
• Loads a doubleword into
the destination register
from the specified
address. ULD loads a
doubleword regardless of
the doubleword's
alignment in memory.
SD Load and Store • Store Doubleword
• Stores the contents of a
doubleword from the
source register in the
memory location
specified by the effective
address. The effective
address must be divisible
by eight, otherwise the
machine signals an
address error exception.
SCD Load and Store • Store Conditional
Doubleword
• Stores the contents of a
doubleword from the
source register into the
memory locations
specified by the effective
address.
SDL Load and Store • Store Doubleword Left
• Stores the most-
significant bytes of a
doubleword in the
memory location
specified by the effective
address. It alters only the
doubleword in memory
which contains the byte
indicated by the effective
address.
ABS Computational • Absolute Value
(arithmetic, logical, • Computes the absolute
shift, multiply, divide) value of the contents of
src1 and puts the result in
the destination register.
ADD Computational (arithmetic, • Add with Overflow
logical, shift, multiply, divide) • Computes the twos-
complement sum of two
signed values.
ADDU Computational (arithmetic, • Add without Overflow
logical, shift, multiply, divide)
 • Computes the twos-
complement sum of two
32-bit values.
AND Computational (arithmetic, Computes the Logical AND of
logical, shift, multiply, divide) two values.
DIV Computational (arithmetic, • Divide Signed
logical, shift, multiply, divide) • Computes the quotient of
two values.
• The special case DIV
generates the real
machine divide
instruction and leaves the
result in the HI/LO
register.
DIVU Computational (arithmetic, • Divide Unsigned
logical, shift, multiply, divide) • Computes the quotient of
two unsigned 32-bit
values.
XOR Computational (arithmetic, • Exclusive-OR
logical, shift, multiply, divide) • Computes the XOR of
two values.
MOVE Computational (arithmetic, Moves the contents of src1 to the
logical, shift, multiply, divide) destination register.
MOVN Computational (arithmetic, • Move Conditional on Not
logical, shift, multiply, divide) Zero
• Conditionally moves the
contents of src1 to the
destination register after
testing that src2 is not
 equal to zero (MIPS4
only.)
MOVZ Computational (arithmetic, • Move Conditional on
logical, shift, multiply, divide) Zero
• Conditionally moves the
contents of src1 to the
destination register after
testing that src2 is equal
to zero (MIPS4 only).
MUL Computational (arithmetic, • Multiply
logical, shift, multiply, divide) • Computes the product of
two values. This
instruction puts the 32-bit
product of src1 and src2,
or the 32-bit product of
src1 and the immediate
value, in the destination
register. The machine
does not report overflow.
• Use MUL when you do
not need overflow
protection: it's often faster
than MULO and
MULOU. For
multiplication by a
constant, the MUL
instruction produces
faster machine instruction
sequences than MULT or
MULTU instructions can
produce.
MULT Computational (arithmetic, • Multiply
logical, shift, multiply, divide) • Computes the 64-bit
product of two 32-bit
signed values. This
instruction multiplies the
contents of src1 by the
contents of src2 and puts
the result in the HI and
LO registers (see Chapter
1). No overflow is
possible.
• Note: The MULT
instruction is a real
machine language
instruction.
MULTU Computational (arithmetic, • Multiply Unsigned
logical, shift, multiply, divide) • Computes the product of
two unsigned 32-bit
values. It multiplies the
contents of src1 and the
contents of src2 and puts
the result in the HI and
LO registers (see Chapter
1). No overflow is
possible.
• Note: The MULTU
instruction is a real
machine language
instruction.
MULO Computational (arithmetic, • Multiply with Overflow
logical, shift, multiply, divide) • Computes the product of
two 32-bit signed values.
• Note: For multiplication
by a constant, MULO
produces faster machine
instruction sequences
than MULT or MULTU
can produce; however, if
you do not need overflow
detection, use the MUL
instruction. It's often
faster than MULO.
MULOU Computational (arithmetic, • Multiply with Overflow
logical, shift, multiply, divide) Unsigned
• Computes the product of
two 32-bit unsigned
values.
• Note: For multiplication
by a constant, MULOU
produces faster machine
instruction sequences
than MULT or MULTU
can reproduce; however,
if you do not need
overflow detection, use
the MUL instruction. It's
often faster than
MULOU.
NEG Computational (arithmetic, • Negate with Overflow
logical, shift, multiply, divide) • Computes the negative of
a value. This instruction
negates the contents of
src1 and puts the result in
the destination register.
NEGU Computational (arithmetic, • Negate without Overflow
logical, shift, multiply, divide) • Negates the integer
contents of src1 and puts
the result in the
destination register. The
machine does not report
overflows.
NOT Computational (arithmetic, Computes the Logical NOT of a
logical, shift, multiply, divide) value. This instruction
complements (bitwise) the
contents of src1 and puts the
result in the destination register.
NOR Computational (arithmetic, • NOT OR
logical, shift, multiply, divide) • Computes the NOT OR of
two values. This
instruction combines the
contents of src1 with the
contents of src2 (or the
immediate value). NOT
OR complements the
result and puts it in the
destination register.
OR Computational (arithmetic, Computes the Logical OR of two
logical, shift, multiply, divide) values.
REM Computational (arithmetic,
logical, shift, multiply, divide)
REMU Computational (arithmetic,
logical, shift, multiply, divide)
ROL Computational (arithmetic,
logical, shift, multiply, divide)
ROR Computational (arithmetic,
logical, shift, multiply, divide)
SEQ Computational (arithmetic,
logical, shift, multiply, divide)
SGT Computational (arithmetic,
logical, shift, multiply, divide)
SGE Computational (arithmetic,
logical, shift, multiply, divide)
SGEU Computational (arithmetic,
logical, shift, multiply, divide)
• Remainder Signed
• Computes the remainder
of the division of two
unsigned 32-bit values.
• Remainder Unsigned
• Computes the remainder
of the division of two
unsigned 32-bit values.
• Rotate Left
• Rotates the contents of a
register left (toward the
sign bit).
• Rotate Right
• Rotates the contents of a
register right (toward the
least-significant bit).
• Set Equal
• Compares two 32-bit
values.
• Set Greater Than
• Compares two signed 32-
bit values.
• Set Greater/Equal
• Compares two signed 32-
bit values.
• Set Greater/Equal
Unsigned
• Compares two unsigned
32-bit values.
SGTU Computational (arithmetic, • Set Greater Than
logical, shift, multiply, divide) Unsigned
• Compares two unsigned
32-bit values.
SLT Computational (arithmetic, • Set Less Than
logical, shift, multiply, divide) • Compares two signed 32-
bit values.
SLE Computational (arithmetic, • Set Less/Equal
logical, shift, multiply, divide) • Compares two signed 32-
bit values.
SLEU Computational (arithmetic, • Set Less/Equal Unsigned
logical, shift, multiply, divide) • Compares two unsigned
32-bit values.
SLTU Computational (arithmetic, • Set Less Than Unsigned
logical, shift, multiply, divide) • Compares two unsigned
32-bit values.
SNE Computational (arithmetic, • Set Not Equal
logical, shift, multiply, divide) • Compares two 32-bit
values. If the contents of
scr1 do not equal the
contents of src2 (or src1
does not equal the
immediate value), this
instruction sets the
destination register to
one; otherwise, it sets the
destination register to
zero.
SLL Computational (arithmetic, • Shift Left Logical
logical, shift, multiply, divide)

SRA Computational (arithmetic,
logical, shift, multiply, divide)
SRL Computational (arithmetic,
logical, shift, multiply, divide)
SUB Computational (arithmetic,
logical, shift, multiply, divide)
SUBU Computational (arithmetic,
logical, shift, multiply, divide)
• Shifts the contents of a
register left (toward the
sign bit) and inserts zeros
at the least-significant bit.
• Shift Right Arithmetic
• Shifts the contents of a
register right (toward the
least-significant bit) and
inserts the sign bit at the
most-significant bit.
• Shift Right Logical
• Shifts the contents of a
register right (toward the
least-significant bit) and
inserts zeros at the most-
significant bit.
• Subtract with Overflow
• Computes the twos-
complement difference
for two signed values.
This instruction subtracts
the contents of src2 from
the contents of src1, or it
can subtract the contents
of the immediate from the
src1 value.
• Subtract without
Overflow
 • Computes the twos-
complement difference
for two 32-bit values.
TEQ Computational (arithmetic, • Trap if Equal
logical, shift, multiply, divide) • Compares two 32-bit
values. If the contents of
src1 equal the contents of
src2 (or src1 equals the
immediate value), a trap
exception occurs.
TNE Computational (arithmetic, • Trap if Not Equal
logical, shift, multiply, divide) • Compares two 32-bit
values. If the contents of
src1 do not equal the
contents of src2 (or src1
does not equal the
immediate value), a trap
exception occurs.
TLT Computational (arithmetic, • Trap if Less Than
logical, shift, multiply, divide) • Compares two signed 32-
bit values. If the contents
of src1 are less than the
contents of src2 (or src1 is
less than the immediate
value), a trap exception
occurs.
TLTU Computational (arithmetic, • Trap if Less Than
logical, shift, multiply, divide) Unsigned
• Compares two unsigned
32-bit values. If the

TGE Computational (arithmetic,
logical, shift, multiply, divide)
TGEU Computational (arithmetic,
logical, shift, multiply, divide)
DABS Computational (arithmetic,
logical, shift, multiply, divide)
contents of src1 are less
than the contents of src2
(or src1 is less than the
immediate value), a trap
exception occurs.
• Trap if Greater than or
Equal
• Compares two signed 32-
bit values. If the contents
of src1 are greater than
the contents of src2 (or
src1 is greater than the
immediate value), a trap
exception occurs.
• Trap if Greater than or
Equal Unsigned
• Compares two unsigned
32-bit values. If the
contents of src1 are
greater than the contents
of src2 (or src1 is greater
than the immediate
value), a trap exception
occurs.
• Doubleword Absolute
Value
• Computes the absolute
value of the contents of
src1, treated as a 64-bit
signed value, and puts the
 result in the destination
register. If the value in
src1 is the machine
signals an overflow
exception.
DADD Computational (arithmetic, • Doubleword Add with
logical, shift, multiply, divide) Overflow
• Computes the twos-
complement sum of two
64-bit signed values.
DADDU Computational (arithmetic, • Doubleword Add without
logical, shift, multiply, divide) Overflow
• Computes the twos-
complement sum of two
64-bit values. The
instruction adds the
contents of src1 to the
contents of src2, or it can
add the contents of src1 to
the immediate value.
Overflow exceptions
never occur.
DDIV Computational (arithmetic, • Doubleword Divide
logical, shift, multiply, divide) Signed
• Computes the quotient of
two 64-bit values.
• The special case DDIV
generates the real
doubleword divide
instruction and leaves the
 result in the HI/LO
register. The HI register
contains the quotient. No
checking for divide-by-
zero is performed
DDIVU Computational (arithmetic, • Doubleword Divide
logical, shift, multiply, divide) Unsigned
• Computes the quotient of
two unsigned 64-bit
values.
DMUL Computational (arithmetic, • Doubleword Multiply
logical, shift, multiply, divide) • Computes the product of
two values. This
instruction puts the 64-bit
product of src1 and src2,
or the 64-bit product of
src1 and the immediate
value, in the destination
register. Overflow is not
reported.
• Note: Use DMUL when
you do not need overflow
protection. It is often
faster than DMULO and
DMULOU. For
multiplication by a
constant, the DMUL
instruction produces
faster machine instruction
sequences than DMULT
 or DMULTU can
produce.
DMULT Computational (arithmetic, • Doubleword Multiply
logical, shift, multiply, divide) • Computes the 128-bit
product of two 64-bit
signed values.
• Note: The DMULT
instruction is a real
machine language
instruction.
DMULTU Computational (arithmetic, • Doubleword Multiply
logical, shift, multiply, divide) Unsigned
• Computes the product of
two unsigned 64-bit
values. It multiplies the
contents of src1 and the
contents of src2, putting
the result in the HI and
LO registers. No
overflow is possible.
• Note: The DMULTU
instruction is a real
machine language
instruction.
DMULO Computational (arithmetic, • Doubleword Multiply
logical, shift, multiply, divide) with Overflow
• Computes the product of
two 64-bit signed values.
• Note: For multiplication
by a constant, DMULO
 produces faster machine
instruction sequences
than DMULT or
DMULTU can produce;
however, if you do not
need overflow detection,
use the DMUL
instruction. It is often
faster than DMULO.
DMULOU Computational (arithmetic, • Doubleword Multiply
logical, shift, multiply, divide) with Overflow Unsigned
• Computes the product of
two 64-bit unsigned
values.
• Note: For multiplication
by a constant, DMULO
produces faster machine
instruction sequences
than DMULT or
DMULTU can produce;
however, if you do not
need overflow detection,
use the DMUL
instruction. It is often
faster than DMULO.
DNEG Computational (arithmetic, • Doubleword Negate with
logical, shift, multiply, divide) Overflow
• Computes the negative of
a 64-bit value. The
instruction negates the
contents of src1 and puts
 the result in the
destination register. If the
value of src1 is -2**63,
the system signals an
overflow exception.
DNEGU Computational (arithmetic, • Doubleword Negate
logical, shift, multiply, divide) without Overflow
• Negates the 64-bit
contents of src1 and puts
the result in the
destination register.
Overflow is not reported.
DREM Computational (arithmetic, • Doubleword Remainder
logical, shift, multiply, divide) Signed
• Computes the remainder
of the division of two
signed 64-bit values.
DREMU Computational (arithmetic, • Doubleword Remainder
logical, shift, multiply, divide) Unsigned
• Computes the remainder
of the division of two
unsigned 64-bit values.
DROL Computational (arithmetic, • Doubleword Rotate Left
logical, shift, multiply, divide) • Rotates the contents of a
64-bit register left
(towards the sign bit).
DROR Computational (arithmetic, • Doubleword Rotate Right
logical, shift, multiply, divide) • Rotates the contents of a
63-bit register right
 (towards the least-
significant bit).
DSLL Computational (arithmetic, • Doubleword Shift Left
logical, shift, multiply, divide) Logical
• Shifts the contents of a
64-bit register left
(towards the sign bit) and
inserts zeros at the least-
significant bit.
DSRA Computational (arithmetic, • Doubleword Shift Right
logical, shift, multiply, divide) Arithmetic
• Shifts the contents of a
64-bit register right
(towards the least-
significant bit) and inserts
the sign bit at the most-
significant bit.
DSRL Computational (arithmetic, • Doubleword Shift Right
logical, shift, multiply, divide) Logical
• Shifts the contents of a
64-bit register right
(towards the least-
significant bit) and inserts
zeros at the most-
significant bit.
DSUB Computational (arithmetic, • Doubleword Subtract
logical, shift, multiply, divide) with Overflow
• Computes the twos-
complement difference
 for two signed 64-bit
values.
DSUBU Computational (arithmetic, • Doubleword Subtract
logical, shift, multiply, divide) without Overflow
• Computes the twos
complement difference
for two unsigned 64-bit
values.
B Jump and Branch • Branch
• Branches unconditionally
to the specified label.
BAL Jump and Branch • Branch and Link
• Branches unconditionally
to the specified label and
puts the return address in
general register
BEQ Jump and Branch • Branch on Equal
• Branches to the specified
label when the contents of
src1 equal the contents of
src2, or when the contents
of src1 equal the
immediate value.
BEQZ Jump and Branch • Branch on Equal to Zero
• Branches to the specified
label when the contents of
src1 equal zero.
BGT Jump and Branch • Branch on Greater Than
• Branches to the specified
label when the contents of
 src1 are greater than the
contents of src2, or it can
branch when the contents
of src1 are greater than
the immediate value. The
comparison treats the
comparands as signed 32-
bit values.
BGEU Jump and Branch • Branch on Greater/Equal
Unsigned
• Branches to the specified
label when the contents of
src1 are greater than or
equal to the contents of
src2, or it can branch
when the contents of src1
are greater than or equal
to the immediate value.
BGEZ Jump and Branch • Branch on Greater/Equal
Zero
• Branches to the specified
label when the contents of
src1 are greater than or
equal to zero.
BGEZAL Jump and Branch • Branch on Greater/Equal
Zero and Link
• Branches to the specified
label when the contents of
src1 are greater than or
equal to zero and puts the
 return address in general
register
BGE Jump and Branch • Branch on Greater or
Equal
• Branches to the specified
label when the contents of
src1 are greater than or
equal to the contents of
src2, or it can branch
when the contents of src1
are greater than or equal
to the immediate value.
BGTU Jump and Branch • Branch on Greater Than
Unsigned
• Branches to the specified
label when the contents of
src1 are greater than the
contents of src2, or it can
branch when the contents
of src1 are greater than
the immediate value.
BGTZ Jump and Branch • Branch on Greater Than
Zero
• Branches to the specified
label when the contents of
src1 are greater than zero.
BLTZ Jump and Branch • Branch on Less Than
Zero
• Branches to the specified
label when the contents of
 src1 are less than zero.
The program must define
the destination.
BLT Jump and Branch • Branch on Less Than
• Branches to the specified
label when the contents of
src1 are less than the
contents of src2, or it can
branch when the contents
of src1 are less than the
immediate value. The
comparison treats the
comparands as signed 32-
bit values.
BLEU Jump and Branch • Branch on Less/Equal
Unsigned
• Branches to the specified
label when the contents of
src1 are less than or equal
to the contents of src2, or
it can branch when the
contents of src1 are less
than or equal to the
immediate value.
BLEZ Jump and Branch • Branch on Less/Equal
Zero
• Branches to the specified
label when the contents of
src1 are less than or equal
to zero. The program
 must define the
destination.
BLE Jump and Branch • Branch on Less or Equal
• Branches to the specified
label when the contents of
src1 are less than or equal
to the contents of src2, or
it can branch when the
contents of src1 are less
than or equal to the
immediate value.
BLTU Jump and Branch • Branch on Less Than
Unsigned
• Branches to the specified
label when the contents of
src1 are less than the
contents of src2, or it can
branch when the contents
of src1 are less than the
immediate value.
BLTZAL Jump and Branch • Branch on Less Than
Zero and Link
• Branches to the specified
label when the contents of
src1 are less than zero and
puts the return address in
general register
BNE Jump and Branch • Branch on Not Equal
• Branches to the specified
label when the contents of
 src1 do not equal the
contents of src2, or it can
branch when the contents
of src1 do not equal the
immediate value.
BNEZ Jump and Branch • Branch on Not Equal to
Zero
• Branches to the specified
label when the contents of
src1 do not equal zero.
J Jump and Branch • Jump
• Unconditionally jumps to
a specified location. A
symbolic address or a
general register specifies
the destination. The
instruction J $31 returns
from a JAL call
instruction.
JAL Jump and Branch • Jump and Link
• Unconditionally jumps to
a specified location and
puts the return address in
a general register.
Branch Likely Jump and Branch • Branch Likely
Instructions
• Same the ordinary branch
instruction (without the
"Likely"), except in a
branch likely instruction,
 the instruction in the
delay slot is nullified if
the conditional branch is
not taken.
• Note: The branch likely
instructions should be
used only inside a. set no
reorder schedule in an
assembly program. The
assembler does not
attempt to schedule the
delay slot of a branch
likely instruction
BCzT Coprocessor Interface • Branch Coprocessor z
True
• Branches to the specified
label when the specified
coprocessor asserts a true
condition. The z selects
one of the coprocessors.
A previous coprocessor
operation sets the
condition.
BCzF Coprocessor Interface • Branch Coprocessor z
False
• Branches to the specified
label when the specified
coprocessor asserts a
false condition. The z
selects one of the
coprocessors. A previous
 coprocessor operation
sets the condition.
BCzTL Coprocessor Interface • Branch Coprocessor z
True Likely
• Branches to the specified
label when the specified
coprocessor asserts a true
condition. If the
conditional branch is not
taken, the instruction in
the branch delay slot is
nullified.
• Note: The branch likely
instructions should be
used only within a. set no
reorder block. The
assembler does not
attempt to schedule the
delay slot of a branch
likely instruction.
BCzFL Coprocessor Interface • Branch Coprocessor z
False Likely
• Branches to the specified
label when the specified
coprocessor asserts a
false condition. If the
conditional branch is not
taken, the instruction in
the branch delay slot is
nullified.
 • Note: The branch likely
instructions should be
used only within a. set no
reorder block. The
assembler does not
attempt to schedule the
delay slot of a branch
likely instruction.
CFCz Coprocessor Interface • Control from
Coprocessor z
• Stores the contents of the
coprocessor control
register specified by the
source in the general
register specified by dest-
gpr.
CTCz Coprocessor Interface • Control to Coprocessor
• Stores the contents of the
general register specified
by src-gpr in the
coprocessor control
register specified by the
destination.
Cz Coprocessor Interface • Coprocessor z Operation
• Executes a coprocessor-
specific operation on the
specified coprocessor.
The z selects one of four
distinct coprocessors.
LWCz Coprocessor Interface • Load Word Coprocessor
z
• Loads the destination
with the contents of a
word that is at the
memory location
specified by the effective
address.
LDCz Coprocessor Interface • Load Double
Coprocessor z
• Loads a doubleword from
the memory location
specified by the effective
address and makes the
data available to
coprocessor unit z.
MFCz Coprocessor Interface • Move from Coprocessor z
• Stores the contents of the
coprocessor register
specified by the source in
the general register
specified by dest-gpr.
MTCz Coprocessor Interface • Move to Coprocessor z
• Stores the contents of the
general register specified
by src-gpr in the
coprocessor register
specified by the
destination.
DMFCz Coprocessor Interface • Doubleword Move from
Coprocessor z
• Stores the 64-bit contents
of the coprocessor
register specified by the
source into the general
register specified by dest-
gpr.
DMTCz Coprocessor Interface • Doubleword Move to
Coprocessor z
• Stores the 64-bit contents
of the general register src-
gpr into the coprocessor
register specified by the
destination.
SWCz Coprocessor Interface • Store Word Coprocessor
z
• Stores the contents of the
coprocessor register in
the memory location
specified by the effective
address.
SDCz Coprocessor Interface • Store Double
Coprocessor z
• Coprocessor z sources a
doubleword, which the
processor writes the
memory location
specified by the effective
address.
BREAK Special • Break
• Unconditionally transfers
control to the exception
handler.
ERET Special • Exception Return
• Returns from an interrupt,
exception or error trap.
Similar to a branch or
jump instruction, ERET
executes the next
instruction before taking
effect. Use this on R4000
processor machines in
place of RFE.
MFHI Special • Move from HI Register
• Moves the contents of the
HI register to a general-
purpose register.
MFLO Special • Move from LO Register
• Moves the contents of the
LO register to a general-
purpose register.
MTHI Special • Move to HI Register
• Moves the contents of a
general-purpose register
to the HI register.
MTLO Special • Move to LO Register
MTLO
 • Moves the contents of a
general-purpose register
to the LO register.
RFE Special • Restore from Exception
• Restores the previous
interrupt called and
user/kernel state. This
instruction can execute
only in kernel state and is
unavailable in user mode.
SYSCALL Special • Syscall
• Causes a system call trap.
The operating system
interprets the information
set in registers to
determine what system
call to do.
EQ Data Processing • Assembler Operator
• The EQ operator
compares the first and
second operands and
returns a value of 0 (false)
if the two operands are
not equal or a value of 1
(true) if the two operands
are equal.
NE Data Processing Not equal
CS/HS Data Processing • Carry set (identical to HS)
• Higher or same (unsigned
>=)
 CC/LO Data Processing • Unsigned lower (or carry
clear).
• Carry clear (identical to
LO)
MI Data Processing Minus or negative result
PL Data Processing Positive or zero result
VS Data Processing Overflow
VC Data Processing No overflow
HI Data Processing • HI instruction takes its
operands as unsigned so
basically it uses C and Z
flag for its operation
• Unsigned higher
LS Data Processing Unsigned lower or same
LT Data Processing Signed less than
GT Data Processing Signed greater than
LE Data Processing Signed less than or equal
AL Data Processing Always (this is the default)
NV Data Processing • Never
• Reserved
LE Data Processing Less than or equal

3. References
1) Chapter 5. The Instruction Set,
csweb.cs.wfu.edu/~torgerse/Kokua/More_SGI/007-2418-006/sgi_html/ch05.html.
2) Shanley, Tom. X86 Instruction Set Architecture: MindShare, 2009.
3) Hamacher, V. Carl., et al. Computer Organization. McGraw-Hill Book Company,
1978.
4) Furber, Stephen B. ARM System-on-Chip Architecture. Addison-Wesley, 2000.