Chapter 9

Design of Counters
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9.0 Introduction
Counter is another class of sequential circuits that tally a series of input pulses
which may be regular or irregular in nature. Counter can be divided into
binary/non-binary and synchronous/asynchronous types. Binary counter follows
the binary sequence such as 0 to 1 to 2 to 3 and then repeats. Non binary counter
does not have orderly sequence.

In the chapter the design of counter using various types of flip-flop are
discussed. Attention is paid particularly for the design of counter that can self-
start.

9.1 Types of Counter

Counter can be broadly divided into synchronous and asynchronous types.
Synchronous counter has its flip-flops clocked at the same time, whilst
asynchronous counter is not. The clock of the preceeding flip-flop of the
asynchronous flip-flop is fed from the output of the previous flip-flop.
Asynchronous counter suffers delay problem whilst, sychronous counter will
not. Asynchronous counter is also referred as ripple counter for the reason of
delay feeding of the clock pulse from one flip-flop to another. Figure 9.1 and
9.2 respectively shown a modulus 4 synchronous and asynchronous counters.
Modulus of a counter is defined as the number of unique states that a counter
will sequence through. Examples of shown in Fig. 9.1 and Fig. 9.2 have four
unique states which are 00, 01, 010, and 11.

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Figure 9.1: A modulus 4 2-bit synchronous counter

Figure 9.2: A modulus 4 2-bit asynchrounous counter

9.2 Propagation Delay

We have mentioned in earlier in Chapter one that there is propagation delay
when data is transmitted from one device to another due to capacitance and
resistance of the device. The problem associated with propagation delay can be
serious. We shall illustrate propagation delay with a 3-bit binary counter and its
timing diagram are shown in Fig. 9.3 and 9.4 respectively.

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 09 Design of Counters

Figure 9.3: 3-bit (modulus 8) binary counter

Figure 9.4: The actual timing diagram of a 3-bit binary counter

From the timing diagram, it shows there are propagation delays due to transition
from clock pulse to output of flip-flop 0 Q0, from output of flip-flop 0 Q0 to
output flip-flop 1 Q1, and from output of flip-flop 1 Q1 to output flip-flop 2 Q2.

If the output Q1 Q 0 , the ideal result i.e. the

assumption of no propagation delay is shown in Fig. 9.5, whereas the result
shown in Fig. 9.6 is different for the case where there is propagation delay.
There are glitches for the non-ideal case.

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09 Design of Counters

Figure 9.5: Ideal result of Q1

Figure 9.6: Non-ideal result of Q1

In reality, the propagation is in the nanosecond region, which is not as large as it

shown in the figure. It is about 10ns for each type.

The propagation delay is caused by switched on channel resistance and

internal capacitance and output capacitance at the output of the flip-flop.

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 09 Design of Counters

9.3 Procedure to Design Synchronous Counters

The procedure to design a synchronous counter is listed here.

Obtain the truth table of the logic sequence for intended counter to be
designed. Alternatively obtain the state diagram of the counter.
Determine the number and type of flip-flop to be used.
From the excitation table of the flip-flop, determine the input of the flip-
flop.
From the output state, use Karnaugh map for simplification to derive the
circuit output functions and the flip-flop output functions, which is logic
equation.
Check wheather the counter can self-start. If it cannot self-start, it is
necessary re-design.
Draw the logic circuit diagram.
Simulate the circuit using software.
Build the circuit.

From the function tables shown in Fig. 7.4, 7.10, 7.17, and 7.20 of the flip-flops
learnt earlier in Chapter 7, the excitation or characteristic table of SR flip-flop,
D flip-flip, JK flip-flop, and T flip-flop are shown in Fig. 9.7. and 9.8
respectively. Qn is denotes the output of the present state and Q n+1 denotes the
output of next state.

Qn Qn+1 S R Qn Qn+1 D
0 0 0 X 0 0 0
0 1 1 0 0 1 1
1 0 0 1 1 0 0
1 1 X 0 1 1 1
Figure 9.7: Characteristic table of SR and D flip-flop

Qn Qn+1 J K Qn Qn+1 T
0 0 0 X 0 0 0
0 1 1 X 0 1 1
1 0 X 1 1 0 1
1 1 X 0 1 1 0
Figure 9.8: Characteristic table of JK and T flip-flop

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09 Design of Counters

9.4 Design of Synchronous Counters

In this section, designing of various types of synchronous counter using
different types of flip-flop are discussed. Using the procedure and function
tables mentioned in Section 9.2, a step by step ways to design the synchronous
counter discussed. The design also includes the analysis if the counter can self-
start.

9.4.1 Design of a Synchronous Decade Counter Using JK Flip-

Flop

A synchronous decade counter will count from zero to nine and repeat the
sequence. The state diagram of this counter is shown in Fig. 9.9.

Figure 9.9: State diagram of synchronous decade counter

Since there are ten states, four JK flip-flops are required. The truth tables of
present and next state for the decade counter are shown in Fig. 9.10. Using the
excitation table of JK flip-flop and the outputs of J and K are filled.

Present State Next State Output of JK flip-flop

Q3 Q2 Q1 Q0 Q3 Q2+ Q1+ Q0+
+
J3 K3 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X
0 0 0 1 0 0 1 0 0 X 0 X 1 X X 1
0 0 1 0 0 0 1 1 0 X 0 X X 0 1 X
0 0 1 1 0 1 0 0 0 X 1 X X 1 X 1
0 1 0 0 0 1 0 1 0 X X 0 0 X 1 X
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 09 Design of Counters

0 1 0 1 0 1 1 0 0 X X 0 1 X X 1
0 1 1 0 0 1 1 1 0 X X 0 X 0 1 X
0 1 1 1 1 0 0 0 1 X X 1 X 1 X 1
1 0 0 0 1 0 0 1 X 0 0 X 0 X 1 X
1 0 0 1 0 0 0 0 X 1 0 X 0 X X 1
Figure 9.10: Truth table and state table of a synchronous decade counter

The Karnaugh maps of the input J0, K0, J1, K1, J2, K2, J3, and K3 are shown in
Fig. 9.11, 9.12, 9.13, and 9.14 respectively. The Karnaugh map has included the
ate. The optimized results are at the
bottom of the Karnaugh maps. Note the best approach is to have both J and K
input has same logic function.

Figure 9.11: Karnaugh maps of J0 and K0

Figure 9.12: Karnaugh maps of J1 and K1

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09 Design of Counters

Figure 9.13: Karnaugh maps of J2 and K2

Figure 9.14: Karnaugh maps of J3 and K3

Based on the results of Karnaugh maps shown in Fig. 9.11 to 9.14, the analysis
of next state for non sequence state 1010, 1011, 1100, 1101, 1110, and 1111 are
shown in Fig. 9.15.

Present State Next State Output

Q3 Q2 Q1 Q0 Q3 Q2+ Q1+
+
Q0 +
J3 K3 J2 K2 J1 K1 J0 K0
1 0 1 0 1 0 1 1 0 0 0 0 0 0 1 1
1 0 1 1 0 1 1 0 1 1 1 1 0 0 1 1
1 1 0 0 1 1 0 1 0 0 0 0 0 0 1 1
1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1
1 1 1 0 1 1 1 1 0 0 0 0 0 0 1 1
1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 1
Figure 9.15: Analysis of next state for sequence 1010, 1011, 1100, 1101, 1110, and 1111

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 09 Design of Counters

Based on the results shown in Fig. 9.15, the analysis of the self-start of this
counter indicates that it can self-start. The results are shown in Fig. 9.16.

Figure 9.16: Analysis of self-start ability of decade counter

Thus, the results obtained from the Karnaugh maps shown in Fig. 9.11 to 9.14
are good for the J and K inputs of the decade counter design and the circuit
design of synchronous decade counter is shown in Fig. 9.17.

Figure 9.17: A synchronous decade counter designed using JK flip-flop

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09 Design of Counters

9.4.2 Design of an Asynchronous Decade Counter Using JK Flip-

Flop

An asynchronous decade counter will count from zero to nine and repeat the
sequence. Since the JK inputs are fed fom the output of previous flip-flop,
therefore, the design will not be as complicated as the synchronous version. At
the nineth count, the counter is reset to begin counting at zero by a NAND gate.
At the ninth count, the outputs of flip-flop Q3 and Q1 will be high

would reset the flip-flop. The logic design of the counter is shown in Fig. 9.18.

Figure 9.18: An asynchronous decade counter

The analysis of asychronous decade counter shows that it would be able to self-
start. If the counter start at non sequence state 1010, it would be reset to 0000
since Q3 and Q1 are at logic 1. If it starts at 1011, would be reset to 0000 since
Q3 and Q1 are at logic 1. If it starts at 1101, it would move to sequence 1110,
1111, and eventually reset to 0000 due Q3 and Q1 are simultaneously at logic 1.
This sequence is happened if it starts at 1110 and 1111.

9.4.3 Design of a Synchronous Modulus-Six Counter Using SR

Flip-Flop

modulus six counter will count 0, 2, 3, 6, 5, and 1 and repeat the

sequence using SR flip-flop. This modulus six counter requires three SR flip-
flops for the design. The truth table of a modulus six counter is shown in Fig.
9.17. From the excitation table of SR flip-flop shown in Fig. 9.8, the logic of
input of S2, R2, S1, R1, S0, and R0 for valid sequence are filled and shown in Fig.
9.19.

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 09 Design of Counters

Present State Next State Output

Q2 Q1 Q0 Q2+ Q1+ Q0+ S2 R2 S1 R1 S0 R0
0 0 0 0 1 0 0 X 1 0 0 X
0 1 0 0 1 1 0 X X 0 1 0
0 1 1 1 1 0 1 0 X 0 0 1
1 1 0 1 0 1 X 0 0 1 1 0
1 0 1 0 0 1 0 1 0 X X 0
0 0 1 0 0 0 0 X 0 X 0 1
Figure 9.19: Truth table and state table of the modulus-six counter

The state diagram is shown in Fig. 9.20, which shows the sequence of the
counter.

Figure 9.20: State diagram of modulus-six counter

The Karnaugh maps of the inputt S0, R0, S1, R1, S2, and R2 are shown in Fig.
9.21, 9.22, and 9.23 respectively. The simplified results are at the bottom of the
Karnaugh maps.

Note that selection logic input of S and R needs to avoid the situation of
both S and R at any of the sequence states. This is because

the case where the SR flip-flop is designed with NOR gate. For SR flip-flop
designed with NAND gate, simultaneous l
avoided because it would cause undefined output.

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09 Design of Counters

Figure 9.21: Karnaugh maps of S0 and R0

Figure 9.22: Karnaugh maps of S1 and R1

Figure 9.23: Karnaugh maps of S2 and R2

With the known output logic functions, the logic design of the synchronous
modulus six counter is shown ing Fig. 9.24.

Figure 9.24: Logic design of synchronous modulus six counters

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 09 Design of Counters

Non sequence
the counter starts with either of these states, will it eventually enter into the
sequence state of the counter. Changing
sequence states from Karnaugh maps shown Fig. 9.21 to 9.23, the non sequence
states have the next state informations shown in Fig. 9.25.

Present State Next State Output of SR flip-flop

Q2 Q1 Q0 Q2+ Q1+ Q0+ S2 R2 S1 R1 S0 R0
1 0 0 0 0 0 0 1 0 1 0 0
1 1 1 1 0 1 1 0 0 1 0 0
Figure 9.25: The next states of non sequence state 100 and 111

If the counter starts at states which are not a counter sequence state like 100 and
111, the counter is able to go into valid states of the sequence. The next state of
100 is 000 a valid counter state and the next state of 111 is 101,which is also a
valid state of the counter. Thus, this design, the counter is able to self-start.

9.4.4 Design of a 3-bit synchonous Counter Using T Flip-Flop

The state diagram of 3-bit binary counter is shown in Fig. 9.26. The binary
counter counts from 000 state to 001 to state and reset to 000 state
after 111 state. Based on the state diagram of the T flip-flop shown in Fig. 9.8,
which states a trigger is needed for output change state, the state table for the
sequence of the counter designed using T flip-flop is shown in Fig. 9.27.

Figure 9.26: The state diagram of 3-bit binary counter

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09 Design of Counters

Present State Next State Input of T flip-flop

Q2 Q1 Q0 Q2+ Q1+ Q0+ T2 T1 T0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
Figure 9.27: The state table of the 3-bit binary counter design using T flip-flop

The Karnaugh maps of the logic functions for input T2, T1, and T0 are
respectively shown in Fig. 9.28 to 9.30.

Figure 9.28: Karnaugh map of T2

Figure 9.29: Karnaugh map of T1

T0 = 1
Figure 9.30: Karnaugh map of T0
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 09 Design of Counters

Based the function equations from the karnaugh map, the design of 3-bit binary
counter using T flip-flop is shown in Fig. 9.31.

Figure 9.31: The design of 3-bit binary counter using T flip-flop

The counter has problem of self-start because any start-up state is a sequence
state of the counter.

9.4.5 Design of a Self-Starting Synchonous Counter

When power is first applied, the initial states of the flip-flops of the counter are
not predictable. For counters that do not use all the state combinations, it may
start with a non sequence state and never enter into the desired designed
sequence. A self-starting counters is one where every possible state including
those not in the desired count sequence has a sequence of transitions that
eventually leads to a counter sequence state. Let take an example of counter
with state diagram shown in Fig. 9.32. The counter can start with any of the non
sequence state 001, 101 or 110 but eventually it must be able to enter into the
any of the sequence state required by the state diagram.

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09 Design of Counters

Figure 9.32: State diagram of counter

To design self-starting counter, it all depends on

mapped in the design. use the state diagram of counter shown in Fig. 9.32
to illustrate the design procedure.

The state table of the design using T flip-flop is shown in Fig. 9.33.

Present State Next State Input of T flip-flop

+
Q2 Q1 Q0 Q2 Q1+ Q0 +
T2 T1 T0
0 0 0 1 0 0 1 0 0
0 0 1 - - - X X X
0 1 0 0 1 1 0 0 1
0 1 1 0 0 0 0 1 1
1 0 0 1 1 1 0 1 1
1 0 1 - - - X X X
1 1 0 - - - X X X
1 1 1 0 1 0 1 0 1
Figure 9.33: The state table of the 3-bit binary counter design using T flip-flop

The Karnaugh map of the input TC is shown in Fig. 9.34

and due to optimization.

Figure 9.34: Karnaugh map of input TC

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 09 Design of Counters

The Karnaugh map of the input TB is shown in Fig. 9.35

.

Figure 9.35: Karnaugh map of input TB

The Karnaugh map of the input TA is shown in Fig. 9.36

logic 1 and logic 0.

Figure 9.36: Karnaugh map of input TA

After replacing the logic 0 and logic 1 and redefined the logic
states of next state for non sequence state, the state table of the design and input
for the T flip-flops is shown in Fig. 9.37.

Present State Next State Input of T flip-flop

+
Q2 Q1 Q0 Q2 Q1+ Q0 +
T2 T1 T0
0 0 0 1 0 0 1 0 0
0 0 1 1 1 1 1 1 0
0 1 0 0 1 1 0 0 1
0 1 1 0 0 0 0 1 1
1 0 0 1 1 1 0 1 1
1 0 1 1 1 0 0 1 1
1 1 0 0 1 1 1 0 1
1 1 1 0 1 0 1 0 1
Figure 9.37: The state table of the 3-bit binary counter design using T flip-flop

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09 Design of Counters

Note that if the counter starts with no sequence state 001, 101 or 110, it would
eventually enter into the sequence state required in the design in next state,
which are 111, 110, or 011. State 110 is not in the sequence of the design.
However, in next state it would enter 011 state which is in the sequence of the
design. The illustration of the start state and enter into the sequence is shown in
Fig. 9.38.

If the start state does not enter into the sequence of the design in next state,
re-mapping of the Karnaugh map is required.

Figure 9.38: Illustration of non sequence state enters into the sequence state of a sell starting
counter

9.5. Design of Count Down Counter

So far we have design counter which starts at lower vlaue and counts to a given
higher number. at a given number
and count down to a lower value. This type of counter is called count down
counter. A 3-bit ripple down counter design with JK flip-flop is shown in Fig.
9.39. The preset input of the JK flip-flops is used to set the output of all flip-
flops logic 1. The input of all J and K inputs of flip-flop are set to logic 1 to
enable flip-flops to toggle with input clock pulse changes. The clock input of
the preceeding flip-flop is fed from the compliment output of the previous flip-
flop would allow count down for the counter.

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 09 Design of Counters

Figure 9.39: The design of 3-bit count down ripple counter using JK flip-flops

The timing of the count down ripple counter design shown in Fig. 9.39 is shown
in Fig. 9.40.

Figure 9.40: The timing diagram of the 3-bit count down ripple counter shown in Fig. 9.39

Tutorials
9.1. State the procedure for design a synchronous counter.

9.2. Shown in figure is a sequential circuit designed with JK flip-flop. If the

initial state for both Q1 and Q2
diagram for the output Q1 and Q2.

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09 Design of Counters

9.3. A sequential circuit is designed with two T flip-flops as shown in below.

Complete the timing diagram for the output Q1 and Q2.

9.4. The counter circuit is formed by the circuit shown below. Find the
counter sequence and draw the timing of the counter.

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 09 Design of Counters

9.5. Draw the timing diagrams of the decade counter shown in Fig. 9.17.

9.6. Design a modulus seven synchronous counter that can count 0, 3, 5, 7, 9,

11, and 12 using D flip-flop.

9.7. Using the truth table shown in Fig. 9.19, design this counter using T flip-
flop.

9.8. Design a counter -flop.

9.9. Design an asychronous modulus 3 counter using D flip-flop and show its
timing diagram.

9.10. Design a counter that has sequence 1, 9, 8, and 7 using three T flip-flop.

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References
1. Thomas L. Floyd, "Digital Fundamentals", Seventh Edition, Prentice-Hall
International, Inc., 2000.
2. Donald D. Givone, "Digital Principles and Designs", McGraw- Hill 2003.
3. Victor P. Nelson, H. Try Nagle, Bill D. Carroll, and J. David Irwin, "Digital
Logic Circuit Analysis & Design", Prentice-Hall Englewood Cliffs.NJ,
1995.

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