Chapter 7

Flip-Flops and Applications

_____________________________________________
7.0 Introduction
The combinational circuits discussed in last few chapters are two-valued
network whereby the instant output depends on the input presents at that instant.
The circuit does not remember event or store event state.

Sequential circuit is also a two-valued network, whereby the output is not

only depended on the instant input state; it also depends on the past history of
input. The past history is memorized. Thus, sequential circuit is said to have
memory.

Flip-flop is a sequential circuit whereby it contains a basic bistable element

and timing circuit, which clock
Synchronous flip-flop is an edge-triggered flip-flop because the input data is
transferred to the flip-
pulse. Asynchronous flip-flop has the timing control depends on output
triggering edge of the previous flip-flop. Latch is the sequential circuits contain
memory used to store single bit of information/data and it does not have clock
input.

The basic bistable element is shown in Fig. 7.1. It contains two NOT gates
where the outputs are fed to inputs of the opposite NOT gate.

Figure 7.1: A basic bistable element

- 111 -
07 Flip-Flops and Applications

If the input logic state of NOT gate

OT gate 2.

the circuit is stable. Likewise, another stable state would exist if one assumed

at

7.1 Latches and Flip-Flops

Latch is a class of flip-flop where the timing of the output is not controlled. We
shall discuss the fundamental set-reset SR flip-flop, data D flip-flop, JK flip-
flop, and trigger T flip-flop.

7.1.1 SR Flip-Flop/Latch

The circuit of set-reset SR latch and its corresponding function table are shown
in Fig. 7.2 and Fig. 7.3 respectively. The shown SR latch has two NOR gates,
where they have their inputs fed from the outputs of the crossed NOR gates. SR
latch can also be designed with two NAND gates. For NAND gate SR latch,
.

Figure 7.2: SR latch

Input Output
S R Q
0 0 Q
0 1 0 1
1 0 1 0
1 1 undefined undefined
Figure 7.3: Function table of a SR latch
- 112 -
 07 Flip-Flops and Applications

Based on Fig. 7.2, the equation of the outputs are and .

Normally S and R are set at logic 0 and if the present state Q = 1 and then
and . Thus, the output Qn+1 remains as the previous state.
If the the present state Q = 0 and then for S and R are set at logic 0
and . If we now set S = 0 and R = 1 then and
.

The excitation function table of the SR latch is shown in Fig. 7.4. Note that
(n+1) means next state.

Input Output
Qn S R Qn+1
0 0 0 0 1
0 0 1 0 1
0 1 0 1 0
0 1 1 X undefined
1 0 0 1 0
1 0 1 0 1
1 1 0 1 0
1 1 1 X undefined
Figure 7.4: Excitation function table of SR latch

Based on the truth table shown in Fig. 7.4, the state diagram of the SR flip-flop
is shown in Fig. 7.5.

Figure 7.5: State diagram of SR latch

Based on the excitation table, the Karnaugh map for the output Q n+1, which is
shown in Fig. 7.6(a), is Qn+1 = S + Qn , whilst the complement output
shown in Fig. 7.6(b) is = = .

- 113 -
07 Flip-Flops and Applications

(a) Qn+1 = S + Qn (b) =

Figure 7.6: Karnaugh map of SR latch output Qn+1 and

Beside, SR latch can remember an event. A basic application of the SR latch is

used to eliminate the contact bouncing. A normal switch in contact such the one
shown in Fig. 7.7(a), it would create bounce during contact. The output voltage
will oscillate between ON and OFF shown in Fig. 7.7(b).

(a) Normal contact switch (b) Output oscillate due to contact bounce
Figure 7.7: Normal contact switch

Using SR latch, one can see from the function table, when a SR latch is reset or
set, its output state would remain until the set or rest logic is applied. A typical
circuit utilizing a SR flip-flop to eliminate contact bouncing is shown in Fig.
7.8(a). Without the SR flip-flop, the contact would cause bouncing set output to
as shown
in Fig. 7.8(b).

- 114 -
 07 Flip-Flops and Applications

(a) SR contact Circuit (b) waveform of Set and Reset

Figure 7.8: SR latch circuit uses to eliminate contact bouncing

A SR flip-flop designed using NAND gates is shown in Fig. 7.9 and its function
table is shown in Fig. 7.10. Note n denotes present state and (n+1) denotes next
state.

Figure 7.9: SR flip-flop design with NAND gate

SR flip-flop is a rising edge-triggered device. When the clock CLK is changing

low state to high the output of the flip-flop would change state.

Input Output
CLK Q
0 0 1 undefined undefined
0 1 1 1 0
1 0 1 0 1
1 1 1 Qn
X X 0 Qn
Figure 7.10: Function table of a SR flip-flop
- 115 -
07 Flip-Flops and Applications

The timing diagram of the SR flip-flop is shown in Fig. 7.11.

Figure 7.11: Timing diagram of SR flip-flop as shown in Fig. 7.9

7.1.2 Data Flip-Flop/Latch

Data latch or D latch has the circuit shown in Fig. 7.12 and its excitation
function table is shown in Fig. 7.13. It consists of a SR latch and a data line. The
data line D is feed directly to set line of a SR latch, whilst the reset line is fed by
the complement of data line .

Figure 7.12: Data latch

Input Output
Qn D Qn+1
0 0 0 1
0 1 1 0
1 0 0 1
1 1 1 0
Figure 7.13: Excitation function table of D latch

Based the excitation functional table, the Karnaugh map of the output Qn+1
shown in Fig. 7.14(a), is Qn+1 = D, whist the is equal to shown in
- 116 -
 07 Flip-Flops and Applications

Fig. 7.14(b). This shall mean that the output of the D latch depends on the logic
state of data line D. The equation is also known as the characteristic equation.

(a) Qn+1 = D (b)

Figure 7.14: Karnaugh map of D latch output Qn+1 and

The circuit of a D flip-flop is shown in Fig. 7.15 and its corresponding function
table is shown in Fig. 7.16.

Figure 7.15: A Data flip-flop

Input Output
D CLK Qn+1
0 1 0 1
1 1 1 0
X 0 Qn
Figure 7.16: Function table of Data flip-flop

Like SR flip-flop and D flip-flop is also a rising edge triggered device. The
result can be shown from the timing diagram of the flip-flop shown in Fig. 7.17.
The output shows that it follows equation Qn+1 = D.

- 117 -
07 Flip-Flops and Applications

Figure 7.17: Timing diagram of a D flip-flop

The state table and state diagram of clocked D flip-flop shown in Fig. 7.15 are
shown in Fig. 7.18 and 7.19 respectively.

CLK D Present State Qn Next State Qn+1 Remark

0 X 0 0 Hold
0 X 1 1 Hold
1 0 0 0 Store 0
1 0 1 0 Store 0
1 1 0 1 Store 1
1 1 1 1 Store 1
Figure 7.18: State table of clocked D flip-flop shown in Fig. 7.15

Figure 7.19: State diagram of clocked D flip-flop shown in Fig. 7.15

Based on the state table shown in Fig. 7.18, the next state Qn+1 equation is equal
to .

7.1.3 JK Flip-Flop

Jack Kilby flip-flop or JK flip-flop is also a form of SR flip-flop without

undefined state in which at time it is termed as forbidden states, which is no
simultaneous S = 1 and R = 1 internally like the case of SR flip-flop. The J input
- 118 -
 07 Flip-Flops and Applications

is used to set the flip-flop whilst the K input is used to reset the flip-flop. With

does not change. When , the output is

toggling. The circuit of JK flip-flop is shown of a JK flip-flop is flown in Fig.
7.20.

Figure 7.20: JK flip-flop

The function table and excitation table are respectively shown in Fig. 7.21 and
Fig. 7.22 respectively.

Input Output
J K Q
0 0 Last state Last state
0 1 0 1
1 0 1 0
1 1
Figure 7.21: Function table of JK flip-flop

Input Output Remarks

J K Qn Qn+1
0 0 0 0 1 Hold
0 0 1 1 0 Hold
0 1 0 0 1 Reset
0 1 1 0 1 Reset
1 0 0 1 0 Set
1 0 1 1 0 Set
1 1 0 1 0 Toggle
1 1 1 0 1 Toggle
Figure 7.22: Excitation function table of JK flip-flop
- 119 -
07 Flip-Flops and Applications

The State diagram of the JK flip-flop is shown in Fig. 7.23.

Figure 7.23: State diagram of the JK flip-flop

Using Karnaugh map for simplification, the output of next state Qn+1 is Qn+1 =
J + Qn and its corresponding truth table is shown in Fig. 7.24(a), whist
the output shown in Fig. 7.24(b) is . The output equation
is also known as the characteristic equation.

(a) Qn+1 = J + Qn (b)

Figure 7.24: Karnaugh map of output for JK flip-flop

The timing diagram of JK latch following next state equation Qn+1 = J+

Qn is shown in Fig. 7.25.

Figure 7.25: Timing diagram of JK latch as shown in Fig. 7.22

- 120 -
 07 Flip-Flops and Applications

7.1.4 Trigger Flip-Flop

Trigger flip-flop or toggle flip-flop is closed resemble of JK flip-flop except the
JK inputs are tied together shown in Fig. 7.26.

Figure 7.26: A trigger flip-flop

The excitation table is respectively shown in Fig. 7.27.

Input Output
Qn T Qn+1
0 0 0 1
0 1 1 0
1 0 1 0
1 1 0 1
Figure 7.27: Excitation table of trigger flip-flop

Using Karnaugh map for simplification which is shown in Fig. 7.28(a), the
output of next state Qn+1 is Qn+1 = T + Qn = Qn T, whist output
shown in Fig. 7.28(b) is .

(a) Qn+1 = Qn T (b)

Figure 7.28: Karnaugh map of output for trigger flip-flop

- 121 -
07 Flip-Flops and Applications

Based excitation table shown in Fig. 7.27, the state diagram of T flip-flop is
shown in Fig. 7.29.

Figure 7.29: State diagram of the T flip-flop

The timing diagram of the T flip-flop as shown by equation Qn+1 = Qn T is

shown in Figure 7.30.

Figure 7.30: Timing diagram of T flip-flop as shown in Fig. 7.27

7.1.5 Master-Slave Flip-Flop

The master-slave flip-flop has the advantage of being edge-triggered, making it
easier to use in larger circuits, since the inputs to a flip-flop often depend on the
state of its output. It can overcome race condition. The master-slave flip-flop
contains a master flip-flop and a slave flip-flop. It is also known as pulse
triggered flip-flop because the leading edge trigger is setting or resetting the
master flip-flop, while it needs a trailing edge pulse trigger to set or reset the
slave flip-flop.

The circuit of the master-slave JK flip-flop is shown in Fig. 7.31. The flip-
flop has same excitation table like the leading edge triggered JK flip-flop.

- 122 -
 07 Flip-Flops and Applications

Figure 7.31: A master-slave JK flip-flop

The timing diagram of the master-slave JK flip-flop is shown in Fig. 7.32. It

shows the timing of the output Qm of master flip- output Q of the slave
flip-flop when it is connected in toggle mode i.e. both J and K inputs are

Figure 7.32: Timing diagram of master-slave JK flip-flop

The master-slave D flip-flop circuitry is shown in Fig. 7.33.

- 123 -
07 Flip-Flops and Applications

Figure 7.33: The circuit of a master-slave D flip-flop

The timing diagram of the master-slave D flip-flop is shown in Fig. 7.34.

Figure 7.34: The timing diagram of master-slave flip-flop as shown in Fig. 7.33

7.2 Flip-Flop with Additional Input

Flip-flops may have additional inputs to initialize it or disable the clock input
such as the D flip-flop shown in Fig. 7.35 that has preset and clr inputs. The
inputs are normal active high, which mean it preset and clr when these input are
set to

Figure 7.35: D flip-flop with preset and clear inputs

The logic circuitry of the D flip-flop shown in Fig. 7.35 is shown in Fig. 7.36.

- 124 -
 07 Flip-Flops and Applications

Figure 7.36: Logic circuitry of the D flip-flop shown in Fig. 7.36

The corresponding truth table for the D flip-flop mentioned in Fig, 7.35 is
shown in Fig. 7.37.

Input Output
Clk D Pre Clr Q
X X 1 1 Not allowed
X X 1 0 1
X X 0 1 0
0 0 0 0
1 0 1 1
0,1 X 0 0 Q
Figure 7.37: Truth table of D flip-flop with preset and clear inputs

The timing diagram of the of D flip-flop with preset and clear inputs as shown
in Fig. 7.35 is shown in Fig. 7.38.

Figure 7.38: Timing digram of D flip-flop with preset and clear inputs

The active low preset and clr D flip-flop is shown in Fig. 7.39, which mean it

- 125 -
07 Flip-Flops and Applications

Figure 7.39: The active low D flip-flop with preset and Clr inputs

The corresponding truth table for the D flip-flop mentioned in Fig, 7.39 is
shown in Fig. 7.40.

Input Output
clk D Q
X X 0 0 Not allowed
X X 0 1 1
X X 1 0 0
0 1 1 0
1 1 1 1
0,1 X 1 1 Q
Figure 7.40: Truth table of D flip-flop with active low preset and clear inputs

The D flip-flop with disable clk input is shown in Fig. 7.41. When En is low,
the clock signal clk will not appear at the output of the AND gate because it
always low. Since the D flip-flop does not receive the clock edge, it will hold
the output.

Figure 7.41: D flip-flop with disable clk input

The corresponding logic diagram of the D flip-flop with disable clk input is
shown in Fig. 7.42.
- 126 -
 07 Flip-Flops and Applications

Figure 7.42: The logic diagram of D flip-flop with disable clock input

The timing diagram of the D flip-flop with disable clock input is shown in Fig.
7.43.

Figure 7.43: The timing diagram of the D flip-flop with disable clock input

7.3 Application of Flip-Flop

There many applications for the flip-flop. Since flip-flop has the capability to
store data, it is used to design circuits such as frequency divider, parallel data
storage, counters, and registers. We shall look at the first application here and
leave the rest to be discussed in other chapters.

You may realize by now that from the timing diagrams of the flip-flop
shown in Fig. 7.16 and Fig. 7.43, the frequency of the flip- half
-flop is a divide by 2 frequency divider.
Connecting N flip-flops in series will provide divide by 2N of the clock
frequency.

- 127 -
07 Flip-Flops and Applications

We shall discuss more application of the flip-flop for design sequential

circuits such as registers and counter in later chapter. A typical 4-bit parallel
data storage designed with 4 D flip-flops is shown in Fig. 7.44.

Figure 7.44: A 4-bit parallel data storage designed with 4 D flip-flops

- 128 -
 07 Flip-Flops and Applications

Tutorials
7.1. The input timing diagram feed to a RS flip-flop is shown below. Draw
output Q and timing for this flip-flop. Verify the output timing with the
equation Qn+1 = S + Qn and draw the timing diagram for three clock
pulse.

7.2. Use Karnaugh map to verify that the output Q of SR flip-flop follows
equation Qn+1 = S + Qn .

7.3. Draw a circuit diagram to illustrate how contact bouncing can be

eliminated with a SR latch.

7.4. Using the characteristic equation of JK flip-flop, complete the output

timing diagram of the flip-flop.

- 129 -
07 Flip-Flops and Applications

7.5. Describe how the trailing edge pulse trigger the set and reset of the
master-slave JK flip-flop.

7.6. Design a divide by 8 frequency divider with JK flip-flop and draw its
timing diagram.

References
1. Donald D. Givone, "Digital Principles and Designs", McGraw- Hill 2003.
2. Thomas L. Floyd, "Digital Fundamentals", Seventh Edition, Prentice-Hall
International, Inc., 2000.
3. Victor P. Nelson, H. Try Nagle, Bill D. Carroll, and J. David Irwin, "Digital
Logic Circuit Analysis & Design", Prentice-Hall Englewood Cliffs.NJ,
1995.

- 130 -