Table of Contents Page

Chapter 10 Synchronous Sequential Network .................................4

10.0 Introduction ............................................................................................. 4
10.1 Model of Synchronous Network ............................................................ 5
10.1.1 Mealy Model of Synchronous Network........................................................ 5
10.1.2 Moore Model of Synchronous Network ....................................................... 5
10.2 Implementation of Synchronous Network ........................................... 6
10.3 Analysis of Synchronous Network ........................................................ 7
Example 10.1 ........................................................................................................................... 10
Example 10.2 ........................................................................................................................... 11
Tutorials ......................................................................................................... 13
References ...................................................................................................... 15

-i-
Table of Contents Page

- ii -
 List of Figures Page
Figure 10.1: General model of a sequential network ............................................................. 4
Figure 10.2: Mealy model of synchronous network ............................................................... 5
Figure 10.3: Moore model of synchronous network .............................................................. 5
Figure 10.4: A state diagram of a Mealy machine ................................................................. 6
Figure 10.5: A state diagram of Moore machine .................................................................... 6
Figure 10.6: A synchronous sequential circuit designed with JK flip-flop ............................ 8
Figure 10.7: Flip-flop input state of synchronous sequential circuit shown in Fig. 10.6 ....... 8
Figure 10.8: Excitation function table of JK flip-flop ............................................................ 9
Figure 10.9: Final state table of synchronous sequential circuit shown in Fig. 10.6 ............. 9
Figure 10.10: State diagram of counter circuit shown in Fig. 10.6 ........................................ 10

- iii -
 Chapter 10

Synchronous Sequential Network

_____________________________________________
10.0 Introduction
Sequential network is a class of sequential circuits that has timing sequence of
inputs, outputs, and states. It can be classified as synchronous and
asynchronous. In the case of synchronous network, it is assumed that the
behavior of the system is totally determined by the values of the present state
and external input signal at discrete instant of time. Only at these instants of
time that the memory of the device is allowed to change. For asynchronous
network, the order of the input signal changes the memory of the network.

In the chapter the design of synchronous networks both Mealy and Moore
models are discussed in detail with examples as illustration. Sequential network
is sometime called as Finite State Machine FSM because its sequential logic has
a fixed number of possible states. We will also discuss two optimization
technique for sequential network.

The general model of a sequential network is shown in Fig. 10.1.

Figure 10.1: General model of a sequential network

One can see that the next state output Qn+1 of flip-flop is a function of present
state Qn and input value X. Thus,

Qn+1 = f(Qn, x) (10.1)

The output Y is a function of present state Qn and input X. Thus,

 10 Synchronous Sequential Network

Y = f(Qn, x) (10.2)

10.1 Model of Synchronous Network

Synchronous network can be divided into two models namely the Mealy and
Moore models. Each model has its own dependent valuables. We shall discuss
each of this type in detail.

10.1.1 Mealy Model of Synchronous Network

The Mealy model of synchronous network is shown in Fig. 10.2.

Figure 10.2: Mealy model of synchronous network

As it shown in the figure, the output Y is a function of present state Qn and input
value X, while the next state Qn+1 of flip-flop is a function of present state Qn
and value of input X.

10.1.2 Moore Model of Synchronous Network

The Moore model of synchronous network is shown in Fig. 10.3.

Figure 10.3: Moore model of synchronous network

-5-
10 Synchronous Sequential Network

As it shown in the figure, the output Y is a function of present state Qn while the
next state Qn+1 of flip-flop is a function of present state Qn and value of input X.
The state diagrams of a Mealy and Moore models are shown respectively in Fig.
10.4 and 10.5 respectively.

Figure 10.4: A state diagram of a Mealy machine

Figure 10.5: A state diagram of Moore machine

10.2 Implementation of Synchronous Network

The implementation of synchronous network involves a number of steps listed
below. Reader is also being reminded that no state reduction is considered in
this stage. State minimization will be considered in next section.

-6-
 10 Synchronous Sequential Network

 Construct a state/output table corresponding to the word description of

specification or use a state diagram.
 Minimize the number of states in the state/output table.
 Choose a set of state variables and assign state-variable combinations to
the named states.
 Substitute the state-variable combinations into the state/output table to
create a transition/output table that shows the desired next state-variable
combination and output for each state/input combination.
 Choose a flip-flop type such as D or J-K types for the state memory.
 Construct an excitation table that shows the excitation values required to
obtain the desired next state for each state/input combination.
 Derive excitation equations from the excitation table.
 Derive output equations from the transition/output table.
 Draw a logic diagram that shows the state-variable storage elements and
realizes the required excitation and output equations.

10.3 Analysis of Synchronous Network

Let’s consider the Mealy circuit shown in Fig. 10.6 and begin the analysis of
this circuit. The equations of the JK inputs and output Y are

J1 = Q0; K1 = Q0 X

J0 = X ; K0 = Q1  X

Y = Q1  X

-7-
10 Synchronous Sequential Network

Figure 10.6: A synchronous sequential circuit designed with JK flip-flop

From the output equations, the input states of flip-flop and output Y shall be
established as shown in Fig. 10.7.

State Table
Next Flip-flop Inputs Output
Present State Input
State
Q1 Q0 X Q1+ Q0+ J1 K1 J0 K0 Y
0 0 0 0 0 1 0 0
0 1 0 1 1 1 0 0
1 0 0 0 0 1 1 1
1 1 0 1 1 1 1 1
0 0 1 0 0 0 1 1
0 1 1 1 0 0 1 1
1 0 1 0 0 0 0 0
1 1 1 1 0 0 0 0
Figure 10.7: Flip-flop input state of synchronous sequential circuit shown in Fig. 10.6

Either from the JK characteristic table as shown in Fig. 10.8 or the function
equation for next state output Qn+1 = Q n J+Qn K , the next state logic values of

-8-
 10 Synchronous Sequential Network

output Q1 and Q0 of JK filip-flop are established from the various JK input

values. The results are shown in Fig. 10.9.

Output of JK
Input
Flip-Flop
J K Qn Qn+1
0 0 0 0
0 1 0 0
1 0 0 1
1 1 0 1
0 0 1 1
0 1 1 0
1 0 1 1
1 1 1 0
Figure 10.8: Excitation function table of JK flip-flop

State Table
Input State of Flip-flop Output
Present State Input Next State
Q1 Q0 X Q1+ Q0+ J1 K1 J0 K0 Y
0 0 0 0 1 0 0 1 0 0
0 1 0 1 1 1 1 1 0 0
1 0 0 1 1 0 0 1 1 1
1 1 0 0 0 1 1 1 1 1
0 0 1 0 0 0 0 0 1 1
0 1 1 1 0 1 0 0 1 1
1 0 1 1 0 0 0 0 0 0
1 1 1 1 1 1 0 0 0 0
Figure 10.9: Final state table of synchronous sequential circuit shown in Fig. 10.6

Based on the finalized state table shown in Fig. 10.9, the state diagram of Mealy
model synchronous sequential network circuitry is drawn and shown in Fig.
10.10.

The excitation table of the JK flip-flop can also be put in Karnaugh map
format for easier reference such as what is shown in Fig. 10.11.

-9-
10 Synchronous Sequential Network

Figure 10.10: State diagram of counter circuit shown in Fig. 10.6

Example 10.1
Write the state table from this state diagram.

Solution
The state table shall be as follow:

Present State Next State Input Output

QA QB QA+ QB+ X Y
0 0 0 1 0 0
0 0 0 1 1 1
0 1 1 1 0 0
0 1 1 1 1 1
1 0 0 0 0 1
1 0 1 1 1 0
1 1 1 0 0 1
1 1 1 1 1 0
- 10 -
 10 Synchronous Sequential Network

Example 10.2
Design the logic circuit for the state diagram shown below using D flip-flop.

Present State Next State Input Output

QA QB QA+ QB+ X Y
0 0 0 1 0 0
0 0 0 1 1 1
0 1 1 1 0 0
0 1 1 1 1 1
1 0 0 0 0 1
1 0 1 1 1 0
1 1 1 0 0 1
1 1 1 1 1 0

Solution
Based on the state diagram, the input of D flip-flop need to be determined is
shown.

Present State Next State Input Output Input of D Flip-Flop

QA QB QA+ QB+ X Y DA DB
0 0 0 1 0 0 0 1
0 0 0 1 1 1 0 1
0 1 1 1 0 0 1 1
0 1 1 1 1 1 1 1
1 0 0 0 0 1 0 0
1 0 1 1 1 0 1 1
1 1 1 0 0 1 1 0
1 1 1 1 1 0 1 1

The Karnaugh maps of the input of D flip-flop and Y output are:

- 11 -
10 Synchronous Sequential Network

The circuit design shall be

- 12 -
 10 Synchronous Sequential Network

Tutorials
10.1. Draw the state diagrams for a JK flip-flop and SR flip-flop.

10.2. Draw the state table from this state diagram.

- 13 -
10 Synchronous Sequential Network

10.3. Design the the logic circuit for the state diagram shown in question 2
using D flip-flop.
10.4. Design a synchronous sequential circuit based on the state diagram shown
below using D flip-flop.

10.5. Design a synchronous sequential circuit based on the state diagram shown
below using JK flip-flop.

- 14 -
 10 Synchronous Sequential Network

References
1. Charles H Roth, Jr., "Fundamentals of Logic Design", Third Edition, West
Publishing Company, 1985.
2. Donald D. Givone, "Digital Principles and Designs", McGraw- Hill 2003.
3. Alan B. Marcovitz, “Introduction to Logic Design”, McGraw- Hill 2002.

- 15 -