31

CHAPTER 2

VOLTAGE SOURCE INVERTERS

2.1 INTRODUCTION

Inverters are static power converters that produce an AC output

waveform from a DC power supply. They are applied in adjustable AC speed
drives, Uninterruptible Power Supplies (UPS), shunt active power filter, etc.
For sinusoidal AC outputs, the magnitude, frequency, and phase should be
controllable. If a DC input is a voltage source, then the inverter is called a
Voltage Source Inverter (VSI). Similarly in case of a Current Source Inverter
(CSI), the input to the circuit is a current source. The VSI circuit has a
capability of controlling AC output voltage, whereas the CSI directly controls
AC output current. Sketch of output voltage waveforms by an ideal VSI,
should be independent of load connected at the output.

According to a number of phases, inverters are classified into two

types

1. Single Phase Voltage Source Inverter

2. Three Phase Voltage Source Inverter

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2.2 SINGLE PHASE VOLTAGE SOURCE INVERTER

Single phase inverters are basic inverters which produce a square

shape AC output with a DC input. These inverters have simple on-off control
logic and obviously they operate at much lower frequencies. Due to a capacity
of low power, they are widely used in power supplies and single phase UPS
.They can be divided into two categories.

1. Half bridge Single Phase Voltage Source Inverter

2. Full bridge Single Phase Voltage Source Inverter.

2.2.1 Half Bridge Voltage Source Inverter

Figure 2.1 shows a circuit topology of a Half-Bridge VSI, where two

large capacitors are required to provide a neutral point O, such that each
V dc
capacitor maintains a constant voltage ( V1 = V2 = ). Due to reason that the
2
current harmonics produced by the operation of the inverter are low-order
harmonics, a set of large capacitors ( C1 and C 2 ) are required. In this topology,
it has a single leg with two power switches Q1 and Q2 . For bidirectional flow
of current, feedback diodes D1 and D2 are employed in parallel with switches
Q1 and Q2 .

According to Figure 2.1, it is clear that both switches cannot be ON

simultaneously, because both are directly connected across the DC link source.
If two switches conduct at the same time, a short circuit across the DC link
voltage source Vdc would be produced. There are two defined switching states
(States 1 and 2) as shown in Table 2.1. In order to avoid the short circuit
across the DC bus and the undefined AC output voltage condition, the
 33

modulating technique should make sure that at any moment either the top or
the bottom switch of the inverter leg is on.

In a half bridge topology, the input DC voltage is split in two equal

parts ( V1 and V2 ) through an ideal and loss-less capacitive potential divider.
The half bridge topology consists of one leg (one pole) of switches whereas
the full bridge topology has two such legs. Each leg of the inverter consists of
two series connected power electronic switches ( Q1 and Q2 ) shown in the
Figure 2.1.

Figure 2.1 Circuit topology of half bridge inverter

Each of these switches consists of an IGBT type controlled switch

across which, an uncontrolled diode is put in anti-parallel approach. These
switches are capable of conducting bi-directional current, but they have to
obstruct only one polarity of voltage. In a half bridge topology, the single-
phase load is connected between the mid-point of the input DC supply and the
junction point of the two switches. These points are marked as ‘O’ and ‘A’
respectively.
 34

2.2.1.1 Principle and operation of half bridge inverter

With refer to the Table 2.1, there are two switching states and the
output voltage is obtained or produced on single phase load from either upper
V dc
half DC voltage ( ) or lower half DC voltage. Principle and operation of this
2
inverter with switching states are discussed below.

State 1

Vdc
In state 1, upper half dc voltage ( V1  ) and power switch Q1 are in
2
conducting mode and remaining components are in non-conducting mode.
V dc
During time period of 0 to T/2, Switch Q1 is on and upper voltage is
2
appeared across a load as an output voltage ( V AO ). The path of conduction of
this state is shown in Figure 2.2.

Figure 2.2 Operation of the inverter in State 1

 35

State 2

Vdc
In state 2, lower half DC voltage ( V2  ) and power switch Q2 are
2
in conduction mode and remaining components are in non- conduction mode.
T
During time period from ( ) to T, switch Q2 is on and lower voltage (
2
Vdc
V2  ) is obtained across a load as an output voltage. Conduction path for
2
this state is shown in Figure 2.3. Due to reverse polarity, output voltage ( V AO )
is negative.

Figure 2.3 Operation of the inverter in State 2

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Table 2.1 Switching states of half bridge single phase inverter

State Switching State Output Voltage

V dc
1 Q1 is ON and Q2 is OFF
2
V dc
2 Q1 is OFF and Q2 is ON -
2

Figure 2.4 shows a typical load voltage waveform output by the half
T
bridge inverter. During the time interval 0 to ( ), V AO acquires a magnitude
2
V dc V
of when Q1 is turned on and the magnitude reverses to - dc , when Q2 is
2 2
T
turned on for the period ( ) to T.
2

Figure 2.4 Output voltage waveform of half bridge inverter

2.2.2 Full Bridge Voltage Source Inverter

Figure 2.5 shows the power topology of a full bridge VSI. This
inverter is similar to the half bridge inverter, however a second leg provides
 37

the neutral point to the load. As in the half bridge inverter, both switches Q1
and Q2 or Q3 and Q4 in a single leg cannot be on simultaneously because a
short circuit across the dc link voltage source Vdc would be occurred.

In a full bridge inverter, there are four defined (states 1, 2, 3, and 4)

switching states as shown in Table 2.2. The undefined condition should be
avoided so as to be always capable of defining the AC output voltage. It can
be observed that the AC output voltage can acquire values up to the DC link
value Vdc which is twice that obtained with half bridge voltage source inverter
topologies. Output voltage is denoted as V AB taken from the load.

In a full bridge inverter, there are four defined (states 1, 2, 3, and 4)

switching states as shown in Table 2.2. The undefined condition should be
avoided so as to be always capable of defining the AC output voltage. It can
be observed that the AC output voltage can acquire values up to the DC link
value Vdc which is twice that obtained with half bridge voltage source inverter

topologies. Output voltage is denoted as V AB taken from the load.

Figure 2.5 Circuit diagram of full bridge voltage source inverter

 38

The single-phase full bridge circuit shown in Figure 2.5 is similar to

that of two half bridge circuits sharing the same DC bus. The full bridge
circuit has two pole-voltages ( V AO and V BO ), which are similar to the pole
voltage ( V AO ) of the half bridge circuit. Both ( V AO ) and ( VBO ) of the full bridge
circuit are square waves but they will have some phase difference. Respective
pole voltages are determined by using Thevenin’s analysis.

State 1

In this state, the power switches Q1 and Q4 are in conduction mode and
remaining switches are OFF condition. By using Thevenin’s analysis, pole
voltages at ‘A’ and ‘B’ are ( V AO and V BO ) measured and the output voltage is
obtained as VAB  VAO  VBO  Vdc . The path for conduction of this state is
shown in Figure 2.6.

Figure 2.6 Conduction flow of inverter at State 1

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State 2

In this state, the power switches Q2 and Q3 are in conduction mode

and remaining switches are in OFF condition. Pole voltages at ‘A’ and ‘B’ are
measured from the load and the output voltage is determined by
VAB  VAO  VBO  Vdc as shown in Table 2.2. Topology of this state is shown

in Figure 2.7.

Figure 2.7 Conduction flow of inverter at State 2

State 3

In this state, the power switches Q1 and Q3 are in conduction mode and
remaining switches are in OFF condition. Voltages at nodes ‘A’ and ‘B’ are
measured and the output voltage VAB  VAO  VBO  0 . Topology of this state is
given in Figure 2.8.
 40

Figure 2.8 Conduction flow of inverter at State 3

State 4

In this state, the power switches Q2 and Q4 are in conduction mode

and remaining switches are in OFF condition. Pole voltages at ‘A’ and ‘B’ are
measured and a load voltage is calculated as VAB  VAO  VBO  0 . Topology of
this state is given in Figure 2.9.

Figure 2.9 Conduction flow of inverter at State 4

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Table 2.2 Switching states and output voltage of single phase inverter

Output voltage
State Switching state
V AO V BO V AB
V dc V dc
1 Q1 and Q4 are ON - Vdc
2 2

V dc V dc
2 Q2 and Q3 are ON - - Vdc
2 2

V dc V dc
3 Q1 and Q3 are ON 0
2 2

V dc V dc
4 Q2 and Q4 are ON - - 0
2 2

Figure 2.10 indicates the representation of two pole voltages and load
voltage wave forms of a full bridge single phase inverter. During the time
period (0 to t), switches Q1 and Q4 are ON, and in which pole voltages are
V dc V
measured as V AO = and V BO = - dc . Then output voltage (load voltage) is
2 2
given by

Vdc Vdc
V AB  V AO  VBO    Vdc
2 2
Similarly, output voltage can be found for next three intervals.
 42

Figure 2.10 Output voltage waveforms of three phase voltage source

inverter

2.3 THREE PHASE VOLTAGE SOURCE INVERTER

From the chapter 2.2.2, it can be understood that the single phase
voltage source inverters can manage only low power applications. For high
power applications, three phase voltage source inverters are preferred to
provide three phase voltage source in addition to that the magnitude, phase
and frequency of voltages should be controlled.

2.3.1 Topology of Three Phase Voltage Source Inverter

The typical three-phase VSI topology is shown in Figure 2.11 and

middle points of the inverter legs are connected to three phase RL load. There
are the eight valid switch states which are given in Table 2.3. The switches of
 43

any leg of the inverter ( S1 and S 4 , S 3 and S 6 or S 5 and S 2 ) cannot be switched

on simultaneously. Because it would result in short circuit across the DC link

voltage supply. Similarly, the switches of any leg of the inverter cannot be
switched off simultaneously to avoid undefined states in the VSI and thus
undefined ac output line voltages.

Figure 2.11 Circuit topology of three phase voltage source inverter

Two of eight valid states (7 and 8) are called as zero switch states to
produce zero AC line voltages. In this case, the AC line currents freewheel
through either the upper or lower components. The remaining states (1 to 6 in
Table 2.3) are called as non-zero switch states to produce non-zero AC output
voltages. The resulting AC output line voltages consist of discrete values of
voltages that are Vdc , 0, and - Vdc for the topology shown in Figure 2.13.

The pole voltages and output voltage waveforms obtained with respect
to switching states from three phase VSI are shown in Figure 2.13. Analysis of
three phase VSI is carried out in either 1200 mode or 1800 mode of conduction.
Here 1800 mode of conduction is presented and each switch turned on at every
600.
 44

Conduction of switches in each switching states, pole voltages

measured at ‘a’ and ‘b’ and load voltage ( Vab ) are noted in the Table 2.3

Table 2.3 Switching states and output voltage of three phase VSI

Output voltage
State Switching state
Va Vb Vab

1 S1 , S 2 and S 6 are ON - Vdc 0 Vdc

2 S 2 , S 3 and S1 are ON - Vdc Vdc 0

3 S 3 , S 4 and S 2 are ON 0 Vdc - Vdc

4 S 4 , S 5 and S 3 are ON Vdc 0 - Vdc

5 S 5 , S 6 and S 4 are ON Vdc - Vdc 0

6 S 6 , S1 and S 5 are ON 0 - Vdc Vdc

7 S1 , S 3 and S 5 are ON 0 0 0

8 S 4 , S 6 and S 2 are ON 0 0 0

2.3.2 Determination of Load Voltage

With reference to Figure 2.12, it may be seen that for 0≤ωt≤π/3, the
power switches S 6 , S1 and S5 conduct and it will represent the equivalent
inverter and load circuit during the above time interval. In the equivalent
circuit representation, only presentation of conducting switches indicated as
cross (x) mark and remaining switches have been omitted.

In such cases, when the load is a balanced one, it is easy to find the
phase voltages for each phase and that can be given as
 45

1
Van  Vdc ,
3
2
Vbn   V dc ,
3
1
Vcn  Vdc . and Va  0 , Vb  Vdc
3
1 2
Hence, Vab  Van  Vbn  Vdc  Vdc  Vdc
3 3
Similarly, remaining all other modes can be explained properly and
verified with reference to Table 2.3 and Figure 2.13.

Figure 2.12 Equivalent circuit representation at 0≤ωt≤π/3

Figure 2.13 Output voltage wave form of three phase VSI

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2.4 FOUR SWITCH VOLTAGE SOURCE INVERTER

In the previous section, a circuit topology of three phase voltage

source inverter composed of three legs with six switches and an operating
principle of the same are presented. Output of the inverter is three phase
alternating voltage which is fed to three phase RL load.

In recent technology, three phase voltage source inverters with four

switches are mainly used in the applications of power electronics, as it consists
of four switches in two legs and third leg is DC link capacitor voltage. Due to
less number of switches, the cost, switching losses and chances of destroying
the power switches are comparatively less. So that four switch voltage source
inverters are preferred over six switch voltage source inverters.

2.4.1 Circuit Topology of Four Switch VSI

Figure 2.14 shows that a circuit topology of Four Switch Voltage

Source Inverter. It is composed of two legs with four switches namely S1 to
S 4 and DC link voltage. Three phase AC output is taken from the mid-points

of each leg and it is fed to three phase load. Pair of switches S1 and S 2 are
engaged with series connection in the first leg. Similarly remaining switches
S3 and S 4 occupies the second leg. In this type of inverter, DC voltage link is

to be considered as third leg.

 47

Figure 2.14 Proposed circuit topology of four switch voltage source

inverter with two legs

2.4.2 The General VSI Modeling

Modeling of VSI can be formed by defining switching functions (SF)

and forming set of equations for passive components. SF’s for upper switches
are defined as follows.

Sk+ = 1, if the switch is on

Sk+ = 0, if the switch is off

Sk- is complementary SF’s for the bottom devices. Consider upper switch of
the kth leg. If bottom switch turned off, an upper diode conducts the negative
current. Then SF for the upper diode using AND operator () is given by

Dk   S k   ik  0 (2.1)
Similarly,
Dk   S k   ik  0 (2.2)
 48

The generalized SF’s are defined as


 
S k   S k   ik  0  S k   ik  0
(2.3)


S k   S k   ik  0  S k   ik  0 

The left of ‘OR’ operator () represents device conduction while the
right one represents the diode conduction.

Due to RL load, load current can be found as follows

dik
Vkn  R ik  L
dt (2.4)
1
Vkn  Ri k d
L
ik 
(2.5)
To obtain an inverter complete model, DC link equations are considered and
the expression of the DC link voltage is written as

1   
VC 
C  
 i dc   k k  d
i S (2.6)

2.4.3 Modeling of VSI under the fault condition

Modeling of VSI with RL load can be achieved by the concepts of

healthy device binary variables (HDBV) and healthy leg binary variables
(HLBV). Such variables allow the management of both faulty and un-faulty
conditions. Under the fault condition, HDBV is defined as

If the upper (+)/ the bottom (-) device is healthy, hk   1

Otherwise it is ‘0’
 49

So the generalized SF’s are defined as



S k   hk  S k   ik  0  hk  S k   ik  0
(2.7)


S k   hk  S k   ik  0  hk  S k   ik  0 

HLBV are introduced under the fault conditions and defined as

hk  hk   hk 

1  t 

VC    i dc  H k S k i k d
 t

C   (2.8)
Where
h 0
H k   1 
0 h2 

hk = healthy inverter leg variable

h  = healthy inverter device variable

k

2.4.4 Mathematical Modeling of Four Switch VSI

Consider, three phase voltage source inverter with star connected

three phase load. Three phase sinusoidal voltages are defined as follows.

Va  Vm sin t (2.9)

2
Vb  Vm sin(t  ) (2.10)
3
2
Vc  Vm sin(t  ) (2.11)
3
 50

For the topology of Figure 2.14, since only two phases and the three
phase load (star connected) neutral are connected to the inverter, the
fundamental RMS current amplitudes in the phases are increased by a factor of
√3 in order to maintain the same rated performance. So, the DC capacitor
value should be doubled. Covic & G. L (1997) proposed a compensation
technique for DC link imbalance in four switch VSI drives. DC-link with the
three phase converter can be extended to three phase four leg converters
(Jacobina et al 2007).

Since, there is no control in DC link leg, only two phase voltages are
given by the following equations.


Van  Va  Vb  3Vm sin(t  ) (2.12)
6

Vbn  Vb  Vc  3Vm sin(t  ) (2.13)
2
Vcn  Vc  Vc  0 (2.14)

To get desired line to ground voltages, switching function can be determined

Van   S1 S 2   Vdc 
V    S S 4    Vdc  (2.15)
 bn   3

where S1  S 2  1 S3  S 4  1 0  Sn  1 n  1   4
(2.16)

From the equations (2.4), (2.5) and (2.7), switching functions can be solved as

1   
S1  1  a sin t   (2.17)
2  6 
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1   
S2  1  a sin t   (2.18)
2  6 

1   
S3  1  a sin t   (2.19)
2  2 

1   
S4  1  a sin t   (2.20)
2  2 

V 
a  3  m 
where,  V dc 

With refer to Figure 2.14, DC link currents can be represented as

T
 ic1   S1 S 2  ibn 
i    S S 4  ian 
 c2   3 (2.21)

im     3 
ic1  sin  t      aim cos 
2   2  4  (2.22)

im     3 
ic 2  sin  t      aim cos 
2  2  4  (2.23)

2.4.5 Operating Modes of Four Switch VSI

Regarding the modes of operation, there are four switching modes and
three voltage vectors ( Va , Vb and Vc ) in four switch voltage source inverter.
The conduction state of power switches is represented with binary variables
either ‘1’ or ‘0’. When an upper level switch of any leg is closed or on, switch
 52

state is indicated by ‘1’. When a lower level switch of any leg is closed or on,
it represents ‘0’.

In general, output phase voltages of four switch VSI with three phase
load are determined from the following equations 2.16 to 2.19 by substituting
the values of switching functions ( S1 and S3 ) as shown in Table 2.4.

Vdc
Va  (4S1  2S 3  1) (2.24)
3
Vdc
Vb  (2S1  4S 3  1) (2.25)
3
Vdc
Vc  (2S1  2S 3  2) (2.26)
3

Table 2.4 Switching functions and output voltage vectors for FSVSI

Output voltage Switching function

Switching
Mode S3
state S1
Va Vb Vc (second
(first leg)
leg)
Vdc Vdc 2V dc
1 S 2 and S 4   0 0
3 3 3
2 S 2 and S 3  Vdc Vdc 0 0 1

3 S1 and S 4 Vdc  Vdc 0 1 0

V dc V dc 2V dc
4 S1 and S 3  1 1
3 3 3

Mode 1

In this mode, the power switches S 2 and S 4 conduct simultaneously.

Output phase voltage equations Va , Vb and Vc are determined by the switching

 53

functions ( S1 and S3 ) and by the two DC-link voltages Vdc . Circuit topology

for this mode is shown in Figure 2.15. Here, switching function is S1 = 0 and

S3 = 0, it means, lower switches of both legs are turned -on.

Vdc V 2V
Hence, Va =  , Vb =  dc , Vc = dc
3 3 3

Figure 2.15 Mode of operation when S1 = 0 , S3=0

Mode 2

In this mode, the power switches S 2 and S 3 conduct simultaneously.

Output voltage vectors Va , Vb and Vc are determined by the gating signals of

the two leg switches and by the two DC-link voltages Vdc . Figure 2.16 shows a

mode of operation for this mode. Here, switching function is S1 = 0 and S3 = 1,

it means, lower switch of first leg and upper switch of second leg are turned -
on.

Hence, Va =  Vdc , Vb = Vdc , Vc = 0

 54

Figure 2.16 Mode of operation when S1 = 0, S3=1

Mode 3

In this mode, the power switches S1 and S 4 conduct simultaneously.

Output voltage vectors Va , Vb and Vc are determined by the gating signals of
the two leg switches and by the two DC-link voltages Vdc . Here, switching

function is S1 = 1 and S3 = 0, it means, upper switch of the first leg and lower
switch of second leg are turned -on. Switching conduction is shown in Figure
2.17.

Hence, Va = Vdc , Vb =  Vdc , Vc = 0

Figure 2.17 Mode of operation when S1 = 1, S3=0

 55

Mode 4

In this mode, the power switches S1 and S 3 conduct simultaneously.

Output voltage vectors Va , Vb and Vc are determined by the gating signals of
the two leg switches and by the two DC-link voltages Vdc . Here, switching

function is S1 = 1 and S3 = 1, it means, upper switches of both legs are turned-

on. Mode of operation is given in Figure 2.18.

V dc V 2V
Hence, Va = , Vb = dc , Vc =  dc
3 3 3

Figure 2.18 Mode of operation when S1 = 1, S3=1

2.5 SUMMARY

The details of voltage source inverters, classifications of voltage

source inverters with circuit topologies and operating principles are discussed
in this chapter. The next chapter deals the concepts of fault tolerant control on
four switch voltage source inverter.