A fast phase tracking reference-less all-digital CDR circuit for human body

channel communication

Proposed Title

An Adaptive N-Phase Tunable reference based CDR circuit for Body

channel communication

Objective

To design a N-Phase adaptive tunable reference and configurable CDR circuit

Abstract

As integration circuit and biomedical technologies continue to develop rapidly,

wearable personal entertainment and healthcare devices have become very
popular electronics products in recent years. Conventional medical healthcare
devices, such as electromyography (EMG) and electrocardiography (ECG), use
the wire line to transfer the physiological signals, which may cause
inconvenience for the patients. In the existing system ADCDR uses the novel
phase-error calculation without a reference clock signal to improve the phase-
tracking ability and reduce overall power consumption by eliminating the
requirement for an external quartz crystal oscillator. In the proposed system
design of an adaptive N-Phase tunable clock reference is designed for CDR
circuit. The N phase circuit is designed in a configurable manner in which the
required phase can be tuned with the high speed clock tree synthesizing circuit
designed in the system. CDR circuit is enabled to recover the clock issues in an
efficient way. The proposed architecture is focused on Low power design and
achieving reduced area utilization.

Existing System

In the existing system ADCDR uses the novel phase-error calculation without a
reference clock signal to improve the phase-tracking ability and reduce overall
power consumption by eliminating the requirement for an external quartz
crystal oscillator.

Problem Statement

 When high speed clock frequencies tuned, the system is not getting
adopted with the phase change

Proposed System

In the proposed system design of an adaptive N-Phase tunable clock reference

is designed for CDR circuit. The N phase circuit is designed in a configurable
manner in which the required phase can be tuned with the high speed clock
tree synthesizing circuit designed in the system. CDR circuit is enabled to
recover the clock issues in an efficient way. The proposed architecture is
focused on Low power design and achieving reduced area utilization.

Solution Statement

N-Phase tunable clock generation circuit

Scope of the study

 This study enable us to get deep knowledge on requirements of CDR

circuits in BCC systems
 This study focus on learning objective on Low power VLSI design

Software Requirements

 MENTOR Graphics – MODELSIM 6.3 G altera

 XILINX ISE 12.5
 Language VHDL

Hardware Requirements

XILINX XC9572XL (Optional)