SAHYADRI

COLLEGE OF ENGINEERING & MANAGEMENT

MANGALURU
DEPARTMENT OF INFORMATION SCIENCE & ENGINEERING
QUESTION
Course Title : Microcontroller and Embedded Systems BANKCourse Code: 18CS44
Faculty: Mr. Ganaraj K Sem : IV

MODULE - I

1 Differentiate Microprocessors and Microcontrollers.

2 Explain RISC design philosophy.
3 Explain the role of ARM in developing flexible embedded processor.
4 Differentiate between CISC & RISC architecture.
5 Summarize ARM design philosophy as applicable to embedded systems.
6 Discuss how the ARM instruction set differs from the pure RISC definition, that
makes the ARM instruction set suitable for embedded applications.
7 Explain the hardware components of embedded systems with necessary diagram./
Discuss ARM based embedded device microcontroller.
8 Explain a typical embedded device based on an ARM core with the help of neat
diagram.
9 Discuss ARM bus technology / Discuss AMBA bus protocol.
10 Narrate the memory trade-offs, that has to be considered while designing memory
system for embedded systems.
11 Write a note on peripherals and controllers.
12 With neat diagram explain the software components required to control an
embedded system.
13 Discuss the applications of ARM processors.
14 Differentiate between DRAM and SRAM.
15 Explain Von Neumann implementation of the ARM with a neat diagram./
Illustrate the working of ARM core DataFlow model
16 Discuss the basic layout of a generic program status register./ Discuss cspr in
detail with a neat diagram.
17 Explain complete ARM register bank.
18 List and explain seven ARM processor modes. Also, explain ARM core changing
from user mode to interrupt request mode on an exception, with a neat diagram.
19 What is pipeline? Compare different pipelinng techniques used in different ARM
processors.
20 Justify the statement: The ARM pipeline will not process an instruction, until it
passes completely through the execute stage.
21 What is Exception and Interrupt? Discuss about handling Exception and Interrupt
using Vector Table.
22 Discuss hardware extensions for ARM core.
23 Write a note on:
a. Complete ARM Register Set
b. Instruction Sets / ARM, Thumb, and Jazzel Instruction Sets
c. Interrupt Masks
d. Condition Flags
e. Conditional Execution
f. Coprocessors

MODULE – II

1. Explain data processing instructions./ Explain various formats of Arithmetic

instruction based on operands
2. Explain the concept of Barrel shifter for data processing instructions. / Illustrate barrel
shifter with an examples.
3. If (PRE) cpsr = nzcvqiFt_USER, r0 = 0x00000000, r1 = 0x80000004 and
MOVS r0, r1, LSL #1 is executed; compute the POST conditions.
4. If (PRE) cpsr = nzcvqiFt_USER, r1 = 0x00000001 and SUBS r1, r1, #1 is executed;
compute the POST conditions.
5. Differentiate between MUL and MLA instructions with an example.
6. If (PRE) r0 = 0x00000000, r1 = 0x00000000, r2 = 0xf0000002 r3 = 0x00000002,
UMULL r0, r1, r2, r3 is executed; compute the POST conditions.
7. Briefly explain branch instructions.
8. Categorize index methods for single-register load-store instructions with
examples.
9. Explain single-register/ multiple register load-store addressing modes with
examples.
10. Compare word or unsigned byte single-register load-store addressing modes.
11. Compare halfword, signed halfword, signed byte and double word single-register
load-store addressing modes.
12. With syntax and examples, explain the addressing modes for load-store multiple
instructions.
13. Construct load-store multiple pairs when base update used with suitable example.
14. With neat diagram and example, explain block memory transfer in the memory
map using load-store multiple instructions.
15. Let r9 = 0x00005000, r10 = 0x00001000, r11 = 0x00005100 and following
instructions are executed:
Loop
LDMIA r9!, {r0 – r7}
STMIA r10!, {r0 – r7}
CMP r9, r11
BNE Loop
Explain the purpose of executing the above set of instructions with diagram.

16. Explain stack operation of ARM processors. Also explain the load-store multiple
addressing aliases available to support stack operations.
17. Write a small piece of code that checks for stack overflow errors for a descending
stack.
18. Write a code fragment to determine what SWI number is being called and then place
that number into register r10.
19. Write a code fragment to
a. Copy the cpsr into register r1
b. Clear bit 7 of r1
c. Copy the register r1 back to cpsr
20. Write code fragments for –
a. Enable IRQ, Disable IRQ
b. Enable FIQ, Disable FIQ
21. Write a note on –
a. Swap instruction.
b. Software interrupt instruction.
c. Program status register instruction
d. Coprocessor instructions.
 e. Loading constants.
22. Explain the following ARM Instructions with examples:

23. How to convert a C function to an assembly function? Explain with an example.

24. How to call a subroutine from an assembly routine? Explain with example.
25. Write a function in assembly that can sum any number of integers. The arguments
should be the number of integers to sum followed by a list of the integers.
26. Write a note on:
a. Profiler and Cycle Counter.
b. ARM Pipeline and Dependencies.
27. With example, explain a one-cycle interlock caused by load use.
28. With example, explain why a branch instruction takes three cycles.
29. Justify with example: Careful scheduling of load instructions so that pipeline stalls
don’t occur can improve performance.
30. Write short note on:
a. Register Allocation
b. Allocating Variables to Register Numbers
31. Differentiate negative indexing and logarithmic indexing with examples.
32. Explain the comparison instructions with example.
33. Justify the statement with Examples: By combining conditional execution and
conditional setting of the flags, you can implement simple if statements without any
need for branches.
34.