Sei sulla pagina 1di 29

Rectiers

Dr. Pramod R. Bokde

July 1, 2019

Contents

1 Introduction / Need of Rectier 3

2 Rectiers 3

3 Half Wave Rectier 4

3.1 Construction of HWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.2 Operation of Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3.3 Mathematical Analysis of Half wave Rectier Circuit . . . . . . . . . . . . . 6

3.3.1 Average DC Load Current (IDC ) . . . . . . . . . . . . . . . . . . . . . 6

3.3.2 Average DC Load Voltage (ED C ) . . . . . . . . . . . . . . . . . . . . 7

3.3.3 RMS value of Load Current (Irms ) . . . . . . . . . . . . . . . . . . . 8

3.3.4 D.C. Power Output (PDC ) . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3.5 AC Power Input (PAC ) . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.3.6 Rectier Eciency (η ) . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3.7 Ripple Factor (γ ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1
EDC Rectiers Dr. P.R. Bokde

3.3.8 Peak Inverse Voltage (PIV) . . . . . . . . . . . . . . . . . . . . . . . 10

3.4 Disadvantages of Half Wave Rectier . . . . . . . . . . . . . . . . . . . . . . 11

4 Centre Tapped Full Wave Rectier 11

4.1 Operation of the circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 Mathematical Analysis of Centre Tapped Full Wave Rectier . . . . . . . . . 14

4.2.1 Average DC Load Current (IDC ) . . . . . . . . . . . . . . . . . . . . . 14

4.2.2 Average DC Load Voltage(EDC ) . . . . . . . . . . . . . . . . . . . . . 15

4.2.3 RMS Load Current IRM S . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2.4 DC Power Output (PDC ) . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2.5 AC Power Input (PAC ) . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2.6 Rectier Eciency (η) . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2.7 Ripple Factor (γ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2.8 Peak Inverse Voltage (P IV ) . . . . . . . . . . . . . . . . . . . . . . . 18

4.3 Comparison of Full Wave and Half Wave Circuit . . . . . . . . . . . . . . . . 18

5 Bridge Rectier 19

5.1 Operation of Bridge Rectier . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2 Advantages of Bridge Rectier Circuit . . . . . . . . . . . . . . . . . . . . . 21

5.3 Disadvantages of Bridge Rectier . . . . . . . . . . . . . . . . . . . . . . . . 21

6 Comparison of Rectier Circuits 22

7 Introduction to Filter 22

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8 Capacitor input Filter 24

8.1 Operation of Capacitor Filter . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.2 Expression for Ripple Factor for Capacitor Input Filter . . . . . . . . . . . . 26

9 Questions asked in RTM Nagpur University Examinations 28

1 Introduction / Need of Rectier

A d.c. power supply is an important element of any type of an electronic circuit.


In everyday life, we are using number of electronic devices such as transistors,
deck, TV, VCR which operate fully or partly on d.c. supply in the range of 0 to
24 V. The successful operation of the device depends on the proper functioning
of the d.c. power supply. The power supply tries to provide a smooth, constant
d.c. voltage, as required by an electronic device. As we know, MSEB provides
a power supply of an alternationg type (a.c.) of 230 V, 50 Hz. Hence to convert
a.c. supply to d.c. we need Rectiers.

2 Rectiers

A rectier is a device which converts a.c. voltage to pulsating d.c. voltage,


using one or more p-n junction diode.

The p-n junction diode conducts only in one direction. It conducts


when forward biased while practically it does not conduct when reverse biased.
thus if an alternating voltage is applied across a p-n junction diode, during
positive half cycle the diode will be forward biased and will conduct successfully.
while during the negative half cycle, it will be reverse biased and will not
conduct at all. thus the conduction occurs only during positive half cycle. If
the resistance is connected in series with the diode, the output voltage across
the resistance will be unidirectional i.e. d.c. Thus p-n junction diode subjected
to an a.c. voltage acts as a rectier converting alternating voltage to a pulsating
d.c. voltage.

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Using one or more dioces, following rectier circuits can be designed.

1. Half Wave Rectier(HWR)


2. Centre Tapped Full Wave Rectier
3. Bridge Rectier.

3 Half Wave Rectier

In half wave rectier, rectifying element conducts only during positive half cycle
of input a.c. supply. The negative half cycles of a.c. supply are eliminated from
the output.

3.1 Construction of HWR

This rectier circuit consists of resistive load, rectifying element, i.e. p-n junc-
tion diode, and the source of a.c. voltage, all connected in series. The circuit
diagram is shown in g. 1. Usually, the rectier circuit is operated from a.c.
mains supply. To obtain the desired d.c. voltage across the load, the a.c. voltage
is applied to rectier circuit using suitable step-up or step-down transformer,
mostly a step-down one, with necessary turns ratio.

Figure 1: Half Wave Rectier

The input voltage to the half wave rectier circuit shown in g 1 is


a sinusoidal a.c. voltage, having a frequency which is the supply frequency, 50
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Hz.

The transformer decides the peak value of the secondary voltage. If


the N1 are primary number of turns and N2 are secondary number of turns and
Epm is the peak value of the primary voltage then,
N2 Esm
=
N1 Epm
where Esm is the peak value of the secondary a.c. voltage.

As the nature of Esm is sinusoidal the instantaneous value will be


es = Esm sin ωt

ω = 2πf
f = supplyf requency

Let Rf represents the forward resistance of the diode. Assume that,


under reverse bias condition, the diode acts almost as open circuit, conducting
no current.

3.2 Operation of Circuit

During the positive half cycle of secondary a.c voltage, terminal (A) becomes
more positive with respect to terminal (B). The diode is forward biased and
the current ows in the circuit in the clockwise direction, as shown in g 1.
The current will ow for almost full positive cycle. This current is also owing
through load resistance RL , hence denoted as iL , the load current.

During negative half cycle when terminal (A) is negative with respect
to terminal (B), diode becomes reverse biased. Hence no current ows in the
circuit. Thus the circuit current, which is also the load current, is in the form
of half sinusoidal pulses.

The load voltage, being the product of load current and load resis-
tance, will also be in the form of half sinusoidal pulses. The dierent waveforms
are illustrated in g. 2
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Figure 2: Load current and Load voltage waveforms for half wave rectier

The d.c. output waveform is expected to be a straight line but the


half wave rectier gives output in the form of positive sinusoidal pulses. Hence
the output is called pulsating d.c. It is discontinuous in nature.

3.3 Mathematical Analysis of Half wave Rectier Circuit

3.3.1 Average DC Load Current (IDC )

The average or dc value of alternating current is obtained by integration. For


nding out the average value of an alternating waveform, we have to determine
the area under the curve over one complete cycle i.e. from 0 to 2π and then
dividing it by the base i.e. 2π .

Mathematically, the expression for load current is given by,


iL = Im sin ωt f or0 ≤ ωt ≤ π

iL = 0 f orπ ≤ ωt ≤ 2π

where, Im is the peak value of load current.


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Z 2π Z 2π
1 1
IDC = iL d(ωt) = Im sin(ωt)d(ωt)
2π 0 2π 0
As no current ows during negative half cycle of a.c. input voltage, ie. between
ωt = π to ωt = 2π we change the limits of integration.
Im π
Z
IDC = sin(ωt)d(ωt)
2π 0
Im
IDC = [− cos(ωt)]π0

Im
IDC = [cos(π) − cos(0)]

Im
IDC = − [−1 − 1]

Im
IDC = = averagevalue
π
Applying Kircho's voltage law, we can write,

Esm
Im =
Rf + RL + RS
where, Rs = resistance of secondary winding of transformer. If Rs is not given
it should be neglected while calculating Im .

3.3.2 Average DC Load Voltage (ED C )

It is the product of average D.C. load current and the load resistance RL .
EDC = IDC RL

Substituting value of IDC ,


Im
EDC = RL
π
Esm
EDC = RL
(Rf + RL + RS )π
The winding resistance RS and forward diode resistance Rf are practically very
small compared to RL , So neglecting RS and Rf , We get
Esm
EDC =
π
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3.3.3 RMS value of Load Current (Irms )

The RMS means squaring, nding mean and then nding square root. Hence
RMS value of load current can be obtained as,
s Z π
1
Irms = (Im sin ωt)2 d(ωt)
2π 0
s Z π
1 2 sin2 ωt)d(ωt)
Irms = (Im
2π 0
s
π
[1 − cos(2ωt)]d(ωt)
Z
1
Irms =
2π 0 2
r
1 ωt sin(2ωt) π
Irms = { − }0

r  2 4
1 π
Irms = Im
2π 2
Im
Irms =
2

3.3.4 D.C. Power Output (PDC )

The D.C. output power can be obtained as,


2
PDC = EDC IDC = IDC RL
 2
Im
PDC = RL
π
2
Im
PDC = 2 RL
π
Esm
But, Im =
Rf + RL + RS
2
Esm RL
PDC =
π 2 [Rf + RL + RS ]2

3.3.5 AC Power Input (PAC )

The power input taken from the secondary of transformer is the power supplied
to three resistances namely load resistance RL , the diode resistance Rf and
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winding resistance RS . The a.c. power is given by,


2
PAC = IRM S [RL + Rf + RS ]
Im
but, IRM S =
2
I2
PAC = m [RL + Rf + RS ]
4

3.3.6 Rectier Eciency (η)

The rectifer eciency is dened as the ratio of output d.c. power to input a.c.
power.
D.C.OutputP ower PDC
η= =
A.C.inputP ower PAC
2
Im
π 2 RL
η= 2
Im
[Rf + RL + RS ]
4
4

π 2 RL
η=
(Rf + RL + RS )
As (Rf + RS ) is very small as compared to RL , neglecting (Rf + RS ), we get
%ηmax = 0.406 × 100 = 40.6%

Thus in half wave rectier, maximum 40.6 % a.c. power gets converted to
d.c. power in the load. If the eciency of rectier is 40 % then the remaining
60 % power is present in terms of ripples in the output which is uctuating
component present in the output.

3.3.7 Ripple Factor (γ )

It is seen that the output of half wave rectier is not pure d.c but pulsating d.c..
The output contain pulsating components called ripples. Ideally there should
not be any ripples in the rectier output. The measure of such ripples present
in the output is with the help of a factor called ripple factor denoted by γ .
It tells how smooth is the output. Smaller the ripple factor closer the output

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to a pure d.c. The ripple factor expresses how much successful the circuit in
obtaining pure d.c. from a.c. input.

Mathematically ripple factor is dened as the ratio of RMS value of


the a.c. component to the average or d.c. component.

The general expression for ripple factor is -


s 2
IRM S
γ= −1
IDC

Now for Half wave rectiifer circuit,


Im
IRM S =
2
Im
IDC =
π
Putting these values in expression for ripple factor, we get
γ = 1.21

This indicates that the ripple content in the output are 1.211 times the d.c.
component i.e. 121.11 % of d.c. component. The ripple factor for half wave is
very high which indicates that the half wave circuit is a poor converter of a.c.
to d.c. The ripple factor is minimized using lter circuits along with rectiers.

3.3.8 Peak Inverse Voltage (PIV)

The Peak Inverse Voltage is the peak voltage across the diode in the reverse
direction i.e. when the diode is reverse biased. In half wave rectier, the load
current is ideally zero when the diode is reverse biased and hence the maximum
value of the voltage that can exist across the diode is nothing but Esm .

Therefore, PIV of diode = Esm = Maximum value of secondary volt-


age.

This is called PIV rating of a diode.

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3.4 Disadvantages of Half Wave Rectier

1. The ripple factor of half wave rectier circuit is 1.21, which is quite high.
The output contains lot of varying components.
2. The maximum theoretical rectication eciency is found to be 40 % . The
practical value will be less than this. This indicates that half wave rectier
is quite inecient.
3. The circuit has low transformer utilization factor, showing that the trans-
former is not fully utilized.
4. The dc current is owing through the secondary winding of the trans-
former which may cause d.c. saturation of the core of the transformer. To
minimize the saturation, transformer size have to be increased accordingly.
This increases the cost.

Because of all these disadvantages, the half wave rectier circuit is normally
not used as a power rectier circuit.

4 Centre Tapped Full Wave Rectier

The full wave rectier conducts during both positive and negative half cycles
of input a.c. supply. In order to rectify both the half cycles of a.c. input, two
diodes are used in this circuit. The diodes feed a common load RL with the
help of a center tap transformer. The a.c. voltage is applied through a suitable
power transformer with proper turns ratio.

The full wave rectier circuit is shown in g 3 .

4.1 Operation of the circuit

Consider the positive half cycle of ac input voltage in which terminal (A) is
positive and terminal (B) is negative. The diode D1 will be forward bised and
hence will conduct; while diode D2 will be reverse biased and will act as open
circuit and will not conduct. This is shown in g 3.
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Figure 3: Centre Tapped Full Wave Rectier

Figure 4: Durrent ow during positive half cycle

The diode D1 supplies the load current i.e. iL = id1 . this current is
owing through upper half of secondary winding while lower half of secondary
winding of the transformer carries no current since diode D2 is reverse biased
and acts as open circuit.

In the next half cycle of a.c. voltage, polarity reverses and terminal
(A) becomes negative and (B) positive. The diode D2 conducts, being forward
biased, while D1 does not, being reverse biased. This is shown in g 4.

The diode D2 supplies the load current i.e. iL = id2 . Now the lower
half of the secondary winding carries the current but the upper half does not.

It is noted that the load current ows in both half cycles of


a.c. voltage and in the same direction through the load resistance.
Hence we get rectied output across the load. The load current is the sum of

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Figure 5: Current ow duirng negative half cycle

individual diode currents owing in corresponding half cycles. It is also noted


that thw two diodes do not conduct simultaneously but in alternate half cycles.
The individual diode current and the load current are shown in g. 5.

Figure 6: Load Current and voltage waveforms of full wave rectier

Thus the full wave rectier circuit essentially consists of two half-
wave rectier circuits working independently (working in alternate half cycles
of a.c.) of each other but feeding a common load. The output load current is
still pulsating d.c. and not pure d.c.
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4.2 Mathematical Analysis of Centre Tapped Full Wave Rectier

4.2.1 Average DC Load Current (IDC )

Consider one cycle of load current iL from 0 to 2π to obtain the average value
which is d.c. value of load current.
iL = Im sin(ωt) f or 0 ≤ ωt ≤ π

But for π to 2π , the current iL is again positive while sin ωt term is negative
during π to 2π . Hence in the region π to 2π the positive iL can be represented
as negative of Im sin(ωt).
iL = −Im sin(ωt) f or π ≤ ωt ≤ 2π

Therefore
Z 2π
1
IDC = iL d(ωt)
2π 0
Z π Z 2π 
1
IDC = Im sin ωtd(ωt) + −Im sinωtd(ωt)
2π 0 π
Z π Z 2π 
1
IDC = Im sin ωtd(ωt) − Im sinωtd(ωt)
2π 0 π
Im h π 2π
i
IDC = (− cos ωt)0 − (− cos ωt)π

Im
IDC = [− cos π + cos 0 + cos 2π − cosπ]

Im
IDC = [−(−1) + 1 + 1 − (−1)]

4Im
IDC =

2Im
IDC =
π

For half wave it is Iπm and full wave rectier is the combination of two half wave
circuits alternately in two half cycles of input. Hence obviously the d.c. value
for full wave circuit is 2Iπm .

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4.2.2 Average DC Load Voltage(EDC )

The d.c. load voltage is


EDC = IDC RL
2Im RL
EDC =
π
Substituting value of Im ,
2Esm RL
EDC =
π(Rf + RS + RL )
But, as Rf and RS is very small as compared to RL neglecting RS and Rf , we
get
2Esm
EDC =
π

4.2.3 RMS Load Current IRM S

The R.M.S. value of current, IRM S is obtained as follows:


s
Z 2π
1
IRM S = i2L d(ωt)
2π 0

Since two half wave rectier are similar in operation we can write,
s Z π
2
IRM S = [Im sin ωt]2 d(ωt)
2π 0
s Z 
1 π 1 − cos 2ωt

IRM S = Im d(ωt)
π 0 2
s   π 
1 π sin 2ωt
IRM S = Im [ωt]0 −
2π 2 0
r
1
IRM S = Im [π − 0]
r 2π
1
IRM S = Im (π)

Im
IRM S =√
2
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4.2.4 DC Power Output (PDC )

2
PDC = EDC IDC = IDC RL
2
PDC = IDC RL
 2
2Im
PDC = RL
π
4 2
PDC = 2 Im RL
π

Substituting value of Im we get,


2
4 Esm
PDC = 2 × RL
π (RS + Rf + RL )

4.2.5 AC Power Input (PAC )

The a.c. power input is given by,


2
PAC = IRM S (Rf + RS + RL )
 2
Im
PAC = √ (Rs + Rf + RL )
2
2
Im (Rf + RS + RL )
PAC =
2

Substituting value of Im we get,


2
Esm 1
PAC = × × (Rf + RS + RL )
(Rf + RS + RL )2 2
2
Esm
PAC =
2(Rf + RS + RL )

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4.2.6 Rectier Eciency (η)

PDC output
η=
PAC input
4 2
π 2 Im RL
η= 2 (R +R +R )
Im f S L
2
8RL
η=
π 2 (Rf + RL + RL )
But , if Rf + RS is very small as compared to RL , neglecting it from denomi-
nator, we get
8 RL
η=
π 2 RL
8
η= 2
π
8
%ηmax = 2 × 100 = 81.2%
π
This is the maximum theoretical eciency of full wave rectier.

4.2.7 Ripple Factor (γ)

The general expression for ripple factor is :


s 2
IRM S
γ= −1
IDC

Now for Full wave rectiifer circuit,


Im
IRM S = √
2
2Im
IDC =
π
Putting these values in expression for ripple factor, we get
v
u" Im #2
u √
γ = t 2Im2 − 1
π
r
π2
γ= −1
8
γ = 0.48

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This indicates that the ripple contents in the output are 48 % of the d.c. com-
ponent which is much less than that for half wave circuit.

4.2.8 Peak Inverse Voltage (P IV )

It can be observed from the circuit that when the diode is reversed biased then
full transformer secondary voltage gets impressed across it. The drop across
conducting diode is assumed zero. Thus the peak value of the inverse voltage to
which diode gets subjected is voltage across both the parts of the transformer
secondary.
P IV of diode = 2Esm
= πEDC at IDC = 0
where Esm = maximum value of a.c. voltage across half the transformer sec-
ondary.

4.3 Comparison of Full Wave and Half Wave Circuit

1. The d.c. load current in case of full wave circuit is twice to that in half
wave circuit; similarly the D.C. load voltage in full wave circuit is twice
that in half wave circuit.
2. The lowest ripple frequency in full wave circuit is twice that in half wave
circuit. Now to remove ripple the additional circuits called lter circuit
are used along with rectier circuits. But as the frequency is more in
full wave, the capacitor values required in capacitance lter are much less
hence smaller elements are sucient in lter circuits used with full wave
circuit to reduce ripple.
3. Because there is no net d.c. current through windings of the transformer
used in full wave rectier circuit, the losses are less as compared to losses
in transformer used in half wave circuit.
4. The full wave connection gives d.c. power output four times as large, when
compared with half wave connection.
5. The eciency of rectication in a full wave connection is twice that for
half wave connection.
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6. The ripple factor is less for full wave , ie. rectication is more nearly
complete for full wave as compared to half-wave.

5 Bridge Rectier

The basic bridge rectier circuits is as shown in g. 7 .

Figure 7: Bridge Rectier Circuit

The bridge rectier circuit is essentially a full wave rectier circuit,


using four diodes, forming the four arms of an electrical bridge. To one of the
diagonal of the bridge, the a.c. voltage is applied through a transformer and
the rectied d.c. voltage is taken from the other diagonal of the bridge. The
main advantage of this circuit is that it does not require a centre tap on the
secondary winding of the transformer. Hence whenever possible, a.c. voltage
can be directly applied to the bridge.

5.1 Operation of Bridge Rectier

Consider the positive half of a.c input votlage. The point A of secondary
becomes positive. The diodes D1 and D2 will be forward biased, while D3 and
D4 reverse biased. The two diodes D1 and D2 conduct in series with the load
and the current ows as shown in g. 8.

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Figure 8: Current owing during positive half cycle.

In the next half cycle, when the polarity of a.c. voltage reverses hence
point B becomes positive. Diode D3 and D4 are forward biased, while D1 and
D2 reverse biased. Now the diodes D3 and D4 conduct in series with the load
and the current ows as shown in g. 9.

Figure 9: Current owing during negative half cycle.

As seen that in both cycles of a.c., the load current is owing in the
same direction, hence we get a full wave rectied output.

The waveforms of load current and voltage remains exactly same as


shown before for full wave centre tapped rectier.

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5.2 Advantages of Bridge Rectier Circuit

1. The current in both the primary and secondary of the power transformer
ows for the entire cycle and hence for a given power output, power trans-
former of a small size and less cost my be used.
2. No center tap is required in the transformer secondary. Hence, whenever
possible, a.c. voltage can directly be applied to the bridge.
3. The current in the secondary of the transformer is in opposite direction in
two half cycles. Hence net d.c. component owing is zero which reduces
the losses and danger of saturation.
4. Due to pure alternating current in secondary of transformer, the trans-
former gets utilized eectively and hence the circuit is suitable for appli-
cations where large powers are required.
5. As two diodes conduct in series in each half cycle, inverse votlage appearing
across diodes get shared. Hence the circuit can be used for high voltage
applications. Such a peak reverse voltage appearing across diode is called
peak inverse voltage rating (PIV) of diode.

5.3 Disadvantages of Bridge Rectier

The only disadvantage of bridge rectier is the use of four diodes as compared
to two diodes in centre tapped full wave rectier. This causes additional voltage
drop as indicated by term 2Rf present in expression of Im instead of Rf . This
reduces the output voltage.

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6 Comparison of Rectier Circuits

S.N. Parameters Half Wave Centre Tap Full Wave Bridge Rectier
1 Number of Diodes 1 2 4
2 Average DC Cur- Im
π
2Im
π
2Im
π
rent IDC
3 Average DC volt- Esm
π
2Esm
π
2Esm
π
age EDC
4 RMS Current Im
2
Im

2
Im

2
(Irms )
2 2 2
5 DC Power Output Im RL
π2
4Im
π2
RL 4Im
π2
RL

(PDC )
2 2 2
6 AC Power input Im (RL +Rf +Rs )
4
Im (RL +Rf +Rs )
2
Im (RL +2Rf +Rs )
2
(PAC )
7 Maximum Rec- 40.6 % 81.2 % 81.2 %
tier Eciency
(η)
8 Ripple Factor(γ) 1.21 0.482 0.482
9 Maximum Load Esm
RS +Rf +RL
Esm
RS +Rf +RL
Esm
RS +2Rf +RL
Current (Im )

7 Introduction to Filter

It is seen that the output of a half wave rectier or full wave rectier is not pure
d.c. but it contains uctuations or ripples, which is undesired. To minimize
the ripple in the output, lter circuits are used. These circuits are connected
between the rectier and load as shown in g 10

An a.c. input is applied to the rectier. At the output of the rectier,


there will be DC and ripple voltage present, which is the input to the lter.
Ideally the output of the lter should be pure DC. Practically, the lter circuit
will try to minimize the ripple at the output.

Basically the ripple is a.c. i.e varying with time, which DC is a


constant w.r.t time. Hence in order to separate DC from ripple, the lter

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EDC Rectiers Dr. P.R. Bokde

Figure 10: Power supply using lter and rectier.

circuit should be use components which have widely dierent impedance for
a.c. and d.c. Two such components are inductance and capacitance. Ideally,
the inductance acts as a short circuit for d.c but it has a large impedance for
a.c. Similarly, the capacitor acts as open for d.c. and almost short for a.c. if
the value of capacitance is suciently large enough.

Since ideally, inductance acts as short circuit for d.c., it cannot be


placed in shunt arm across the load, otherwise the d.c. will be shorted. Hence,
in a lter circuit, the inductance is always connected in series with the load.
The inductance used in lter circuits is also called as "choke".

Similarly, since the capacitance is open for d.c., i.e. it blocks d.c.,
hence it cannot be connected in series with the load. It is always connected in
shunt arm, parallel to the load.

Thus lter is an electronic circuit composed of capacitor, inductor or


combination of both and connected between the rectier and the load so as to
convert pulsating d.c. to pure d.c..

There are basically two types of lter circuits,

• Capacitor input lter

• Choke(Inductor) input lter

Looking from the rectier side, if the rst element in the lter circuit
is capacitor, then the lter circuit is called capacitor-input lter. While if the
rst element is an inductor, it is called choke input lter. The choke input lter
PBCOE. Nagpur Page 23 Department of Electronics Engg.
EDC Rectiers Dr. P.R. Bokde

is not in use now a days as inductors are bulky, expensive and consume more
power.

8 Capacitor input Filter

The block schematic of capacitor input lter is shown in g 11, looking from
the rectier side the rst element in lter is a capacitor.

Figure 11:

Figure 12: Capacitor input lter

The g 12 shows a full wave rectier circuit, followed by a capacitor


input lter. The lter uses a single capacitor connected in shunt arm i.e. in
parallel with the load resistance RL . In order to minimize the ripple in the
output, the capacitor C used in the lter circuit is quite large, of the order of
tens of microfarads.

PBCOE. Nagpur Page 24 Department of Electronics Engg.


EDC Rectiers Dr. P.R. Bokde

8.1 Operation of Capacitor Filter

During the rst quarter cycle of the rectied output votlage, obtained from the
rectier circuit, the capacitor C gets charged to peak value Esm . This is shown
in g 13.

Figure 13: Waveform of capacitor lter

Now in the next quarter cycle from π2 to π , the rectier output voltage,
shown dotted starts decreasing. But as capacitor C is charged upto the maxi-
mum value Esm , it makes the conducting diode reverse biased and the diode
stops conducting. The current through diode reduces to zero when capacitor
charges upto Esm which is shown by a shaded portion in g 13.

Now the capacitor C starts discharging through load resistance RL .


As the capacitor C is large, the time constant CRL is large and capacitor
discharges to less extent, from point A to B as shown in g 13. At this point,
it can be seen that the rectier output voltage, in the quarter π to 3π2 exceeds
the capacitor voltage at point B. And the another diode gets forward biased
and starts conducting. The capacitor C, again starts charging and quickly gets
charged through the forward biased diode having very small forward resistance.
The time required by the capacitor to charge to the peak value is quite small
and diode current again reduces to zero.

In this circuit, the two diodes are conducting in alternate half cycles
of the output of the rectier circuit. The diodes are not conducting for the
entire half cycle but only for a part of the half cycle, during which the capac-
itor is getting charged. When the capacitor is discharging through the load
resistance RL , both the diodes are non-conducting. The capacitor supplies the

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EDC Rectiers Dr. P.R. Bokde

load current. As the time required by capacitor to charge is very small and it
discharges very little due to large time constant, hence ripple in the output gets
reduced considerably. Though the diodes conduct partly, the load current gets
maintained due to the capacitor. This tler is very popularly used in practice.

8.2 Expression for Ripple Factor for Capacitor Input Filter

Consider a full wave rectier circuit using a capacitor input lter. The basic
circuit diagram and various waveforms for the circuit are shown in g 14 and
15.

Figure 14: Centre Tapped Full Wave Rectier with Capacitor Filter.

Figure 15: Waveform across the capacitor

Let T2 be the time for half cycle of a.c. input voltage. During the
time interval T1 the diode is conducting and the capacitor C is getting charged.

While in the time interval T2 , the diode is reverse biased and the
capacitor discharges through the load resistance RL .

Let Vr be the peak to peak value of ripple voltage, which is assumed


to be triangular as shown in g 16.
PBCOE. Nagpur Page 26 Department of Electronics Engg.
EDC Rectiers Dr. P.R. Bokde

Figure 16: Triangular approximation of ripple voltage

It can be shown mathematically that the r.m.s. value of such a tri-


angular waveform is
Vr
Vrms = √ (1)
2 3
During the time interval T2 , the capacitor C is discharging through the load
resistance RL . The charge lost is,
Q = CVr (2)
But,
i = dQ (3)
R T2dt
Q = 0 idt (4)
Q = IDC T2 (5)
An integration gives the average or dc value. Hence,
IDC T2 = CVr (6)
IDC T2
∴ Vr = (7)
c
(8)
Now
T
T1 + T2 = (9)
2
Normally, T2  T1 ,
T
∴ T1 + T2 u T2 = (10)
  2
IDC T IDC × T IDC
∴ Vr = = = (11)
C 2 2C 2f C
But,
EDC
IDC = (12)
RL
EDC
∴ Vr = (13)
2f CRL

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EDC Rectiers Dr. P.R. Bokde

Therefore, Ripple Factor,


Vrms
γ= (14)
EDC
EDC
1 Vr
=
2f CRL
√ × since Vrms = √ (15)
2 3 EDC 2 3
Therefore, for full wave rectier with capacitor lter, the ripple factor is
1
γ= √ (16)
4 3f CRL
And, for full wave rectier with capacitor lter, the ripple factor is
1
γ= √ (17)
2 3f CRL
The product CRL is the time constant of the lter circuit.

From the expression of the ripple factor, it is clear that increasing


the value of capacitor C, the ripple factor gets decreased. Thus the output
can be made smoother, reducing the ripple content by selecting large value
of capacitor. Similarly, the another factor controlling the ripple factor is load
resistance RL .

The d.c. output votlage from a capacitor lter fed from a full
wave rectier is given by -
 
1
EDC = Esm − IDC (18)
4f C
While the d.c. output votlage from a capacitor leter fed from a half wave
rectier is given by,  
1
EDC = Esm − IDC (19)
2f C

9 Questions asked in RTM Nagpur University Examina-


tions
Que.1 Draw and explain working of Half Wave Rectier with diode current and
output voltage waveforms. Also derive expression for d.c. output voltage
and rms value of load current. (Summer − 16)(8 − M arks).
PBCOE. Nagpur Page 28 Department of Electronics Engg.
EDC Rectiers Dr. P.R. Bokde

Que.2 What is the signicance of ripple factor and eciency in rectier? Derive
the expression for ripple factor of full wave rectier. (Summer − 17)(7 −
M arks)

Que.3 Explain the working of full wave bridge rectier & derive the expression
for its ripple factor. (W inter − 17)(7 − M arks).
Que.4 Draw the circuit diagram of full wave rectier and explain its operation
with the help of waveforms. (Summer − 18)(6 − M arks)
Que.5 Show that maximum eciency of half wave rectier is 40.6 %. (W inter −
18)(6 − M arks)

Que.6 A half wave rectier supplies a power to 1KΩ load. The input supply
voltage is 220 V rms. Neglecting forward resistance of diode, calculate, (i)
Vrms (ii) Irms (iii) Ripple Factor. (W inter −18, W inter −17)(7−M arks)

Que.7 A 120 V, 50 Hz is applied to a primary of 5:1 step down simple transformer


whose secondary is connected to the four diode in bridge structure allowing
a load resistance of 1KΩ . The diode have forward resistance of 5Ω and
winding resistance of 10Ω . Determine
1. The d.c. voltage across the load.
2. The d.c. current through the load.
3. The d.c. power delivered to the load.
4. The eciency of a rectier circuit.
5. The ripple factor of the rectier circuit.
6. The PIV across each diode
(Summer − 18)(8 − M arks)

Que.8 A full wave rectier is fed from a transformer having centre tapped sec-
ondary winding. The rms voltage from either end of secondary to centre
tap is 30 V. The diode resistance is 2Ω and resistance half of secondary is
8Ω for a load of 1KΩ. Calculate : (i) DC Current (ii) Power delivered to
load (iii) % regulation (iv) Eciency (W inter − 16)(8 − M arks)

PBCOE. Nagpur Page 29 Department of Electronics Engg.

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