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July 1, 2019
Contents
2 Rectiers 3
1
EDC Rectiers Dr. P.R. Bokde
5 Bridge Rectier 19
7 Introduction to Filter 22
2 Rectiers
In half wave rectier, rectifying element conducts only during positive half cycle
of input a.c. supply. The negative half cycles of a.c. supply are eliminated from
the output.
This rectier circuit consists of resistive load, rectifying element, i.e. p-n junc-
tion diode, and the source of a.c. voltage, all connected in series. The circuit
diagram is shown in g. 1. Usually, the rectier circuit is operated from a.c.
mains supply. To obtain the desired d.c. voltage across the load, the a.c. voltage
is applied to rectier circuit using suitable step-up or step-down transformer,
mostly a step-down one, with necessary turns ratio.
Hz.
ω = 2πf
f = supplyf requency
During the positive half cycle of secondary a.c voltage, terminal (A) becomes
more positive with respect to terminal (B). The diode is forward biased and
the current ows in the circuit in the clockwise direction, as shown in g 1.
The current will ow for almost full positive cycle. This current is also owing
through load resistance RL , hence denoted as iL , the load current.
During negative half cycle when terminal (A) is negative with respect
to terminal (B), diode becomes reverse biased. Hence no current ows in the
circuit. Thus the circuit current, which is also the load current, is in the form
of half sinusoidal pulses.
The load voltage, being the product of load current and load resis-
tance, will also be in the form of half sinusoidal pulses. The dierent waveforms
are illustrated in g. 2
PBCOE. Nagpur Page 5 Department of Electronics Engg.
EDC Rectiers Dr. P.R. Bokde
Figure 2: Load current and Load voltage waveforms for half wave rectier
iL = 0 f orπ ≤ ωt ≤ 2π
Z 2π Z 2π
1 1
IDC = iL d(ωt) = Im sin(ωt)d(ωt)
2π 0 2π 0
As no current ows during negative half cycle of a.c. input voltage, ie. between
ωt = π to ωt = 2π we change the limits of integration.
Im π
Z
IDC = sin(ωt)d(ωt)
2π 0
Im
IDC = [− cos(ωt)]π0
2π
Im
IDC = [cos(π) − cos(0)]
2π
Im
IDC = − [−1 − 1]
2π
Im
IDC = = averagevalue
π
Applying Kircho's voltage law, we can write,
Esm
Im =
Rf + RL + RS
where, Rs = resistance of secondary winding of transformer. If Rs is not given
it should be neglected while calculating Im .
It is the product of average D.C. load current and the load resistance RL .
EDC = IDC RL
The RMS means squaring, nding mean and then nding square root. Hence
RMS value of load current can be obtained as,
s Z π
1
Irms = (Im sin ωt)2 d(ωt)
2π 0
s Z π
1 2 sin2 ωt)d(ωt)
Irms = (Im
2π 0
s
π
[1 − cos(2ωt)]d(ωt)
Z
1
Irms =
2π 0 2
r
1 ωt sin(2ωt) π
Irms = { − }0
2π
r 2 4
1 π
Irms = Im
2π 2
Im
Irms =
2
The power input taken from the secondary of transformer is the power supplied
to three resistances namely load resistance RL , the diode resistance Rf and
PBCOE. Nagpur Page 8 Department of Electronics Engg.
EDC Rectiers Dr. P.R. Bokde
The rectifer eciency is dened as the ratio of output d.c. power to input a.c.
power.
D.C.OutputP ower PDC
η= =
A.C.inputP ower PAC
2
Im
π 2 RL
η= 2
Im
[Rf + RL + RS ]
4
4
π 2 RL
η=
(Rf + RL + RS )
As (Rf + RS ) is very small as compared to RL , neglecting (Rf + RS ), we get
%ηmax = 0.406 × 100 = 40.6%
Thus in half wave rectier, maximum 40.6 % a.c. power gets converted to
d.c. power in the load. If the eciency of rectier is 40 % then the remaining
60 % power is present in terms of ripples in the output which is uctuating
component present in the output.
It is seen that the output of half wave rectier is not pure d.c but pulsating d.c..
The output contain pulsating components called ripples. Ideally there should
not be any ripples in the rectier output. The measure of such ripples present
in the output is with the help of a factor called ripple factor denoted by γ .
It tells how smooth is the output. Smaller the ripple factor closer the output
to a pure d.c. The ripple factor expresses how much successful the circuit in
obtaining pure d.c. from a.c. input.
This indicates that the ripple content in the output are 1.211 times the d.c.
component i.e. 121.11 % of d.c. component. The ripple factor for half wave is
very high which indicates that the half wave circuit is a poor converter of a.c.
to d.c. The ripple factor is minimized using lter circuits along with rectiers.
The Peak Inverse Voltage is the peak voltage across the diode in the reverse
direction i.e. when the diode is reverse biased. In half wave rectier, the load
current is ideally zero when the diode is reverse biased and hence the maximum
value of the voltage that can exist across the diode is nothing but Esm .
1. The ripple factor of half wave rectier circuit is 1.21, which is quite high.
The output contains lot of varying components.
2. The maximum theoretical rectication eciency is found to be 40 % . The
practical value will be less than this. This indicates that half wave rectier
is quite inecient.
3. The circuit has low transformer utilization factor, showing that the trans-
former is not fully utilized.
4. The dc current is owing through the secondary winding of the trans-
former which may cause d.c. saturation of the core of the transformer. To
minimize the saturation, transformer size have to be increased accordingly.
This increases the cost.
Because of all these disadvantages, the half wave rectier circuit is normally
not used as a power rectier circuit.
The full wave rectier conducts during both positive and negative half cycles
of input a.c. supply. In order to rectify both the half cycles of a.c. input, two
diodes are used in this circuit. The diodes feed a common load RL with the
help of a center tap transformer. The a.c. voltage is applied through a suitable
power transformer with proper turns ratio.
Consider the positive half cycle of ac input voltage in which terminal (A) is
positive and terminal (B) is negative. The diode D1 will be forward bised and
hence will conduct; while diode D2 will be reverse biased and will act as open
circuit and will not conduct. This is shown in g 3.
PBCOE. Nagpur Page 11 Department of Electronics Engg.
EDC Rectiers Dr. P.R. Bokde
The diode D1 supplies the load current i.e. iL = id1 . this current is
owing through upper half of secondary winding while lower half of secondary
winding of the transformer carries no current since diode D2 is reverse biased
and acts as open circuit.
In the next half cycle of a.c. voltage, polarity reverses and terminal
(A) becomes negative and (B) positive. The diode D2 conducts, being forward
biased, while D1 does not, being reverse biased. This is shown in g 4.
The diode D2 supplies the load current i.e. iL = id2 . Now the lower
half of the secondary winding carries the current but the upper half does not.
Thus the full wave rectier circuit essentially consists of two half-
wave rectier circuits working independently (working in alternate half cycles
of a.c.) of each other but feeding a common load. The output load current is
still pulsating d.c. and not pure d.c.
PBCOE. Nagpur Page 13 Department of Electronics Engg.
EDC Rectiers Dr. P.R. Bokde
Consider one cycle of load current iL from 0 to 2π to obtain the average value
which is d.c. value of load current.
iL = Im sin(ωt) f or 0 ≤ ωt ≤ π
But for π to 2π , the current iL is again positive while sin ωt term is negative
during π to 2π . Hence in the region π to 2π the positive iL can be represented
as negative of Im sin(ωt).
iL = −Im sin(ωt) f or π ≤ ωt ≤ 2π
Therefore
Z 2π
1
IDC = iL d(ωt)
2π 0
Z π Z 2π
1
IDC = Im sin ωtd(ωt) + −Im sinωtd(ωt)
2π 0 π
Z π Z 2π
1
IDC = Im sin ωtd(ωt) − Im sinωtd(ωt)
2π 0 π
Im h π 2π
i
IDC = (− cos ωt)0 − (− cos ωt)π
2π
Im
IDC = [− cos π + cos 0 + cos 2π − cosπ]
2π
Im
IDC = [−(−1) + 1 + 1 − (−1)]
2π
4Im
IDC =
2π
2Im
IDC =
π
For half wave it is Iπm and full wave rectier is the combination of two half wave
circuits alternately in two half cycles of input. Hence obviously the d.c. value
for full wave circuit is 2Iπm .
Since two half wave rectier are similar in operation we can write,
s Z π
2
IRM S = [Im sin ωt]2 d(ωt)
2π 0
s Z
1 π 1 − cos 2ωt
IRM S = Im d(ωt)
π 0 2
s π
1 π sin 2ωt
IRM S = Im [ωt]0 −
2π 2 0
r
1
IRM S = Im [π − 0]
r 2π
1
IRM S = Im (π)
2π
Im
IRM S =√
2
PBCOE. Nagpur Page 15 Department of Electronics Engg.
EDC Rectiers Dr. P.R. Bokde
2
PDC = EDC IDC = IDC RL
2
PDC = IDC RL
2
2Im
PDC = RL
π
4 2
PDC = 2 Im RL
π
PDC output
η=
PAC input
4 2
π 2 Im RL
η= 2 (R +R +R )
Im f S L
2
8RL
η=
π 2 (Rf + RL + RL )
But , if Rf + RS is very small as compared to RL , neglecting it from denomi-
nator, we get
8 RL
η=
π 2 RL
8
η= 2
π
8
%ηmax = 2 × 100 = 81.2%
π
This is the maximum theoretical eciency of full wave rectier.
This indicates that the ripple contents in the output are 48 % of the d.c. com-
ponent which is much less than that for half wave circuit.
It can be observed from the circuit that when the diode is reversed biased then
full transformer secondary voltage gets impressed across it. The drop across
conducting diode is assumed zero. Thus the peak value of the inverse voltage to
which diode gets subjected is voltage across both the parts of the transformer
secondary.
P IV of diode = 2Esm
= πEDC at IDC = 0
where Esm = maximum value of a.c. voltage across half the transformer sec-
ondary.
1. The d.c. load current in case of full wave circuit is twice to that in half
wave circuit; similarly the D.C. load voltage in full wave circuit is twice
that in half wave circuit.
2. The lowest ripple frequency in full wave circuit is twice that in half wave
circuit. Now to remove ripple the additional circuits called lter circuit
are used along with rectier circuits. But as the frequency is more in
full wave, the capacitor values required in capacitance lter are much less
hence smaller elements are sucient in lter circuits used with full wave
circuit to reduce ripple.
3. Because there is no net d.c. current through windings of the transformer
used in full wave rectier circuit, the losses are less as compared to losses
in transformer used in half wave circuit.
4. The full wave connection gives d.c. power output four times as large, when
compared with half wave connection.
5. The eciency of rectication in a full wave connection is twice that for
half wave connection.
PBCOE. Nagpur Page 18 Department of Electronics Engg.
EDC Rectiers Dr. P.R. Bokde
6. The ripple factor is less for full wave , ie. rectication is more nearly
complete for full wave as compared to half-wave.
5 Bridge Rectier
Consider the positive half of a.c input votlage. The point A of secondary
becomes positive. The diodes D1 and D2 will be forward biased, while D3 and
D4 reverse biased. The two diodes D1 and D2 conduct in series with the load
and the current ows as shown in g. 8.
In the next half cycle, when the polarity of a.c. voltage reverses hence
point B becomes positive. Diode D3 and D4 are forward biased, while D1 and
D2 reverse biased. Now the diodes D3 and D4 conduct in series with the load
and the current ows as shown in g. 9.
As seen that in both cycles of a.c., the load current is owing in the
same direction, hence we get a full wave rectied output.
1. The current in both the primary and secondary of the power transformer
ows for the entire cycle and hence for a given power output, power trans-
former of a small size and less cost my be used.
2. No center tap is required in the transformer secondary. Hence, whenever
possible, a.c. voltage can directly be applied to the bridge.
3. The current in the secondary of the transformer is in opposite direction in
two half cycles. Hence net d.c. component owing is zero which reduces
the losses and danger of saturation.
4. Due to pure alternating current in secondary of transformer, the trans-
former gets utilized eectively and hence the circuit is suitable for appli-
cations where large powers are required.
5. As two diodes conduct in series in each half cycle, inverse votlage appearing
across diodes get shared. Hence the circuit can be used for high voltage
applications. Such a peak reverse voltage appearing across diode is called
peak inverse voltage rating (PIV) of diode.
The only disadvantage of bridge rectier is the use of four diodes as compared
to two diodes in centre tapped full wave rectier. This causes additional voltage
drop as indicated by term 2Rf present in expression of Im instead of Rf . This
reduces the output voltage.
S.N. Parameters Half Wave Centre Tap Full Wave Bridge Rectier
1 Number of Diodes 1 2 4
2 Average DC Cur- Im
π
2Im
π
2Im
π
rent IDC
3 Average DC volt- Esm
π
2Esm
π
2Esm
π
age EDC
4 RMS Current Im
2
Im
√
2
Im
√
2
(Irms )
2 2 2
5 DC Power Output Im RL
π2
4Im
π2
RL 4Im
π2
RL
(PDC )
2 2 2
6 AC Power input Im (RL +Rf +Rs )
4
Im (RL +Rf +Rs )
2
Im (RL +2Rf +Rs )
2
(PAC )
7 Maximum Rec- 40.6 % 81.2 % 81.2 %
tier Eciency
(η)
8 Ripple Factor(γ) 1.21 0.482 0.482
9 Maximum Load Esm
RS +Rf +RL
Esm
RS +Rf +RL
Esm
RS +2Rf +RL
Current (Im )
7 Introduction to Filter
It is seen that the output of a half wave rectier or full wave rectier is not pure
d.c. but it contains uctuations or ripples, which is undesired. To minimize
the ripple in the output, lter circuits are used. These circuits are connected
between the rectier and load as shown in g 10
circuit should be use components which have widely dierent impedance for
a.c. and d.c. Two such components are inductance and capacitance. Ideally,
the inductance acts as a short circuit for d.c but it has a large impedance for
a.c. Similarly, the capacitor acts as open for d.c. and almost short for a.c. if
the value of capacitance is suciently large enough.
Similarly, since the capacitance is open for d.c., i.e. it blocks d.c.,
hence it cannot be connected in series with the load. It is always connected in
shunt arm, parallel to the load.
Looking from the rectier side, if the rst element in the lter circuit
is capacitor, then the lter circuit is called capacitor-input lter. While if the
rst element is an inductor, it is called choke input lter. The choke input lter
PBCOE. Nagpur Page 23 Department of Electronics Engg.
EDC Rectiers Dr. P.R. Bokde
is not in use now a days as inductors are bulky, expensive and consume more
power.
The block schematic of capacitor input lter is shown in g 11, looking from
the rectier side the rst element in lter is a capacitor.
Figure 11:
During the rst quarter cycle of the rectied output votlage, obtained from the
rectier circuit, the capacitor C gets charged to peak value Esm . This is shown
in g 13.
Now in the next quarter cycle from π2 to π , the rectier output voltage,
shown dotted starts decreasing. But as capacitor C is charged upto the maxi-
mum value Esm , it makes the conducting diode reverse biased and the diode
stops conducting. The current through diode reduces to zero when capacitor
charges upto Esm which is shown by a shaded portion in g 13.
In this circuit, the two diodes are conducting in alternate half cycles
of the output of the rectier circuit. The diodes are not conducting for the
entire half cycle but only for a part of the half cycle, during which the capac-
itor is getting charged. When the capacitor is discharging through the load
resistance RL , both the diodes are non-conducting. The capacitor supplies the
load current. As the time required by capacitor to charge is very small and it
discharges very little due to large time constant, hence ripple in the output gets
reduced considerably. Though the diodes conduct partly, the load current gets
maintained due to the capacitor. This tler is very popularly used in practice.
Consider a full wave rectier circuit using a capacitor input lter. The basic
circuit diagram and various waveforms for the circuit are shown in g 14 and
15.
Figure 14: Centre Tapped Full Wave Rectier with Capacitor Filter.
Let T2 be the time for half cycle of a.c. input voltage. During the
time interval T1 the diode is conducting and the capacitor C is getting charged.
While in the time interval T2 , the diode is reverse biased and the
capacitor discharges through the load resistance RL .
The d.c. output votlage from a capacitor lter fed from a full
wave rectier is given by -
1
EDC = Esm − IDC (18)
4f C
While the d.c. output votlage from a capacitor leter fed from a half wave
rectier is given by,
1
EDC = Esm − IDC (19)
2f C
Que.2 What is the signicance of ripple factor and eciency in rectier? Derive
the expression for ripple factor of full wave rectier. (Summer − 17)(7 −
M arks)
Que.3 Explain the working of full wave bridge rectier & derive the expression
for its ripple factor. (W inter − 17)(7 − M arks).
Que.4 Draw the circuit diagram of full wave rectier and explain its operation
with the help of waveforms. (Summer − 18)(6 − M arks)
Que.5 Show that maximum eciency of half wave rectier is 40.6 %. (W inter −
18)(6 − M arks)
Que.6 A half wave rectier supplies a power to 1KΩ load. The input supply
voltage is 220 V rms. Neglecting forward resistance of diode, calculate, (i)
Vrms (ii) Irms (iii) Ripple Factor. (W inter −18, W inter −17)(7−M arks)
Que.8 A full wave rectier is fed from a transformer having centre tapped sec-
ondary winding. The rms voltage from either end of secondary to centre
tap is 30 V. The diode resistance is 2Ω and resistance half of secondary is
8Ω for a load of 1KΩ. Calculate : (i) DC Current (ii) Power delivered to
load (iii) % regulation (iv) Eciency (W inter − 16)(8 − M arks)