Microelectronic circuits(ECL 5303)

Syllabus Total No. Weightage

of Lectures
Introduction to Microelectronics: Introduction, Mosfet Basics, Latch- up, 11 22%
CMOS Process flow, Mosfet Layout & Design Rules, Mosfet Scaling
Inverter Design: Introduction, Static characteristics of resitive load inverter, 15 30%
saturated load inverter & CMOS inverter , delay definitions, noise margins and
Layout of CMOS inverter.
Logic implementation: Layout of complex gates(Stick diagram), Transmission 4 8%
and pass transistor based switch logic, Pseudo nmos
Memory Design: SRAM & DRAM Design. 6 12%

Dynamic CMOS Logic: Pre- Charge evaluation, Domino, Multiple output 14 28%
domino, Zipper, TSPC,

Institute / School Name Chitkara School of Engineering & Technology

Program Name B.E.(Electronics & Communication Engineering

Course Code ECL 5303

Course Name Microelectronic Circuits

Lecture / Tutorial (per week) 4/1 Course Credits 4.5

Course Coordinator Name Ajaypal Singh Dhillon

1. Scope and Objectives of the Course

This course is an introduction to digital integrated circuits. The material will cover CMOS devices
and manufacturing technology along with CMOS inverters and gates. Other topics include
propagation delay, noise margins, Power dissipation, and regenerative logic circuits. We will look
at various design styles and architectures as well as the issues that designers must face, such as
technology scaling and the impact of interconnect. Examples presented in class include arithmetic
circuits, semiconductor memories, and other novel circuits
2. Textbooks
TB1: Sung- Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis and Design ,
3rd Edition, Tata McGraw Hill, 2003
TB2: Jan M Rabaey, Digital integrated circuits a design perspective, Prentice hall, 2006

3. Course Plan
Lect. Ref. to
Text Book/Ref.
No. Topics Section of TB1
book/Class
Notes

Introduction to Ch-1(Sec- 1.1, 1.2,

1-2 TB1/class notes
Microelectronics 1.3, 1.4)

Mosfet Basics
3-6 TB1/class notes Ch-3(Sec- 3.3, 3.4)
Latch-up

Ch-2(Sec 2.2- Pg-53

Cmos Process flow TB1/class notes
7-8 to 56)

9-10 Mosfet layout and Design rules TB1/class notes Ch-2(Sec-2.4, 2.5)

Ch-3{ Sec- 3.5 (Pg-

11 MOSFET Scaling TB1/class notes
115 to 119)}

Mos Inverter: static

12-17 characteristic - resistive load TB1/class notes Ch-5(Sec- 5.1, 5.2)
inverter

Inverters with n-type mosfet

18-19 TB1/class notes Ch-5(Sec- 5.3)
load

Cmos Inverter: DC operation

TB1/class notes Ch-5(Sec-5.4)
20-22 and characteristics

Noise margin and layout of

23-25 TB1/class notes Ch-5(Sec-5.4)
cmos inverter

26 Delay Definitions(Brief) TB1/class notes Ch-6(Sec-6.2)

Layut of complex Cmos logic TB1/class notes

27-28 Ch-7(Sec-7.4)
gates(Stick diagram)

Transmission and pass

29-30 transistor-based Switch Logic TB1/class notes Ch-7(Sec-7.5)
Realization
 Ch-7(Sec-7.5)
Pseudo nmos logic and static
31-33 TB1/class notes Ch-10{Sec-10.3(pg-
sram cell
438-446)}

34-35 Dynamic ckt. techniques TB1/class notes Ch-9(Sec-9.1)

Ch-10{ Sec-10.2(pg-
36-38 Dynamic RAM Cell TB1/class notes
410 to 420)

39 Bootstrapping TB1/class notes Ch-9(Sec-9.3)

40-41 Clocked-CMOS TB1/class notes Ch-9(Sec-9.5)

42-44 Pre-Charge/ Evaluate Logic TB1/class notes Ch-9(Sec-9.5)

Domino Logic, Multiple-

45-47 Output Domino Logic, NORA TB1/class notes Ch-9(Sec-9.6)
Logic.

48-50 Zipper ,TSPC TB1/class notes Ch-9(Sec-9.6)

4. Tutorial Plan

Tutorial Topics to be covered( Total Syllabus is to be covered either in the form

No of tutorial sheets/

1 Basic Conceptual MOSFET Questions

2 Logic Implementation using CMOS Complimentary logic

3 Numerical Based on MOSFET

4 Numerical based on Resistive inverter Design

5 Numerical based on Saturated load inverter Design

6 Numerical based on CMOS inverter Design

7 Numerical based on Inverter Design

8 Transmission gate and pass transistor based design problems

9 Layout & Stick Diagrams based Questions

10 Dynamic logic problems

5. Evaluation Scheme:
 Component Duration Weightage frequency Remarks Week
Tutorial test 20 min 10 Once CB 4/5 week
I
Tutorial test 20 min 10 Once CB 13/14 week
II/ Surprise
test/ Open
book test
20 min 5 Once CB 9/10 week
Quiz
Sessional 1hour 30 25 Twice(7th week CB ST1
Test I& II min and 16th week)
End term Announced 50 Once CB End of
exam semester

Component 1 Quizzes /Tutorial Test/Surprise Test 25

Component 2* Sessional Tests (STs)* 25
Component End Term Examination** 50
3**
Total 100
* There are three Sessional Tests (STs) for all theory papers, the first two are compulsory and the third
one is the non-mandatory make up / mercy test. The average of best two is considered.
** The End Term Comprehensive examination will be held at the end of semester. The mandatory
requirement of 75% attendance in all theory classes is to be met for being eligible to appear in this
component.
This Document is approved by:

Designation Name Signature

Course Coordinator Ajaypal Singh Dhillon
PI/ CoD/ HoD Ms. Pooja Arora
Dean Dr Rajnish Sharma
Date