Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
ISL6700 FN9077
80V/1.25A Peak, Medium Frequency, Low Cost, Half-Bridge Driver Rev.6.00
December 29, 2004
Pinouts
ISL6700IB (SOIC) ISL6700IR (QFN)
TOP VIEW TOP VIEW
VDD
NC
HB
VDD 1 8 HB
HI 2 HO 12 11 10
7
LI 3 6 HS HI 1 9 HO
VSS 4 5 LO
NC 2 EPAD 8 NC
LI 3 7 HS
4 5 6
NC
LO
VSS
VDD SECONDARY
HB CIRCUIT
HI DRIVE HO
HI
CONTROL
HS
PWM
CONTROLLER
LI DRIVE LO
LO
REFERENCE
ISL6700 AND
VSS ISOLATION
HB
U/V LEVEL HO
SHIFT
HS
HI
LI TURN-ON
LO
DELAY
VDD DETECTOR
UNDERVOLTAGE
VSS
+48V
+12V
ISL6700 SECONDARY
PWM CIRCUIT
ISOLATION
+48V
+12V SECONDARY
CIRCUIT
ISL6700
PWM
ISOLATION
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES:
1. All voltages referenced to VSS unless otherwise specified.
2. Based on VDD=15V. The magnitude of the allowable negative transient on the HS pin is a function of the VDD supply voltage. VHS<15.6V-
VDD+VF, where VHS is the magnitude of the allowable negative transient and VF is the forward voltage drop of the bootstrap diode.
3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. JC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
TJ = -40°C TO
TJ = 25°C 125°C
PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS
VDD Rising Undervoltage Threshold VDDUV+ 6.8 7.6 8.25 6.5 8.5 V
VDD Falling Undervoltage Threshold VDDUV- 6.5 7.1 7.8 6.25 8.1 V
Low Level Input Voltage VIL Full Operating Conditions 0.8 1.6 - 0.8 - V
High Level Input Voltage VIH Full Operating Conditions - 1.7 2.2 - 2.2 V
Low Level Input Current IIL VIN = 0V, Full Operating Conditions -70 -60 -30 -80 -30 A
High Level Input Current IIH VIN = 5V, Full Operating Conditions 30 115 130 30 145 A
Electrical Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)
TJ = -40°C TO
TJ = 25°C 125°C
PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS
Switching Specifications VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified
TJ = -40°C
TJ = 25°C TO 125°C
TEST
PARAMETERS SYMBOL CONDITIONS MIN TYP MAX MIN MAX UNITS
Rise Time tR - 5 20 - 25 ns
Fall Time tF - 5 20 - 25 ns
Delay Matching: Lower Turn-On and Upper Turn-Off tMON - 8 20 - 25 ns
Pin Descriptions
SYMBOL DESCRIPTION
VDD Positive supply to control logic and lower gate drivers. De-couple this pin to VSS. Connect anode of bootstrap diode to this pin.
HS High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this
pin.
HO High-side output. Connect to gate of high-side power MOSFET.
HB High-side bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive
side of bootstrap capacitor to this pin.
EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
Timing Diagrams
LI
HI, HI
LI
tHPLH , tHPHL,
LO
tLPLH tLPHL
tMON tMOFF
HO,
LO HO
FIGURE 3. FIGURE 4.
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
N
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
INDEX
AREA H 0.25(0.010) M B M PACKAGE
E
INCHES MILLIMETERS
-B- SYMBOL MIN MAX MIN MAX NOTES
A 0.0532 0.0688 1.35 1.75 -
1 2 3
L A1 0.0040 0.0098 0.10 0.25 -
-C-
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
e A1
C H 0.2284 0.2440 5.80 6.20 -
B 0.10(0.004) h 0.0099 0.0196 0.25 0.50 5
0.25(0.010) M C A M B S L 0.016 0.050 0.40 1.27 6
N 8 8 7
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of 0o 8o 0o 8o -
Publication Number 95. Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.