MAX1737 Stand-Alone Switch-Mode Lithium-Ion Battery-Charger Controller

19-1626; Rev 4; 9/07
KIT
ATION
EVALU BLE
A
AVA IL
Stand-Alone Switch-Mode
Lithium-Ion Battery-Charger Controller
General Description Features
MAX1737
The MAX1737 is a switch-mode lithium-ion (Li+) battery ♦ Stand-Alone Charger for Up to Four Li+ Cells
charger that charges one to four cells. It provides a
♦ ±0.8% Accurate Battery Regulation Voltage
regulated charging current and a regulated voltage
with only a ±0.8% total voltage error at the battery ter- ♦ Low Dropout: 98% Duty Cycle
minals. The external N-channel switch and synchronous ♦ Safely Precharges Near-Dead Cells
rectifier provide high efficiency over a wide input volt-
age range. A built-in safety timer automatically termi- ♦ Continuous Voltage and Temperature Monitoring
nates charging once the adjustable time limit has been ♦ <1µA Shutdown Battery Current
reached.
♦ Input Voltage Up to +28V
The MAX1737 regulates the voltage set point and charg-
ing current using two loops that work together to transi- ♦ Safety Timer Prevents Overcharging
tion smoothly between voltage and current regulation. An ♦ Input Current Limiting
additional control loop monitors the total current drawn
from the input source to prevent overload of the input ♦ Space-Saving 28-Pin QSOP
supply, allowing the use of a low-cost wall adapter. ♦ 300kHz PWM Oscillator Reduces Noise
The per-cell battery voltage regulation limit is set ♦ 90% Conversion Efficiency
between +4.0V and +4.4V and can be set from one to
four by pin strapping. Battery temperature is monitored
by an external thermistor to prevent charging if the bat- Ordering Information
tery temperature is outside the acceptable range. PART TEMP RANGE PIN-PACKAGE
The MAX1737 is available in a space-saving 28-pin MAX1737EEI -40°C to +85°C 28 QSOP
QSOP package. Use the evaluation kit (MAX1737EVKIT)
to help reduce design time.
Typical Operating Circuit
Applications
INPUT SUPPLY
Notebook Computers Li+ Battery Packs
DCIN CSSP
Hand-Held Instruments Desktop Cradle Chargers VL CSSN SYSTEM
LOAD
Pin Configuration DHI
REF MAX1737 LX
TOP VIEW
BST
VL 1 28 DCIN ISETIN
VLO
ISETOUT
ISETIN 2 27 CSSP
CELL DLO
ISETOUT 3 26 CSSN
VADJ
THM 4 25 DHI
PGND
REF 5 24 LX
MAX1737 CS
GND 6 23 BST
BATT 7 22 VLO RS
CCS
VADJ 8 21 DLO BATT
CCV 9 20 PGND Li+

BATTERY
CCV THM 1 TO 4
CCS 10 19 CS CELLS
CCI FASTCHG
CCI 11 18 SHDN
TIMER1 FULLCHG
CELL 12 17 FULLCHG
TIMER2 FAULT
TIMER1 13 16 FASTCHG
ON SHDN
TIMER2 14 15 FAULT OFF GND
QSOP
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
ABSOLUTE MAXIMUM RATINGS
MAX1737
CSSP, CSSN, DCIN to GND ...................................-0.3V to +30V BATT, CS to GND ...................................................-0.3V to +20V
BST, DHI to GND....................................................-0.3V to +36V PGND to GND, CSSP to CSSN..............................-0.3V to +0.3V
BST to LX..................................................................-0.3V to +6V VL to VLO ..............................................................-0.3V to +0.3V
DHI to LX ..........................................-0.3V to ((BST - LX) + 0.3V) VL Source Current...............................................................50mA
LX to GND ...............................................-0.3V to (CSSN + 0.3V) Continuous Power Dissipation (TA = +70°C)
FULLCHG, FASTCHG, FAULT to GND ..................-0.3V to +30V 28-Pin QSOP (derate 10.8mW/°C above +70°C)........860mW
VL, VLO, SHDN, CELL, TIMER1, TIMER2, CCI, Operating Temperature Range ...........................-40°C to +85°C
CCS, CCV, REF, ISETIN, ISETOUT, VADJ, Junction Temperature ......................................................+150°C
THM to GND ........................................................-0.3V to +6V Storage Temperature Range .............................-65°C to +150°C
DLO to GND...............................................-0.3V to (VLO + 0.3V) Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDCIN = VCSSN = VCSSP = +18V, SHDN = VL, CELL = GND, VBATT = VCS = +4.2V, VVADJ = VREF / 2, ISETIN =
ISETOUT = REF, RTHM = 10kΩ, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
SUPPLY AND REFERENCE
DCIN Input Voltage Range 6 28 V
DCIN Quiescent Supply Current 6.0V < VDCIN < 28V 5 7 mA
DCIN to BATT Undervoltage Threshold,
0.05 0.155 V
DCIN Falling
DCIN to BATT Undervoltage Threshold,
0.19 0.40 V
DCIN Rising
VL Output Voltage 6.0V < VDCIN < 28V 5.10 5.40 5.70 V
VL Output Load Regulation IVL = 0 to 15mA 44 65 mV
REF Output Voltage 4.179 4.20 4.221 V
REF Line Regulation 6V < VDCIN < 28V 2 6 mV
REF Load Regulation IREF = 0 to 1mA 6 14 mV
SWITCHING REGULATOR
PWM Oscillator Frequency VBATT = 15V, CELL = VL 270 300 330 kHz
In dropout fOSC / 4, VCCV = 2.4V,
LX Maximum Duty Cycle 97 98 %
VBATT = 15V, CELL = VL
CSSN + CSSP Off-State Leakage VCSSN = VCSSP = VDCIN = 28V, SHDN = GND 2 10 µA
DHI, DLO On-Resistance 7 Ω
LX Leakage LX = VDCIN = 28V, SHDN = GND 0.1 10 µA
SHDN = GND, VBATT = 19V 0.1 5
BATT, CS Input Current µA
CELL = SHDN = VL, VBATT = 17V 225 500
BATT, CS Input Voltage Range 0 19 V
Battery Regulation Voltage (VBATTR) CELL = float, GND, VL, or REF (Note 1) 4.167 4.2 4.233 V/cell
Not including VADJ resistor tolerances -0.8 +0.8
Absolute Voltage Accuracy %
With 1% VADJ resistors -1 +1
Battery Regulation Voltage Adjustment VVADJ = GND 3.948 3.979 4.010
VCCV = 2V V/cell
Range VVADJ = REF 4.386 4.421 4.453
2 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
MAX1737

ERROR AMPLIFIERS
CCV Amplifier Transconductance (Note 2) 4.15V < VBATT < 4.25V, VCCV = 2V 0.39 0.584 0.80 mS
CCV Amplifier Maximum Output Current 3.5V < VBATT < 5V, VCCV = 2V ±50 µA
CS to BATT Current-Sense Voltage VISETOUT = VREF / 5 30 40 50 mV
CS to BATT Full-Scale Current-Sense
VBATT = 3V to 17V, CELL = GND or VL 185 200 215 mV
Voltage
CS to BATT Current-Sense Voltage When in
VBATT < 2.4V per cell 5 10 15 mV
Prequalification State
CS to BATT Hard Current-Limit Voltage 355 385 415 mV
6V < VCSSP < 28V, VISETIN = VREF / 5,
CSSP to CSSN Current-Sense Voltage 10 20 30 mV
VCCS = 2V
CSSP to CSSN Full-Scale
6V < VCSSP < 28V, VCCS = 2V 90 105 115 mV
Current-Sense Voltage
CCI Amplifier Transconductance VCCI = 2V 0.6 1 1.4 mS
CCI Amplifier Output Current VCS - VBATT = 0, 400mV ±100 µA
CCS Amplifier Transconductance ISET = REF, VCCS = 2V 1.2 2 2.6 mS
CCS Amplifier Output Current VCSSP - VCSSN = 0, 200mV ±100 µA
CCI, CCS Clamp Voltage with Respect
25 200 mV
to CCV
CCV Clamp Voltage with Respect
25 200 mV
to CCI, CCS
STATE MACHINE
THM low-temperature or high-temperature
THM Trip-Threshold Voltage 1.386 1.4 1.414 V
current
THM Low-Temperature Current VTHM = 1.4V 46.2 49 51.5 µA
THM High-Temperature Current VTHM = 1.4V 344 353 362 µA
Combines THM low-temperature current and
THM COLD Threshold Resistance (Note 3) 26.92 28.70 30.59 kΩ
THM rising threshold, VTRT/ITLTC
Combines THM high-temperature current and
THM HOT Threshold Resistance (Note 3) 3.819 3.964 4.115 kΩ
THM rising threshold, VTRT/ITHTC
BATT Undervoltage Threshold (Note 4) 2.4 2.5 2.6 V/cell
BATT Overvoltage Threshold (Note 5) 4.55 4.67 4.8 V/cell
BATT Charge Current Full-Charge
35 44 55 mV
Termination Threshold CS-BATT (Note 6)
% of
BATT Recharge Voltage Threshold (Note 7) 94 95 96
VBATTR
TIMER1, TIMER2 Oscillation Frequency 2.1 2.33 2.6 kHz
Prequalification Timer 6.25 7.5 8.75 min
Fast-Charge Timer 81 90 100 min
Full-Charge Timer 81 90 100 min
_______________________________________________________________________________________ 3
MAX1737

Top-Off Timer 40.5 45 49.8 min
Temperature Measurement Frequency 1nF on TIMER1 and TIMER2 0.98 1.12 1.32 Hz
CONTROL INPUTS/OUTPUTS
SHDN Input Voltage High 1.4 V
SHDN Input Voltage Low (Note 8) 0.6 V
VADJ, ISETIN, ISETOUT Input Voltage
0 VREF V
Range
VADJ, ISETIN, ISETOUT
VVADJ, VISETIN, VISETOUT = 0 or 4.2V -50 50 nA
Input Bias Current
SHDN Input Bias Current SHDN = GND or VL -1 1 µA
CELL Input Bias Current -5 5 µA
ISETIN Adjustment Range VREF / 5 VREF V
ISETOUT Adjustment Range VREF / 5 VREF V
ISETOUT Voltage for ICHG = 0 150 220 300 mV
For 1 cell 0 0.5
For 2 cells 1.5 2.5
CELL Input Voltage V
For 3 cells VREF - 0.3 VREF + 0.3
For 4 cells VVL - 0.4 VVL
FASTCHG, FULLCHG, FAULT
ISINK = 5mA 0.5 V
Output Low Voltage
FASTCHG, FULLCHG, FAULT Output High FASTCHG, FULLCHG, FAULT = 28V;
1 µA
Leakage SHDN = GND
4 _______________________________________________________________________________________
MAX1737
ISETOUT = REF, RTHM = 10kΩ, TA = -40°C to +85°C, unless otherwise noted.) (Note 9)
PARAMETER CONDITIONS MIN MAX UNITS
SUPPLY AND REFERENCE
DCIN Input Voltage Range 6 28 V
VL Output Voltage 6.0V < VDCIN < 28V 5.1 5.7 V
REF Output Voltage 4.166 4.242 V
REF Line Regulation 6V < VDCIN < 28V 6 mV
SWITCHING REGULATOR
PWM Oscillator Frequency VBATT = 15V, CELL = VL 260 340 kHz
DHI, DLO On-Resistance 7 Ω
BATT, CS Input Voltage Range 0 19 V
Battery Regulation Voltage (VBATTR) CELL = float, GND, VL, or REF 4.158 4.242 V/cell
Absolute Voltage Accuracy Not including VADJ resistor tolerances -1 1 %
ERROR AMPLIFIERS
CS to BATT Current-Sense Voltage VISETOUT = VREF / 5 25 55 mV
CS to BATT Full-Scale Current-Sense
VBATT = 3V to 17V, CELL = GND or VL 180 220 mV
Voltage
CS to BATT Current-Sense Voltage When in
VBATT < 2.4V per cell 3 17 mV
Prequalification State
CS to BATT Hard Current-Limit Voltage 350 420 mV
6V < VCSSP < 28V, VISETIN = VREF / 5,
CSSP to CSSN Current-Sense Voltage 5 35 mV
VCCS = 2V
CSSP to CSSN Full-Scale Current-Sense
6V < VCSSP < 28V, VCCS = 2V 85 115 mV
Voltage
STATE MACHINE
THM Trip-Threshold Voltage THM low-temperature or high-temperature current 1.386 1.414 V
THM Low-Temperature Current VTHM = 1.4V 46.2 51.5 µA
Combines THM low-temperature current and
THM COLD Threshold Resistance (Note 3) 26.92 30.59 kΩ
THM rising threshold, VTRT/ITLTC
BATT Undervoltage Threshold (Note 4) 2.4 2.6 V/cell
BATT Overvoltage Threshold (Note 5) 4.55 4.8 V/cell
BATT Charge Current Full-Charge
35 55 mV
Termination Threshold, CS-BATT (Note 6)
Temperature Measurement Frequency 1nF on TIMER1 and TIMER2 0.93 1.37 Hz
_______________________________________________________________________________________ 5
MAX1737
ISETOUT = REF, RTHM = 10kΩ, TA = -40°C to +85°C, unless otherwise noted.) (Note 9)
CONTROL INPUTS/OUTPUTS
SHDN Input Voltage High 1.4 V
SHDN Input Voltage Low (Note 8) 0.6 V
Note 1: Battery Regulation Voltage = Number of Cells × (3.979V + 0.10526 × VVADJ).
Note 2: This transconductance is for one cell. Divide by number of cells to determine actual transconductance.
Note 3: See Thermistor section.
Note 4: Below this threshold, the charger reverts to prequalification mode and ICHG is reduced to about 5% of full scale.
Note 5: Above this threshold, the charger returns to reset.
Note 6: After full-charge state is complete and peak inductor current falls below this threshold, FULLCHG output switches high.
Battery charging continues until top-off timeout occurs.
Note 7: After charging is complete, when BATT voltage falls below this threshold, a new charging cycle is initiated.
Note 8: In shutdown, charging ceases and battery drain current drops to 5µ A ( max), but internal IC bias current remains on.
Note 9: Specifications to -40°C are guaranteed by design and not production tested.
6 _______________________________________________________________________________________
Typical Operating Characteristics
MAX1737
(Circuit of Figure 1, VDCIN = +18V, ISETIN = ISETOUT = REF, VVADJ = VREF / 2, TA = +25°C, unless otherwise noted.)
BATTERY VOLTAGE CHARGING CURRENT-SENSE VOLTAGE INPUT CURRENT-SENSE VOLTAGE

vs. CHARGING CURRENT vs. ISETOUT VOLTAGE vs. ISETIN VOLTAGE
4.5 225 120
MAX1737 toc03
MAX1737 toc02
MAX1737 toc01
R18 = 0.1Ω
CHARGING CURRENT-SENSE VOLTAGE (mV)
INPUT CURRENT-SENSE VOLTAGE (mV)

4.0 200
100
3.5 175
BATTERY VOLTAGE (V)
3.0 150 80
2.5 125
60
2.0 100
1.5 75 40
1.0 50
20
0.5 25
0 0 0
0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
CHARGING CURRENT (A) ISETOUT VOLTAGE (V) ISETIN VOLTAGE (V)
REFERENCE VOLTAGE
VOLTAGE LIMIT vs. VADJ VOLTAGE vs. TEMPERATURE EFFICIENCY vs. INPUT VOLTAGE
4.45 4.205 100
MAX1737 toc04
MAX1737 toc05
MAX1737 toc06
4.40
4.35 4.200
90
REFERENCE VOLTAGE (V)
4.30
VOLTAGE LIMIT (V)
4.195
EFFICIENCY (%)
4.25 80
4.20 4.190
4.15 70
4.10 4.185
4.05 60
4.180 CELL = FLOAT (2 CELLS)
4.00 VBATT = 7V
R18 = 0.1Ω (IBATT = 2A)
3.95 4.175 50
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -40 -20 0 20 40 60 80 100 8 12 16 20 24 28
VADJ VOLTAGE (V) TEMPERATURE (°C) INPUT VOLTAGE (V)
FAST-CHARGE TIMEOUT
REFERENCE LOAD REGULATION TIMEOUT vs. TIMER1 CAPACITANCE vs. TIMER2 CAPACITANCE
4.210 1000 1000
MAX1737 toc08
MAX1737 toc07
MAX1737 toc09
4.208
TOP-OFF MODE
4.206 FULL-CHARGE
REFERENCE VOLTAGE (V)
100
4.204 MODE
100
TIMEOUT (MINUTES)
TIMEOUT (MINUTES)
4.202
4.200 10
4.198
4.196 10
PREQUALIFICATION MODE
1
4.194
4.192
4.190 0.1 1
0 100 200 300 400 500 600 700 800 900 1000 0.1 1 10 0.1 1 10
REFERENCE CURRENT (μA) CAPACITANCE (nF) CAPACITANCE (nF)
________________________________________________________________________________________ 7
Pin Description
MAX1737
PIN NAME FUNCTION

Chip Power Supply. Output of the 5.4V linear regulator from DCIN. Bypass VL to GND with a
1 VL
2.2µF or larger ceramic capacitor.
Input Current Limit Adjust. Use a voltage-divider to set the voltage between 0 and VREF.
2 ISETIN
See Input Current Regulator section.
Battery Charging Current Adjust. Use a voltage-divider to set the voltage between 0 and VREF.
3 ISETOUT
See Charging Current Regulator section.
Thermistor Input. Connect a thermistor from THM to GND to set a qualification temperature
4 THM
range. If unused, connect a 10kΩ resistor from THM to ground. See Thermistor section.
5 REF 4.2V Reference Voltage Output. Bypass REF to GND with a 1µF or larger ceramic capacitor.
6 GND Analog Ground
7 BATT Battery Voltage-Sense Input and Current-Sense Negative Input
Voltage Adjust. Use a voltage-divider to set the VADJ voltage between 0 and VREF to adjust the
8 VADJ
battery regulation voltage by ±5%. See Setting the Voltage Limit section.
9 CCV Voltage Regulation Loop Compensation Point
10 CCS Input Source Current Regulation Compensation Point
11 CCI Battery-Current Regulation Loop Compensation Point
12 CELL Cell-Count Programming Input. See Table 2
Timer 1 Adjustment. Connect a capacitor from TIMER1 to GND to set the prequalification,
13 TIMER1
full-charge, and top-off times. See Timers section.
Timer 2 Adjustment. Connect a capacitor from TIMER2 to GND to set the fast-charge time. See
14 TIMER2
Timers section.
Charge Fault Indicator. Open-drain output pulls low when charging terminates abnormally
15 FAULT
(Table 1).
16 FASTCHG Fast-Charge Indicator. Open-drain output pulls low when charging with constant current.
Full-Charge Indicator. Open-drain output pulls low when charging with constant voltage in
17 FULLCHG
full-charge state.
Shutdown Input. Drive SHDN low to disable charging. Connect SHDN to VL for normal
18 SHDN
operation.
19 CS Battery Current-Sense Positive Input. See Charging Current Regulator section.
20 PGND Power Ground
21 DLO Synchronous-Rectifier MOSFET Gate-Drive Output
22 VLO Synchronous-Rectifier MOSFET Gate-Drive Bias. Bypass VLO to PGND with a 0.1µF capacitor.
23 BST High-Side MOSFET Gate Drive Bias. Connect a 0.1µF or greater capacitor from BST and LX.
24 LX Power Inductor Switching Node. Connect LX to the high-side MOSFET source.
25 DHI High-Side MOSFET Gate-Drive Output
26 CSSN Source Current-Sense Negative Input. See Input Current Regulator section.
27 CSSP Source Current-Sense Positive Input. See Input Current Regulator section.
Power-Supply Input. DCIN is the input supply for the VL regulator. Bypass DCIN to GND with a
28 DCIN
0.1µF capacitor. Also used for the source undervoltage sensing.
8 _______________________________________________________________________________________
Detailed Description The DC-DC converter uses an external dual N-channel
MAX1737
MOSFET as a switch and a synchronous rectifier to
The MAX1737 includes all of the functions necessary to
convert the input voltage to the charging current or volt-
charge between one and four series Li+ battery cells. It
age. The typical application circuit is shown in Figure 1.
includes a high-efficiency synchronous-rectified step-
Figure 2 shows a typical charging sequence and
down DC-DC converter that controls charging voltage
Figure 3 shows the block diagram. Charging current is
and current. It also includes input source-current limit-
set by the voltage at ISETOUT and the voltage across
ing, battery temperature monitoring, battery undervolt-
R18. The battery voltage is measured at the BATT pin.
age precharging, battery fault indication, and a state
The battery regulation voltage is set to 4.2V per cell
machine with timers for charge termination.
and can be adjusted ±5% by changing the voltage at
the VADJ pin. By limiting the adjust range, the voltage
D1
D2
INPUT 28 27
DCIN CSSP
SUPPLY C7 C8
0.1μF 0.1μF
R12
1 MAX1737 26
VL CSSN
C1 C2 C9 SYSTEM
4.7μF 0.1μF 0.1μF + + LOAD
C18 C19
18 22μF 22μF
SHDN
22
VLO
C11
5 D3 0.1μF
REF
23
2 BST
ISETIN
R8 25 L1
3 DHI
ISETOUT C10 22μH R18
C3 8 0.1μF
1μF VADJ 24
12 LX C15
CELL 68μF
R9
6
GND 21
DLO
C4 R1
0.1μF 10k 20
9 PGND THERMISTOR
CCV
1nF
19
CS Li+
C5 BATTERY
47nF 0.1μF (1 TO 4 CELLS)
11
CCI
C6 7
47nF BATT
10 0.1μF
CCS
C13
1nF 4
13 THM
TIMER1
C14
1nF
14
TIMER2
16
FASTCHG
FAST CHARGE
17
FULLCHG
FULL CHARGE
15
FAULT
FAULT
Figure 1. Typical Application Circuit
_______________________________________________________________________________________ 9
tor (CTIMER2). If the battery temperature is outside the
MAX1737
FAST- FULL-
CHARGE CHARGE TOP-OFF
STATE STATE STATE DONE limits, charging pauses and the timers are suspended
until the temperature returns to within the limits.
BATTERY
CURRENT
CHARGE I = 1C In the full-charge state, the FULLCHG output goes low
and the batteries charge at a constant voltage (see the
Voltage Regulator section). When the charging current
drops below 10% of the charging current limit, or if the
full-charge timer expires, the state machine enters the
BATTERY
VOLTAGE top-off state. In the top-off state, the batteries continue
FASTCHG OPEN- to charge at a constant voltage until the top-off timer
OUTPUT DRAIN
LOW
expires, at which time it enters the done state. In the
done state, charging stops until the battery voltage
FULLCHG OPEN-
OUTPUT DRAIN drops below the recharge-voltage threshold. It then
LOW enters the reset state to start the charging process
TOP-OFF TIMER
BATTERY
INSERTION TIMES OUT, END OF ALL
again. In the full-charge or the top-off state, if the bat-
OR SHDN HIGH CHARGE FUNCTIONS tery temperature is outside the limits, charging pauses
TRANSITION TO FULL-CHARGE TIMER
and the timers are suspended until the battery temper-
VOLTAGE MODE TIMES OUT OR ature returns to within limits.
(APPROX 85% CHARGE) BATTERY CURRENT
DROPS TO C/10
(APPROX 95% CHARGE) Voltage Regulator
Li+ batteries require a high-accuracy voltage limit while
Figure 2. Charge State and Indicator Output Timing for a charging. The MAX1737 uses a high-accuracy voltage
Typical Charging Sequence regulator (±0.8%) to limit the charging voltage. The bat-
accuracy is better than 1% while using 1% setting tery regulation voltage is nominally set to 4.2V per cell
resistors. and can be adjusted ±5% by setting the voltage at the
VADJ pin between reference voltage and ground. By
The MAX1737 includes a state machine that controls limiting the adjust range of the regulation voltage, an
the charging algorithm. Figure 4 shows the state dia- overall voltage accuracy of better than 1% is main-
gram. Table 1 lists the charging state conditions. When tained while using 1% resistors. CELL sets the cell
power is applied or SHDN is driven high, the part goes count from one to four series cells (see Setting the
into the reset state where the timers are reset to zero to Battery Regulation Voltage section).
prepare for charging. From the reset state, it enters the
prequalification state. In this state, 1/20 of the fast- An internal error amplifier (GMV) maintains voltage reg-
charge current charges the battery, and the battery ulation (Figure 3). The GMV amplifier is compensated
temperature and voltage are measured. If the voltage is at CCV. The component values shown in Figure 1 pro-
above the undervoltage threshold and the temperature vide suitable performance for most applications.
is within the limits, then it will enter the fast-charge Individual compensation of the voltage regulation and
state. If the battery voltage does not rise above the current regulation loops allows for optimal compensa-
undervoltage threshold before the prequalification timer tion of each.
expires, the charging terminates and the FAULT output Charging Current Regulator
goes low. The prequalification time is set by the The charging current-limit regulator limits the charging
TIMER1 capacitor (CTIMER1). If the battery is outside current. The current is sensed by measuring the volt-
the temperature limits, charging and the timer are sus- age across the current-sense resistor (R18, Figure 1)
pended. Once the temperature is back within limits, placed between the BATT and CS pins. The voltage on
charging and the timer resume. the ISETOUT pin also controls the charging current.
In the fast-charge state, the FASTCHG output goes low, Full-scale charging current is achieved by connecting
and the batteries charge with a constant current (see ISETOUT to REF. In this case, the full-scale current-
the Charging Current Regulator section). If the battery sense voltage is 200mV from CS to BATT.
voltage reaches the voltage limit before the fast timer When choosing the charging current-sense resistor,
expires, the part enters the full-charge state. If the fast- note that the voltage drop across this resistor causes
charge timer expires before the voltage limit is further power loss, reducing efficiency. However,
reached, charging terminates with a fault indication. adjusting ISETOUT to reduce the voltage across the
The fast-charge time limit is set by the TIMER2 capaci-
10 ______________________________________________________________________________________
MAX1737
SHDN
160ns
SLOPE
BATT COMP
STOP
CS SAW MAX1737
REF/42 BATT
5x
CSI CCI
GMI
3R
ISETOUT
R/9 R
SW+
PREQ GND GATE BST
SW- CONTROL
DHI
GND CS+ ON DHI
CSSP
PWMCOMP PWMCMP LX
10x CS- ILIMIT
CSSN CSS DLO
CCI GND LOWILIM
LVC EA+
OSC VLO
3R GMS CCS LO DLO
REF/2.6
EA- PGND
ISETIN CCV
R
R
REF/2
GND
REF/42
R R/2 R/2 R/2
ONE 160ns
CELL TWO PWMOSC

CELL
THREE
FOUR
REF
GND
R
CCV
VADJ 9R GMV
CCS
GND
Figure 3. PWM Controller Block Diagram
current-sense resistor may degrade accuracy due to Input Current Regulator

the input offset of the current-sense amplifier. The total input current (from a wall cube or other DC
The charging-current error amplifier (GMI) is compen- source) is the sum of system supply current plus the
sated at CCI. A 47nF capacitor at CCI provides suit- battery-charging current. The input current regulator
able performance for most applications. limits the source current by reducing charging current
when input current exceeds the set input current limit.
System current normally fluctuates as portions of the
system are powered up or put to sleep. Without input
______________________________________________________________________________________ 11
MAX1737
SHUTDOWN SHUTDOWN IS
FASTCHG = HIGH
ENTERED FROM ALL STATES
FULLCHG = HIGH
VDCIN < BATT WHEN SHDN IS LOW.
FAULT = HIGH
SHDN HIGH
VBATT < UNDERVOLTAGE RESET
THRESHOLD FASTCHG = HIGH
FULLCHG = HIGH
VDCIN > VBATT FAULT = HIGH
PREQUAL PREQUAL FAULT

FASTCHG = LOW TIMEOUT FASTCHG = HIGH
FULLCHG = HIGH FULLCHG = HIGH
FAULT = HIGH FAULT = LOW
VBATT > 2.5V

FAST-CHARGE
TEMP TIMEOUT
NOT OK TEMP FAST CHARGE
OK
FASTCHG = LOW
FULLCHG = HIGH
ONCE PER FAULT = HIGH VBATT < 0.95 × VBATTR
SECOND
TEMP VBATT = BATTERY
OK REGULATION VOLTAGE (VBATTR)
ONCE PER
SECOND FULL CHARGE
TEMP FASTCHG = HIGH VBATT < 0.95 × VBATTR
QUAL FULLCHG = LOW
TEMP FAULT = HIGH
OK
TEMP ICHARGE < IMIN OR
NOT OK TEMP FULL-CHARGE
NOT OK TIMEOUT
TEMP
OK TOP-OFF DONE
FASTCHG = HIGH FASTCHG = HIGH
FULLCHG = HIGH FULLCHG = HIGH
TOP-OFF
FAULT = HIGH FAULT = HIGH
TIMEOUT
Figure 4. State Diagram
current regulation, the input source must be able to across the current-sense resistor may degrade input
supply the maximum system current plus the maximum current limit accuracy due to the input offset of the
charger input current. By using the input current limiter, input current-sense amplifier.
the current capability of the AC wall adapter may be The input current error amplifier (GMS) is compensated
lowered, reducing system cost. at CCS. A 47nF capacitor at CCS provides suitable per-
Input current is measured through an external sense formance for most applications.
resistor at CSSP and CSSN. The voltage at ISETIN also
adjusts the input current limit. Full-scale input current is PWM Controller
achieved when ISETIN is connected to REF, setting the The PWM controller drives the external MOSFETs to
full-scale current-sense voltage to 100mV. control the charging current or voltage. The input to the
PWM controller is the lowest of CCI, CCV, or CCS. An
When choosing the input current-sense resistor, note internal clamp limits the noncontrolling signals to within
that the voltage drop across this resistor adds to the 200mV of the controlling signal to prevent delay when
power loss, reducing efficiency. Reducing the voltage switching between regulation loops.
12 ______________________________________________________________________________________
MAX1737
Table 1. Charging State Conditions
STATE ENTRY CONDITIONS STATE CONDITIONS
From initial power on

or
From done state if battery voltage < Timers reset, charging current = 0,
Reset recharge voltage threshold FASTCHG = high, FULLCHG = high,
or FAULT = high
VDCIN - VBATT < 100mV or VBATT > bat-
tery overvoltage threshold
From reset state if input power, Battery voltage ≤ undervoltage threshold, charging
Prequalification reference, and internal bias are within current = C/20, timeout = 7.5min typ (CTIMER1 = 1nF),
limits FASTCHG = low, FULLCHG = high, FAULT = high
Undervoltage threshold ≤ battery voltage ≤ battery regu-

Fast Charge From prequalification state if battery lation voltage, charging current = current limit,
(Constant Current) voltage > undervoltage threshold timeout = 90min typ (CTIMER2 = 1nF),
FASTCHG = low, FULLCHG = high, FAULT = high
Battery voltage = battery regulation voltage, charging

Full Charge From fast-charge state if battery current ≤ current limit,
(Constant Voltage) voltage = battery regulation voltage timeout = 90min typ (CTIMER1 = 1nF),
FASTCHG = high, FULLCHG = low, FAULT = high
Battery voltage = battery regulation voltage, charging

From full-charge state if full-charge timer
Top-Off current ≤ 10% of current limit, timeout = 45min typ
expires or charging current ≤ 10% of
(Constant Voltage) (CTIMER1 = 1nF), FASTCHG = high, FULLCHG = high,
current limit
FAULT = high
Recharge voltage threshold ≤ battery voltage ≤ battery

Done From top-off state if top-off timer expires regulation voltage, charging current = 0, FASTCHG =
high, FULLCHG = high, FAULT = high
From fast-charge state or full-charge Charge current = 0, timers suspended,

Over/Under Temperature state if battery temperature is outside of FASTCHG = no change, FULLCHG = no change,
limits FAULT = no change
From prequalification state if prequalifi-

cation timer expires Charging current = 0,
Fault or FASTCHG = high, FULLCHG = high,
From fast-charge state if fast-charge FAULT = low
timer expires
______________________________________________________________________________________ 13
The current-mode PWM controller uses the inductor cycle (approximately 85% charge) and is operating in
MAX1737
current to regulate the output voltage or current, simpli- voltage mode. The FASTCHG and FULLCHG outputs
fying stabilization of the regulation loops. Separate can be tied together to indicate charging (see Figure 2).
compensation of the regulation circuits allows each to FAULT indicates the charger has detected a charging
be optimally stabilized. Internal slope compensation is fault and that charging has terminated. The charger can
included, ensuring stable operation over a wide range be brought out of the FAULT condition by removing and
of duty cycles. reapplying the input power, or by pulling SHDN low.
The controller drives an external N-channel MOSFET Thermistor
switch and a synchronous rectifier to step the input The intent of THM is to inhibit fast-charging the cell
voltage down to the battery voltage. A bootstrap when it is too cold or too hot (+2.5°C ≤ TOK ≤ +47.5°C),
capacitor drives the high-side MOSFET gate to a volt- using an external thermistor. THM time multiplexes two
age higher than the input source voltage. This capaci- sense currents to test for both hot and cold qualification.
tor (between BST and LX) is charged through a diode The thermistor should be 10kΩ at +25°C and have a
from VLO when the synchronous rectifier is on. The negative temperature coefficient (NTC); the THM pin
high-side MOSFET gate is driven from BST, supplying expects 3.97kΩ at +47.5°C and 28.7kΩ at +2.5°C.
sufficient voltage to fully drive the MOSFET gate even Connect the thermistor between THM and GND. If no
when its source is near the input voltage. The synchro- temperature qualification is desired, replace the ther-
nous rectifier is driven from DLO to behave like a diode, mistor with a 10kΩ resistor. Thermistors by
but with a smaller voltage drop for improved efficiency. Philips/BCcomponents (2322-640-63103), Cornerstone
A built-in dead time (50ns typ) between switch and syn- Sensors (T101D103-CA), and Fenwal Electronics (140-
chronous rectifier turn-on and turn-off prevents crowbar 103LAG-RB1) work well.
currents (currents that flow from the input voltage to
ground due to both the MOSFET switch and synchro- Shutdown
nous rectifier being on simultaneously). This dead time When SHDN is pulled low, the MAX1737 enters the
may allow the body diode of the synchronous rectifier shutdown mode and charging is stopped. In shutdown,
to conduct. If this happens, the resulting forward volt- the internal resistive voltage-divider is removed from
age and diode recovery time will cause a small loss of BATT to reduce the current drain on the battery to less
efficiency and increased power dissipation in the syn- than 1µA. DHI and DLO are low. However, the internal
chronous rectifier. To prevent the body diode from con- linear regulator (VLO) and the reference (REF) remain
ducting, place an optional Schottky rectifier in parallel on. The status outputs FASTCHG, FULLCHG, and
with the drain and source of the synchronous rectifier. FAULT are high impedance. When exiting shutdown
The internal current-sense circuit turns off the synchro- mode, the MAX1737 goes back to the power-on reset
nous rectifier when the inductor current drops to zero. state, which resets the timers and begins a new charge
cycle.
Timers
The MAX1737 includes safety timers to terminate Source Undervoltage Shutdown
charging and to ensure that faulty batteries are not (Dropout)
charged indefinitely. TIMER1 and TIMER2 set the time- If the voltage on DCIN drops within 100mV of the volt-
out periods. age on BATT, the charger resets.
TIMER1 controls the maximum prequalification time,
maximum full-charge time, and the top-off time. TIMER2
controls the maximum fast-charge time. The timers are Table 2. Cell-Count Programming
set by external capacitors. The typical times of 7.5 min-
utes for prequalification, 90 minutes for full charge, 45 CELL CELL COUNT (N)
minutes for top-off, and 90 minutes for fast charge are GND 1
set by using a 1nF capacitor on TIMER1 and TIMER2
(Figure 1). The timers cannot be disabled. Float 2
Charge Monitoring Outputs REF 3

FASTCHG, FULLCHG, and FAULT are open-drain out- VL 4
puts that can be used as LED drivers. FASTCHG indi-
cates the battery is being fast charged. FULLCHG
indicates the charger has completed the fast-charge
14 ______________________________________________________________________________________
Design Procedure Figure 1) between CSSP and CSSN. The full-scale
MAX1737
source current is IFSS = 0.1V / R12.
Setting the Battery Regulation Voltage The input current limit (IIN) is therefore:
VADJ sets the per-cell voltage limit. To set the VADJ
voltage, use a resistor-divider from REF to GND. A V
GND-to-VREF change at VADJ results in a ±5% change IIN = I FSS ISETIN
VREF
in the battery limit voltage. Since the full VADJ range
results in only a 10% change on the battery regulation Set ISETIN to REF to get the full-scale current limit.
voltage, the resistor-divider’s accuracy need not be as Short CSSP and CSSN to DCIN if the input source cur-
high as the output voltage accuracy. Using 1% resis- rent limit is not used.
tors for the voltage-dividers results in no more than
In choosing the current-sense resistor, note that the
0.1% degradation in output voltage accuracy. VADJ is
drop across this resistor causes further power loss,
internally buffered so that high-value resistors can be
reducing efficiency. However, too low a resistor value
used. Set VVADJ by choosing a value less than 100kΩ
may degrade input current limit accuracy.
for R8 and R9 (Figure 1) from VADJ to GND. The per-
cell battery termination voltage is a function of the bat- Inductor Selection
tery chemistry and construction; thus, consult the The inductor value may be changed to achieve more or
battery manufacturer to determine this voltage. Once less ripple current. The higher the inductance, the
the per-cell voltage limit battery regulation voltage is lower the ripple current will be; however, as the physi-
determined, the VADJ voltage is calculated by the cal size is kept the same, higher inductance typically
equation: will result in higher series resistance and lower satura-
⎛ 9.5 × V ⎞ tion current. A good trade-off is to choose the inductor
VADJ = ⎜ BATTR − (9.0 × V
⎟ REF ) so that the ripple current is approximately 30% to 50%
⎝ N ⎠ of the DC average charging current. The ratio of ripple
where VBATTR is N x the cell voltage. CELL is the pro- current to DC charging current (LIR) can be used to
gramming input for selecting cell count N. Table 2 calculate the optimal inductor value:
shows how CELL is connected to charge one to four VBATT (VDCIN(MAX) − VBATT )
cells. L=
VDCIN(MAX) × f × I CHG × LIR
Setting the Charging Current Limit
A resistor-divider from REF to GND sets the voltage at where f is the switching frequency (300kHz).
ISETOUT (V ISETOUT ). This voltage determines the The peak inductor current is given by:
charging current during the current-regulation fast-
charge mode. The full-scale charging current (IFSI) is ⎛ LIR ⎞
I PEAK = I CHG ⎜1 + ⎟
set by the current-sense resistor (R18, Figure 1) ⎝ 2 ⎠
between CS and BATT. The full-scale current is IFSI =
0.2V / R18. Capacitor Selection
The charging current ICHG is therefore: The input capacitor absorbs the switching current from
the charger input and prevents that current from circu-
V lating through the source, typically an AC wall cube.
I CHG = I FSI ISETOUT
VREF Thus, the input capacitor must be able to handle the
input RMS current. Typically, at high charging currents,
In choosing the current-sense resistor, note that the drop the converter will operate in continuous conduction (the
across this resistor causes further power loss, reducing inductor current does not go to 0). In this case, the
efficiency. However, too low a value may degrade the RMS current of the input capacitor may be approximat-
accuracy of the charging current. ed by the equation:
Setting the Input Current Limit

A resistor-divider from REF to GND can set the voltage I CIN ≈ I CHG D − D2
at ISETIN (VISETIN). This sets the maximum source cur-
rent allowed at any time during charging. The source where I CIN = the input capacitor RMS current, D =
current (IFSS) is set by the current-sense resistor (R12, PWM converter duty ratio (typically VBATT / VDCIN), and
ICHG = battery charging current.
_______________________________________________________________________________________ 15
The maximum RMS input current occurs at 50% timeout. The typical timeouts for a 1C charge rate are
MAX1737
duty cycle, so the worst-case input ripple current is set to 7.5 minutes for the prequalification timer, 90 min-
0.5 × ICHG. If the input to output voltage ratio is such utes for the fast-charge timer, 90 minutes for the full-
that the PWM controller will never work at 50% duty charge timer, and 45 minutes for the top-off timer by
cycle, then the worst-case capacitor current will occur connecting a 1nF capacitor to TIMER1 and TIMER2.
where the duty cycle is nearest 50%. Each timer period is directly proportional to the capaci-
The impedance of the input capacitor is critical to pre- tance at the corresponding pin. See the Typical
venting AC currents from flowing back into the wall cube. Operating Characteristics.
This requirement varies depending on the wall cube’s Compensation
impedance and the requirements of any conducted or Each of the three regulation loops—the input current
radiated EMI specifications that must be met. Aluminum limit, the charging current limit, and the charging volt-
electrolytic capacitors are generally the least costly, but age limit—can be compensated separately using the
are usually a poor choice for portable devices due to CCS, CCI, and CCV pins, respectively.
their large size and low equivalent series resistance
(ESR). Tantalum capacitors are better in most cases, as The charge-current loop error amp output is brought
are high-value ceramic capacitors. For equivalent size out at CCI. Likewise, the source-current error amplifier
and voltage rating, tantalum capacitors will have higher output is brought out at CCS; 47nF capacitors to
capacitance and ESR than ceramic capacitors. This ground at CCI and CCS compensate the current loops
makes it more critical to consider RMS current and in most charger designs. Raising the value of these
power dissipation when using tantalum capacitors. capacitors reduces the bandwidth of these loops.
The output filter capacitor is used to absorb the induc- The voltage-regulating loop error amp output is brought
tor ripple current. The output capacitor impedance out at CCV. Compensate this loop by connecting a
must be significantly less than that of the battery to capacitor in parallel with a series resistor-capacitor
ensure that it will absorb the ripple current. Both the (RC) from CCV to GND. Recommended values are
capacitance and ESR rating of the capacitor are impor- shown in Figure 1.
tant for its effectiveness as a filter and to ensure stabili- Applications Information
ty of the PWM circuit. The minimum output capacitance
for stability is: MOSFET Selection
The MAX1737 uses a dual N-channel external power
⎛ VBATT ⎞ MOSFET switch to convert the input voltage to the
VREF ⎜1 + ⎟
⎝ VDCIN(MIN) ⎠ charging current or voltage. The MOSFET must be
COUT > selected to meet the efficiency and power-dissipation
VBATT × f × RCS requirements of the charging circuit, as well as the tem-
where COUT is the total output capacitance, VREF is the perature rise of the MOSFETs. The MOSFET character-
reference voltage (4.2V), VBATT is the maximum battery istics that affect the power dissipation are the
voltage (typically 4.2V per cell), and VDCIN(MIN) is the drain-source on-resistance (R DS(ON) ) and the gate
minimum source input voltage. charge. In general, these are inversely proportional.
The maximum output capacitor ESR allowed for stability To determine the MOSFET power dissipation, the oper-
is: ating duty cycle must first be calculated. When the
charger is operating at higher currents, the inductor
RCS × VBATT current will be continuous (the inductor current will not
RESR <
VREF drop to 0A) and, in this case, the high-side MOSFET
duty cycle (D) can be approximated by the equation:
where RESR is the output capacitor ESR and RCS is the
current-sense resistor from CS to BATT. VBATT
D≈
Setting the Timers VDCIN
The MAX1737 contains four timers: a prequalification and the synchronous-rectifier MOSFET duty cycle (D′)
timer, fast-charge timer, full-charge timer, and top-off will be 1 - D or:
timer. Connecting a capacitor from TIMER1 to GND
V −V
and TIMER2 to GND sets the timer periods. The D′ ≈ DCIN BATT
TIMER1 input controls the prequalification, full-charge, VDCIN
and top-off times, while TIMER2 controls fast-charge
16 ______________________________________________________________________________________
For the high-side switch, the worst-case power dissipa- connect a Schottky rectifier across the drain source of
MAX1737
tion due to on-resistance occurs at the minimum source the synchronous rectifier to stop the body diode from
voltage VDCIN(MIN) and the maximum battery voltage conducting. The Schottky rectifier may be omitted, typi-
VBATT(MAX), and can be approximated by the equation: cally degrading the efficiency by approximately 1% to
2%, causing a corresponding increase in the low-side
VBATT(MAX) synchronous-rectifier power dissipation.
PR ≈ × RDS(ON) × ICHG 2
VDCIN(MIN)
VL and REF Bypassing
The transition loss can be approximated by the equation: The MAX1737 uses an internal linear regulator to drop
the input voltage down to 5.4V, which powers the inter-
nal circuitry. The output of the linear regulator is the VL
V × ICHG × f × t TR
PT ≈ DCIN pin. The internal linear regulator may also be used to
3 power external circuitry as long as the maximum current
where tTR is the MOSFET transition time. So the total and power dissipation of the linear regulator are not
power dissipation of the high-side switch is PTOT = PR exceeded. The synchronous-rectifier MOSFET gate dri-
+ PT. ver (DLO) is powered from VLO. An internal 12Ω resistor
from VL to VLO provides the DC current to power the
The worst-case synchronous-rectifier power occurs at gate driver. Bypass VLO to PGND with a 0.1µF or
the minimum battery voltage VBATT(MIN) and the maxi- greater capacitor.
mum source voltage VDC(MAX), and can be approxi- A 4.7µF bypass capacitor is required at VL to ensure
mated by: that the regulator is stable. A 1µF bypass capacitor is
also required between REF and GND to ensure that the
VDCIN(MAX) − VBATT(MIN) internal 4.2V reference is stable. In both cases use a
PDL ≈ × RDS(ON) × ICHG 2 low-ESR ceramic capacitor.
VDCIN(MAX)
There is a brief dead time where both the high-side Chip Information
switch and synchronous rectifier are off. This prevents TRANSISTOR COUNT: 5978
crowbar currents that flow directly from the source volt-
age to ground. During the dead time, the inductor cur-
rent will turn on the synchronous-rectifier MOSFET body
diode, which may degrade efficiency. To prevent this,
______________________________________________________________________________________ 17
Package Information
MAX1737
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QSOP.EPS
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055 F 1
Note: The MAX1737EEI is a 28-pin QSOP and does not have a heat slug.
Revision History
Pages changed at Rev 4: 1, 9, 18
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 18
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
TPS68000
(6,4 mm x 7,8 mm)
www.ti.com SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006
HIGHLY EFFICIENT PHASE SHIFT FULL BRIDGE CCFL CONTROLLER

FEATURES DESCRIPTION
• 8-V to 30-V Input Voltage Range The TPS68000 device provides a power supply
• Full Bridge Topology With Integrated Gate controller solution for CCFL backlight applications in a
Drives for 4 NMOS Switches large variety of applications. The wide input voltage
range of 8 V to 30 V makes it suitable to be powered
• Synchronizable Constant Frequency
directly from regulated 12-V or 24-V rails, or any
Operation other source with output voltages in this range. When
• Programmable Phase Delays of Operating using a 10% accurate regulated 5-V rail, it also can
Frequency for Master-Slave Operation be used in notebook computers or other portable
• Lamp Voltage and Lamp Current Regulation battery-powered equipment having lower minimum
supply voltages. The controller is capable of driving
• Analog and Burst Dimming the gates of all 4 NMOS switches directly without the
• Configurable Distributed Burst Dimming in need for any additional circuitry, like dedicated gate
Multiple Controller Applications drivers or gate-drive transformers. The wide input
• Programmable Voltage Regulation Timeout voltage range also makes it easy to design CCFL
for Startup and Fault Conditions converters with higher input voltages like 120 V or
400 V available at the output of a power factor
• Open-Lamp and Short-Circuit Protection correction unit. The TPS68000 also supports CCFL
• Internal Over-Temperature Protection converter circuits driving multi-lamp applications,
• Undervoltage Lockout either by using higher power-rated switches and
transformers, or using several TPS68000s
• 30-pin TSSOP Package synchronized. When synchronized, they can be
operated either at the same frequency and phase, or
APPLICATIONS phase shifted to minimize RMS input current. Already
• CCFL Backlight Power Supplies for Desktop implemented smart dimming features, such as
Monitors and LCD TVs support of distributed dimming, also help to optimize
• CCFL Backlight Power Supplies for Notebook the performance of multi-controller applications.
Computers (Continued on next page)
C10
TPS68000
Supply Voltage
VCC V5A QA QC
8V .. 30V C1 VLOGIC
GA C
R2 3 C12
SA C14
Error Output FAULT V5C
Synchronization SYNC C4 T1
2.0 V GC
Synchronization Phase Shift 0V PH
SET SC
Operating Frequency
QB QD
R1
Device Enable EN GB
C5 C13
STC GD C2
R3 R4
V5
Lamp current 3.3 V
(Analog Dimming Input) 0V ABR
OCP
2V
Burst Duty Cycle 0V BBR CSEN
(Burst Dimming Input) C6 CAO C8
Burst Frequency BF
CA−
Direct Burst Dimming Input VSEN
(Frequency + Duty Cycle) BC
C7 VAO C9
VREF VA−
GND PGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Distributed Dimming is a registered trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS68000
www.ti.com
SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
To start the lamp, an automatic strike control is implemented. It smoothly increases the lamp voltage by
sweeping the operating frequency across the self resonance frequency of the transformer-series capacitor
resonant circuit. During this time the maximum lamp voltage is limited and regulated by a voltage control loop
until the lamp current increases to a value allowing the current control loop to take over control. The lamp current
is regulated over a wide current range. To set the lamp brightness, analog and PWM dimming circuits are
implemented. Analog and PWM dimming can be used independent of each other to control lamp brightness over
a wide range.
To protect the circuit during fault conditions, for example broken, disconnected, or shorted lamps, overvoltage
protection and overcurrent protection circuits are implemented. To protect the TPS68000 from overheating, an
internal temperature sensor is implemented that triggers controller turn-off at an excessive device temperature.
The device is packaged in a 30-pin TSSOP package measuring 6,4 mm x 7,8 mm (DBT).
AVAILABLE DEVICE OPTIONS

TA PACKAGE PART NUMBER (1)
–40°C to 85°C 30-Pin TSSOP TPS68000DBT
(1) The DBT package is available taped and reeled. Add R suffix to device type (e.g., TPS68000DBTR) to order quantities of 2000 devices
per reel.
ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted)
TPS68000
Input voltage range on VCC, EN, FAULT –0.3 V to 33 V
Input voltage range on SYNC, SET, PH, STC, ABR, BBR, BF, BC, VREF, VA-, VAO, CA-, CAO –0.3 V to 6 V
Input voltage range on VSEN, CSEN, OCP –6 V to 6 V
Input voltage range on GD, GB, V5 –0.3 V to 6 V
maximum differential voltage between GA, V5A and SA 6V
maximum differential voltage between GC, V5C and SC 6V
maximum differential voltage between SA and PGND 35 V
maximum differential voltage between SC and PGND 35 V
Operating virtual junction temperature range, TJ –40°C to 150°C
Storage temperature range Tstg –65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated uner "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
THERMAL RESISTANCE POWER RATING DERATING FACTOR POWER RATING POWER RATING
PACKAGE
θJA TA≤ 25°C ABOVE TA = 25°C TA≤ 70°C TA≤ 85°C
DBT 63.9°C/W 1565 mW 16 mW/°C 860 mW 626 mW
RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT
VI Supply voltage at VCC 8.0 30 V
TA Operating free air temperature range –40 85 °C
TJ Operating virtual junction temperature range –40 125 °C
2 Submit Documentation Feedback

TPS68000
www.ti.com
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MAIN CONTROL
V5 Internal control supply regulator IOUT-V5< 25 mA 4.5 5 5.5 V
including internal current
IOUT-V5 Control supply output current 25 mA
consumption
VUVLO Under voltage lockout threshold at V5 Voltage at V5 decreasing 4.0 4.1 4.3 V
VOL FAULT output low voltage IFAULT = 500 µA 0.2 0.4 V
Vlkg FAULT output leakage current VFAULT= 5 V 0.1 1 µA
VIL EN input low voltage 0.4 V
VIH EN input high voltage 1.4 V
EN input current VCC = 24 V 0.05 0.1 µA
ISTC STC source current during strike 6 µA
ISTC STC source current during wait 2 µA
normal operation, VSTC =
ISTC STC source and sink current 10 µA
1.25 V
Overtemperature protection 140 °C
Overtemperature hysteresis 20 °C
Quiescent current into VCC VCC = 12 V, V5 = 5.5 V 30 50 µA
Quiescent current into VCC VCC = V5 = 5.5 V 25 40 µA
Quiescent current into V5 VCC = V5 = 5.5 V 1000 1500 µA
Shutdown current into VCC VCC = V5 = 5.5 V, EN = 0V 1 2 µA
Shutdown current into V5 VCC = V5 = 5.5 V, EN = 0V 1 2 µA
Shutdown current into VCC VCC = 12 V, EN = 0V 2.5 5 µA
VREF Reference Voltage IOUT-VREF < 5 mA 3.27 3.3 3.33 V
IOUT-VREF Reference output current 5 mA
GATE DRIVE
High side drive sink resistance ID = 0.05 A 1.2 2.0 Ω
High side drive source resistance ID = 0.05 A 1.5 2.5 Ω
High side drive rise time CG = 4.7 nF, SA = SC = 0 V, 35 50 ns
V5A = V5C = 5 V
High side drive fall time CG = 4.7 nF 15 25 ns
Time delay between high side off and CG = 4.7 nF 100 ns
low side on
Time delay between low side off and CG = 4.7 nF 100 ns
high side on
Low side drive sink resistance ID = 0.05 A 1.2 2.0 Ω
Low side drive source resistance ID = 0.05 A 1.5 2.5 Ω
Low side drive rise time CG = 4.7 nF, V5 = 5 V 35 50 ns
Low side drive fall time CG = 4.7 nF 15 25 ns
MAIN OSCILLATOR
Oscillator frequency programming
f 30 100 kHz
range
Frequency capture range for
fSYNC 0.5 x f 2xf
synchronization
VIL SYNC low voltage 0.4 V
VIH SYNC high voltage 1.4 V
VPH≤ V5 - 1.3 V, VSYNC = 3.3
ISYNC SYNC input current 0.5 1.5 µA
V
ISYNC SYNC drive current VSYNC≥ 1.4 V, VPH = 5 V 1000 1250 1500 µA
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over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISYNC SYNC sink current VSYNC≤ 0.4 V, VPH = 5 V 1000 1250 1500 µA
Minimum pulse width for
100 ns
synchronization
VSET SET output voltage 1.25 V
Phase shift of the main oscillator clock VPH = 0.1 V .. 1.9 V 90 ° / VPH
IPH PH input current VPH = 2.0 V 0.1 1 µA
Threshold for programming device as
VPH V5– 1.3 V V5– 0.7 V V
main oscillator frequency master
VOLTAGE AND CURRENT CONTROL
RCSEN Current sense input impedance VCSEN = 3.3 V 35 kΩ
RCSEN Current sense input impedance VCSEN = –3.3 V 25 kΩ
RVSEN Voltage sense input impedance VVSEN = 3.3 V 25 kΩ
RVSEN Voltage sense input impedance VVSEN = –3.3 V 30 kΩ
Voltage and current amplifier output
ICAO, IVAO VCAO, VVAO = 2.5 V 55 µA
source current
Voltage and current amplifier output
ICAO, IVAO VCAO, VVAO = 2.5 V 200 µA
sink current
VREFVREG Voltage regulator reference voltage (0.8 ×VREF) / π V
VREFOVP Overvoltage comparator threshold VREF V
VREFCREG Current regulator reference voltage VABR / π V
IOCP Overcurrent comparator input current VOCP = 3.3V 0.1 1 µA
IOCP Overcurrent comparator input current VOCP = –3.3V 50 µA
VREFOCP Overcurrent comparator threshold VREF V
DIMMING
IABR ABR input current VABR = 3.3 V 0.01 0.1 µA
ABR input voltage range for lamp
VABR BC = V5 0 3.3 V
current programming
IBBR BBR input current VBBR = 2.0 V 0.1 1 µA
Burst duty cycle VBBR = 0 V .. 2 V 50 % / VBBR
BBR input voltage threshold for
VBBR V5– 1.3 V V5– 0.7 V V
selecting synchronized burst dimming
IBF BF source current 10 µA
fBurst Internal burst frequency range 20 1000 Hz
Frequency lock / capture range for 0.5 x
fBC 1.5 x fBurst
synchronized burst dimming fBurst
tr Burst current pulse rise time 400 µs
IBC BC input current VBC = 3.3V 0.1 1 µA
VIL BC input low voltage 0.4 V
VIH BC input high voltage 1.4 V
minimum pulse width at BC 100 ns
Phase shift of the dimming burst VPH = 0 V .. 2 V, distributed
180 ° / VPH
compared to BC clock dimming selected

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PIN ASSIGNMENTS
DBT PACKAGE
(TOP VIEW)
SYNC 1 30 VREF
SET 2 29 GND
STC 3 28 SA
PH 4 27 GA
BBR 5 26 V5A
BC 6 25 GB
BF 7 24 VCC
ABR 8 23 V5
VAO 9 22 PGND
VA− 10 21 GD
VSEN 11 20 V5C
CA− 12 19 GC
CAO 13 18 SC
CSEN 14 17 EN
OCP 15 16 FAULT
Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
ABR 8 I Analog brightness programming input. A DC voltage applied at that pin programs the lamp current
the current regulator regulates. 0 V means no current and 3.3 V means maximum current.
BBR 5 I Burst brightness programming input. A DC voltage applied at that pin programs the duty cycle of the
burst pulses generated to dimm the brightness. 0 V means zero duty cycle and 2 V means
maximum duty cycle. Applying V5 (5 V) programs the device to operate in synchronized burst
dimming mode.
BC 6 I Burst control. A PWM signal applied at that pin is directly used for burst dimming. Frequency and
duty cycle are used directly. This input has priority against the burst frequency programming with
BBR and BF
BF 7 I Burst frequency programming. A capacitor at that pin programs the burst frequency.
CA- 12 I Current amplifier negative input. This input is used to connect the compensation capacitor for
compensating the current loop.
CAO 13 O Current amplifier output. This is the output for the current amplifier. It is used to connect the
compensation capacitor for the current loop.
CSEN 14 I Current sense. Measuring input for the lamp current. The applied voltage (coming from a shunt
resistor) will be used for lamp current regulation. Sensed AC voltages can be applied directly. They
will be rectified internally.
EN 17 I Enable input. Logic high enables the device.
FAULT 16 O Error output, any detected malfunctioning of the application will be reported as error on this pin.
Error means the output is pulled low. The output is open drain to allow connecting multiple error
outputs of similar devices together.
GA 27 O Gate drive output of switch A
GB 25 O Gate drive output of switch B
GC 19 O Gate drive output of switch C
GD 21 O Gate drive output of switch D
GND 29 Analog ground pin. Reference ground for all control signals.
OCP 15 I Over current protection. This input is used to monitor a voltage derived from a current sensor in any
part of the converter. This voltage is compared to an internal reference voltage. Exceeding the
internal reference voltage causes the device logic to turn the device off and report an error signal at
the fault pin.
PGND 22 Reference ground for the gate drivers and the gate drive supply.

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PIN ASSIGNMENTS (continued)

Terminal Functions (continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
PH 4 I Phase delay programming input. A voltage between 0 V and 2 V applied to that pin programs the
phase delay of the operating frequency compared to the synchronizing frequency. Applying V5 (5.0
V) programs the device as a master regarding the main oscillator frequency (see SYNC). The
voltage applied to that pin is also used to determine the phase delay in a distributed dimming
configuration
SA 28 Source connection of switch A
SC 18 Source connection of switch C
SET 2 I Operating frequency programming input. A resistor connected to this pin programs the internal
operating frequency.
STC 3 I Startup capacitor. A capacitor connected to that pin determines the the time the device waits in
voltage regulation for the lamp to strike.
SYNC 1 I/O Synchronization input or operating frequency output. If the device is configured as master (see PH)
the pin is used to provide the synchronization frequency for the slaves. Otherwise the device works
as slave and uses the applied frequency at that pin for synchronizing the operating frequency.
V5 23 I/O Input/Output of the internal 5 V regulator for gate drive supply and control supply. A capacitor must
be connected to that pin to decouple switching noise caused by the gate drivers.
V5A 26 O Supply input for the gate driver of the high-side switch A. A capacitor must be connected to that pin
to supply the gate driver during switching (bootstrap).
V5C 20 O Supply input for the gate driver of the high side switch C. A capacitor must be connected to that pin
to supply the gate driver during switching (bootstrap).
VA- 10 I Voltage amplifier negative input. This input is used to connect the compensation capacitor for
compensating the voltage loop.
VAO 9 O Voltage amplifier output. This is the output for the voltage amplifier. It is used to connect the
compensation capacitor for the voltage loop.
VCC 24 I Device supply voltage input. VCC must be connected to V5 in case the device is powered directly
from a regulated 5 V rail.
VREF 30 O Voltage reference. Output of the internal 3.3 V reference for use with all the analog control inputs.
VSEN 11 I Voltage sense. Measuring input for the lamp voltage. This voltage is used for lamp voltage
regulation (open lamp regulation) and overvoltage protection. Sensed AC voltages can be applied
directly. They are rectified internally.

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FUNCTIONAL BLOCK DIAGRAM (TPS68000)
V5A
GA
SA
V5
V5 GB
VCC Control Supply
OVP Gate
Main Control
Control
V5C
OCP
FAULT GC
SC
V5
V5
GD
PGND
OCP OCP
SYNC
VREF VREF_OCP
SET Oscillator Phase Shift
PH Control
CAO
CA−
EN Startup
and Strike Rectifier CSEN
STC Control
VAO
VA−
ABR
Analog Rectifier VSEN
BBR and VREF_VREG
Burst
BF Dimming
BC OVP
OVP
VREF
VREF_OVP
VREF
GND
PARAMETER MEASUREMENT INFORMATION

C10
TPS68000
Supply Voltage
VCC V5A QA QC
8V .. 30V C1 VLOGIC
GA C
R2 3 C12
SA C14
Error Output FAULT V5C
Synchronization SYNC C4 T1
2.0 V GC
Synchronization Phase Shift 0V PH
SET SC
Operating Frequency
QB QD
R1
Device Enable EN GB
C5 C13
STC GD C2
R3 R4
V5
Lamp current 3.3 V
(Analog Dimming Input) 0V ABR
OCP
2V
Burst Duty Cycle 0V BBR CSEN
(Burst Dimming Input) C6 CAO C8
Burst Frequency BF
CA−
Direct Burst Dimming Input VSEN
(Frequency + Duty Cycle) BC
C7 VAO C9
VREF VA−
GND PGND

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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Output voltage at V5 vs output current at V5 1
Output voltage at VREF vs output current at VREF 2
Operating frequency vs resistance at SET 3
Phase shift of operating frequency vs voltage at PH 4
Burst dimming duty cycle vs voltage at BBR 5
Burst dimming phase shift vs voltage at PH 6
Startup of V5 (VCC = 12 V) 7
Startup of V5 (VCC = 24 V) 8
Startup of VREF (VCC = V5 = 5V) 9
Waveforms
Lamp current and lamp voltage at startup (VCC = 12 V) 10
Lamp current and lamp voltage at startup (VCC = 24 V) 11
Lamp current softstart at burst dimming 12
OUTPUT VOLTAGE AT V5 OUTPUT VOLTAGE AT VREF

vs vs
OUTPUT CURRENT AT V5 OUTPUT CURRENT at VREF
5.5 3.35
V5 = 5 V
5.4 3.34
5.3 3.33
VO − Output Voltage at VREF − V
VO − Output Voltage at V5 − V
5.2 3.32
5.1 3.31
VCC = 24 V
5.0 3.30
4.9 3.29
4.8 3.28
VCC = 12 V
4.7 3.27
4.6 3.26
4.5 3.25
0 10 20 30 40 50 60 70 80 0 2 4 6 8 10 12 14 16
IO − Output Current at V5 − mA IO − Output Current at VREF − mA
Figure 1. Figure 2.

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OPERATING FREQUENCY PHASE SHIFT OF OPERATING FREQUENCY

vs vs
RESISTANCE AT SET VOLTAGE AT PH
140 180
V5 = 5 V
V5 = 5 V
160
Phase Shift of Operating Frequency − °

120
140
Operating Frequency − kHz
100
120
80
100
60 80
60
40
40
20
20
0 0
60 90 120 150 180 210 240 270 300 330 360 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Resistance at SET − kΩ Voltage at PH − V
Figure 3. Figure 4.
BURST DIMMING DUTY CYCLE BURST DIMMING PHASE SHIFT

vs vs
VOLTAGE AT BBR VOLTAGE AT PH
100 360
V5 = 5 V V5 = 5 V
90 330
300
80
Burst Dimming Duty Cycle − %
Burst Dimming Phase Shift − °
270
70
240
60 210
50 180
40 150
120
30
90
20
60
10 30
0 0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Voltage at BBR − V Voltage at PH − V
Figure 5. Figure 6.

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STARTUP OF V5 STARTUP OF V5
VCC = 12 V VCC = 24 V
VEN (5 V / div) VEN (5 V / div)
V5 (2 V / div) V5 (2 V / div)
Input Current (20 mA / div) Input Current (20 mA / div)

VCC = 12 V, IOUT_V5 = 5 mA VCC = 24 V, IOUT_V5 = 5 mA
Timebase (100 µs /div) Timebase (100 µs /div)
Figure 7. Figure 8.
STARTUP OF VREF
VCC = V5 = 5 V
VEN (5 V / div)
VREF (1 V / div)
Input Current (10 mA / div)

VCC = V5 = 5 V, IOUT_VREF = 2 mA
Timebase (100 µs /div)
Figure 9.

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LAMP CURRENT AND

LAMP VOLTAGE AT STARTUP
VCC = 12 V
VCC = 12 V
Lamp Current (Voltage at CSEN) (5 V / div)
Lamp Voltage (Voltage at VSEN) (2 V / div)
Timebase (200 ms /div)

Figure 10.
LAMP CURRENT AND

LAMP VOLTAGE AT STARTUP
VCC = 24V
VCC = 24 V
Lamp Voltage (Voltage at VSEN) (2 V / div)
Timebase (200 ms /div)

Figure 11.

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LAMP CURRENT SOFTSTART

AT BURST DIMMING
VCC = 12 V
Voltage at BC (2 V / div)
Timebase (100 µs /div)

Figure 12.

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DETAILED DESCRIPTION
Supply Voltages
The TPS68000 and the connected H-bridge power stage can be completely supplied by a voltage connected to
VCC. This voltage must be between 8 V to 30 V. In this configuration an internal linear regulator generates the 5
V required for control supply and gate drive supply. It is available at the V5 pin. The external capacitors for
supplying the high side gate drivers during operation are charged using internal diodes during the time when the
low side switches are turned on. The 3.3-V reference voltage is generated with a precise linear regulator, which
is also supplied from the 5-V control supply.
Optionally, the device can be supplied using a regulated 5-V rail. This is done by connecting the external 5 V to
VCC and V5. This way the internal regulator is bypassed and the internal power dissipation is reduced. It also
makes it possible to use any voltage lower than 30 V to supply the H-bridge power stage. When using
appropriate means of isolating the gate drive outputs of the device from their respective gates of the H-bridge
switches, the device can control power stages with higher input voltages as well. An example for this
configuration is using the output voltage of the PFC directly as a supply for the H-bridge power stage.
Gate Driver
The TPS68000 is a controller for converters, built with a full bridge topology. To control the output power
high-side and low-side switches in each of the two half bridges are driven alternately with 50% duty cycle. By
phase shifting both half-bridge parts to each other, output power is controlled. Current can only flow into the
transformer if one of the high side switches is turned on the same time as the low-side switch on the other
half-bridge is turned on. Maximum output power can be achieved if the turn on time of the high-side switch on
one half-bridge exactly overlaps with the turn on time of the low side on the other half bridge. Zero output power
will be if there is no overlap.
To properly control the 4 switches required for this phase shift full bridge topology, 4 gate drivers are
implemented. To obtain maximum efficiency at lowest costs the gate drivers are designed to drive 4 N-Channel
MOSFETs. The gate drive outputs can be connected directly to the gates of the FETs. There is no gate drive
circuit required as long as the operating input voltage range does not exceed the isolation voltage of the high
side drivers or the drive capability is not sufficient for larger FETs. The nominal gate drive voltage is 5 V. This
5-V rail is generated internally in the device and is used directly to supply the low side drivers. For the high side
drivers external capacitors are used to supply the drivers. They are charged up during the on time of the low-side
drivers.
Control Circuit
The device is able to control lamp current and lamp voltage directly. Lamp voltage and lamp current are sensed
with an appropriate feedback divider and a shunt resistor. By suitable designing feedback divider and shunt
resistor lamp current and maximum lamp voltage are programmed. Since the lamp needs to be operated with AC
current, the feedback signals in simple applications usually are AC voltages. To directly support this and to save
external components for rectification, internal half wave rectifiers are built in the device.
Regulating current and voltage is done by two independent error amplifiers. Both are compensated externally to
be flexible to meet the demands for a wide variety of CCFL backlight applications. Both error amplifier outputs
feed the phase shift modulator. Whichever error amplifier requires the lower duty cycle, takes over control of the
system. The control circuit also detects whether the device operates in voltage regulation or in current regulation.
If voltage regulation is detected a fault condition is assumed, for example a broken lamp. In this condition the
control circuit waits for a programmed wait time. If the current regulator does not take over control again during
this wait time, the device shuts down and sets the FAULT flag. The wait time is programmed with the size of the
capacitance at STC.
Protection
In addition to the voltage regulator other means of protection are implemented. To ensure that the secondary
voltage of the transformer does not exceed the isolation breakdown voltage of the transformer an overvoltage
comparator is implemented. This comparator monitors the rectified voltage at the VSEN input. If the peak voltage
level at VSEN rises 20% above the nominal regulation voltage, regulated by the voltage amplifier, the
overvoltage comparator trips and the device immediately enters FAULT condition. For detailed threshold values
please check the electrical characteristics table.

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DETAILED DESCRIPTION (continued)

For additional protection there is a standalone comparator implemented. It can be used to monitor any voltage in
the system. The switching threshold is set to the VREF voltage.
. This comparator monitors a voltage at its input and compares it with the internal reference voltage. As soon as
the input voltage of the comparator exceeds the reference voltage the comparator asserts FAULT at its output.
Negative voltages can be applied at that pin but there is no rectification. Since the input of the overcurrent
comparator is directly accessible at a pin it can be connected to any part of the circuit. It must not necessarily
use the shunt resistor used for current regulation. Monitoring the current in the secondary winding or any other
DC voltage in the system may be a desired approach as well.
Finally the device has an internal temperature sensor to monitor the IC temperature. If the temperature gets too
high FAULT is asserted as well. For detailed values for threshold and hysteresis of the thermal protection please
check the electrical characteristics table.
Oscillator
The device is operating at a fixed frequency which is generated by a built in PLL circuit. The frequency is
programmed with a resistor at SET. It also can be synchronized to an external frequency at SYNC. When
synchronizing to an external clock two modes are possible. One is to synchronize directly to the external clock,
the other is to synchronizeto the external clock but phase shifted. This helps to minimize the RMS input current
of the complete power converter application in a multi controller topology. This phase shift is programmed with a
DC voltage of 0 V to 2 V at PH for a phase shift of 0° to 180°.
Dimming
To dimm the lamp, two basic methods of dimming are supported. The first is to control the lamp current directly,
called analog dimming. The second is to turn the lamp on and off at a low frequency with a certain duty cycle,
called burst dimming. Analog dimming, is done by just providing a DC voltage at ABR. The lamp current will be
regulated propotional to that voltage. The maximum lamp current in burst dimming is also programmed with this
voltage at ABR.
Turning the lamp on and off, burst dimming, needs some more information. A low frequency must be generated
and duty cycle information for the on time needs to be provided. The simplest burst dimming mode, independent
burst dimming, is to program the low frequency with an external capacitor at BF. Applying a DC voltage at BBR
sets the duty cycle of the burst pulse. The burst duty cycle will be programmed proportional to the DC voltage at
BBR.
If the burst dimming frequency and duty cycle must be synchronized to an external PWM signal this external
signal can be connected to BC. The bursts follow the PWM signal directly. A PWM signal detected at BC has
priority to any internally generated burst signal. To force the device to take the BC PWM signal BBR can be tied
high (V5).
To minimize RMS input current in a multiple controller application the burst signal can be phase shifted to the
external PWM connected to BC, which is called Distributed Dimming®. Frequency and duty cycle stay the same.
The phase shift information is derived from the voltage at PH. Voltages of 0 V to 2 V at PH generate burst phase
shifts of 0° to 360°. For this mode of operation the internal low frequency oscillator is used. It is operated as a
PLL synchronized to the PWM frequency at BC and its center frequency has to be programmed at BF. The
compensation of the low frequency PLL is done with and R - C network connected at BBR.
Startup
When the device is enabled or the device is powered up with EN tied high, the device enters lamp strike mode.
In this mode no dimming and synchronization is possible. During the strike procedure the lamp current which
should flow when the lamp has turned on is programmed at ABR.
The device starts operating at double the programmed operating frequency and sweeps down to half of the
nominal frequency. During this sweep it can cross the self resonance frequency of the system with its maximum
voltage gain. As soon as the lamp current has reached its programmed value the device stops sweeping and
switches to the nominal operating frequency. The device will continue to regulate the lamp current and all other
control features like synchronization and burst dimming are enabled and will be used. If during this sweep the

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lamp voltage, which is programmed at the voltage regulator is reached, frequency sweeping is stopped and the
voltage regulator regulates the voltage at the programmed level. At that time a timer is started. If during this
waiting, the lamp current reaches its programmed value, the device will continue operating as described above. If
for any reason the timer reaches its programmed end, programmed by a capacitor at STC, the device stops
working and enters FAULT condition.

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APPLICATION INFORMATION
DESIGN PROCEDURE
This section describes the basic configuration and calculations which need to be done for getting the component
values necessary for configuring the device properly. Backlight inverters can be significantly more complex
especially when driving multiple lamps with one or more controllers. This will be described in seperate application
notes and documentation for reference designs and EVM's which are also available.
Decoupling and Filtering

For decoupling and filtering it is recommended to use capacitors with a low series resistance and inductance to
achieve optimum performance. Surface mount ceramic capacitors are a good choice. It is also recommended to
use short and wide traces to connect those decoupling capacitors to the controller.
For the high side gate drivers in typical applications at least a 1-µF supply capacitor is recommended. It should
be connected between SA to V5A and SC to V5C with connectio placed as close as possible to the respective
pins to make sure that the gate drive outputs have a low impedance power source.
The V5 control supply requires a decoupling capacitor as well. It should be similar in capacitance as used for
both of the high side gate drivers. Example if a typical 1uF capacitor is used at the high side drivers therefore 2.2
µF is recommended at V5.
If V5 is used as an input, which means the controller is supplied with regulated 5 V directly, V5 must be
connected to VCC to avoid reverse current flowing and malfunctioning of the control circuits directly powered
from VCC.
In case the V5 regulator is supplied via the VCC input it is recommended to use a decoupling capacitor at the
VCC pin. The capacitor should be at least 0.1 µF. For additional filtering a resistor in series can be used.
For all those capacitors the PGND pin at the IC should be the reference ground.
Connecting the Gates of the MOSFETs

The gates of the MOSFETs of the power stage should be connected with short and wide traces having a low
impedance. The respective ground connection should be similar in width and length. Special care should be
taken on the loop area formed by the gate drive trace and the respective ground return trace, that it is as small
as possible. Any vias in this traces should be avoided.
If there is a need to slow down the switching speed of the FETs to reduce EMI caused by switching transients,
gate resistors at the gate drive outputs can be used.
Voltage Reference
The internal reference voltage is available at the VREF pin. It is recommended to decouple it at this pin using a
minimum 0.22 µF capacitor to the analog ground reference pin GND. Short direct connections are
recommended.
Enabling the Controller

A logic high at the EN pin enables the controller. The enable thresholds are designed to meet requirements of
3.3 V and 1.8 V logic standards. Nevertheless it is also possible to connect EN directly to VCC to enable the
controller at power up, since the EN pin can withstand voltages as high as allowed at VCC.
If the device detects a fault it is automatically disabled. To allow the device to automatically restart after a fault,
FAULT and EN pins can be directly connected together using a common pull up resistor to VCC.
Fault Output
The fault output is open drain. It is low impedance to GND if the controller detected a fault. In normal operation it
is always high impedance. To make sure that a logic low at the FAULT pin has a lower voltage than 0.4 V the
pullup resistor should limit the current into the FAULT pin to a value lower than 0.5 mA. Equation 1 shows the
calculation:

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APPLICATION INFORMATION (continued)

V
R FAULT LOGIC
0.5 mA (1)
RFAULT is the minimum resistance value of the pullup resistor, VLOGIC is the maximum supply voltage of the logic
connected to FAULT.
Main Oscillator
In normal operation the controller operates at the frequency of the main oscillator. It is programmed with a
resistor connecting the SET pin to GND. The resistor value is calculated using Equation 2:
R SET 9720 k kHz
fN
(2)
If the controller should be synchronized to an external clock the main oscillator frequency should be programmed
close to the synchronizing frequency. This avoids large variations in case external clock pulses are missing. It
also speeds up the locking to the external clock. The SET pin should never be left open.
Synchronization of the Main Oscillator

The main oscillator can be used in different modes of operation. The first and most important mode is using it as
a reference clock. This is also the mode of choice in a single controller application which is not synchronized to
an external clock. In this mode the SYNC pin is used as an output and should be left open if no circuit needs to
be synchronized to the device main oscillator clock. To force the device operating in this mode 5 V (V5) must be
connected to the PH pin.
Lower voltages applied at the PH pin configure the SYNC pin as an input. Detailed voltage levels for this can be
found in the electrical characteristics table. If the SYNC pin is configured as an input the device automatically
synchronizes the main oscillator to the frequency which must be applied at the SYNC pin. The compensation for
this main oscilator PLL circuit is done with a capacitor connected at the STC pin. Since this capacitor is used for
defining sweep and wait timing during startup and voltage regulation, synchronization is only possible when the
device has started and is regulating lamp current. Any capacitance value which makes sense for defining sweep
and wait time should offer a reasonable compensation for the main oscillator PLL. How to calculate the value for
the capacitor at STC to program the startup and wait timing is shown in the following paragraph. Typical values
are in a µF range.
Also a phase shifted synchronization can be programmed. For this a voltage in the range between 0 V and 2 V
must be applied at the PH pin. For calculating the phase shift of the main oscillator clock to the clock applied at
the SYNC pin Equation 3 can be used:
o
N VPH 90
V (3)
In this equation φN is the main oscillator clock phase shift and VPH is the voltage applied at the PH pin.
Startup and Wait Timing

After enabling the device the device is starting at double the programmed main oscillator frequency and is
sweeping down to half the programmed main oscillator frequency. The timing for the sweep is programmed with
a capacitor connected between STC and GND. It can be calculated using Equation 4:
t SW CSTC 0.42 s
F (4)
tSW is the sweep time and CSTC is the capacitance connected between the pins STC and GND.
If at any time the voltage regulator becomes active a wait timer is started. The timing is also programmed with a
capacitor connecting STC and GND. Open lamp condition will lead to shutdown after timeout. Equation 5 shows
how to calculate the wait time, tW:

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t W CSTC 0.63 s
F (5)
Programming the Lamp Current

The lamp current which is an AC signal is sensed at the CSEN input. The AC signal is half-wave rectified
through internal circuits eliminating the need for external parts except for a current sense resistor. The error
amplifier will generate an average voltage from the half wave rectified input signal. This average voltage is
compared to the steering signal for the lamp current. This steering signal is always provided at the ABR input. It
is recommended to use the reference voltage as a maximum input voltage. For a sinusoidal feedback voltage at
CSEN the peak voltage matches the voltage applied at ABR. With this information the shunt resistor for a given
RMS lamp current can be calculated using Equation 6:
VABR
R Shunt
I 2
Lamp (6)
Assuming that the reference voltage is connected to ABR the lamp current is calculated as shown in the
following Equation 7:
R Shunt 3.3 V
I Lamp 2
(7)
RShunt is the value of the shunt resistor used for current sensing, VABR is the voltage applied at ABR and ILamp is
the RMS value of the lamp current which should be programmed.
Analog Dimming
By modifiying the voltage at ABR the lamp current steering signal is changed. With this the lamp current is
changed. The resulting lamp current for a certain voltage at ABR can be calculated as shown in Equation 8:
VABR
I Lamp
R 2
Shunt (8)
ILamp is the RMS lamp current, VABR is the voltage at ABR and RShunt is the value of the resistor used for lamp
current sensing.
Programming the Voltage Regulation and Overvoltage Protection

The lamp voltage and the transformer secondary voltage are AC signals as is the lamp current. They are sensed
at the VSEN input. Circuits similar to the current amplifier (CSEN) half wave rectified input are eliminating the
requirement for rectification on VSEN. The error amplifier will generate an average voltage from the half wave
rectified input signal. This average voltage is compared to the steering signal for the voltage. This steering signal
is derived from the internal reference voltage VREF. The overvoltage comparator is monitoring the peak voltage at
VSEN. Its threshold is the internal reference voltage. The voltage divider ratio can be calculated using
Equation 9:
V
r V REG
1.87 V (9)
rV is the ratio of the voltage feedback divider and VREG is the maximum RMS voltage the regulator should
regulate at the lamp or transformer secondary.
The corresponding RMS voltage where the overvoltage protection comparator turns off can be calculated using
Equation 10:
V OVP 2.33 V r V
(10)
To build the voltage feedback divider, resistive and capacitive dividers can be used. In case of a resistive divider
the ratio of the feedback divider is defined as shown in Equation 11:

TPS68000
www.ti.com

RH RL
rV
RL
(11)
RH is the upper resistor in the divider at the high voltage side, RL is the resistor to GND.
In case of a capacitive divider the ratio can be calculated as shown in Equation 12:
C CL
rV H
CH
(12)
In this case CH is the upper capacitor in the divider at the high voltage side, CL is the capacitor to GND.
Protection
The overcurrent protection comparator (OCP) is typically used to monitor output current but can be configured to
monitor any voltage. The comparator uses the internal reference voltage VREF as a fixed threshold. Any voltage
above the internal reference voltage at OCP for more than 4 clock cycles of the main oscillator causes the
comparator to trip and generate a fault. The comparator only will trip with positive voltages above the internal
reference voltage at applied to OCP. Although the input can withstand higher negative voltages there is no
rectification implemented.
Compensating the Current and Voltage Regulators

The compensation networks for current and voltage regulators are connected between the negative inputs and
the outputs of the respecive amplifier. At the current amplifier the pins are CAM (input) and CAO (output). At the
voltage amplifier VAM (input) and VAO (output) are used. The compensation network must have a dominating
capacitive characteristic, since the error amplifiers are also used for smoothing the half wave rectified feedback
input signal. capacitors in parallel with resistor and capacitor in series or just capacitors are recommended. In
typical applications a 2200 pF capacitor at the current amplifier and a 0.022 µF capacitor at the voltage amplifier
can be used.
Synchronized Burst Dimming

To configure the device for synchronized burst dimming the dimming PWM signal must be connected directly to
the BC logic input pin. The controller will turn the lamp on and off, following directly the PWM pulses applied at
BC regarding frequency, phase and duty cycle. The slopes of the lamp current are controlled internally. The other
pins used for configuring burst dimming, BBR and BF should have a defined state as well. It is recommended to
connect BBR to 5 V (V5) and to connect BF to GND.
Independent Burst Dimming

In this configuration the device generates the low dimming frequency and the duty cycle internally. To use this
feature the BC pin should be connected to GND. A capacitor connected to BF is used to program the frequency
of the low frequency oscillator. The capacitance necessary to program a given burst dimming frequency can be
calculated using Equation 13:
C BF 4.7 F Hz
fD
(13)
CBF is the capacitor required to be connected between BF and GND and fD is the low frequency oscillator
frequency which should be programmed. For example a 0.047 µF capacitor is needed to program a burst
frequency of 100 Hz.
To program the burst duty cycle a voltage at BBR is used. The duty cycle can be calculated using Equation 14:
D B VBBR 50 %
V (14)
DB is the resulting burst duty cycle and VBBR is the voltage applied at the BBR pin. The operating voltage range
for duty cycle programming is 0 V to 2 V. 0 V at BBR will program 0% burst duty cycle and 2 V will program
100% burst duty cycle.

TPS68000
www.ti.com

Phase Shifted Burst Dimming
The device also supports phase shifted burst dimming. In this configuration a direct PWM burst signal is used
which must be connected to BC. The internal low frequency oscillator must be programmed as described in the
independent burst dimming section and in Equation 13. Since the internal low frequency oscillator will be
synchronized to the frequency connected to BC it is recommended to program the internal low frequency close to
the frequency at BC. The synchronization is done using a PLL circuit. This PLL circuit needs an external
compensation network connected at BBR. For a typical burst frequency in the 100 Hz range using a 0.68 µF
capacitor in series with a 100 kΩ resistor is recommended. This R - C network should be connected between
BBR and GND.
The phase shift of the dimming burst compared to the input signal at BC is programmed with a voltage applied at
PH. The resulting phase shift can be calculated using Equation 15:
o
B VPH 180
V (15)
φB is the phase shift of the dimming burst and VPH is the voltage applied at the PH pin.
Layout Considerations
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. Use a common ground node for power ground and a different one for control ground to minimize the
effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
To layout the control ground, it is recommended to use short traces as well, separated from the power ground
traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and
control ground current.
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below.
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
The maximum recommended junction temperature (TJ) of the TPS68000 device is 125°C. The thermal resistance
of the 30-pin TSSOP package (PW) is RθJA = 63.9°C/W. Specified regulator operation is assured to a maximum
ambient temperature TA of 85°C. Therefore, the maximum power dissipation is about 626 mW. More power can
be dissipated if the maximum ambient temperature of the application is lower.
T J(MAX) T A
125 C o 85 C 626 mW
o o
P D(MAX)
R JA 63.9 C
W (16)

PACKAGE OPTION ADDENDUM
www.ti.com 12-Feb-2008
PACKAGING INFORMATION
Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TPS68000DBT ACTIVE TSSOP DBT 30 60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS68000DBTG4 ACTIVE TSSOP DBT 30 60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS68000DBTR ACTIVE TSSOP DBT 30 2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TPS68000DBTRG4 ACTIVE TSSOP DBT 30 2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 (mm) B0 (mm) K0 (mm) P1 W Pin1
Type Drawing Diameter Width (mm) (mm) Quadrant
(mm) W1 (mm)
TPS68000DBTR TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS68000DBTR TSSOP DBT 30 2000 346.0 346.0 33.0
Pack Materials-Page 2
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19-1626; Rev 4; 9/07

CCV 9 20 PGND Li+

________________________________________________________________ Maxim Integrated Products 1

PARAMETER CONDITIONS MIN TYP MAX UNITS

PARAMETER CONDITIONS MIN TYP MAX UNITS

BATTERY VOLTAGE CHARGING CURRENT-SENSE VOLTAGE INPUT CURRENT-SENSE VOLTAGE

CHARGING CURRENT-SENSE VOLTAGE (mV)

INPUT CURRENT-SENSE VOLTAGE (mV)

PIN NAME FUNCTION

Figure 1. Typical Application Circuit

R R/2 R/2 R/2

CELL TWO PWMOSC

Figure 3. PWM Controller Block Diagram

current-sense resistor may degrade accuracy due to Input Current Regulator

PREQUAL PREQUAL FAULT

VBATT > 2.5V

Figure 4. State Diagram

From initial power on

Undervoltage threshold ≤ battery voltage ≤ battery regu-

Battery voltage = battery regulation voltage, charging

Battery voltage = battery regulation voltage, charging

Recharge voltage threshold ≤ battery voltage ≤ battery

From fast-charge state or full-charge Charge current = 0, timers suspended,

From prequalification state if prequalifi-

Charge Monitoring Outputs REF 3

Setting the Input Current Limit

HIGHLY EFFICIENT PHASE SHIFT FULL BRIDGE CCFL CONTROLLER

AVAILABLE DEVICE OPTIONS

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

2 Submit Documentation Feedback

Submit Documentation Feedback 3

ELECTRICAL CHARACTERISTICS (continued)

4 Submit Documentation Feedback

Submit Documentation Feedback 5

PIN ASSIGNMENTS (continued)

6 Submit Documentation Feedback

FUNCTIONAL BLOCK DIAGRAM (TPS68000)

PARAMETER MEASUREMENT INFORMATION

Submit Documentation Feedback 7

OUTPUT VOLTAGE AT V5 OUTPUT VOLTAGE AT VREF

8 Submit Documentation Feedback

OPERATING FREQUENCY PHASE SHIFT OF OPERATING FREQUENCY

Phase Shift of Operating Frequency − °

BURST DIMMING DUTY CYCLE BURST DIMMING PHASE SHIFT

Burst Dimming Phase Shift − °

Submit Documentation Feedback 9

VEN (5 V / div) VEN (5 V / div)

Input Current (20 mA / div) Input Current (20 mA / div)

Timebase (100 µs /div) Timebase (100 µs /div)

Input Current (10 mA / div)

Timebase (100 µs /div)

10 Submit Documentation Feedback

LAMP CURRENT AND

Lamp Current (Voltage at CSEN) (5 V / div)

Lamp Voltage (Voltage at VSEN) (2 V / div)

Timebase (200 ms /div)

LAMP CURRENT AND

Lamp Current (Voltage at CSEN) (5 V / div)

Lamp Voltage (Voltage at VSEN) (2 V / div)

Timebase (200 ms /div)

Submit Documentation Feedback 11

LAMP CURRENT SOFTSTART

Timebase (100 µs /div)