Study of Boost type DC-DC Converter

for Single Solar Cell

Atsushi Nakajima Shigeo Masukawa

Department of Electrical and Electronic Engineering Department of Electrical and Electronic Engineering
Tokyo Denki University Tokyo Denki University
5 Senju Asahi-cho, Adachi-ku, Tokyo 120-8551, Japan 5 Senju Asahi-cho, Adachi-ku, Tokyo 120-8551, Japan
nakajima@atsushi.org masukawa@cck.dendai.ac.jp

Abstract— Solar cell systems have become popular with the
gradual improvement in cost and conversion efficiency. As a
recent trend, paint-type solar cells have been proposed. These
solar cells have several advantages which include: a follow-up
curved surface, free-shape and seam-less high design. In general,
a solar cell is fabricated based on a series of possible
configurations, and the output voltage of the solar module setup
can be up to several tens of volts. In applications which involve
exploiting the free-shape, these devices may not provide sufficient
current. Moreover, this current may then be interrupted as a
result of the small cell size or partial light blockage due to the
series construction. To address these problem, DC-DC converters
based on the performance of high-design solar cells have been
investigated. These components can be boosted to an easy-to-use
voltage for practical daily usage.
Keywords— Single Solar Cell; Boost type DC-DC Converter;
Start up in low voltage; High boost-up voltage ratio
I. INTRODUCTION
Solar power generation systems are in widespread use
around the globe (Fig. 1). In recent years, various types of solar
cells, such as thin film solar cells, have been put into practical
use in addition to crystalline Si based solar systems. [1] Recently,
the efficiency of perovskite based solar cells has improved to
over 20%[2], which has attracted significant attention. Painted
type solar cells are unique with features which include curved
surface conformability, free shape, and high design without
seams (Fig. 2, Fig. 3(b)). Generally, when using a solar cell, a
series structure is formed into a module with an output voltage
of tens of volts for ease of use (Fig. 3(a)). However, in the case
of a painted type, cells are painted directly on an object, and it
is considered to be difficult to separate the devices. When
curved surface compliance and free-shape are required, there is
the possibility that the cell may be limited by the current of the
shadow cell or by the cell with the smallest area, when
connected in series. As such the painted solar cell may not be
able to exhibit acceptable performance (Fig. 3(a)). In order to
address this problem, the authors have proposed[5] a DC-DC
converter that can boost the low voltage of a single-cell solar
cell to a voltage that is easy to use and can maximize the
performance of a highly-designed solar cell (Fig. 3(b)).

Enlarge

It be able to make any shape PVs

there are series structed lines to get high voltage

For Residence use For Industrial use Solar Watch For Vehicle roof Output decreases only for
(SHARP) (Kyocera) (Casio) (Toyota) The part which is not shadow shaded area
also decreases in output The Sun
The Sun

EV Charger Charging Smart phone Shadow

Shadow
(Nichicon) (InfinityPV)
(a)problem of the series structed PV (b)Merit of the single solar cell

(a)Stationary PV System (b)Mobile PV System

Fig. 3 Merit of the single solar cell
Fig. 1 Example of applications of PV system

Enlarge 0.5V 12V

Single DC-DC
Load
Solar Cell With MPPT
0.5V 5V 5V
Low
Voltage Control Power Supply
Charging a smartphone with a PV Start Up Circuit to control
incorporated in a suit Circuit
Fig. 2 Schematic of application of the painted PV Fig. 4 A block diagram of the single solar cell system

978-1-5090-6684-1/18/$31.00 ©2018 IEEE 1946

 II. CIRCUIT CONFIGURATION AND ITS OPERATION switching device is a challenge. To address this problem, one
II-I Circuit configuration possibility is to use a charge pump IC [3] with a threshold
voltage of 0.3 V using a SOI (Silicon on insulator) process.
A Block diagram of the boost type DC-DC converter However, in this report, a self-excited flyback power supply
system for the single solar cell is represented in Fig. 4. It circuit that can be initiated with a general transistor will be
consists of a low voltage start up circuit, a control circuit, a investigated. The circuit diagram is shown in Fig. 6 and Fig. 7.
control power supply, and a DC-DC converter. A general The current from the solar cell charges the capacitor Cf via the
overview of the flow of operation is provided in Fig. 5. During resistor Rs. As the capacitor Cf is charged, the base potential VB
operation, the low voltage starting power supply circuit is of the transistor Tr approaches the threshold voltage Vth, and
activated by the open voltage of the single solar cell and the collector-emitter resistance RCE gradually decreases. Then,
supplies power to the control circuit. The control circuit turns the voltage VLs across the transformer primary winding Ls
ON/OFF the semiconductor switch of the main circuit, and the approaches the solar cell voltage VPV. When a voltage is
main circuit boosts the voltage of the single solar cell to several generated in Ls, a voltage corresponding to the winding ratio of
tens of volts. The boosted output voltage is used as the control Ls:Lf is generated in the secondary winding Lf. VLf is added to
power supply, and when the operation is stabilized, the low VCf, and VB exceeds the threshold voltage of the transistor Tr.
Then, VLs is equal to VPV, a voltage VLo is generated in the
0.5V 0.5V 12V
tertiary winding Lo, and energy is stored. When the charge of
Single
Solar Cell
DC-DC
With MPPT
Load Single
Solar Cell
DC-DC
With MPPT
Load Cf is released and VB becomes lower than Vth, Tr turns OFF,
0.5V
Low
5V 0.5V
Low
5V and a voltage of opposite polarity is generated from Lo to
Voltage
Start Up
Control
Circuit
Power Supply
to control
Voltage
Start Up
Control
Circuit
Power Supply
to control
charge Co. This operating is repeated as a 1 cycle. When Co is
Circuit Circuit charged and the Pch-FET Tro of the output stage is turned on, a
(a) The Start Up Circuit is going to operate (c) The Main Conv. operates and provides power to the Load
switchable voltage is supplied to the control circuit.
0.5V 0.5V 12V
II-III the DC-DC converter circuit
Single
Solar Cell
DC-DC
With MPPT
Load Single
Solar Cell
DC-DC
With MPPT
Load In a DC-DC converter for realizing a comparatively high
0.5V
Low
5V 0.5V
Low
5V input / output voltage ratio, a system in which the step-up ratio
Voltage
Start Up
Control
Circuit
Power Supply
to control
Voltage
Start Up
Control
Circuit
Power Supply
to control
is increased by using a high-frequency transformer is generally
Circuit Circuit used. Since the DC-DC converter has low voltage and large
(b) The Control Circuit is going to operate (d) The Power Supply operates, the Start Up Circuit stop operating
input current, it is necessary to maintain the resistance of the
Fig. 5 Operating procedure of the single solar cell system circuit at a low value. Considering the MPPT control in this
voltage starting power supply circuit is disconnected, and the setting, the push-pull configuration was selected[4] (Table 1).
operation shifts to the MPPT (Maximum Power Point Table 1 Choice of main circuit
Tracking) control. In the next section, the low voltage start up Non Insulated type Insulated type (Push Pull)
circuit and the DC-DC converter circuit will be described. Boost Buck Boost Buck(Typical Push Pull)
Importance

L DB SW L T
Do1 Io Do1 Io
T L
Ipv L Co RL Vo Ipv Co RL Vo

II-II The low voltage start up circuit Vpv

PV
Ci SW CO VO Vpv
PV
Ci DA CO VO
Vpv
PV
Ci
SW1 SW2
Do2
Vpv
PV
Ci
SW1 SW2
Do2

4<α<20 0<α<20
In the case of boosting a voltage in the low of 0.5 to 0.7 V Boost ratio α 10 △ 1<α<5 × 0<α<1 ◎
(winding ratio1:4)
○
(winding ratio1:20)
Continuity of
for a single cell solar cell, establishing a voltage to drive the input current
9 ○ continuous × discontinuous ○ continuous × discontinuous
SW:1, SW:1,
Number of SW:1, SW:1,
Di:1, Di:1,
passing elements 8 ◎ ◎ Di:1, ○ Di1,○
Transformer L:1, L:1,
(for efficiency) L:1 L:1
T:1 T:1
Resister to start T
Do Tro Output SW
Diode Transistor Cost 7 ◎ SW:1, Di:1, L:1, C2 ◎ SW:1, Di:1, L:1, C2 ○ SW:2, Di:2, L:1, T:1, C2 ○ SW:2, Di:2, L:1, T:1, C2
Judgment △ × ◎ ○
Iout
Single Solar Cell Rs Ls T Do1
Lo iL
Vin Co RL
Condenser to Load Iin Co RL Vout
Cf Rf store energy
Ld
(control circuit)
Tr

Transistor to Lf vL
switching Do2
Vin Cin
Fig. 6 The low voltage start up circuit PV SW1 SW2

Do Tro - ＋ Do Tro
Fig. 8 The boost type DC-DC converter circuit.
Rs Ls Rs Ls
Vin≧0.5V ＋ Do1
Lo Co RL Lo Co RL Io Do1 Io
Vin - T T
＋ -
＋ - Ipv Ld Co1 RL1 Vo1 Ipv Co1 RL1 Vo1
Ld
OFF Cf Rf -
Cf Rf Tr
Tr Lf Lf Do2 Do2
＋ Vpv Ci Vpv
SW1：ON Ci

× Tro PV SW1 SW2 PV SW1 SW2 SW1：OFF

(a) Mode Start Up Do (c) Mode2 SW OFF SW2：ON
＋ On output Do Tro SW2：ON
(a) Mode1 (c) Mode3
Ls Ls Do1 Io Do1 Io
Rs Rs T T
＋
Lo Co RL Lo Co RL
Vin Vin - Ipv Co1 RL1 Vo1 Ipv Ld Co1 RL1 Vo1
＋ Ld
＋ Vco≧5V
Do2 Do2 This Mode is not used
Tr ON Cf Rf
Lf
Cf Rf
Lf Vo≧5V Vpv Vpv
Tr Ci Ci
SW1 SW2 SW1：ON PV SW1：OFF
PV SW1 SW2
SW2：OFF SW2：OFF
(b) Mode1 SW ON (d) Mode Output (d) Mode4
(b) Mode2

Fig. 7 Operating modes of the low voltage start up circuit Fig. 9 Operating modes of the main circuit

1947
The circuit diagram of the boost type converter with a high waveforms before and after the output Pch FET Tro. This
frequency transformer is shown in Fig. 8. Since it is necessary represents the voltage before the FET output starts to gradually
to secure a current path of the DC inductor current iL, there is rise, beginning at the circuit starting time, until a certain
no timing whereby both switches SW1 and SW2 are OFF (Fig. threshold voltage is achieved; the FET turns on and the voltage
9). Therefore, it is necessary to control the switching timing is outputted. As a result, start-up failure due to an inrush
within 0.5 <Duty <1. current of the control circuit connected to the subsequent stage
is suppressed.
III. FUNDAMENTAL EXPERIMENT III-II Target solar cell and load
III-I The low voltage start up circuit The target solar cell is assumed to be applied to wearable
The low voltage start up circuit is shown in Fig. 6 and its devices and the like. Assuming that the area is 100,000 mm2
operation is confirmed. The parameters are shown in Table 2 (one side is about 300 mm) and the photoelectric conversion
and the waveforms of each component is shown in Fig. 10. Fig. efficiency is 10%, the solar cell output when the solar radiation
10(a) shows the waveform of the collector-emitter voltage VCE intensity is 1 kW/m2 is set to PPV = 10 W. When the solar cell
of the transistor and the base potential VBE. Oscillation occurs Table 3 The main circuit configuration
at a frequency of 410 kHz, the duty cycle = 81%, and an output
Components SPECs
voltage VCO = 5 V is obtained. Fig. 10(b) shows the voltage PV Kikusui PWR400L Vin:0~80V,
Table 2 Circuit configuration of the low voltage start up circuit DC Source Iin:0~25A,
RL Kikusui PLZ164WA Vout:0~150V
Parts SPECs Electronic Load Iout:0~33A
Tr 2n4923 Ci, Co Electrolytic capacitor 100μF
Rs 470Ω DC Inductor Ld Core:TDK PC40 Ni-Zn 10μH
Cf 5μF Transformer Core TDK PC40 Ni-Zn winding ratio 1:10
Rf 10Ω SW1, SW2 ON Semiconductor RDS(ON)<=0.7mΩ
Ls 5Turn NVMFS5C404N
Lf 10Turn Do1, Do2 Sanken VF=0.55V
FMEN-2208
Lo 30Turn
SWf 100kHz
Co 100μF
Voltage [2V/div.]

Do D1FH3 6

Tro REP15P05 4

2
Experimental DATA
8 Vco 2.0 GND
Experimental DATA Vcar Vsw1 Vsw2 Vdy*
1.5 -2 0 8 16 24 32 40
6 Vce
Vbe, Vo[V]

(b) Duty80% Time t[μsec.]

Vce[V]

4 1.0
Fig. 11 Waveform of the boost type push-pull PWM signal
0.5 10 25
2 Vbe 8 200kHz 20
6 15
4 iL： 5A/div. 10
-2 -0.5 2 vL：2V/div. 5
vL：GND iL ：GND
-2 200kHz -5
-4 -1.0
-4 -10
0 1 2 43 5 6 7 8 9 10 -15
t[μsec.] -6
-8 Experimental DATA 2μs/div. -20
(a) Output Voltage vo and Transistor Voltage vbe, vce
0 4 8 12 16 20
Vin[200mV/div.], Vco, Vo[2V/div.]

Vin:200mV/div, Vco:2V/div, Vo:2V/div, 4sec./div 8 Time t[μsec.]

0.6 (a) DC Inductor Voltage and Current
0.4 6 50 iSW1：
Experimental DATA
40 5A/div. 25
0.2 Vin=0.5V Vco=5V 4 30 20
vSW1：
Vin GND

Vo
20 100kHz 10V/div. 15
2
10 10
vSW1：GND 5
Experimental DATA -10 100kHz iSW1 ：GND
28 32 -20 2μs/div. -5
0 8 12 24 ON OFF ON
t[sec.] 0 4 8 16 12 20
(b) Operation of the Output Transistor Tro Time t[μsec.]
(b) Switch SW1 Voltage and Current
Fig. 10 Operating modes of the low voltage start up circuit Fig. 12 Waveform of the DC inductor and semiconductor switches

1948
voltage VPV = 0.5 V, the current IPV = 20 A is obtained. Also, the region of 0.7 V<Vin<1.3 V, almost no change in efficiency
the load is assumed to be a 12 V battery. In this situation, a DC is seen. In the region where Vin>1.3, the efficiency gradually
power supply with suitable specifications was used for stable increases, with peaks at Vin=1.8 V, η=64.4%. As Vin is further
measurement of the electric performance. increased, the efficiency gradually decreased, with η =61.5% at
Vin=2.0 V. Fig. 13(b) shows the power conversion efficiency η
III-III Boost operation with input voltage Vin=1.5 V and output voltage Vout=12 V,
To confirm the operation of the main circuit, an experiment versus the output power Pout. When the output power Pout=2.6
was conducted. Various parameters are shown in Table 3. The W, the power conversion efficiency η is 44%, and the
gate pulses Vsw1 and Vsw2 are shown in Fig. 11. Fig. 13 efficiency increases as the output power increases. A peak is
shows the power that can be output when the output power observed with η=65% at Pout=7 W, and the output power has a
Vout is fixed at 12 V. When the input voltage Vin=0.5 V, the high efficiency and starts to decrease, with η=53% at Pout=10
output power Pout is obtained as 1.5 W, and a sufficient output W.
is not obtained from the single solar cell. As the input voltage
Vin is increased, the output Pout also increases, and in the range IV. MODELING OF INPUT RESISTANCE OF MAIN CIRCUIT
of Vin> 1.4 V, an output of Pout=10 W is obtained. The
waveforms of the DC inductor voltage vL and current iL when IV-I Modeling of input resistance
Vin=1.5 V, Vout=12 V and Pout=10 W are shown in Fig. 12(a). Similar to this study, when attempting to obtain a high
The drain-source voltage vSW1 and current iSW1 of the switch output for a circuit with an input voltage as low as 0.5 V, the
SW1 are shown in Fig. 12(b). As shown in Fig. 12, while the input resistance becomes a problem. According to the
switch voltage and current are at 100 kHz, the DC inductor experimental results of a fabricated test circuit, when the input
voltage and the current are at 200 kHz, and the currents of voltage Vin=0.5 V and Vout=12 V, the input current Iin is up to
switches 1 and 2 are summed. Also, at the moment when the 7 A and the input power Pin is up to 3.5 W. Further, the output
conductor switch turns off, a large surge voltage is generated in power Pout at this time is 1.5 W, and the efficiency is slightly
both the switch and the DC inductor, whereby the DC inductor lower than 50%. In order to consider the operation of such a
current drops sharply. Subsequently, the convergence of the low voltage input DC-DC converter, we model the circuit in
surge voltage and the DC inductor current become constant. the steady state of the converter, as shown in Fig. 15. In the
III-IV Power conversion efficiency DC-DC converter with a low input voltage (Vin), a large current
Iin flows through the input stage, so the loss due to the input
Fig. 13 (a) shows the power conversion efficiency η when resistance Rin is large. The power Pin-a which can be input to
the output voltage Vout=12 V is fixed under the same conditions the actual DC-DC converter is given by Equation (1).
as in Section III-III, versus the input voltage Vin. In the vicinity
of Vin=0.1 V, η=65%; the efficiency decreases as Vin is
increased, such that η=33% in the vicinity of Vin=0.7 V, and in 30 6 0.6
Iin[A] Experimental DATA Simulation 20A,5.2W

Available Input Power[W]

25

Actual Input Voltage[V]

Resistance[mΩ] 5 0.5
Cuttent[A], Circuit
Resistance[mΩ]

20 4 0.4
Duty100%
Vin：Parameter, Vout=12V Const. 15
12 3 0.3
100.0% 12 10
2 At20A, Available Input Power=5.2W 0.2
1.4V,10W 5 Circuit inside Resistance is 12mΩ
Output Power Pout[W]

available Input Power[W]

80.0% 10 0
1
Actual Input Voltage[V]
0.1
VOut=12V Const.
Efficiency η[%]

0 0.1 0.2 0.3 0 0

8 Input Voltage Vin[V] 0 5 10 15 20
60.0% Input Current[A]
(a)Experimental DATA of Inside Resistance of the Main Circuit (c) Calculated value of the Available Input Power
6 (In the case of Circuit inside resistance=12mΩ)
40.0% 0.6
4 Vin=0.5V Const. Voltage Drop[V]
0.5 The Relationship of each part of Power
20.0% 0.5V,1.5W Efficiency[%] Actual Input Voltage[V]
2 Rin[mΩ] Pin[W] Pin-a[W] Pout
Voltage[V]

0.4
Pout[W] 0.3 Static 12 10.4 5.2 -
20A,0.26V
0.0% 0 0.2 Simulation With Switching 35.6 3.5 1.76 1.5
0 0.5 1 1.5 2 0.1
At 20A, Actual Input Voltage=0.26V
0
Input Voltage Vin[V] 0 5 10 15 20 25
(a) The Relationship between Input voltage, Output power and Efficiency Current[A]
(b) Calculated value of the Actual Input Voltage
(In the case of Circuit inside resistance=12mΩ)

Vin=1.5V Const., Vout=12V Const.

100.0 Fig. 14 Relation between input resistance and available input power
Experimental DATA
7W,65%
80.0
Efficiency η[%]

Previous of the
2.6W,44% 10W,53% Pin Later of the
60.0 Transformer Pin-a
Iin Rin Transformer Pout
40.0
Efficiency[%]
20.0 35.6mΩ
Vin Vin-a Vout
0.0
0 2 4 6 8 10 12
Pin=3.5W Pin-a=1.76W Pout=1.5W
Putput power Pout[W]
(b) The Relationship between Output power and Efficiency
Fig. 13 Static characteristics of the main circuit Fig. 15 A input model of the boost type DC-DC Converter

1949
Pin-a=-Rin 2 +Vin・Iin ・・・・・・・・・・・・・・・(1) and finally the combination effect of these changes is discussed.
When the input power Pin of the prototype circuit is Pin=3.5 W, V-II Reduction of element resistance
the input resistance is Rin=35.6 mΩ, and the maximum real The relationship between the actual input power Pin-a and
input power Pin-aMAX=1.76 W, which is indicated by equation the efficiency η of the input stage when the input resistance Rin
(2). is used as a parameter is shown in equation (3).
Vin 2  =1-
R in
Pin-a MAX  ・・・・・・・・・・・・・・(2) V in
Iin
4・Rin 2
V in  V in  4・ P i n - a
The relationship between the input current Iin and the actual R in
± 
 R in 
 
R in ・・・・・・・・・・・(3)
Iin =
input power Pin-a is shown in Fig. 16 2
A graph of the actual input power Pin-a versus the input
2 Vin 2 efficiency η when the input resistance Rin is reduced, is shown
1.76W Pin-a MAX 
in Fig. 17(b). With the input resistance Rin<5 mΩ, electric
Actual Input Ppower

1.5 4・Rin
Simulation power of 10 W or more can be obtained and the efficiency is
Pin-a[W]

1 about 70%.

0.5
V-III Main circuit parallelization
2
Pin-a=-Rin・Iin +Vin・Iin By parallelizing the primary side across the transformer of
0
the main circuit, the input resistance Rin can be reduced, and by
0 5 10 15
serializing the secondary side of the transformer, this
Input Cirrent Iin[A]
contributes to a high voltage output. The main circuit of “m”
Fig. 16 Relation between input current and actual input power parallel input and “n” serial output type is shown in Fig. 18.
Vin 2 2
Vin・ Para
V. EXAMINATION OF HIGH POWER AND HIGH EFFICIENCY Pin-a MAX = =
4・Rin 4・Rin1 ・・・・・・・・・(4)
V-I Resistance reduction of main circuit Rin1
Rin=
Reducing the input resistance Rin leads to a high power Para
input and high efficiency. There are two directions of how to assuming that the input resistance of the main circuit is Rin1
reduce the input resistance Rin. One is reducing resistance of where the parallel number of the primary side is Para. The
the circuit elements itself for example switching devices, DC actual input power Pin-aMAX that can be input is as shown in
inductors and transformers etc. The other is multiply equation (4).
parallelizing the circuit without changing the elements. In this
study, firstly, the effect of lowering the resistance of the The relationship between the number of primary side Para
element is discussed, secondly, the parallelization is performed, and feasible real input power Pin-aMAX is shown in Fig. 19. In
this case, by substituting the second line of equation (4) into
equation (3), a relational expression between the real input
2.5 100% 100%
35.6mΩ power when the primary side of the main circuit is parallel and
Input Efficiency ηin[%]

2 80% 30mΩ
80%
the efficiency η of the input stage is obtained. A graph of the
Losses[W]

Experimental 72% 25mΩ

1.5 60% 20mΩ
1
DATA 40%
60%
15mΩ
10mΩ
real input power Pin-a versus the input efficiency η under this
0.5 20% 40%
Simulation
7.5mΩ
5mΩ
condition is shown in Fig. 8. It can be seen that an input of 10
0 0% 20%
Simulation
2.5mΩ
1mΩ
W or more is possible if the primary side of the main circuit
0%
0 10 20 30 40
has 6 or more parallel circuits. The efficiency is approximately
Actual Input Power Pin-a[W] 60%.
(a)Target of Reducing Losses of the Main Circuit (b) Relation actual input power between input efficiency
(Parameter is resistance of circuit)
V-IV Reduction of element resistance and parallelization
Fig. 17 Effect of reducing input resistance
Do1-1 Iout Fig. 20 shows a graph of the actual input power and
T-1
iL-1
Iin Co-1
Ld-1 100%
90% 1para.
vL-1 2para.
Input efficiency ηin[%]

Vin Do2- 80%

Cin-1 1 70%
3para.
RL Vout
PV SW1-1 SW2-1 60%
4para.
50%
5para.
T-n Do1-n 6para.
iL-n 40%
7para.
Co-n 30%
Ld-n 8para.
20%
Simulation 9para.
vL-n 10%
Do2-n 10para.
0%
Cin-n
0 5 10 15 20 25 30
SW1-n SW2-n
Actual Input Power Pin-a[W]
Fig. 18 A proposed circuit of the boost type DC-DC Converter Fig. 19 Relation between actual input power and input efficiency

1950
 efficiency when the input resistance Rin1 of one main circuit is 12
reduced to 7.5 mΩ and further parallelized. By reducing the 10

Power Pin, Pout[W]

1Para. Pin
input resistance, making the circuit four in parallel, it is found 8 4Para. Pin
that the efficiency becomes 90% or more while ensuring an
input power of 10 W. Four parallel and four series circuits were 6 1Para. Pout
fabricated and the effect was verified. As shown in Fig. 21, the 4 4Para. Pout
control phases of the four parallel circuits are shifted by 45 °. 2
The control phase of the “m” parallel circuit is obtained by 360 0
÷ 2 m. As shown in Fig. 22, the input and output voltage 0 0.1 0.2 0.3 0.4 0.5
current waveforms are combined with the switching Input Voltage Vin[V]
components of each circuit, resulting in a ripple of 800 MHz. (a) Input Voltage VS Available Power
As shown in Fig. 23 (a), it can be seen that both the input
power and the output power have improved by 4-parallelization. Input Power Pin[W]
The efficiency is approximately 50 to 60%; thus, the reduction 0 5 10
of the switching and transformer losses is important. 70.0
60.0

Efficiency η[%]
50.0
100%
40.0
Input Efficiency ηin[%]

1para.
95% 30.0
2para. Pout-Efficiency
20.0
90% 3para. Pin-Efficiency
10.0
85% 4para. 0.0
0 2 4
80% When the Input Resistance of one Output Power Pout[W]
75% circuit Rin1 is reduced to 7.5mΩ (b) Power VS Efficiency

70% Fig. 23 Static characteristics of the 4 parallel 4 series circuit

0 10 20 30
Actual Input Power Pin-a[W] VI. CONCLUSION
A boost type DC-DC converter for single solar cells was
Fig. 20 Relation between actual input power and input efficiency investigated. A low voltage starting circuit was fabricated, and
it was experimentally confirmed that it is possible to
commence operation at a low voltage in a circuit using
Circuit4-Ch1 common elements. Moreover, a prototype of the main circuit
was constructed, and the operation was confirmed by
Voltage [5V/div.]

Circuit3-Ch1 experiment. In the case of boost operation for voltages in the

range of 0.5 V to 12 V, assuming a single solar cell, an output
Circuit2-Ch1 power of 1.5 W was obtained. We then investigated the input
resistance reduction method for high output and high efficiency
Circuit1-SW1 of the low voltage input DC-DC converter. The effect was
5V/div., 2μs/div. experimentally confirmed, and it was possible to obtain an
0 4 8 12 16 20 output of approximately 4 W for the condition Vin=0.5 V,
Time t[μsec.] Vout=12 V. The next step of this investigation will involve the
Experimental DATA
application of this approach to actual solar cells.
Fig. 21 Waveforms of the 4 phases PWM pulses
(each shifted by 45°) REFERENCES
20 2
18 Output Voltage 1.8 [1] N. Kasa, H. Asahara and T. Dansako, “Demonstration Test of Organic
Input Current
Output Voltage Vout[V]

Output Current Iout[A]

16 1.6 Photovoltaics:-A Visit to Mizushima Plant of Mitsubishi Chemical

Input Voltage Vin[V],
Input Current Iin[A],

Input Voltage
14 1.4 Corporation-”, IEEJ Magazine, Vol.136 No.5, pp.266-269, 2016
Vout 12V Output Current
12 1.2 [2] Best Reserch-Cell Efficiencies, National Renewable Energy Laboratory,
10 Iin 11.3A 1 Rev. 03-09-2016
Vin DC0.5V+ Ripple1.2Vp-p800MHz [3] SII very low voltage charge pump IC S882Z Datasheet
8 0.8
6 0.6 [4] D. Yoshitomi, K. Hirachi and K. Fujisawa, “Control of Surge Voltage
4 0.4 for Current Mode DC/DC Converter”, IEEJ SPC11 25-48.50-54 pp.89-
94, 2011-1
2 Iout 280mA
0.2
1.25μs/div. [5] A. Nakajima, S. Masukawa, “A study of the Boost type DC-DC
0 0
Converter for the Single Solar Cell” IEEJ industrial application section
0 1.25 2.5 3.75 5 6.25 7.5 8.75 10 meeting 1-45 Aug. 30th, 2016
time[μsec.]

Fig. 22 Waveforms of the 4 parallel 4 series circuit

1951

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