1.

DESIGN AND SIMULATION OF 8-BIT ADDER

PROGRAM:
module ripple_8adder( a,b,cin,sum,carry );
input [7:0] a;
input [7:0] b;
inputcin;
output [7:0] sum;
output carry;
wire [6:0]c;
fulladder FA1(a[0],b[0],cin,sum[0],c[0]);
fulladder FA2(a[1],b[1],c[0],sum[1],c[1]);
fulladder FA3(a[2],b[2],c[1],sum[2],c[2]);
fulladder FA4(a[3],b[3],c[2],sum[3],c[3]);
fulladder FA5(a[4],b[4],c[3],sum[4],c[4]);
fulladder FA6(a[5],b[5],c[4],sum[5],c[5]);
fulladder FA7(a[6],b[6],c[5],sum[6],c[6]);
fulladder FA8(a[7],b[7],c[6],sum[7],carry);
endmodule

modulefulladder (x, y, z, s, co);

input x, y, z;
output s, co;
wire t1, t2, t3;
xor G1 (t1, x, y), G2 (s, t1, z);
and G3 (t2, x, y), G4 (t3, t1, z);
or G5 (co, t2, t3);
endmodule
RTL – SCHEMATIC:

VERILOG TEST FIXTURE:

module rcas;

// Inputs
reg [7:0] a;
reg [7:0] b;
reg cin;
 // Outputs
wire [7:0] sum;
wire carry;

// Instantiate the Unit Under Test (UUT)

RCA uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.carry(carry)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
cin = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

a=8'h02; b=8'h43;cin=1'b1;
#100
a=8'h01; b=8'h03;cin=1'b0;

end

endmodule

SIMULATED OUTPUT:
 2.DESIGN AND SIMULATION OF 4-BIT BOOTH’S MULTIPLIER AND SHIFT & ADD
MULTIPLIER
(i)BOOTHS MULTIPLIER
PROGRAM:
modulebm(xa,ya,za);
input [3:0]xa;
input [3:0]ya;
output [7:0]za;
integeri;
reg[9:0]temp;
reg[1:0]a;
reg[5:0]y;
reg[5:0]x;
reg[9:0]z;
reg[7:0]za;
always@ (xa or ya)
begin
y[5:0]=6’b000000;
y[5:1]=ya[3:0];
x[4:0]=xa[3:0];
z=9’b000000000;
temp=10’b0000000000;
for(i=0;i<=4;i=i+1)
begin
a[0]=y[i];
a[1]=y[i+1];
case(a)
2’b01:temp[4:0]=x[4:0];
2’b10:temp[4:0]=(~x[4:0])+5’b0001;
2’b11:temp[4:0]=5’b00000;
2’b00:temp[4:0]=5’b00000;
endcase
if(temp[4]==0)
begin
temp[9:5]=5’b00000;
end
else
begin
temp[9:5]=5’b11111;
end
temp=temp<<i;
z=z+temp;
end
za=z;
endendmodule
RTL- SCHEMATIC:

VERILOG TEST FIXTURE:

module bms;

// Inputs
reg [3:0] xa;
reg [3:0] ya;

// Outputs
wire [7:0] za;

// Instantiate the Unit Under Test (UUT)

bm uut (
.xa(xa),
.ya(ya),
.za(za)
);

initial begin
// Initialize Inputs
xa = 0;
ya = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

xa=4'b0001;ya=4'b0100;
#100
xa=4'b1001;ya=4'b001;
end

endmodule
SIMULATED OUTPUT:

(ii)SHIFT AND ADD MULTIPLIER

PROGRAM:
modulesmul(x,y, reset,z);
input [3:0]x;
input [3:0]y;
input reset;
output [7:0]z;
wireco,ci;
reg[7:0]t;
reg[7:0]z;
integeri,j;
always@(x or y or reset)
begin
if(reset)
z=8'b0;
j=0;
for(i=0;i<4;i=i+1)
begin
t=8'b0;
if(y[i])
begin
t[i]=x[0];
t[i+1]=x[1];
t[i+2]=x[2];
t[i+3]=x[3];
end
z=z+t;
end
end
endmodule
RTL-SCHEMATIC:

VERILOG TEST FIXTURE:

module smuls;

// Inputs
reg [3:0] x;
reg [3:0] y;
reg reset;

// Outputs
wire [7:0] z;

// Instantiate the Unit Under Test (UUT)

smul uut (
.x(x),
.y(y),
.reset(reset),
.z(z)
);

initial begin
// Initialize Inputs
x = 0;
y = 0;
reset = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

reset = 1;
x=4'b0001;y=4'b0100;
#100
x=4'b1001;y=4'b001;
 end

endmodule

SIMULATED OUTPUT:

3.DESIGN AND SIMULATE 4-BIT ALU

PROGRAM:
module imp(a,b,opcode,dataz,compz);
input [3:0]a;
input [3:0]b;
input [1:0]opcode;
output [3:0]dataz;
outputcompz;
parameter ADD=0,NAND=1,GT=2,XOR=3;
assign
dataz=(opcode==ADD)?a+b:(opcode==NAND)?~(a&b):(opcode==XOR)?a^b:'bx;
assign
compz=(opcode==GT)?a>b:'bx;
endmodule
RTL- SCHEMATIC:
VERILOG TEST FIXTURE:

module imps;

// Inputs
reg [3:0] a;
reg [3:0] b;
reg [1:0] opcode;

// Outputs
wire [3:0] dataz;
wire compz;

// Instantiate the Unit Under Test (UUT)

imp uut (
.a(a),
.b(b),
.opcode(opcode),
.dataz(dataz),
.compz(compz)
);

initial begin
// Initialize Inputs
a = 0;
b = 0;
opcode = 0;

// Wait 100 ns for global reset to finish

#100;
a=4'b0101;b=4'b1010;
opcode=2'b00;
#100;
a=4'b1101;b=4'b1010;
opcode=2'b01;
#100;
a=4'b0111;b=4'b1010;
opcode=2'b10;
#100;
a=4'b0101;b=4'b1010;
opcode=2'b11;
// Add stimulus here

end

endmodule
SIMULATED OUTPUT:

4.DESIGN AND SIMULATION OF UNIVERSAL SHIFT REGISTER

PROGRAM:
module uni_shift_8b1(op,clk,rst_a, sh_ro_lt_rt,ip);
outputreg [7:0] op;
input [1:0] sh_ro_lt_rt;
input [7:0] ip;
inputclk, rst_a;
reg [7:0]temp;
always @(posedgeclk or posedgerst_a)
begin
if (rst_a)
op = 8'h00;
else
begin //Load Input
temp = ip;
end
//Operation
case (sh_ro_lt_rt)
2'b00: op = temp<<1; //Left Shift
2'b01: op = temp>>1; //Right Shift
2'b10: op = {temp[6:0],temp[7]}; //Rotate Left
2'b11: op = {temp[0], temp[7:1]}; //Rotate Right
default: $display("Invalid Shift Control Input");
endcase
endendmodule

RTL- SCHEMATIC:
VERILOG TEST FIXTURE:

`timescale 1ns/1ps
module uni_shift_8b1_tst;
reg [7:0] ip;
reg [1:0] sh_ro_lt_rt;
regrst_a,clk;
wire [7:0] op;

uni_shift_8b1 u1 (.op(op),.clk(clk),.rst_a(rst_a),.sh_ro_lt_rt(sh_ro_lt_rt), .ip(ip));

initial
begin
clk=1'b1;
forever #10 clk=~clk;
end

initial
begin
$monitor("ip:%b,rst_a:%b,sh_ro_lt_rt:%b, op:%b",ip,rst_a,sh_ro_lt_rt,op);
ip = 8'b11001100;
rst_a = 1'b1;
sh_ro_lt_rt = 2'b00;
#40;

ip = 8'b10001100;
rst_a = 1'b0;
sh_ro_lt_rt = 2'b00;
#80;

ip = 8'b11001100;
sh_ro_lt_rt = 2'b01;
#120;

ip = 8'b10101101;

sh_ro_lt_rt = 2'b10;
#160;

ip = 8'b11001101;
sh_ro_lt_rt = 2'b11;
#200;
$finish;

end
endmodule

SIMULATED OUTPUT:

5.ANALYSIS AND SIMULATION OF STATE MACHINES

PROGRAM:
Mealy Model:
moduleMealy_Zero_Detector ( output regy_out, input x_in, clock, reset );
reg[1: 0] state, next_state;
parameterS0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always @ ( posedgeclock, negedgereset)
if (reset == 0) state <= S0;
elsestate <= next_state;
always @ (state, x_in) // Form the next state
case(state)
S0: if (x_in) next_state = S1; else next_state = S0;
S1: if (x_in) next_state = S3; else next_state = S0;
S2: if (~x_in) next_state = S0; else next_state = S2;
S3: if (x_in) next_state = S2; else next_state = S0;
endcase
always @ (state, x_in) // Form the Mealy output
case(state)
S0: y_out = 0;
S1, S2, S3: y_out = ~x_in;
endcase
endmodule
RTL-SCHEMATIC:
SIMULATED OUPUT:

Moore Model:
moduleMoore_Model ( output [1: 0] y_out, input x_in, clock, reset );
reg[1: 0] state;
parameterS0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
always@ ( posedgeclock, negedgereset)
if(reset == 0) state <= S0; // Initialize to state S0
else case (state)
S0: if (~x_in) state <= S1; else state <= S0;
S1: if (x_in) state <= S2; else state <= S3;
S2: if (~x_in) state <= S3; else state <= S2;
S3: if (~x_in) state <= S0; else state <= S3;
endcase
assigny_out = state; // Output of flip-fl ops
endmodule
RTL-SCHEMATIC:

VERILOG TEST FIXTURE:

moduleMoore_Model_test;
reg clock, x_in, reset; wire [1:0] y_out;
Moore_Modeluut (y_out, x_in, clock,reset);
initial
begin
clock = 1'b0; reset = 1'b0;
#15 reset = 1'b1;
end
always #5 clock = ~clock;
initial
begin
#12 x_in = 1'b1; #10 x_in = 1'b0;
#10 x_in = 1'b1; #10 x_in = 1'b0;
#10 $finish;
end
endmodule

SIMULATED OUPUT:
6.DESIGN AND SIMULATION OF SYNCHRONOUS SINGLE PORT RANDOM ACCESS
MEMORY

PROGRAM:
module memory(clk_write, address_write,
data_write, write_enable,
clk_read, address_read, data_read);

parameter D_WIDTH = 16;

parameter A_WIDTH = 4;
parameter A_MAX = 16; // 2^A_WIDTH

// Write port
inputclk_write;
input [A_WIDTH-1:0] address_write;
input [D_WIDTH-1:0] data_write;
inputwrite_enable;

// Read port
inputclk_read;
input [A_WIDTH-1:0] address_read;
output [D_WIDTH-1:0] data_read;

reg [D_WIDTH-1:0] data_read;

// Memory as multi-dimensional array

reg [D_WIDTH-1:0] memory [A_MAX-1:0];

// Write data to memory

always @(posedgeclk_write) begin
if (write_enable) begin
memory[address_write] <= data_write;
end
end

// Read data from memory

always @(posedgeclk_read) begin
 data_read<= memory[address_read];
end
endmodule

RTL-SCHEMATIC:

VERILOG TEST FIXTURE:

modulememtest;

// Inputs
regclk_write;
reg [3:0] address_write;
reg [15:0] data_write;
regwrite_enable;
regclk_read;
reg [3:0] address_read;

// Outputs
wire [15:0] data_read;

// Instantiate the Unit Under Test (UUT)

ramuut (
.clk_write(clk_write),
.address_write(address_write),
.data_write(data_write),
.write_enable(write_enable),
.clk_read(clk_read),
.address_read(address_read),
 .data_read(data_read)
);

initial begin
// Initialize Inputs
clk_write = 0;
address_write = 0;
data_write = 0;
write_enable = 0;
clk_read = 0;
address_read = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

address_read = 5'h1B;
address_write = address_read;

// $display("Read initial data.");

toggle_clk_read;
// $display("data[%0h]: %0h", address_read, data_read);

// $display("Write new data.");

write_enable = 1;
data_write = 8'hC5;
toggle_clk_write;
write_enable = 0;

// $display("Read new data.");

toggle_clk_read;
//$display("data[%0h]: %0h", address_read, data_read);
end

tasktoggle_clk_write;
begin
#10 clk_write = ~clk_write;
#10 clk_write = ~clk_write;
end
endtask

tasktoggle_clk_read;
begin
#10 clk_read = ~clk_read;
#10 clk_read = ~clk_read;
end
endtask

endmodule

SIMULATED OUPUT:

7.IMPLEMENTATION OF DIGITAL CIRCUITS USING FPGA

RIPPLE CARRY ADDER

PROGRAM:
module ripple_8adder( a,b,cin,sum,carry );
input [7:0] a;
input [7:0] b;
inputcin;
output [7:0] sum;
output carry;
wire [6:0]c;
fulladder FA1(a[0],b[0],cin,sum[0],c[0]);
fulladder FA2(a[1],b[1],c[0],sum[1],c[1]);
fulladder FA3(a[2],b[2],c[1],sum[2],c[2]);
fulladder FA4(a[3],b[3],c[2],sum[3],c[3]);
fulladder FA5(a[4],b[4],c[3],sum[4],c[4]);
fulladder FA6(a[5],b[5],c[4],sum[5],c[5]);
fulladder FA7(a[6],b[6],c[5],sum[6],c[6]);
fulladder FA8(a[7],b[7],c[6],sum[7],carry);
endmodule

modulefulladder (x, y, z, s, co);

input x, y, z;
output s, co;
wire t1, t2, t3;
xor G1 (t1, x, y), G2 (s, t1, z);
and G3 (t2, x, y), G4 (t3, t1, z);
or G5 (co, t2, t3);
endmodule

USER CONSTRAINT FILE (UCF):

INPUT PORT OUTPUT PORT

NET “a[0]” LOC = G13; NET “sum[0]” LOC = M16 ;
NET “a[1]” LOC = T18; NET “sum[1]” LOC = P18 ;
NET “a[2]” LOC = L16; NET “sum[2]” LOC = N18;
NET “a[3]” LOC = M14; NET “sum[3]” LOC = N17 ;
NET “a[4]” LOC = K16; NET “sum[4]” LOC = L15 ;
NET “a[5]” LOC = K15 ; NET “sum[5]” LOC = U18 ;
NET “a[6]” LOC = K12 ; NET “sum[6]” LOC = M18 ;
NET “a[7]” LOC = T17; NET “sum[7]” LOC = U17 ;
NET “b[0]” LOC = L18; NET “carry” LOC = K19 ;
NET “b[1]” LOC = L17 ;
NET “b[2]” LOC = L13;
NET “b[3]” LOC = N15;
NET “b[4]” LOC = N16 ;
NET “b[5]” LOC = H15 ;
NET “b[6]” LOC = H16;
NET “b[7]” LOC = K13 ;

BOOTHS MULTIPLIER
PROGRAM:
modulebm(xa,ya,za);
input [3:0]xa;
input [3:0]ya;
output [7:0]za;
integeri;
reg[9:0]temp;
reg[1:0]a;
reg[5:0]y;
reg[5:0]x;
reg[9:0]z;
reg[7:0]za;
always@ (xa or ya)
begin
y[5:0]=6’b000000;
y[5:1]=ya[3:0];
x[4:0]=xa[3:0];
z=9’b000000000;
temp=10’b0000000000;
for(i=0;i<=4;i=i+1)
begin
a[0]=y[i];
a[1]=y[i+1];
case(a)
2’b01:temp[4:0]=x[4:0];
2’b10:temp[4:0]=(~x[4:0])+5’b0001;
2’b11:temp[4:0]=5’b00000;
2’b00:temp[4:0]=5’b00000;
endcase
if(temp[4]==0)
begin
temp[9:5]=5’b00000;
end
else
begin
temp[9:5]=5’b11111;
end
temp=temp<<i;
z=z+temp;
end
za=z;
endendmodule

USER CONSTRAINT FILE (UCF):

INPUT PORT OUTPUT PORT

NET “xa[0]” LOC = G13; NET “za[0]” LOC = M16 ;
NET “xa[1]” LOC = T18; NET “za[1]” LOC = P18 ;
NET “xa[2]” LOC = L16; NET “za[2]” LOC = N18;
NET “xa[3]” LOC = M14; NET “za [3]” LOC = N17 ;
NET “ya[0]” LOC = L18; NET “za [4]” LOC = L15 ;
NET “ya[1]” LOC = L17 ; NET “za [5]” LOC = U18 ;
NET “ya[2]” LOC = L13; NET “za [6]” LOC = M18 ;
NET “ya[3]” LOC = N15; NET “za [7]” LOC = U17 ;

4-BIT ALU
PROGRAM:
module imp(a,b,opcode,dataz,compz);
input [3:0]a;
input [3:0]b;
input [1:0]opcode;
output [3:0]dataz;
outputcompz;
parameter ADD=0,NAND=1,GT=2,XOR=3;
assign
dataz=(opcode==ADD)?a+b:(opcode==NAND)?~(a&b):(opcode==XOR)?a^b:'bx;
assign
compz=(opcode==GT)?a>b:'bx;
endmodule

USER CONSTRAINT FILE (UCF):

INPUT PORT OUTPUT PORT
NET “a[0]” LOC = G13; NET “dataz[0]” LOC = M16 ;
NET “a[1]” LOC = T18; NET “dataz [1]” LOC = P18 ;
NET “a[2]” LOC = L16; NET “dataz [2]” LOC = N18;
NET “a[3]” LOC = M14; NET “dataz [3]” LOC = N17 ;
NET “a[4]” LOC = K16; NET “compz[4]” LOC = L15 ;
NET “b[0]” LOC = L18;
NET “b[1]” LOC = L17 ;
NET “b[2]” LOC = L13;
NET “b[3]” LOC = N15;
NET “opcode[0]” LOC = K13 ;
NET “opcode[0]” LOC = H16;

8.DESIGN AND SIMULATION OF 4-BIT SYNCHRONOUS COUNTER

PROGRAM:
modulesyncou(clock, data, q);
input clock;
input data;
output [3:0] q;
tff a(q[0],clock,data);
tff b(q[1],clock,data&q[0]);
tff c(q[2],clock,data&q[1]&q[0]);
tff d(q[3],clock,data&q[2]&q[1]&q[0]);
endmodule
moduletff(q,clock,t);
inputclock,t;
output q;
reg q;
initial q=0;
always@(negedge clock)
begin
q=(q^(t));
end
endmodule
RTL SCHEMATIC:
VERILOG TEST FIXTURE:

modulesyncou_test;
reg clock, data; wire [3:0]q;
syncoumycounter (clock,data,q);
initial
begin
//$dumpfile ("sequence.vcd"); $dumpvars (0, test_sequence);
clock = 1'b0; data = 1'b1;
end
always #5 clock = ~clock;
endmodule

SIMULATED OUTPUT:

9. SCHEMATIC ENTRY AND SPICE SIMULATION OF CMOS INVERTER USING TANNER

EDA TOOL
SCHEMATIC DIAGRAM

SIMULATION STATUS
T-Spice - Tanner SPICE
Version 15.02
Network license from: server.VLSILab.local
Product Release ID: T-Spice Win32 15.02.20100805.03:20:03
Copyright © 1988-2010 Tanner EDA

Parsing "C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\Cell0.sp"
Reading library entry "TT" from "C:/Documents and Settings/Administrator/My
Documents/Tanner EDA/Tanner Tools
v15.0/Process/Generic_250nm/Generic_250nm_Tech/Generic_250nm.lib"
Reading library entry "TT_NMOS_PARAMETERS" from "Generic_250nm.lib"
Reading library entry "TT_PMOS_PARAMETERS" from "Generic_250nm.lib"
Reading library entry "MOS_BIN_MODEL" from "Generic_250nm.lib"
Reading library entry "Typ" from "Generic_250nm.lib"
Reading library entry "RES_CAP" from "Generic_250nm.lib"
Loaded BSIM3v31 model library, Berkeley BSIM3 VERSION 3.1 with extensions
Opening simulation database
"C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\Cell0.tsim"
General options:
threads = 2
Output options:
prtdel = 1e-008
Device and node counts:
MOSFETs - 2 MOSFET geometries - 2
BJTs - 0 JFETs - 0
MESFETs - 0 Diodes - 0
Capacitors - 0 Resistors - 0
Inductors - 0 Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 2 Current sources - 0
VCVS - 0 VCCS - 0
CCVS - 0 CCCS - 0
V-control switch - 0 I-control switch - 0
 Macro devices - 0 Verilog-A devices - 0
Subcircuits - 0 Subcircuit instances - 0
Model Definitions - 2 Computed Models - 2
Independent nodes - 1 Boundary nodes - 3
Total nodes - 4

Parsing 0.01 seconds

Setup 0.01 seconds
DC operating point 0.00 seconds
Transient Analysis 0.14 seconds
Overhead 23.86 seconds
-----------------------------------------
Total 24.03 seconds

Simulation completed

OUTPUT WAVEFORM

10. SCHEMATIC ENTRY AND SPICE SIMULATION OF CMOS DIFFERENTIAL AMPLIFIER

USING TANNER EDA TOOL
SCHEMATIC DIAGRAM
SIMULATION RESULTS
COMMON MODE OUTPUT WAVEFORM

Measurement result summary

AC_Measure_Gain_1 = 1.7296
At = 10.0000k
AC_Measure_GainBandwidthProduct_1 = 3.5176k
DIFFERENTIAL MODE OUTPUT WAVEFORM
Measurement result summary
AC_Measure_Gain_1= 27.3657 At 10.0000
AC_Measure_GainBandwidthProduct_1 = 1.6360X
AC_Measure_Gain_1= 17.5 At 10.0000k

CMRR= Ad / Ac
CMRR in dB = Ad in dB – Ac in dB =17.5-1.7296 = 15.7704

SEQUENCE DETECTOR FOR PATTERN “0110”

moduleseq_detector (x, clk, reset, z);
input x, clk, reset;
outputreg z;
parameter S0=0, S1=1, S2=2, S3=3;
reg [0:1] PS, NS;
always @(posedgeclk or posedge reset)
if (reset) PS <= S0;
else PS <= NS;
always @(PS,x)
case (PS)
S0: begin
z = x ?0 : 0;
NS = x ?S0 : S1;
end
S1: begin
z = x ?0 : 0;
NS = x ?S2 : S1;
end
S2: begin
z = x ?0 : 0;
NS = x ?S3 : S1;
end
S3: begin
z = x ?0 : 1;
NS = x ?S0 : S1;
end
endcase
endmodule
//testbench for sequence detector
moduletest_sequence;
regclk, x, reset; wire z;
seq_detector SEQ (x, clk, reset, z);
initial
begin
$dumpfile ("sequence.vcd"); $dumpvars (0, test_sequence);
clk = 1'b0; reset = 1'b1;
#15 reset = 1'b0;
end
always #5 clk = ~clk;
initial
begin
#12 x = 0; #10 x = 0; #10 x = 1; #10 x = 1;
#10 x = 0; #10 x = 1; #10 x = 1; #10 x = 0;
#10 x = 0; #10 x = 1; #10 x = 1; #10 x = 0;
#10 $finish;
end
endmodule