DI-69 Design Idea

®
DPA-Switch

15 W Multi-Output DC-DC Converter

Application Device Power Output Input Voltage Output Voltage Topology

VoIP Phone DPA424PN 15 W 36 – 75 VDC 5 V, 7.5 V, 20 V Forward

Design Highlights Capacitor C1, C2 and L1 provide line filtering. Resistor R2

• Low component count
• Built-in accurate OV/UV with single resistor programming
• High efficiency (88%) using synchronous rectification
• Multiple outputs with good cross-regulation
• Built-in output overload, open loop and thermal protec-
tion
• 400 kHz switching frequency
• No primary current sense resistor required
Operation
Resistor R1 programs the input under/over voltages to 33 V and
86 V. It also linearly reduces the maximum device duty cycle
(DCMAX) with increasing input voltage, helping to prevent core
saturation during transients.
programs the U1 current limit. The Q22 reflected gate capacitance
provides optimum reset for transformer T1. Zener VR1 clamps the
peak drain voltage to a safe level during transient conditions.
Resistors R21, R22, C21 and MOSFETs Q21 and Q22 form a
capacitively coupled direct driven synchronous rectifier for the
main (5 V) output. Zener diode VR21 acts both as a clamp and as
a diode to quickly recharge the Q21 drive capacitor C21. Resistor
R23 holds Q21 off when no switching signal is present.
The 20 V output is generated from a flyback winding on the L2
inductor, which is rectified and filtered by diode D41 and C41.
Zener VR31 and diode D32 provide a pre-load on the 7.5 V output
to enhance regulation at light load.

D41
BAV19WS 20 V, 10 mA
C41 J2-4
4.7 μF, 35 V
VR31 D32
4 3 6.8 V IN4148
J1-1 L1 D31
36-75 VDC 1 μH 2.5 A 20CJQ060 7.5 V, 0.4 A
1 8
+ 7 6 C31 J2-3
Q22 100 μF
Si4804 10 V
3 7 C25
L2 C22-C24 R4 1 μF
6 C21 16 μH 4 A 100 μF 5 V
R1 2.2 nF 160 Ω 10 V 5 V, 2.4 A
619 kΩ 8 5
DC 1% R21 J2-2
Input 4 10 Ω 7 2
Voltage R22 D6
10 Ω BAV
5 19WS RTN
T1 Q21 VR21 D21 J2-1
Si4804 SL13
R23 15 V
C6 U2
C1 C2 10 kΩ 4.7 μF
1 μF R16
1 μF 20 V 10.0 kΩ
100 V 100 V R11
DPA-Switch U2 1%
10 kΩ
U1 PC357N1T
DPA424PN R12 C12
D L 150 Ω 100 nF

CONTROL
R13
C 11 Ω
D11
BAV19WS

S X F R3 C11 C13 R14

VR1 1.0 Ω 2.2 μF
SMBJ 68 nF 1 kΩ
C4 10 V
150 220 nF C5 U3
R2 47 μF LM431AIM3 R15
13.3 kΩ 10 V 10.0 kΩ
1% 1%
RTN PI-3799-031008
J1-2 Figure 1. 15 W DC-DC Converter Using DPA424PN.

www.powerint.com March 2008

Key Design Points Voltage Load Cross-Regulation (%)
• Zener VR1 safely limits the DRAIN voltage below BVDSS. VOUT Range Range
• At zero load, maximum input voltage, the bias voltage across (VDC) (%) -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8
C6 should be >8 V (12 V to 15 V under normal conditions). 5 36-72 20-100
• The 5 V output is the regulated output. All other outputs are
7.5 36-72 0-100
derived from it. Therefore, tight transformer secondary coupling
and low PC board trace impedance from the 5 V output to the 7 36-72 100
7.5 V output are crucial to achieve good cross-regulation.
Table 1. Worst Case Output Cross-Regulation - All Outputs Taken from Minimum
• The transformer must reset completely under all line and load to Maximum Load.
conditions to prevent core saturation. The gate capacitance of
Q22 (with other parasitic circuit capacitances), determines the
minimum reset period. The transformer core reset voltage also Transformer Parameters
drives the secondary synchronous rectifier Q22. Efficiency is Core Material Ferroxcube P/N: PTS14/8-3F3, ungapped
maximized when Q22 conduction period is maximized. This 8-pin P1408 surface mount B&B B-096 or
Bobbin
Q22 conduction period can be extended by adding more equivalent
capacitance (an R-C snubber across the 5 V winding). The reset Primary: 8T + 7T, 27 AWG
period should be set to give as long a reset as possible when Winding Details 5 V: 4T, 4 × 28 AWG
operating at low-line (maximum duty cycle) while still guarantee- 7.5 V: 2T, 4 × 28 AWG
ing complete reset.
Winding Order Primary-1 (4–3), 7.5 V (7–8), 5 V (5–6),
• Good layout practices should be followed:
(pin numbers) Primary-2 (3–1)
• Locate C4, C5 and R3 close to U1 with grounds returned to
the SOURCE pin. Primary Inductance 434 μH, ±25% at 100 kHz
• Minimize the primary and secondary loop areas to reduce
parasitic leakage inductance. Primary Resonant 3.8 MHz (minimum)
Frequency
• Locate D21 and Q22 return connections very close to each
other to provide best cross-regulation between 5 V and Leakage
Inductance 1 μH (maximum)
7.5 V.
Table 2. Transformer Parameters. (AWG = American Wire Gauge,
NC = No Connection)

Output Inductor Parameters

EPCOS N87, P/N: B65755-J-R87, gap for
Core Material
AL = 160 nH/T2
8-pin P1408 surface mount B&B B-096 or
Bobbin
equivalent
Bias: 26T, 34 AWG
5 V: 6T, 2 × 28 AWG
Winding Details
7.5 V: 12T, 28 AWG
20 V: 40T, 34 AWG
Inductance Pin (5–8): 16 μH, ±10% at 100 kHz
Table 3. Output Inductor Parameters.

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03/08 DI-69