160 MHz Rail-to-Rail

Amplifier with Disable

AD8041
FEATURES CONNECTION DIAGRAM
Fully Specified for +3 V, +5 V, and ⴞ5 V Supplies 8-Lead PDIP, CERDIP and SOIC
Output Swings Rail to Rail
Input Voltage Range Extends 200 mV Below Ground
No Phase Reversal with Inputs 1 V Beyond Supplies NC 1 8 DISABLE
Disable/Power-Down Capability –INPUT 2 7 ⴙVS
Low Power of 5.2 mA (26 mW on 5 V) ⴙINPUT 3 6 OUTPUT
High Speed and Fast Settling on 5 V: –VS 4 AD8041 5 NC
(Top View)
160 MHz –3 dB Bandwidth (G = +1)
NC = NO CONNECT
160 V/␮s Slew Rate
30 ns Settling Time to 0.1% The output voltage swing extends to within 50 mV of each rail,
Good Video Specifications (RL = 150 ⍀, G = +2) providing the maximum output dynamic range. Additionally, it
Gain Flatness of 0.1 dB to 30 MHz features gain flatness of 0.1 dB to 30 MHz while offering differ-
0.03% Differential Gain Error ential gain and phase error of 0.03% and 0.03° on a single 5 V
0.03ⴗ Differential Phase Error supply. This makes the AD8041 ideal for professional video
Low Distortion electronics such as cameras, video switchers, or any high speed
–69 dBc Worst Harmonic @ 10 MHz portable equipment. The AD8041’s low distortion and fast settling
Outstanding Load Drive Capability make it ideal for buffering high speed A-to-D converters.
Drives 50 mA 0.5 V from Supply Rails
The AD8041 has a high speed disable feature useful for mul-
Cap Load Drive of 45 pF
tiplexing or for reducing power consumption (1.5 mA). The
APPLICATIONS disable logic interface is compatible with CMOS or open-
Power Sensitive High Speed Systems collector logic. The AD8041 offers a low power supply current
Video Switchers of 5.8 mA maximum and can run on a single 3 V power supply.
Distribution Amplifiers These features are ideally suited for portable and battery-
A/D Drivers powered applications where size and power are critical.
Professional Cameras The wide bandwidth of 160 MHz along with 160 V/µs of slew
CCD Imaging Systems rate on a single 5 V supply make the AD8041 useful in many
Ultrasound Equipment (Multichannel) general-purpose high speed applications where dual power
Single-Supply Multiplexer supplies of up to ± 6 V and single supplies from 3 V to 12 V are
PRODUCT DESCRIPTION needed. The AD8041 is available in 8-lead PDIP and SOIC
The AD8041 is a low power voltage feedback, high speed ampli- over the industrial temperature range of –40°C to +85°C.
fier designed to operate on +3 V, +5 V, or ± 5 V supplies. It has 2
true single-supply capability with an input voltage range extending 1 VS = 5V
200 mV below the negative rail and within 1 V of the positive rail. G = +2
0 RF = 400⍀
NORMALIZED GAIN (dB)

–1
5V
–2

–3

–4
2.5V
–5

–6

–7
0V
1V 200ns
–8
0 20 40 60 80 100
Figure 1. Output Swing: G = –1, VS = 5 V FREQUENCY (MHz)

Figure 2. Frequency Response: G = +2, VS = 5 V

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com
registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD8041–SPECIFICATIONS (@ T = 25ⴗC, V = 5 V, R = 2 k⍀ to 2.5 V, unless otherwise noted.)
A S L

AD8041A
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p G = +1 130 160 MHz
Bandwidth for 0.1 dB Flatness G = +2, RL = 150 Ω 30 MHz
Slew Rate G = –1, VO = 2 V Step 130 160 V/µs
Full Power Response VO = 2 V p-p 24 MHz
Settling Time to 0.1% G = –1, VO = 2 V Step 35 ns
Settling Time to 0.01% 55 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kΩ –72 dB
Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 10 kHz 600 fA/√Hz
Differential Gain Error (NTSC) G = +2, RL = 150 Ω to 2.5 V 0.03 %
G = +2, RL = 75 Ω to 2.5 V 0.01 %
Differential Phase Error (NTSC) G = +2, RL = 150 Ω to 2.5 V 0.03 Degrees
G = +2, RL = 75 Ω to 2.5 V 0.19 Degrees
DC PERFORMANCE
Input Offset Voltage 2 7 mV
TMIN to TMAX 8 mV
Offset Drift 10 µV/°C
Input Bias Current 1.2 3.2 µA
TMIN to TMAX 3.5 µA
Input Offset Current 0.2 0.5 µA
Open-Loop Gain RL = 1 kΩ 86 95 dB
TMIN to TMAX 90 dB
INPUT CHARACTERISTICS
Input Resistance 160 kΩ
Input Capacitance 1.8 pF
Input Common-Mode Voltage Range –0.2 to +4 V
Common-Mode Rejection Ratio VCM = 0 V to 3.5 V 74 80 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing: RL = 10 kΩ 0.05 to 4.95 V
Output Voltage Swing: RL = 1 kΩ 0.35 to 4.75 0.1 to 4.9 V
Output Voltage Swing: RL = 50 Ω 0.4 to 4.4 0.3 to 4.5 V
Output Current VOUT = 0.5 V to 4.5 V 50 mA
Short-Circuit Current Sourcing 90 mA
Sinking 150 mA
Capacitive Load Drive G = +1 45 pF

POWER SUPPLY
Operating Range 3 12 V
Quiescent Current 5.2 5.8 mA
Quiescent Current (Disabled) 1.4 1.7 mA
Power Supply Rejection Ratio VS = 0, +5 V, ± 1 V 72 80 dB
DISABLE CHARACTERISTICS VO = 2 V p-p @ 10 MHz, G = +2
Turn-Off Time RF = RL = 2 kΩ 120 ns
Turn-On Time RF = RL = 2 kΩ 230 ns
Off Isolation (Pin 8 Tied to –VS) RL = 100 Ω, f = 5 MHz, G = +2, RF = 1 kΩ 70 dB
Off Voltage (Device Disabled) <VS – 2.5 V
On Voltage (Device Enabled) Open or +VS V
Specifications subject to change without notice.

–2– REV. B
 AD8041
SPECIFICATIONS (@ T = 25ⴗC, V = 3 V, R = 2 k⍀ to 1.5 V, unless otherwise noted.)
A S L

AD8041A
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p G = +1 120 150 MHz
Bandwidth for 0.1 dB Flatness G = +2, RL = 150 Ω 25 MHz
Slew Rate G = –1, VO = 2 V Step 120 150 V/µs
Full Power Response VO = 2 V p-p 20 MHz
Settling Time to 0.1% G = –1, VO = 2 V Step 40 ns
Settling Time to 0.01% 55 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, G = –1, RL = 100 Ω –55 dB
Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 10 kHz 600 fA/√Hz
Differential Gain Error (NTSC) G = +2, RL = 150 Ω to 1.5 V, Input VCM = 1 V 0.07 %
Differential Phase Error (NTSC) G = +2, RL = 150 Ω to 1.5 V, Input VCM = 1 V 0.05 Degrees
DC PERFORMANCE
Input Offset Voltage 2 7 mV
TMIN to TMAX 8 mV
Offset Drift 10 µV/°C
Input Bias Current 1.2 3.2 µA
TMIN to TMAX 3.5 µA
Input Offset Current 0.2 0.6 µA
Open-Loop Gain RL = 1 kΩ 85 94 dB
TMIN to TMAX 89 dB
INPUT CHARACTERISTICS
Input Resistance 160 kΩ
Input Capacitance 1.8 pF
Input Common-Mode Voltage Range –0.2 to +2 V
Common-Mode Rejection Ratio VCM = 0 V to 1.5 V 72 80 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing: RL = 10 kΩ 0.05 to 2.95 V
Output Voltage Swing: RL = 1 kΩ 0.45 to 2.7 0.1 to 2.9 V
Output Voltage Swing: RL = 50 Ω 0.5 to 2.6 0.25 to 2.75 V
Output Current VOUT = 0.5 V to 2.5 V 50 mA
Short-Circuit Current Sourcing 70 mA
Sinking 120 mA
Capacitive Load Drive G = +1 40 pF
POWER SUPPLY
Operating Range 3 12 V
Quiescent Current 5.0 5.6 mA
Quiescent Current (Disabled) 1.3 1.5 mA
Power Supply Rejection Ratio VS = 0, +3 V, ± 0.5 V 68 80 dB
DISABLE CHARACTERISTICS VO = 2 V p-p @ 10 MHz, G = +2
Turn-Off Time RF = RL = 2 kΩ 90 ns
Turn-On Time RF = RL = 2 kΩ 170 ns
Off Isolation (Pin 8 Tied to –VS) RL = 100 Ω, f = 5 MHz, G = +2, RF = 1 kΩ 70 dB
Off Voltage (Device Disabled) <VS – 2.5 V
On Voltage (Device Enabled) Open or +VS V
Specifications subject to change without notice.

REV. B –3–
AD8041
SPECIFICATIONS (@ TA = 25ⴗC, VS = ⴞ5 V, RL = 2 k⍀ to 0 V, unless otherwise noted.)

AD8041A
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth, VO < 0.5 V p-p G = +1 140 170 MHz
Bandwidth for 0.1 dB Flatness G = +2, RL = 150 Ω 32 MHz
Slew Rate G = –1, VO = 2 V Step 140 170 V/µs
Full Power Response VO = 2 V p-p 26 MHz
Settling Time to 0.1% G = –1, VO = 2 V Step 30 ns
Settling Time to 0.01% 50 ns
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion fC = 5 MHz, VO = 2 V p-p, G = +2, RL = 1 kΩ –77 dB
Input Voltage Noise f = 10 kHz 16 nV/√Hz
Input Current Noise f = 10 kHz 600 fA/√Hz
Differential Gain Error (NTSC) G = +2, RL = 150 Ω 0.02 %
G = +2, RL = 75 Ω 0.02 %
Differential Phase Error (NTSC) G = +2, RL = 150 Ω 0.03 Degrees
G = +2, RL = 75 Ω 0.10 Degrees
DC PERFORMANCE
Input Offset Voltage 2 7 mV
TMIN to TMAX 8 mV
Offset Drift 10 µV/°C
Input Bias Current 1.2 3.2 µA
TMIN to TMAX 3.5 µA
Input Offset Current 0.2 0.6 µA
Open-Loop Gain RL = 1 kΩ 90 99 dB
TMIN to TMAX 95 dB
INPUT CHARACTERISTICS
Input Resistance 160 kΩ
Input Capacitance 1.8 pF
Input Common-Mode Voltage Range –5.2 to +4 V
Common-Mode Rejection Ratio VCM = –5 V to +3.5 V 72 80 dB
OUTPUT CHARACTERISTICS
Output Voltage Swing: RL = 10 kΩ –4.95 to +4.95 V
Output Voltage Swing: RL = 1 kΩ –4.45 to +4.6 –4.8 to +4.8 V
Output Voltage Swing: RL = 50 Ω –4.3 to +3.2 –4.5 to +3.8 V
Output Current VOUT = –4.5 V to +4.5 V 50 mA
Short-Circuit Current Sourcing 100 mA
Sinking 160 mA
Capacitive Load Drive G = +1 50 pF
POWER SUPPLY
Operating Range 3 12 V
Quiescent Current 5.8 6.5 mA
Quiescent Current (Disabled) 1.6 2.2 mA
Power Supply Rejection Ratio VS = –5 V, +5 V, ± 1 V 68 80 dB
DISABLE CHARACTERISTICS VO = 2 V p-p @ 10 MHz, G = +2
Turn-Off Time RF = 2 kΩ 120 ns
Turn-On Time RF = 2 kΩ 320 ns
Off Isolation (Pin 8 Tied to –VS) RL = 100 Ω, f = 5 MHz, G = +2, RF = 1 kΩ 70 dB
Off Voltage (Device Disabled) <VS – 2.5 V
On Voltage (Device Enabled) Open or +VS V
Specifications subject to change without notice.

–4– REV. B

ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage ............................................................ 12.6 V
Internal Power Dissipation2
PDIP Package (N) .................................................... 1.3 W
SOIC Package (R) .................................................... 0.9 W
Input Voltage (Common Mode) ...................................... ± VS
Differential Input Voltage ........................................... ± 3.4 V
Output Short-Circuit Duration
.......................................... Observe Power Derating Curves
Storage Temperature Range N, R .............. –65°C to +125°C
Operating Temperature Range (A Grade) ... –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) ............... 300°C
AD8041
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can result
in device failure.
While the AD8041 is internally short-circuit protected, this may
not be sufficient to guarantee that the maximum junction tem-
perature (150°C) is not exceeded under all conditions. To
ensure proper operation, it is necessary to observe the maximum
power derating curves.
2.0
8-LEAD PDIP PACKAGE

MAXIMUM POWER DISSIPATION (W)

TJ = 150 ⴗC
NOTES 1.5
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating 1.0
conditions for extended periods may affect device reliability.
2
Specification is for the device in free air:
8-Lead PDIP Package: θJA = 90°C/W. 8-LEAD SOIC PACKAGE
8-Lead SOIC Package: θJA = 155°C/W. 0.5

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the 0
–50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
AD8041 is limited by the associated rise in junction temperature. AMBIENT TEMPERATURE (ⴗC)
The maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the Figure 3. Maximum Power Dissipation vs. Temperature
plastic, approximately 150°C. Exceeding this limit temporarily
may cause a shift in parametric performance due to a change in

ORDERING GUIDE

Temperature Package Package

Model Range Description Options
AD8041AN –40°C to +85°C 8-Lead PDIP N-8
AD8041AR –40°C to +85°C 8-Lead Plastic SOIC R-8
AD8041AR-REEL –40°C to +85°C 13" Tape and Reel R-8
AD8041AR-REEL7 –40°C to +85°C 7" Tape and Reel R-8
AD8041ARZ-REEL1 –40°C to +85°C 13" Tape and Reel R-8
5962-9683901MPA2 –55°C to +125°C 8-Lead CERDIP Q-8
NOTES
1
The Z indicates a lead-free product.
2
Refer to official DSCC drawing for tested specifications.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD8041 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. B –5–
AD8041–Typical Performance Characteristics
30 100

VS = ⴞ2.5V
TA = 25ⴗC 95
25
91 PARTS
MEAN = +0.21
NUMBER OF PARTS IN BIN

STD DEVIATION = 1.47

OPEN-LOOP GAIN (dB)

20 90

15 85
VS = 5V
TA = 25ⴗC
10 80

5 75

0 70
–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 0 250 500 750 1000 1250 1500 1750 2000
VOS (mV) LOAD RESISTANCE (⍀)

TPC 1. Typical Distribution of VOS TPC 4. Open-Loop Gain vs. RL to 25°C

0.20 100
MEAN = 0.02␮V/ⴗC
STD DEV = 2.87␮V/ⴗC
SAMPLE SIZE = 45 97
0.15
PROBABILITY DENSITY

OPEN-LOOP GAIN (dB)

94

0.10 VS = 5V
RL = 1k⍀ TO 2.5V
91

0.05
88

0 85
–10 –7.5 –5 –2.5 0 2.5 5 7.5 10 –60 –40 –20 0 20 40 60 80 100 120
VOS DRIFT (␮V/ⴗ C) TEMPERATURE (ⴗC)

TPC 2. VOS Drift Over –40°C to +85°C TPC 5. Open-Loop Gain vs. Temperature

2 100
RL = 500⍀ TO 2.5V VS = 5V
VS = 5V
VCM = 0V 90
1.5
INPUT BIAS CURRENT (␮A)

OPEN-LOOP GAIN (dB)

80
RL = 50⍀ TO 2.5V

1 70

60
0.5

50

0 40
–45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
TEMPERATURE (ⴗC) OUTPUT VOLTAGE (V)

TPC 3. IB vs. Temperature TPC 6. Open-Loop Gain vs. Output Voltage

–6– REV. B
 AD8041
200 0.035
0.030 VS = 5V

DIFF GAIN (%)

0.025 G = +2
0.020 RL = 150⍀ TO 2.5V VS = 5V
INPUT VOLTAAGE NOISE (nV/ Hz)

0.015 G = +2
150 0.010 RL = 150⍀
0.005
0.000
–0.005
–0.010
1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
100
0.035

DIFF PHASE (Degrees)

0.030 VS = 5V
0.025 G = +2
0.020 RL = 150⍀ TO 2.5V
0.015
50 0.010 VS = 5V
0.005
G = +2
0.000
RL = 150⍀
–0.005
–0.010
0 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th
10 100 1k 10k 100k
DC OUTPUT LEVEL (100 IRE MAX)
FREQUENCY (Hz)

TPC 7. Input Voltage Noise vs. Frequency TPC 10. Differential Gain and Phase Errors

–30 6.5
VS = 3V, AV = –1,
RL = 100⍀ TO 1.5V 6.4
TOTAL HARMONIC DISTORTION (dBc)

–40 VS = 5V
6.3 G = +2
VS = 5V, AV = 2, RL = 150⍀ TO 2.5V

CLOSED-LOOP GAIN (dB)

–50 RL = 100⍀ TO 2.5V 6.2 RF = 402⍀

6.1
–60 VS = 5V, AV = 1,
RL = 100⍀ TO 2.5V 6.0
32.4MHz
–70 5.9

–80 5.8
VS = 5V, AV = 2,
5.7
RL = 1k⍀ TO 2.5V
–90
VS = 5V, AV = 1, 5.6
RL = 1k⍀ TO 2.5V
–100 5.5
1 2 3 4 5 6 7 8 9 10 1 10 100 500
FUNDAMENTAL FREQUENCY (MHz) FREQUENCY (MHz)

TPC 8. Total Harmonic Distortion TPC 11. 0.1 dB Gain Flatness

90 450
–30
10MHz
–40 80 VS = 5V 360
RL = 2k⍀ TO 2.5V
–50 70 270
CL = 5pF TO 2.5V
5MHz GAIN
OPEN-LOOP GAIN (dB)
WORST HARMONIC (dBc)

–60 60 180

–70 90

PHASE (ⴗC)
50
–80
1MHz 40 0
–90 PHASE
30 –90
–100
VS = 5V 20 –180
–110
RL = 2k⍀ TO 2.5V 10 –270
–120 G = +2
0 –360
–130
–10 –450
–140
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.01 0.1 10 100 500
OUTPUT VOLTAGE (VP-P) FREQUENCY (MHz)

TPC 12. Open-Loop Gain and Phase vs. Frequency

TPC 9. Worst Harmonic vs. Output Voltage

REV. B –7–
AD8041
5 50
VS = 5V
4 G = –1
RL = 2k⍀ TO 2.5V T = +125ⴗC
3 CL = 5pF VS = 3V, 0.1%
G = +1 40
CLOSED-LOOP GAIN (dB)

2 T = +25ⴗC

VS = ⴞ5V, 0.1%
1

TIME (ns)
0 30
T = –55ⴗC
–1
VS = 3V, 1%
–2
20
–3
VS = ⴞ5V, 1%
–4
10
–5
1 10 100 500 0.5 1 1.5 2
FREQUENCY (MHz) INPUT STEP (V p-p)

TPC 13. Closed-Loop Frequency Response TPC 16. Settling Time vs. Input Step
vs. Temperature

5 –10

4 G = +1 –20
VS = 3V
RL = 2k⍀ VS = +3V AND ⴞ5V
RL AND CL TO 1.5V
3 CL = 5pF –30
CLOSED-LOOP GAIN (dB)

2 VS = 5V –40
RL AND CL TO 2.5V
1 –50
CMRR (dB)

0 –60
VS = ⴞ5V
–1 –70

–2 –80

–3 –90

–4 –100

–5 –110
1 10 100 500 0.01 0.1 1 10 100 500
FREQUENCY (MHz) FREQUENCY (MHz)

TPC 14. Closed-Loop Frequency Response vs. Supply TPC 17. CMRR vs. Frequency

1000
100
OUTPUT SATURATION VOLTAGE (mV)

G = +1 VS = 5V
VS = 5V
5ⴗ
C
OUTPUT RESISTANCE (⍀)

10 12
,+
100 H
VO
– 5ⴗC
V , –5
+5 V OH
1 – ⴗC
+5V +125
V L,
O

55ⴗC
0.1 10 V OL, –

0.01

0
0.01 0.1 1 10 100 500 0.001 0.01 0.1 1 10 10
FREQUENCY (MHz) 0
LOAD CURRENT (mA)

TPC 15. Output Resistance vs. Frequency TPC 18. Output Saturation Voltage vs. Load Current

–8– REV. B
 AD8041
8 90
100k⍀ VS = 5V
80 1k⍀
RSERIES
7
70 CLOAD
SUPPLY CURRENT (mA)

CAPACITIVE LOAD (pF)

VIN
6 VS = ⴞ5V 60

VS = 5V 50
5
20ⴗ PHASE
40
VS = 3V MARGIN
45ⴗ PHASE
4 30 MARGIN

20
3
10

2 0
–60 –40 –20 0 20 40 60 80 100 120 0 10 20 30 40 50 60
TEMPERATURE (ⴗC) SERIES RESISTANCE (⍀)

TPC 19. Supply Current vs. Temperature TPC 22. Capacitive Load vs. Series Resistance

40 5

20 4
VS = 5V VS = 5V
0 3 RL = 5k⍀ TO 2.5V

NORMALIZED OUTPUT (dB)

G = +2 RF = 2k⍀
–20 –PSRR 2

–40
PSRR (dB)

–60 0
+PSRR
–80 –1
G = +5
–100 –2
G = +10 G = +2,
–120 –3
RF = 402⍀
–140 –4
–160 –5
0.01 0.1 1 10 100 500 1 10 100 500
FREQUENCY (MHz) FREQUENCY (MHz)

TPC 20. PSRR vs. Frequency TPC 23. Frequency Response vs. Closed-Loop Gain

10 1.600V
9 VIN = 0.1V p-p
1.575V RL = 2k⍀
8 VS = 3V
VS = ⴞ5V 1.550V
7 G = +1
RL = 2k⍀
1.525V
6
VOUT p-p (V)

5 1.500V

4 1.475V

3 1.450V
2
1.425V
1 50mV 10ns
1.400V
0
0.1 1 10 100 1000
FREQUENCY (MHz)

TPC 21. Output Voltage Swing vs. Frequency TPC 24. Pulse Response, VS = 3 V

REV. B –9–
AD8041
5V
4.840V MAX
2.60V VS = 5V
G = +1
4V RL = 2k⍀
RL = 150⍀ TO 2.5V
2.55V VL = 5pF

3V
2.50V

2V
2.45V

1V

0.111V MIN 2.40V

1V 200␮s 50mV 40ns
0V

a. TPC 27. 100 mV Step Response, VS = 5 V, G = +1

5V 3.0V
4.741V MAX VIN = 3V p-p
2.5V f = 0.1MHz
4V RL = 2k⍀
RL = 150⍀ TO GND
VS = 3V
2.0V
G = –1
3V
1.5V

2V
1.0V

1V
0.5V
0.043V MIN
1V 200␮s 500mV 2␮s
0V 0V

b.
TPC 25. Output Swing vs. Load Reference Voltage, TPC 28. Output Swing, VS = 3 V, VIN = 3 V p-p
VS = 5 V, G = –1

4.5V 3.0V

VS = 5V VIN = 2.8V p-p

G = +2 2.5V f = 0.8MHz
RL = 2k⍀ RL = 2k⍀
3.5V
VIN = 1V p-p VS = 3V
2.0V
G = –1

2.5V 1.5V

1.0V

1.5V
0.5V

1V 40ns 500mV 2␮s

0.5V 0V

TPC 26. One Volt Step Response, VS = 5 V, G = +2 TPC 29. Output Swing, VS = 3 V, VIN = 2.8 V p-p

–10– REV. B
 AD8041
Overdrive Recovery Capacitor C9. R1 is the output resistance of the input stage; gm
Overdrive of an amplifier occurs when the output and/or input is the input transconductance. C7 and C9 provide Miller com-
range are exceeded. The amplifier must recover from this over- pensation for the overall op amp. The unity gain frequency will
drive condition. As shown in Figure 4, the AD8041 recovers occur at gm/C9. Solving the node equations for this circuit yields:
within 50 ns from negative overdrive and within 25 ns from
positive overdrive. VOUT A0
=
Vi  g  
( sR1 [C 9 ( A2 + 1)] + 1) ×  s  m2  + 1
5.0V   C3  

OUTPUT where A0 = gmgm2 R2 R1 (Open-Loop Gain of Op Amp)

INPUT
2.5V
G = +2
VS = 5V
0V
50mV 40ns
Figure 4. Overdrive Recovery
Circuit Description
The AD8041 is fabricated on Analog Devices’ proprietary
eXtra-Fast Complementary Bipolar (XFCB) process, which
enables the construction of PNP and NPN transistors with similar
fT in the 2 GHz to 4 GHz region. The process is dielectrically
isolated to eliminate the parasitic and latch-up problems caused
by junction isolation. These features allow the construction of
high frequency, low distortion amplifiers with low supply currents.
This design uses a differential output input stage to maximize
bandwidth and headroom (see Figure 5). The smaller signal
swings required on the first stage outputs (nodes S1P, S1N) reduce
the effect of nonlinear currents due to junction capacitances and
improve the distortion performance. With this design harmonic
distortion of better than –85 dB @ 1 MHz into 100 Ω with VOUT =
2 V p-p (Gain = +2) on a single 5 V supply is achieved.
The complementary common-emitter design of the output stage
provides excellent load drive without the need for emitter follow-
ers, thereby improving the output range of the device consider-
ably with respect to conventional op amps. High output drive
capability is provided by injecting all output stage predriver
currents directly into the bases of the output devices Q8 and
Q36. Biasing of Q8 and Q36 is accomplished by I8 and I5,
along with a common-mode feedback loop (not shown). This
A2 = gm2 R2 (Open-Loop Gain of Output Stage)
The first pole in the denominator is the dominant pole of the
amplifier and occurs at about 180 Hz. This equals the input
stage output impedance R1 multiplied by the Miller-multiplied
value of C9. The second pole occurs at the unity-gain bandwidth
of the output stage, which is 250 MHz. This type of architecture
allows more open-loop gain and output drive to be obtained
than a standard two-stage architecture would allow.
Output Impedance
The low frequency open-loop output impedance of the common
emitter output stage used in this design is approximately 6.5 kΩ.
While this is significantly higher than a typical emitter follower
output stage, when connected with feedback, the output imped-
ance is reduced by the open-loop gain of the op amp. With
110 dB of open-loop gain, the output impedance is reduced
to less than 0.1 Ω. At higher frequencies, the output impedance
will rise as the open-loop gain of the op amp drops; however, the
output also becomes capacitive due to the integrator capacitors
C9 and C3. This prevents the output impedance from ever becom-
ing excessively high (see TPC 15), which can cause stability
problems when driving capacitive loads. In fact, the AD8041
has excellent cap-load drive capability for a high frequency op
amp. TPC 22 demonstrates that the AD8041exhibits a 45°
margin while driving a 20 pF direct capacitive load. In addition,
running the part at higher gains will also improve the capacitive
load drive capability of the op amp.
VCC
I1 I10 I2 I3 Q25 Q50 I9
R26 R39
Q36
Q4 Q5 Q39 I5
Q51
Q23 VEE
R15 R2
Q40

circuit topology allows the AD8041 to drive 50 mA of output VEE Q22 R23 R27
Q7 Q31 C3
current with the outputs within 0.5 V of the supply rails. VINP Q13 Q17 VOUT
Q21 Q27
VINN
On the input side, the device can handle voltages from –0.2 V C9
S1P S1N
below the negative rail to within 1.2 V of the positive rail. Exceed-
ing these values will not cause phase reversal; however, the Q2 Q11 Q8
input ESD devices will begin to conduct if the input voltages Q3 Q24 Q47 I8
exceed the rails by greater than 0.5 V. C7 R5 R21 R3 I7 VCC

A “Nested Integrator” topology is used in the AD8041 (see VEE

the small-signal schematic in Figure 6). The output stage can Figure 5. AD8041 Simplified Schematic
be modeled as an ideal op amp with a single-pole response and
a unity-gain frequency set by transconductance gm2 and

REV. B –11–
AD8041
C9
VS = 5V

S1N 100
90
C3
gmVi R1
R2
VOUT
gm2

S1P
10
0%
gmVi R1 C7
1V 200ns

Figure 6. Small Signal Schematic Figure 8. 2:1 Multiplexer Performance

Disable Operation Single-Supply A/D Conversion
The AD8041 has an active-low disable pin, which can be used Figure 9 shows the AD8041 driving the analog inputs of the
to three-state the output of the part and also lower its supply AD9050 in a dc-coupled system with single-ended signals. All
current. If the disable pin is left floating, the part is enabled and components are powered from a single 5 V supply. The AD820
will perform normally. If the disable pin is pulled to 2.5 V (min) is used to offset the ground referenced input signal to the level
below the positive supply, output of the AD8041 will be disabled required by the AD9050. The AD8041 is used to add in the offset
and the nominal supply current will drop to less than 1.6 mA. with the ground referenced input signal and buffer the input to
For best isolation, the disable pin should be pulled to as low a AD9050. The nominal input range of the AD9050 is 2.8 V
voltage as possible; ideally, the negative supply rail. and 3.8 V (1 V p-p centered at 3.3 V). This circuit provides
The disable pin on the AD8041 allows it to be configured as a 2:1 40 MSPS analog-to-digital conversion on just 330 mW of power
mux as shown in Figure 7 and can be used to switch many types of while delivering 10-bit performance.
high speed signals. Higher order multiplexers can also be built.
1k⍀
The break-before-make switching time is approximately 50 ns to
disable the output and 300 ns to enable the output. 5V 5V
1k⍀
VIN
5V –0.5V TO +0.5V 10
10␮F AD8041
2.8V – 3.8V
AD9050
9
CH0 3 7 0.1␮F 5V 3.3V
5MHz
50⍀ AD8041 6
4 G = +2 1k⍀ 1k⍀
2 0.1␮F
8 AD820
330⍀ 330⍀

50⍀
5V Figure 9. 10-Bit, 40 MSPS A/D Conversion
10␮F

CH1 3 7 0
10MHz F1 = 4.9MHz
50⍀ AD8041 6 –10
4 G = +2 FUNDAMENTAL = 0.6dB
2 –20 SECOND HARMONIC = 66.9dB
8
THIRD HARMONIC = 74.7dB
330⍀ 330⍀
–30 SNR = 55.2dB
NOISE FLOOR = – 86.1dB
–40 ENCODE FREQUENCY = 40MHz

13 12 11 10 –50

74HC04 –60

Figure 7. 2:1 Multiplexer –70

–80

–90

–100

Figure 10. FFT Output of Circuit in Figure 9

–12– REV. B
 AD8041
APPLICATIONS Single-Supply Composite Video Line Driver
RGB Buffer Figure 13 shows a schematic of a single-supply gain-of-two
The AD8041 can provide buffering of RGB signals that include composite video line driver. Since the sync tips of a composite
ground while operating from a single 3 V or 5 V supply. video signal extend below ground, the input must be ac-coupled
The signals that drive an RGB monitor are usually supplied by and shifted positively to provide signal swing during these nega-
current output DACs that operate from a 5 V only supply. These tive excursions in a single-supply configuration.
can triple DACs like the ADV7120 and ADV7122 from Analog The input is terminated in 75 Ω and ac-coupled via CIN to a
Devices or integrate into the graphics controller IC as in most voltage divider that provides the dc bias point to the input.
PCs these days. Setting the optimal bias point requires some understanding of
During the horizontal blanking interval, the currents output the nature of composite video signals and the video performance
from the DACs go to zero and the RGB signals are pulled to of the AD8041.
ground via the termination resistors. If more than one RGB Signals of bounded peak-to-peak amplitude that vary in duty
monitor is desired, it cannot simply be connected in parallel cycle require larger dynamic swing capability than their peak-to-
because it will provide an additional termination. Therefore, peak amplitude after ac coupling. As a worst case, the dynamic
buffering must be provided before connecting a second monitor. signal swing required will approach twice the peak-to-peak value.
Since the RGB signals include ground as part of their dynamic The two bounding cases are for a duty cycle that is mostly low,
output range, it has previously been required to use a dual- but occasionally goes high at a fraction of a percent duty cycle
supply op amp to provide this buffering. In some systems, this is and vice versa.
the only component that requires a negative supply, so it can be Composite video is not quite this demanding. One bounding
quite inconvenient to incorporate this multiple monitor feature. extreme is for a signal that is mostly black for an entire frame
Figure 11 shows a schematic of one channel of a single-supply, but has a white (full intensity), minimum width spike at least
gain-of-two buffer for driving a second RGB monitor. No cur- once per frame.
rent is required when the amplifier output is at ground. The The other extreme is for a video signal that is full white every-
termination resistor at the monitor helps pull the output down where. The blanking intervals and sync tips of such a signal will
at low voltage levels. have negative going excursions in compliance with composite
3V OR 5V video specifications. The combination of horizontal and vertical
blanking intervals limit such a signal to being at its highest level
0.1␮F 10␮F
(white) for only about 75% of the time.
NC As a result of the duty cycle variations between the two extremes
R, G OR B 7
3 presented above, a 1 V p-p composite video signal that is multi-
8 75⍀
AD8041 6 plied by a gain of two requires about 3.2 V p-p of dynamic voltage
2
4 75⍀ swing at the output for an op amp to pass a composite video
signal of arbitrary duty cycle without distortion.
1k⍀
75⍀
SECOND RGB Some circuits use a sync tip clamp along with ac coupling to
1k⍀ MONITOR hold the sync tips at a relatively constant level in order to lower
PRIMARY RGB the amount of dynamic signal swing required. However, these
MONITOR
circuits can have artifacts like sync tip compression unless they
Figure 11. Single-Supply RGB Buffer are driven by sources with very low output impedance.
Figure 12 is an oscilloscope photo of the circuit in Figure 11 5V
operating from a 3 V supply and driven by the blue signal of a 4.99k⍀
color bar pattern. Note that the input and output are at ground
4.99k⍀ 10␮F 0.1␮F
during the horizontal blanking interval. The RGB signals are 10␮F
47␮F
specified to output a maximum of 700 mV peak. The output of COMPOSITE 7 75⍀
3 1000␮F COAX
the AD8041 is 1.4 V with the termination resistors providing a VIDEO IN VOUT
75⍀ 10k⍀ AD8041 6
divide-by-two. The red and green signals can be buffered in the RT
8 RL
same manner with duplication of this circuit. 2
4 75⍀ 75⍀
0.1␮F
NC
500mV 5␮s
RG RF
100 1k⍀ 1k⍀
VIN 90
220␮F
GND

Figure 13. Single-Supply Composite Video Line Driver

VOUT
10 GND
The AD8041 not only has ample signal swing capability to
0% handle the dynamic range required without using a sync tip
500mV clamp but also has good video specifications like differential
gain and differential phase when buffering these signals in an ac-
Figure 12. 3 V, RGB Buffer coupled configuration.

REV. B –13–
AD8041
To test this, the differential gain and differential phase were
measured for the AD8041 while the supplies were varied. As the
lower supply is raised to approach the video signal, the first effect
to be observed is that the sync tips become compressed before
the differential gain and differential phase are adversely affected.
Thus, there must be adequate swing in the negative direction to
pass the sync tips without compression.
As the upper supply is lowered to approach the video, the differ-
ential gain and differential phase were not significantly adversely
Referring to Figure 15, the green plus sync signal is output
from an ADV7120, a single-supply triple video DAC. Because
the DAC is single supply, the lowest level of the sync tip is at
ground or slightly above. The AD8041 is set for a gain of two to
compensate for the divide by two of the output terminations.
500mV 10␮s
100
90

affected until the difference between the peak video output and
the supply reached 0.6 V. Thus, the highest video level should
be kept at least 0.6 V below the positive supply rail.
Taking the above into account, it was found that the optimal 10

point to bias the noninverting input is at 2.2 V dc. Operating at 0%

this point, the worst-case differential gain is measured at 0.06% 500mV

and the worst-case differential phase is 0.06°.
The ac coupling capacitors used in the circuit at first glance Figure 15. Single-Supply Sync Stripper
appear quite large. A composite video signal has a lower fre- The reference voltage for R1 should be twice the dc blanking
quency band edge of 30 Hz. The resistances at the various ac level of the G signal. If the blanking level is at ground and the
coupling points—especially at the output—are quite small. In sync tip is negative as in some dual-supply systems, then R1 can
order to minimize phase shifts and baseline tilt, the large value be tied to ground. In either case, the output will have the sync
capacitors are required. For video system performance that is removed and have the blanking level at ground.
not to be of the highest quality, the value of these capacitors can
Layout Considerations
be reduced by a factor of up to five with only a slightly observ-
The specified high speed performance of the AD8041 requires
able change in the picture quality.
careful attention to board layout and component selection.
Sync Stripper Proper RF design techniques and low-pass parasitic component
Some RGB monitor systems use only three cables total and selection are necessary.
carry the synchronizing signals along with the green (G) signal
The PCB should have a ground plane covering all unused portions
on the same cable. The sync signals are pulses that go in the
of the component side of the board to provide a low impedance
negative direction from the blanking level of the G signal.
path. The ground plane should be removed from the area near
In some applications like prior to digitizing component video the input pins to reduce the stray capacitance.
signals with A/D converters, it is desirable to remove or strip the
Chip capacitors should be used for the supply bypassing.
sync portion from the G signal. Figure 14 is a schematic of a
One end should be connected to the ground plane and the other
circuit using the AD8041 running on a single 5 V supply that
within 1/8 inch of each power pin. An additional large (0.47 µF
performs this function.
to 10 µF) tantalum electrolytic capacitor should be connected in
GREEN W/SYNC GREEN W/OUT SYNC
parallel, but not necessarily so close, to supply current for fast,
large signal changes at the output.
5V
The feedback resistor should be located close to the inverting
VBLANK +0.4 GROUND
input pin in order to keep the stray capacitance at this node to a
GROUND 0.1␮F 10␮F minimum. Capacitance variations of less than 1 pF at the inverting
input will significantly affect high speed performance.
7
VIN 3
75⍀
Stripline design techniques should be used for long signal traces
75⍀ AD8041 6 (greater than about 1 inch). These should be designed with a
2
4
characteristic impedance of 50 Ω or 75 Ω and be properly termi-
75⍀ nated at each end.
(MONITOR)

R1 R2
1k⍀ 1k⍀

0.8V
(2X VBLANK)

Figure 14. Single-Supply Sync Stripper

–14– REV. B
 AD8041
OUTLINE DIMENSIONS

8-Lead Plastic Dual In-Line Package [PDIP] 8-Lead Standard Small Outline Package [SOIC]
(N-8) (R-8)
Dimensions shown in inches and (millimeters) Dimensions shown in millimeters and (inches)

0.375 (9.53) 5.00 (0.1968)

0.365 (9.27) 4.80 (0.1890)
0.355 (9.02)
8 5
8 5 0.295 (7.49) 4.00 (0.1574) 6.20 (0.2440)
0.285 (7.24) 3.80 (0.1497) 1 4 5.80 (0.2284)
1 4 0.275 (6.98)
0.325 (8.26)
0.310 (7.87) 1.27 (0.0500) 0.50 (0.0196)
0.100 (2.54)
0.300 (7.62) 0.150 (3.81) 1.75 (0.0688) ⴛ 45ⴗ
BSC BSC 0.25 (0.0099)
0.135 (3.43) 0.25 (0.0098) 1.35 (0.0532)
0.015 0.120 (3.05)
0.180 0.10 (0.0040)
(4.57) (0.38)
MIN 0.51 (0.0201) 8ⴗ
MAX
0.015 (0.38)
COPLANARITY 0.31 (0.0122) 0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.10 SEATING 0.40 (0.0157)
0.150 (3.81) 0.010 (0.25) PLANE 0.17 (0.0067)
SEATING
0.130 (3.30) PLANE 0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MS-012AA
0.110 (2.79) 0.060 (1.52)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
0.022 (0.56) 0.050 (1.27) (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
0.018 (0.46) 0.045 (1.14) REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.014 (0.36)

COMPLIANT TO JEDEC STANDARDS MO-095AA

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

8-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-8)
Dimensions shown in inches and (millimeters)

0.005 (0.13) 0.055 (1.40)

MIN MAX

8 5

0.310 (7.87)
PIN 1 0.220 (5.59)
1 4

0.100 (2.54) BSC

0.405 (10.29) MAX 0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.200 (5.08) 0.015 (0.38)
MAX

0.200 (5.08) 0.150 (3.81)

0.125 (3.18) MIN

0.023 (0.58) SEATING 0.015 (0.38)

0.070 (1.78) PLANE 15
0.014 (0.36) 0 0.008 (0.20)
0.030 (0.76)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

REV. B –15–
AD8041
Revision History
Location Page
5/03—Data Sheet changed from REV. A to REV. B.
Deleted all references to evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Updated OUTLINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

C01058–0–6/03(B)
4/01—Data Sheet changed from REV. 0 to REV. A.
Specifications changed DISABLE CHARACTERISTICS, Off Voltage (Device Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

–16– REV. B