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Semiconductor processing

Tai-Chang Chen
University of Washington

©UWEE TC Chen

Semiconductor
processing
(microfabrication)

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SOME DEVELOPMENT AT VIETNAM

• HCM CITY – The market for integrated circuits (IC) and


semiconductors in Việt Nam has huge potential, offering great
investment opportunities for domestic and foreign enterprises,
according to experts. (Vietnam news, 2019)
• Seoul Semiconductor to Construct New LED Fab in Vietnam (2016)
• Samsung to build Southeast Asia’s largest R&D center in Hanoi
(2019)
• FabMax, Becamex IDC and Vietsens, for the next step in realizing
the first semiconductor manufacturing and packaging factory in
Binh Duong, Vietnam. (2019)

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Cleanroom

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WHAT IS A CLEAN ROOM?

• A clean environment designed to reduce the contamination of


processes and materials.
• This is accomplished by removing or reducing contamination
sources.
Contamination Sources
• People ~75%
• Ventilation ~15%
• Room Structure ~5%
• Equipment ~5%

©UWEE TC Chen

WHAT IS A CLEAN ROOM?

Entrance: gowning area

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UNBELIEVABLE HOW DANGEROUS WE
ARE!

PEOPLE ACTIVITY PARTICLES/MINUTE (0.3


microns and larger)
Motionless (Standing or 100,000
Seated)
Walking about 2 mph 5,000,000

Walking about 3.5 mph 7,000,000

Walking about 5 mph 10,000,000

Horseplay 100,000,000

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WHAT IS A CLEAN ROOM?

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CLEANROOM CONSTRUCTION

• Cleanroom takes up three floors; ground floor and 2nd floor for
supporting facilities, with the actual cleanroom on the first floor.

from ULSI Technology by Chang and Sze


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SUBSTRATES

• Silicon is the workhorse of microfabrication.


– Resistivity can be tailored over a wide range: from 0.001 to
20,000 ohm-cm.
– Silicon wafers are available in sizes and thicknesses.
– It is smooth, flat, mechanically strong and fairly cheap.
• Bulk silicon wafers are single crystal pieces cut from larger single
crystal ingots and polished.

http://www.xbitlabs.com/images/news/2011-
03/silicon_wafer.jpg

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WHY USE SILICON?

• take advantage of extensive experience from IC production


• readily available in very pure form (“nine nines”)
• material properties are very well known
• exceptional properties:
very strong
yield strength 7 × 109 N/m2 vs. steel 4.2 × 109 N/m2
relatively light
density 2.3 g/cm3 vs. steel 7.9 g/cm3
semiconductor
resistivity .5m-cm (doped) to 230 k-cm

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TENSILE STRESS AND STRAIN

A tensile test is commonly used to determine the stress-strain relation.

• Strong: high yield strength


or ultimate strength.

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PROCESSES

Three basic techniques:


• Pattern definition
(usually lithography)
• Additive processes
(deposition of material: thin film deposition, sputtering,
evaporation, plating, spin-on, …)
• Subtractive processes
(removal of material: etching, …)

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PROCESSES/PATTERNING

• Patterning processes define structures usually in two steps,


– Polymer processing to form an intermediate pattern which then
acts as a mask for etching, deposition, ion implantation.
– After the pattern has been transferred to solid materials, the
intermittent polymer mask is removed.
Spin Coating /Photoresist Spin Coating resist dispenser

photoresist
excess resist flies
off during rotation

wafer to be coated
vacuum chuck

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PROCESSES/PATTERNING

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PROCESSES/PATTERNING

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OVERVIEW OF ALIGN/EXPOSE/DEVELOP
STEPS

(x,y,) alignment of uniform UV exposure illumination


mask to substrate

chrome on glass photomask

photoresist (PR)

latent image created in substrate wafer


photoresist after exposure

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PHOTOLITHOGRAPHY

Process flow for patterning


photoresist with a photomask.
Process of lithographically patterning a
thin film using the photoresist as a
mask.

THIN FILM DEPOSITION

Formation of films on surface of substrate


• Structural layers
• Device layers
• Sacrificial layers
Wide variety of techniques:
• CVD, PECVD
• Evaporation
• Sputtering
• Epitaxial growth
• Oxidation of Si

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THIN FILM DEPOSITION

Source: R. B. Darling, 2011

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PHYSICAL VAPOR DEPOSITION

The general idea of physical vapor deposition (PVD) is material ejection


from a solid target material, transported in a vacuum to the substrate
surface where film deposition take place.

Gas Phase Gas Phase

Transport
Evaporation In vacuum
Resistive heating,
electron beam Condensation
heating, ion
bombardment,
laser beam
bombardment Condensed Phase Condensed Phase
(solid or liquid) (usually solid)
Target materials Thin films formed

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THIN FILM DEPOSITION

A process of evaporating a thin film. A schematic diagram of the metal evaporation


equipment.

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Sputtering

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PLASMAS 101: INTRODUCTION

TECHNOLOGICAL PLASMAS: PARTIALLY IONIZED GASES


An energetic free electron collides with an atom, creating a positive
ion and another free electron.

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PLASMAS 101: INTRODUCTION

Creation of plasma (glow-discharge)


Tube filled with argon, neutral, no charged particles between cathode
and anode
Elastic collision, no energy exchange
Inelastic collision
• Energy not enough high, excite
electrons, emitting photons
• Energy high enough, ionize
electrons, cause secondary free
electrons
• Both free electrons are accelerated
again, so cause cascading or gas
break down
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SPUTTER DEPOSITION

Steps of the sputtering process


• Create plasma
• Plasma provides ions
• Ions accelerated in electric field between target (cathode) and
substrate (anode)
• Sputtering of target
• Transport of sputtered material
• Adsorption to substrate
• Surface diffusion
• Nucleation and film formation

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THIN FILM DEPOSITION

• A method for placing thin film


materials on a wafer surface is
chemical vapor deposition.
• Two or more active species
arrive at the vicinity of the wafer
surface, react, and produce a
solid phase on the surface of the
wafer.

A process of chemical reactive deposition (e.g.,


chemical vapor deposition).

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CVD/CVD PROCESS FLOW

Byproduct diffusion
Reactant diffusion

Desorption
Absorption
Surface diffusion Surface reaction

Three major CVD Techniques


• APCVD: atmospheric pressure (mass-transport-limited)
• LPCVD: low pressure (surface-reaction-limited)
• PECVD: plasma enhanced (mass-transport-limited)

©UWEE TC Chen

CVD/LPCVD

LPCVD quartz tube batch furnace


• low pressure (0.25 - 5 torr)
• up to 200 wafers
• good uniformity

Plasma enhanced CVD


• Some sputtering (conformality
controllable by deposition /
sputter rate)
• Low temperature process (about
http://www.dowcorning.com/content/etronics/etronicschem 100 - 400°C)
/etronics_newcvd_tutorial3.asp
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THERMAL OXIDATION OF SILICON

• Normal operation temperature: 900C and above


• As the thickness of oxide grows, the rate of oxidation growth
decreases.

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ETCHING

• Subtractive process - removing materials


• Wet etching - liquid etchants:
– acids
– hydroxides
• Dry etching - etching gases / plasma:
– physical etching (impact of atoms/ions)
– reactive chemicals / ions
– enhanced by RF energy (instead of temperature)

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WET ETCHING

• Most micromachining is presently done with silicon, and a large


amount of that is etching with wet chemicals.
• Isotropic etchants (e.g. HNA) give rounded profiles.
• Anisotropic etchants (e.g. KOH, TMAH) slow down markedly on
(111) crystal planes of silicon, yielding flat surfaces.
• Dopants such as high concentrations of boron can be used to stop
the progress of etchants such as KOH.
• Electrochemical etch-stop techniques can also be used since at
certain potentials, silicon forms an anodic oxide that stops etching.

©UWEE TC Chen

REACTIVE ION ETCHING

• Replacing the neutral gas by one or more


chemical species
• Chemical etching and physical ion
bombardment
– Reactive ions damage wafer surface
– Dangling bonds = chemical reaction
sites
– Increases etch rate
• Anisotropic
• High selectivity
• Low pressure process

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SEMICONDUCTOR/DOPING

• Doping: “the introduction of controlled amounts of impurities into


semiconductor to change their electrical properties”.
• Common techniques of doping
– Diffusion: accomplish by placing semiconductor wafers in a
carefully controlled, high temperature quartz-tube furnace and
passing a gas mixture that contains the desired dopant through
it.
– Ion Implantation: energetic dopant ions are implanted into
semiconductor by means of an ion beam.

©UWEE TC Chen

DOPING PROCESS

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DOPING PROCESS

• Common techniques of
doping
– Ion Implantation:
energetic dopant
ions are implanted
into semiconductor
by means of an ion
beam.

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CMOS INVERTER PROCESS

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CMOS INVERTER STRUCTURE

NMOS PMOS
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

©UWEE TC Chen

CMOS INVERTER STRUCTURE

Input

GND VDD
output pMOS transistor
nMOS transistor
substrate tap well tap

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INVERTER MASK SET

• Six masks n well

– n-well
– Polysilicon Polysilicon

– n+ diffusion
– p+ diffusion n+ Diffusion

– Contact p+ Diffusion

– Metal Contact

Metal

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FABRICATION STEPS

• Start with blank wafer


• Build inverter from the bottom up
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

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OXIDATION

• Grow SiO2 on top of Si wafer


– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

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PHOTOLITHOGRAPHY/PHOTORESIST

• Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

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PHOTOLITHOGRAPHY/EXPOSURE(MASK 1)

• Expose photoresist through n-well mask


• Strip off exposed photoresist

Photoresist
SiO2

p substrate

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ETCH/TRANSFER PATTERN

• Etch oxide with RIE


– Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

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STRIP PHOTORESIST

• Strip off remaining photoresist


• Necessary so resist doesn’t melt in next step

SiO2

p substrate

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N-WELL/DOPING

• n-well is formed ion implantation


• Ion Implantation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si

SiO2

n well

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STRIP OXIDE

• Strip off the remaining oxide using HF


• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps

n well
p substrate

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GATE OXIDE/POLYSILICON DEPOSITION

• Deposit very thin layer of gate oxide


– < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

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POLYSILICON PATTERNING (MASK 2)

• Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

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OXIDATION

• Use oxide and masking to expose where n+ dopants should be


implanted
• N-diffusion forms nMOS source, drain, and n-well contact

n well
p substrate

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PATTERN N+ REGIONS (MASK 3)

• Pattern oxide and form n+ regions

n+ Diffusion

n well
p substrate

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N-DIFFUSION

• ion implantation

n+ n+ n+

n well
p substrate

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OXIDE REMOVAL

• Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

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P-DIFFUSION (MASK 4)

• Similar set of steps form p+ diffusion regions for pMOS source and
drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

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CONTACTS (MASK 5)

• Now we need to wire together the devices


• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide


p+ n+ n+ p+ p+ n+

n well
p substrate

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METALLIZATION (MASK 6)

• Sputter on aluminum over whole wafer


• Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

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PENTIUM III

• 9.5 million transistors


• 0.25 micron technology

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INTEL CORE 2 DUO MICROPROCESSOR

July 2006 version


• 291 million transistors
• 65 nanometer technology
(transistors 300 times
smaller than a white blood
cell)
• 2.93 GHz clock
(light has time to travel only
10 cm between two clock
signals)

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INTEL'S LOGIC TECHNOLOGY EVOLUTION

Design rule 90nm 65nm 45nm 32nm 22nm

Dielectric SiO2 SiO2 High-K High-K High-K

Gate Poly-Si Poly-Si Metal Metal Metal

1st 2003 2005 2007 2009 2011


Production

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TRI-GATE TRANSISTOR

The old flat transistor


has been replaced
by a thin 3D fin that
comes up vertically
from the silicon
substrate.

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RESEARCHERS BUILD A WORKING CARBON
NANOTUBE COMPUTER

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RESEARCHERS BUILD A WORKING CARBON


NANOTUBE COMPUTER

• The nanotubes, which are cylinder-shaped molecules, have long


held the promise of allowing smaller, faster and lower-powered
computing
• In a paper in the journal Nature at 2013, the researchers reported
that they had successfully built a working computer —an
extremely simple one — entirely from transistors fashioned from
carbon nanotubes.
• The carbon nanotube processor is comparable in capabilities to
the Intel 4004, that company’s first microprocessor, which was
released in 1971,
• by industry standards — one micron vs. 22 nanometers — it is
what computer scientists refer to as a “Turing complete”
machine, meaning that it is capable of performing any
computation, given enough time.
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