DADI INSTITUTE OF ENGINEERING & TECHNOLOGY

(Approved by A.I.C.T.E., New Delhi& Affiliated to JNTUK, Kakinada)

NAAC Accredited Institute
An ISO 9001:2008, 14001:2004 & OHSAS 18001:2007 Certified Institute
NH–5, Anakapalle, Visakhapatnam–531002, Andhra Pradesh
DEPRTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
COURSE DELIVERY PLAN
Subject : Digital Signal Processing Class : III B.Tech ECE B-II Sem
Faculty Name : Designation :
Department : ECE Academic Year: 2019-2020
No. of Teaching Proposed Actual
Unit No Topic periods Learning date of date of
required Method completion completi
1. Syllabus, Course objectives, Course outcomes 1 TLM1 on
Discrete Time Signals and Systems 1 TLM1
2. Discrete time signals & sequences 1 TLM1
3. Classification of Discrete time systems 1 TLM1
4. Stability of LTI systems 1 TLM1
5. Invertability 1 TLM1
6. Response of LTI systems to arbitrary inputs. 1 TLM1
Unit 1 7. Solution of Linear constant coefficient 1 TLM1
Discrete difference equations.
Time Signals
8. Frequency domain representation of discrete 1 TLM1
and Systems time signals and systems.
&
Z-Transform 1 TLM1
Z-Transform
9. Z-Transform of a sequence, various classes of 1 TLM1
signals
10. ROC and its properties 1 TLM4
11. Properties of Z-Transform 1 TLM1
12. Inverse Z-Transform 1 TLM1
13. System function 1 TLM1
14. solution of difference equations using 1 TLM1
Z-transforms
15. Problems 1 TLM4
16. Discrete Fourier series 1 TLM1
17. Properties of discrete Fourier series 1 TLM1
Unit 2 18. DFS representation of periodic sequences 1 TLM1
Discrete Discrete Fourier transform 1 TLM1
Fourier Series
19. DFT, Properties of DFT 1 TLM1
&
Discrete 20. linear filtering methods based on DFT 1 TLM1
Fourier 21. Fast Fourier transform (FFT) 1 TLM1
Transform 22. decimation in time FFT Algorithm 1 TLM1
23. decimation in time FFT Algorithm 1 TLM1
24. decimation in frequency FFT Algorithm 1 TLM1
25. decimation in frequency FFT Algorithm 1 TLM1
26. Problems 1 TLM4
27. Analog Butter worth filter 1 TLM1
28. Analog Butter worth filter 1 TLM1
Unit 3 29. Analog Chebyshev filter 1 TLM1
IIR Digital 30. Analog Chebyshev filter 1 TLM1
Filters & 31. frequency transformation in analog domain 1 TLM1
Realizations 32. Impulse Invariant Transformation 1 TLM1
33. Bilinear Transformation 1 TLM1
34. frequency transformation in digital domain 1 TLM1
35. Realization of IIR Filters : Transposed forms 1 TLM1
36. Problems 1 TLM4
Total Number of Periods for Unit 1,Unit 2,Unit 3 : 36 Periods
 Unit No Topic No. of Teaching Proposed Actual date
periods Learning date of of
required Method completion completion
37. Characteristics of FIR Digital Filters 1 TLM1
38. frequency response of FIR Digital Filters 1 TLM1
39. Design of FIR Digital Filters using 1 TLM1
Window Technique
40. Design of FIR Digital Filters using 1 TLM1
Unit 4
Window Technique
FIR Digital 41. Design of FIR Digital Filters using 1 TLM1
Filters & Window Technique
Realizations 42. Problems 1 TLM4
43. Design of FIR Digital Filters using 1 TLM1
Frequency Sampling technique
44. Realization of FIR Filters: Lattice structures 1 TLM1
45. Lattice-ladder structures 1 TLM1
46. Problems 1 TLM4
47. Decimation 1 TLM4
48. Interpolation 1 TLM1
Unit 5 49. Sampling rate conversion, Implementation 1 TLM1
Multirate of sampling rate converters
Digital Signal 50. Applications: 1 TLM1
Processing Implementation of Digital Filter Banks
51. Implementation of Trans-multiplexers 1 TLM1
52. Sub-band Coding of Speech Signals TLM1
Introduction to programmable DSPs 1 TLM1
53. Multiplier and Multiplier Accumulator 1 TLM1
54. Modified bus structures and memory 1 TLM1
access schemes in P-DSPs
55. Multiple Access Memory, 1 TLM1
Unit 6 Multiported memory
Digital Signal 56. VLIW architecture, Pipelining 1 TLM1
Processors 57. Special addressing modes, On-Chip 1 TLM1
Peripherals
Architecture of TMS320C5X 1 TLM1
58. Introduction, Bus Structure, Central 1 TLM1
Arithmetic Logic Unit,
59. Auxiliary Register ALU, Index Register, Block 1 TLM1
Move Address Register
60. Parallel Logic Unit, Memory mapped 1 TLM1
registers, program controller
61. some flags in the status registers 1 TLM1
62. On- chip memory, On-chip peripherals 1 TLM1
63. Advanced Topics 1 TLM1
Advanced 64. Advanced Topics 1 TLM1
Topics 65. Review of Unit 1 1 TLM1
and 66. Review of Unit 2 1 TLM1
Review of 67. Review of Unit 3 1 TLM1
Syllabus 68. Review of Unit 4 1 TLM1
69. Review of Unit 5 1 TLM1
70. Review of Unit 6 1 TLM1
Total Number of Periods for Unit 4,Unit 5,Unit 6,Review of Syllabus : 34 Periods

Signature of Faculty Signature of HOD PRINCIPAL