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IRFP7530PbF
Application HEXFET® Power MOSFET
Brushed Motor drive applications
BLDC Motor drive applications D VDSS 60V
Battery powered circuits RDS(on) typ. 1.65m
Half-bridge and full-bridge topologies
Synchronous rectifier applications G max 2.00m
Resonant mode power supplies ID (Silicon Limited) 281A
S
OR-ing and redundant power switches
ID (Package Limited) 195A
DC/DC and AC/DC converters
DC/AC Inverters
Benefits
S
Improved Gate, Avalanche and Dynamic dV/dt Ruggedness GD
Fully Characterized Capacitance and Avalanche SOA
Enhanced body diode dV/dt and dI/dt Capability
TO-247
Lead-Free, RoHS Compliant
IRFP7530PbF
G D S
Gate Drain Source
Base part number Package Type Standard Pack Orderable Part Number
Form Quantity
IRFP7530PbF TO-247 Tube 25 IRFP7530PbF
7 300
RDS(on), Drain-to -Source On Resistance (m)
ID = 100A
6 250 Limited by package
ID, Drain Current (A)
5 200
4 150
TJ = 125°C
3 100
TJ = 25°C
2 50
1 0
2 4 6 8 10 12 14 16 18 20 25 50 75 100 125 150 175
TC , Case Temperature (°C)
VGS, Gate -to -Source Voltage (V)
Fig 1. Typical On-Resistance vs. Gate Voltage Fig 2. Maximum Drain Current vs. Case Temperature
Notes:
Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 195A by
source bonding technology. Note that current limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction temperature.
Limited by TJmax, starting TJ = 25°C, L = 111µH, RG = 50, IAS = 100A, VGS =10V.
ISD 100A, di/dt 1338A/µs, VDD V(BR)DSS, TJ 175°C.
Pulse width 400µs; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS.
R is measured at TJ approximately 90°C.
Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 47A, VGS =10V.
4.5V
4.5V 100
10
2.0
100
(Normalized)
TJ = 175°C TJ = 25°C 1.6
10
1.2
1
0.8
VDS = 25V
60µs PULSE WIDTH
0.1 0.4
2 3 4 5 6 7 -60 -20 20 60 100 140 180
VGS, Gate-to-Source Voltage (V) TJ , Junction Temperature (°C)
8.0
Ciss
10000
6.0
Coss
Crss 4.0
1000
2.0
0.0
100
0 50 100 150 200 250 300 350
0.1 1 10 100
QG, Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 8. Typical Gate Charge vs.
Fig 7. Typical Capacitance vs. Drain-to-Source Voltage
Gate-to-Source Voltage
4 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback November 7, 2014
IRFP7530PbF
1000
1000
TJ = 175°C
100
100
Limited by Package
TJ = 25°C 1msec
10 OPERATION IN THIS AREA
10 LIMITED BY RDS(on)
10msec
1 1
Tc = 25°C DC
VGS = 0V Tj = 175°C
Single Pulse
0.1 0.1
0.1 0.4 0.7 1.0 1.3 1.6 1.9 0.1 1 10
Fig 9. Typical Source-Drain Diode Forward Voltage Fig 10. Maximum Safe Operating Area
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
80 2.0
Id = 1.0mA
1.8
77 1.6
1.4
1.2
Energy (µJ)
74
1.0
71 0.8
0.6
68 0.4
0.2
65 0.0
-60 -20 20 60 100 140 180 0 10 20 30 40 50 60
TJ , Temperature ( °C ) VDS, Drain-to-Source Voltage (V)
Fig 11. Drain-to-Source Breakdown Voltage Fig 12. Typical Coss Stored Energy
10
RDS (on), Drain-to -Source On Resistance (m)
VGS = 5.5V
9 VGS = 6.0V
VGS = 7.0V
8 VGS = 8.0V
VGS = 10V
7
1
0 100 200 300 400 500
ID, Drain Current (A)
1000
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming Tj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
100
10
600
TOP Single Pulse Notes on Repetitive Avalanche Curves , Figures 15, 16:
BOTTOM 1.0% Duty Cycle (For further info, see AN-1005 at www.irf.com)
500 ID = 100A 1.Avalanche failures assumption:
EAR , Avalanche Energy (mJ)
4.0 VR = 51V
15 TJ = 25°C
3.5 TJ = 125°C
IRRM (A)
3.0
10
2.5
2.0 ID = 250µA
ID = 1.0mA 5
ID = 1.0A
1.5
1.0 0
-75 -50 -25 0 25 50 75 100 125 150 175 0 200 400 600 800 1000
TJ , Temperature ( °C ) diF /dt (A/µs)
Fig 17. Threshold Voltage vs. Temperature Fig 18. Typical Recovery Current vs. dif/dt
450
20
IF = 100A IF = 60A
400
VR = 51V VR = 51V
250
10
200
150
5
100
50
0
0 200 400 600 800 1000
0 200 400 600 800 1000
diF /dt (A/µs)
diF /dt (A/µs)
Fig 19. Typical Recovery Current vs. dif/dt Fig 20. Typical Stored Charge vs. dif/dt
400
IF = 100A
350 VR = 51V
TJ = 25°C
300 TJ = 125°C
QRR (nC)
250
200
150
100
50
0 200 400 600 800 1000
diF /dt (A/µs)
Fig 22. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs
V(BR)DSS
15V
tp
L DRIVER
VDS
RG D.U.T +
V
- DD
IAS A
20V
tp 0.01 I AS
Fig 23a. Unclamped Inductive Test Circuit Fig 23b. Unclamped Inductive Waveforms
Fig 24a. Switching Time Test Circuit Fig 24b. Switching Time Waveforms
Id
Vds
Vgs
VDD
Vgs(th)
Fig 25a. Gate Charge Test Circuit Fig 25b. Gate Charge Waveform
Notes: This part marking information applies to devices produced after 02/26/2001
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Qualification Information†
Industrial
Qualification Level (per JEDEC JESD47F) ††
Revision History
Date Comments
Updated EAS (L =1mH) = 1102mJ on page 2
11/7/2014
Updated note 9 “Limited by TJmax, starting TJ = 25°C, L = 1mH, RG = 50, IAS = 47A, VGS =10V”. on page 2