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Output
Author : Khairi
LOGIC GATES
TRUTH TABLE
Input Output
A B C X
Author : Khairi
LOGIC GATES
NOT GATE
Output is opposite to input
A X
A X
1 0 X=A
0 1
Truth table
Author : Khairi
LOGIC GATES
NOT GATE
A X
INPUT OUTPUT
A X
1 0
0 1
Truth table
Author : Khairi
LOGIC GATES
NOT GATE
A X
INPUT OUTPUT
A X
1 0
0 1
Truth table
Author : Khairi
LOGIC GATES
A
X
B
Boolean expression
X=A B
INPUT OUTPUT
A B X
0 0 0
0 1 0
1 0 0
1 1 1
Corresponding electric circuit
Author : Khairi
LOGIC GATES
AND GATE
A
X
B
Boolean expression
X=A B
INPUT OUTPUT
A B X
0 0 0
0 1 0
1 0 0
1 1 1
A
B X = A B C
C
X= A B C
Author : Khairi
LOGIC GATES
AND GATE (3 inputs)
A
B X = A B C
C
23 = 2 x 2 x 2
=8
Author : Khairi
LOGIC GATES
AND GATE (3 inputs)
A
B X =A B C
C
Truth table
A B C X=A B C
0 0 0 0
0 0 1 0
0 1 0 0
1 0 0 0
1 1 0 0
1 0 1 0
0 1 1 0
1 1 1 1
Author : Khairi
LOGIC GATES
NAND GATE
A
X
B
X=A B
Author : Khairi
LOGIC GATES
NAND GATE
A
X=A B
B
22 = 2 x 2
=4
Author : Khairi
LOGIC GATES
NAND GATE
A
X=A B
B
Truth table
A B X=A B
0 0
Author : Khairi
LOGIC GATES
NAND GATE
A
X=A B
B
Truth table
A B X=A B
0 0 1
0 1
Author : Khairi
LOGIC GATES
NAND GATE
A
X=A B
B
Truth table
A B X=A B
0 0 1
0 1 1
Author : Khairi
LOGIC GATES
NAND GATE
A
X=A B
B
Truth table
A B X=A B
0 0 1
0 1 1
1 0 1
1 1 0
EXERCISE
A
B
C X
Author : Khairi
LOGIC GATES
EXERCISE
A
B
C X =A B C
INPUT OUTPUT
A B C X
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0 Author : Khairi
LOGIC GATES
A
X
B
Boolean expression for X
X=A+B
INPUT OUTPUT
A B X
0 0 0
0 1 1
1 0 1
1 1 1
Author : Khairi
LOGIC GATES
OR GATE
A
X
B
Boolean expression for X
X=A+B
INPUT OUTPUT
A B X
0 0 0
0 1 1
1 0 1
1 1 1
Corresponding electric circuit
Author : Khairi
OR GATE LOGIC GATES
A
B X
C Boolean expression for X
INPUT OUTPUT X=A+B+C
A B C X
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1 Author : Khairi
LOGIC GATES
NOR GATE
A
X
B
Boolean expression for X
X=A+B
INPUT OUTPUT
A B X
0 0 1
0 1 0
1 0 0
1 1 0
Author : Khairi
LOGIC GATES
EXERCISE
P
Q X
R
INPUT OUTPUT Write Boolean expression for X.
P Q R X List all possible inputs and
outputs for the logic gate in a
0 0 0 1 truth table
0 0 1 0
0 1 0 0
0 1 1 0 X=P+Q+R
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0 Author : Khairi
LOGIC GATES
COMBINATION OF LOGIC GATES
AND
AND
NAND
Author : Khairi
LOGIC GATES
COMBINATION OF LOGIC GATES
A A B
B
C
D
Author : Khairi
LOGIC GATES
COMBINATION OF LOGIC GATES
A A B
B
C
D
C D
Author : Khairi
LOGIC GATES
COMBINATION OF LOGIC GATES
A A B
B
A B C D
X
C
D
C D
Author : Khairi
LOGIC GATES
COMBINATION OF LOGIC GATES
P+Q
P
X
Q
P+Q
P
X
Q
P
Q
R
S
X=P+ Q + R S
Author : Khairi
LOGIC GATES
COMBINATION OF LOGIC GATES
1 0
0
0 X
0
1 1
Author : Khairi
LOGIC GATES
EXERCISE
B X
A B X
0 0 0
0 1 1
1 0 0
1 1 0
Author : Khairi
LOGIC GATES
EXERCISE
1 1
1
X
0
1
1 0
Author : Khairi
LOGIC GATES
EXERCISE
1 1
1
X
1
0
1 0
Author : Khairi
LOGIC GATES
EXERCISE
1 1
1
X
0
0
1 0
Author : Khairi
LOGIC GATES
SERIAL INPUT
1011
X
1001
Author : Khairi
LOGIC GATES
SERIAL INPUT
1011 1
X
1001
Author : Khairi
LOGIC GATES
SERIAL INPUT
1011 10
X
1001
Author : Khairi
LOGIC GATES
SERIAL INPUT
1011 1 01
X
1001
Author : Khairi
LOGIC GATES
SERIAL INPUT
1011 1 011
X
1001
Author : Khairi
LOGIC GATES
SERIAL INPUT
1011 1 011
X
1001
Output X = 1011
Author : Khairi
LOGIC GATES
SERIAL INPUT
1011 1
1001 X
Author : Khairi
LOGIC GATES
SERIAL INPUT
1011 10
1001 X
Author : Khairi
LOGIC GATES
SERIAL INPUT
1011 100
1001 X
Author : Khairi
LOGIC GATES
SERIAL INPUT
1011 1001
1001 X
Output X = 1001
Author : Khairi
LOGIC GATES
EXERCISE
1111 1111
1001
X
1111
1101
0001 0001
Author : Khairi
LOGIC GATES
EXERCISE
0000
1111
1001
X
1110
1101
0001 1110
State the output for X
Author : Khairi
LOGIC GATES
EXERCISE
0000
1111
1001
X
0001
1101
0001 1110
State the output for X
Author : Khairi
LOGIC GATES
INPUT FROM TIMING DIAGRAM
1 1
0 0
Author : Khairi
LOGIC GATES
INPUT FROM TIMING DIAGRAM
1 0 1
X = 101
0 0 1
INPUT Q
OUTPUT X
Author : Khairi
LOGIC GATES
EXERCISE
1 0 1 1 1 0 0
Draw the output if the inputs
are fed to NOR GATE
0 0 1 1 0 1 0
0 1 0 0 0 0 1
Author : Khairi
LOGIC GATES
EXERCISE
Author : Khairi
ENRICHMENT PRACTICE
Q Security lamp
Light sensor X
Relay switch
Author : Khairi
ENRICHMENT PRACTICE
Q Security lamp
Light sensor X
Relay switch
Author : Khairi
ENRICHMENT PRACTICE
Q Security lamp
Light sensor X
Relay switch
1 0 0
1 1 0
Author : Khairi
ENRICHMENT PRACTICE
Q Security lamp
Light sensor X
Relay switch
Author : Khairi
PAST YEARS QUESTION
Author : Khairi
PAST YEARS QUESTION
Author : Khairi
PAST YEARS QUESTION
What is the get X which produces the output in the truth table ?
A. AND
B. OR
C. NAND
D. NOR
Author : Khairi
PAST YEARS QUESTION
C. Z=X Y
D. Z=X Y
Author : Khairi
PAST YEARS QUESTION
0101 1110
1110
1001
0110
Which of the following output signals is produced by the logic
gate circuit ?
A. B. C. D.
Author : Khairi
PAST YEARS QUESTION
Author : Khairi
PAST YEARS QUESTION
S1 S2 Output P S1 S2 Output Q
0 0 0 0 0 1
1 0 1 1 0 1
1 1 0 1 1 1
Author : Khairi
PAST YEARS QUESTION
Figure shows the system used to control the level of pesticide in a bottle
Input S1 and S2 is “0” when they receive a low level of radiation and “1”
when they receive a high level of radiation.
a. State the level of the pesticide in the bottle if the input S1 is “0”.
Give your reason.
Level of pesticide in the bottle is high because it receives low radiation
due to less penetration of radioactive radiation
Author : Khairi
PAST YEARS QUESTION
Figure shows the system used to control the level of pesticide in a bottle
Input S1 and S2 is “0” when they receive a low level of radiation and “1”
when they receive a high level of radiation.
b. State the level of the pesticide in the bottle if the input S1 is “1”.
Give your reason.
Level of pesticide in the bottle is low because it receives high radiation
due to higher penetration of radioactive radiation
Author : Khairi
PAST YEARS QUESTION
Figure shows the system used to control the level of pesticide in a bottle
Input S1 and S2 is “0” when they receive a low level of radiation and “1”
when they receive a high level of radiation.
c. If the output of logic gate system is “1” when the volume of pesticide
accepted and “0” if it is rejected.Which combination of logic gate P or Q is
suitable to be used ?Give reason for your answer.
Combination of logic gate P because both S1 and S2 have to be “0” when the volume
is acceptable
Author : Khairi
PAST YEARS QUESTION
output
Author : Khairi