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CMOS Technology
Want VP ≤ VN
saturated
IDS
Increasing VGS
VTH = 0.5V
n n p p
p n
Connect B to Connect B
D GND to keep PN S
to VDD to
reverse-biased
B B keep PN
G (Vp ≤ Vn); keeps G
D and S reverse-
insulated from biased
S D
B
“off”: “off”:
VGS < VTH,NFET S D VGS > VTH,PFET S D
VGS ︎ ⇒ “R”➡︎
“on”: “on”:
VGS > VTH,NFET S “ “ D VGS < VTH,PFET S “ “ D
G
S
pullup
CMOS Inverter VTC
D Ipu
D Steady state reached
G pulldown Ipd when Vout reaches
S value where Ipu = Ipd.
When VIN is in the middle, both the pfet and nfet are “on” and the shape
of the VTC depends on the details of the devices’ characteristics. CMOS
gates have very high gain in this region (small changes in VIN produce
large changes in VOUT) and the VTC is almost a step function.
6.004 Computation Structures L3: CMOS Technology, Slide #8
Beyond Inverters:
Complementary pullups and pulldowns
Now you know what the “C”
in CMOS stands for!
We want complementary pullup and pulldown logic,
i.e., the pulldown should be “on” when the pullup is
“off” and vice versa.
Power supply
pullup pulldown F(inputs) Pullup
on off driven “1” switches
A
A B
B
A
A B
B
A B Z
0 0 1
0 1 1 NAND
82λ
1 0 1
1 1 0
A
Step 2. Walk the hierarchy replacing
nfets with pfets, series subnets with C
B
parallel subnets, and parallel subnets Does this
with series subnets recipe work
for all logic
functions?
A B
Step 3. Combine pfet pullup C
network from Step 1 with nfet
pulldown network from Step 2 to A
form a fully-complementary CMOS B C
gate.
6.004 Computation Structures L3: CMOS Technology, Slide #12
CMOS Gates Are Naturally Inverting
A B A·B
Corollary: you can’t build 0 0 0
positive logic, e.g., AND, 0 1 0
with one CMOS gate
1 0 0
1 1 Oops, output is
1 also rising!
A=1, B rising…
6.004 Computation Structures L3: CMOS Technology, Slide #13
CMOS Timing Specifications
Circuit:
CP
Vout R
Electrical model: VIN
CW
CN
VIN
VIN GOAL:
minimize
VIH propagation
delay!
VIL
ISSUE:
VOUT keep
≤ tPD ≤ tPD capacitances
VOH low and
transistors
fast
VOL
VIN
Do we really need
VIH tCD?
VIL
Usually not… it’ll
be important when
we design circuits
VOUT ≥ tCD ≥ tCD with registers
(coming soon!)
VOH
If tCD is not
VOL specified, safe to
assume it’s 0.
A
B
≥ tCD
Must be ___________
≤ tPD
Must be ___________
Notes:
1. No Promises during
2. Default (conservative) spec: tCD = 0
12
tPD = _______ nS
tCD is the minimum
cumulative contamination
delay over all paths from 2
tCD = _______ nS
inputs to outputs
B
C Y
NOR:
A B Z A
0 0 1
A
Z 0 1 0 B
B 1 0 0 tPD
1 1 0 tCD
Z
X
determine
CMOS NOR: B the output
A
X
Z
B
A X tCD
tPD