Compal LA-F951P DH5VF DH7VF DH53F DH73F REV 1A (1.0) - Acer Nitro AN515-52

A
I B I C I D I E
Compal Confidential
1 1
V15 /DH5VF
2
V17 /DH7VF 2
Vxl 5/DH53F MB Schematic Document

* Vxl 7/DH73F
Intel CoffeeLake H
3
Nvidia N17P-G0/G1 3
LA-F 951P
Rev: lA
4 2018.02.22 4
Security Classification
2017/12 /18
Compal Secret Data
2018/09 / 01 Title
Cnmpnl Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R8D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITFER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Sustorr
-
DH5 VF M/ B LA F591PR01 1.0
Date : Thursday, February 22, 2018 ISheet 1 of 67

A B C D E
BOM Structure Table
BOM Option Table

BOM Structure
VX15@
SATA HDD W REDRIVER SATARD@
SATA HDD WO REDRIVER SATANRD@ +VCCIO
NV N17P-G0(1050) G0@ +VCC_SA
NV N17P-G1(1050TI) G1@ +1.8VSDGPU_AON
i5 CPU i5@ +1.8VSDGPU_MAIN
i7 CPU i7@ +1.8VGA_CORE
+1.35VSDGPU
I5QP89 PG1 4G 32HDMI

I78750 PG1 4G 32HDMI
X76730BOL51 SAMSUNG1280
X76730BOL52 HYNLX1280
X76730BOL53 SAMSUNG2560
X76730BOL54 HYNIX2560
X76730BOL55 MICRON2560
UQ2 +1.8VS
+1.05VALW_PRIM
RH92 PCH
+1.05VALW_PCH
RH94 PCH
RH102
RH103 PCH
RH105
+19VB -> +19V_CPU

LX1
A B C D E
DH5VF_EVT Power Sequence AC mode

BIOS ver: V0.02W1
EC: ver: V002AT04
1 1
Plug in Power On S3 S3 Resume Power Off

+3VLP
+3VLP
EC_ON
EC_ON → 330.8ms
+5VALW
+5VALW → 333.3ms
ON/OFFBTN#
ON/OFFBTN#
→
92.03ms
+3VALW +3VALW
→ 293.7us
→
94.88ms
+1.05VALW +1.05VALW
EC_RSMRST# → 29.19ms
EC_RSMRST#
20.1ms
2.439ms → ← →
PBTN_OUT# PBTN_OUT#
PM_SLP_S4#
174.6ms
→ 19.18ms PM_SLP_S4#
PM_SLP_S3# → 19.22ms 100.5us

PM_SLP_S3#
2 SYSON → 72.1us → 152.8us

SYSON 2
+1.05V_VCCST → 275.9us → 88.37us

+1.05V_VCCST
+1.2V_VDDQ → 692.9us → 367.6us

+1.2V_VDDQ
→ 910.1us
→ 2.266ms
+2.5VS +2.5VS
→ 12.7ms
→ 13.01us
→ 67.04ms
→ 13us
SUSP# SUSP#
+1.05VS_VCCSTG → 8.378us → 55.47us → 8.502us

→ 68.53us +1.05VS_VCCSTG
+5VS → 877.7us → 618.5us → 906.0us

→ 686.0us +5VS
+3VS → 630.4us → 8.679ms → 656.1us

→ 11.65ms
+3VS
+1.8VS → 412us → 347.6us → 424.9us 446.2us

+1.8VS
EC_VCCST_PG → 25.34ms → 0us → 25.25ms 0us

EC_VCCST_PG
SM_PG_CTRL → 25.35ms
→ 0us → 25.25ms
→ 13.97ms
SM_PG_CTRL
+0.6VS_VTT → 25.36ms
→ 3.819ms → 25.26ms
→ 2.034ms
+0.6VS_VTT
VR_ON → 25.19ms
→ 26.91us
→ 25.59ms
→ 27.06us VR_ON
+VCC_SA → 1.759ms
→ 51.25us
→ 1.757ms
→ 48.00us +VCC_SA
3 +VCC_CORE → 173.0ms
→ 87.75us
→ 167.1ms
→ 112.0us +VCC_CORE 3
+VCC_GT → NA
→ NA
→ NA NA
+VCC_GT
PCH_PWROK → 12.42ms
→ 47.39us
→ 12.18ms
→ 47.83us
PCH_PWROK
SYS_PWROK → 150.3ms
→ 61.95us
→ 150.6ms
→ 62.37us
SYS_PWROK
PLT_RST# → 152.3ms
→ 318.7us
→ 151.8ms
PLT_RST#
4 4
2017/12/18
Compal Secret Data
2018/09/01 Title
Compal Electronics, Inc.
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
DH5VF M/B LA-F591PR01 1.0
Date: Thursday, February 22, 2018 Sheet 5 of 67

A B C D E
5 4 3 2 1
2.2K 2.2K
+3VALW_PCH_PRIM
+3VS
2.2K +3VS 2.2K
PCH_SMBCLK D_CK_SCLK
(QH7)
PCH_SMBDATA 2N7002DW D_CK_SDATA SO-DIMM A & B
PCH_SML0CLK 499
G-Sensor
+3VALW_PCH_PRIM 1.8K
D
PCH_SML0DATA 499 D
Skylake-H 2K
2.2K +1.8VSDGPU_AON
PCH 1.8K +1.8VSDGPU_AON
+3VALW_PCH_PRIM 2K
2.2K +1.8VSDGPU_MAIN I2CB_SCL
PCH_SML1CLK EC_SMB_CK2 VGA_I2CS_SCL
I2CB_SDA
(RH189/RH190) (QV2)
PCH_SML1DATA R-short EC_SMB_DA2 PJT138KA VGA_I2CS_SDA 2K
2.2K N17P-G0 2K
+1.8VSDGPU_AON
2.2K
+3VLP_EC N17P-G1 I2CC_SCL
EC_SMB_CK1 100 ohm EC_SMB_CK1-1 I2CC_SDA

BATTERY (co-lay) 179F_SMB_CK2
EC_SMB_DA1 EC_SMB_DA1-1 2N7002
100 ohm CONN R-Short USB CC EJ179F
179F_SMB_DA2
KB9022 0 ohm EC_SMB_CK1_CHGR

2.2K
0 ohm EC_SMB_DA1_CHGR Charger
+3VS
+3VS 2.2K
EC_SMB_CK2
TMS_SMB_CLK
(QF1)
C EC_SMB_DA2 2N7002DW THERMAL SENSOR C
TMS_SMB_DATA
B B
A A
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/12/18 Deciphered Date 2018/09/01 Title
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17E-GDDR5_D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH5VF M/B LA-F591PR01
5 4 3 2 1
A B C D E
CO-LAY FOR VGA OUTPUT
<27> GPU_EDP_TXP0 RG183 1 @ 2 0_0201_5%

<27> GPU_EDP_TXN0 RG184 1 @ 2 0_0201_5%
<27> GPU_EDP_TXP1 RG185 1 @ 2 0_0201_5%
<27> GPU_EDP_TXN1 RG186 1 @ 2 0_0201_5%
<27> GPU_EDP_TXP2 RG187 1 @ 2 0_0201_5%
<27> GPU_EDP_TXN2 RG188 1 @ 2 0_0201_5%
<27> GPU_EDP_TXP3 RG189 1 @ 2 0_0201_5%
1 <27> GPU_EDP_TXN3 RG190 1 @ 2 0_0201_5% 1
RG191 1 @ 2 0_0201_5% EDP_AUXP

<27> GPU_EDP_AUXP EDP_AUXN
RG192 1 @ 2 0_0201_5%
<27> GPU_EDP_AUXN
CFL-H
UC1D
K36 D29 EDP_TXP0

DDI1_TXP_0 EDP_TXP_0 EDP_TXN0 EDP_TXP0 <33>
K37 E29
DDI1_TXN_0 EDP_TXN_0 EDP_TXP1 EDP_TXN0 <33>
2 J35 F28 2
J34 E28
DDI1_TXN_1 EDP_TXN_1 EDP_TXP2 EDP_TXN1 <33>
H37 A29
EDP_TXP2 <33>
H36 DDI1_TXP_2
DDI1_TXN_2
EDP_TXP_2
EDP_TXN_2
B29 EDP_TXN2
EDP_TXP3 EDP_TXN2 <33>
eDP
J37 C28
J38 B28
DDI1_TXN_3 EDP_TXN_3 EDP_TXN3 <33>
D27 C26 EDP_AUXP
DDI1_AUXP EDP_AUXP EDP_AUXN EDP_AUXP <33>
E27 B26 EDP_AUXN <33>
DDI1_AUXN EDP_AUXN
H34
H33 DDI2_TXP_0
F37 DDI2_TXN_0 A33 +VCCIO
G38 DDI2_TXP_1 EDP_DISP_UTIL
F34 DDI2_TXN_1
F35 DDI2_TXP_2 D37 DP_RCOMP RC1 1 2 24.9_0402_1%
E37 DDI2_TXN_2 DISP_RCOMP
E36 DDI2_TXP_3 Trace Width/Space: 15 mil/ 20 mil
DDI2_TXN_3 Max Trace Length: 600 mil
F26
E26 DDI2_AUXP
DDI2_AUXN
C34
D34 DDI3_TXP_0
Coffee Lake-H CPU SKU B36 DDI3_TXN_0
DDI3_TXP_1
B34
F33 DDI3_TXN_1
E33 DDI3_TXP_2
3 UC1 UC1 C33 DDI3_TXN_2 3
B33 DDI3_TXP_3
DDI3_TXN_3 G27 CPU_DISPA_BCLK_R
PROC_AUDIO_CLK CPU_DISPA_SDO_R CPU_DISPA_BCLK_R <19>
I5@ I7@ A27 G25 CPU_DISPA_SDO_R <19>
B27 DDI3_AUXP PROC_AUDIO_SDI G29 CPU_DISPA_SDI RC2 2 1 20_0402_5% CPU_DISPA_SDI_R
CFL-H 2.3G BGA CFL-H 2.2G BGA DDI3_AUXN CPU_DISPA_SDI_R <19>
4 ofPROC_AUDIO_SDO
13
SA0000BPJ40 SA0000BPZ40 follow CRB
CFL-H_BGA1440
Cannon Lake PCH SKU
UH1
QNDQ@
CNP-H_BGA874
SA0000BVP10
NV N17P SKU
UV1 UV1
4 4
G0@ G1@
N17P-G0-A1 N17P-G1-A1
SA0000A0540 SA0000A0660
2017/12/18
Compal Secret Data
2018/09/01 Title
CFL-H(1/8)DDI/eDP
Custom

A B C D E
A B C D E
CHANNEL-A
Interleaved Memory
UC1A
CFL-H
DDR CHANNEL A
1 <23> DDR_A_D[0..63] 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_A_D0 BR6 AG1 DDR_A_CLK0
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK#0 DDR_A_CLK0 <23>
BT6 AG2 DDR_A_CLK#0 <23>
DDR_A_D2 BP3 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 AK2 DDR_A_CLK1
DDR_A_D3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR_A_CLK#1 DDR_A_CLK1 <23>
BR3 AK1 DDR_A_CLK#1 <23>
DDR_A_D4 BN5 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 AL3
DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3
DDR_A_D6 BP2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 AL2
DDR_A_D7 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1
DDR_A_D8 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3
DDR_A_D9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_A_CKE0
DDR_A_D10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE1 DDR_A_CKE0 <23>
BL2 AT2 DDR_A_CKE1 <23>
DDR_A_D11 BM1 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 AT3
DDR_A_D12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5
DDR_A_D13 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3
DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 DDR_A_CS#0
DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#1 DDR_A_CS#0 <23>
BK2 AE2 DDR_A_CS#1 <23>
DDR_A_D16 BG4 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 AD2
DDR_A_D17 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5
DDR_A_D18 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3
DDR_A_D19 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_A_ODT0
DDR_A_D20 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT1 DDR_A_ODT0 <23>
BG2 AE4 DDR_A_ODT1 <23>
DDR_A_D21 BG1 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 AE1
DDR_A_D22 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4
DDR_A_D23 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3
DDR_A_D24 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_A_BA0
DDR_A_D25 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA1 DDR_A_BA0 <23>
BD1 AH1 DDR_A_BA1 <23>
DDR_A_D26 BC4 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 AU1 DDR_A_BG0
DDR_A_D27 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <23>
2 BC5 2
DDR_A_D28 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_A_MA16_RAS#
DDR_A_D29 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR_A_MA14_W E# DDR_A_MA16_RAS# <23>
BD4 AG4 DDR_A_MA14_W E# <23>
DDR_A_D30 BC1 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 AD1 DDR_A_MA15_CAS#
DDR_A_D31 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA15_CAS# <23>
BC2
DDR_A_D32 AB1 DDR0_DQ_31/DDR0_DQ_47 AH3 DDR_A_MA0
DDR_A_D33 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 DDR_A_MA1 DDR_A_MA0 <23>
AB2 AP4 DDR_A_MA1 <23>
DDR_A_D34 AA4 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 AN4 DDR_A_MA2
AA5 AP5 DDR_A_MA3 <23>
DDR_A_D36 AB5 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 AP2 DDR_A_MA4
DDR_A_D37 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 DDR_A_MA5 DDR_A_MA4 <23>
AB4 AP1 DDR_A_MA5 <23>
DDR_A_D38 AA2 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 AP3 DDR_A_MA6
DDR_A_D39 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 DDR_A_MA7 DDR_A_MA6 <23>
AA1 AN1 DDR_A_MA7 <23>
DDR_A_D40 V5 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 AN3 DDR_A_MA8
V2 AT4 DDR_A_MA9 <23>
DDR_A_D42 U1 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AH2 DDR_A_MA10
U2 AN2 DDR_A_MA11 <23>
DDR_A_D44 V1 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 AU4 DDR_A_MA12
V4 AE3 DDR_A_MA13 <23>
DDR_A_D46 U5 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 AU2 DDR_A_BG1
DDR_A_D47 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR_A_ACT# DDR_A_BG1 <23>
U4 AU3 DDR_A_ACT# <23>
DDR_A_D48 R2 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT#
DDR_A_D49 P5 DDR0_DQ_48/DDR1_DQ_32 AG3 DDR_A_PAR
DDR_A_D50 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR_A_ALERT# DDR_A_PAR <23>
R4 AU5 DDR_A_ALERT# <23>
DDR_A_D51 P4 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT#
DDR_A_D52 R5 DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL)
DDR_A_D53 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0
DDR_A_D54 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR_A_DQS#1 DDR_A_DQS#0 <23>
R1 BL3 DDR_A_DQS#1 <23>
DDR_A_D55 P1 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 BG3 DDR_A_DQS#2
3 DDR_A_D56 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 DDR_A_DQS#3 DDR_A_DQS#2 <23> 3
M4 BD3 DDR_A_DQS#3 <23>
DDR_A_D57 M1 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 AA3 DDR_A_DQS#4
L4 U3 DDR_A_DQS#5 <23>
DDR_A_D59 L2 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 P3 DDR_A_DQS#6
M5 L3 DDR_A_DQS#7 <23>
DDR_A_D61 M2 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5
DDR_A_D62 L5 DDR0_DQ_61/DDR1_DQ_45 BP5 DDR_A_DQS0
DDR_A_D63 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR_A_DQS1 DDR_A_DQS0 <23>
L1 BK3 DDR_A_DQS1 <23>
DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 BF3 DDR_A_DQS2
DDR0_DQSP_2/DDR0_DQSP_4 DDR_A_DQS3 DDR_A_DQS2 <23>
LP3/DDR4 BC3 DDR_A_DQS3 <23>
BA2 DDR0_DQSP_3/DDR0_DQSP_5 AB3 DDR_A_DQS4
NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 DDR_A_DQS5 DDR_A_DQS4 <23>
BA1 V3 DDR_A_DQS5 <23>
AY4 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 R3 DDR_A_DQS6
NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 DDR_A_DQS7 DDR_A_DQS6 <23>
AY5 M3 DDR_A_DQS7 <23>
BA5 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5
BA4 NC/DDR0_ECC_4 AY3
AY1 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 BA3 For ECC DIMM
AY2 NC/DDR0_ECC_6 1 OFDDR0_DQSN_8/DDR0_DQSN_8
13
For ECC DIMM NC/DDR0_ECC_7
CFL-H_BGA1440
4 4
2017/12/18
Compal Secret Data
2018/09/01 Title
CFL-H(2/8)DIMMA
Custom

A B C D E
A B C D E
CHANNEL-B
Interleaved Memory
UC1B
CFL-H
<24> DDR_B_D[0..63] DDR CHANNEL B

1 1
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_B_D0 BT11 AM9 DDR_B_CLK0
DDR_B_D1 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK#0 DDR_B_CLK0 <24>
BR11 AN9 DDR_B_CLK#0 <24>
DDR_B_D2 BT9 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 AM7 DDR_B_CLK1
DDR_B_D3 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 DDR_B_CLK#1 DDR_B_CLK1 <24>
BR8 AM8 DDR_B_CLK#1 <24>
DDR_B_D4 BP11 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 AM11
DDR_B_D5 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10
DDR_B_D6 BP8 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2 AJ10
DDR_B_D7 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11
DDR_B_D8 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
DDR_B_D9 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8 DDR_B_CKE0
DDR_B_D10 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE1 DDR_B_CKE0 <24>
BL8 AT10 DDR_B_CKE1 <24>
DDR_B_D11 BJ8 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 AT7
DDR_B_D12 BJ11 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT11
DDR_B_D13 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
DDR_B_D14 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11 DDR_B_CS#0
DDR_B_D15 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#1 DDR_B_CS#0 <24>
BJ7 AE7 DDR_B_CS#1 <24>
DDR_B_D16 BG11 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 AF10
DDR_B_D17 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
DDR_B_D18 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
DDR_B_D19 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7 DDR_B_ODT0
DDR_B_D20 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT1 DDR_B_ODT0 <24>
BF11 AE8 DDR_B_ODT1 <24>
DDR_B_D21 BF10 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 AE9
DDR_B_D22 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
DDR_B_D23 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
DDR_B_D24 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10 DDR_B_MA16_RAS#
DDR_B_D25 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA14_W E# DDR_B_MA16_RAS# <24>
BC11 AH11 DDR_B_MA14_W E# <24>
DDR_B_D26 BB8 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 AF8 DDR_B_MA15_CAS#
DDR_B_D27 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 DDR_B_MA15_CAS# <24>
2 BC8 2
DDR_B_D28 BC10 DDR1_DQ_27/DDR0_DQ_59 AH8 DDR_B_BA0
DDR_B_D29 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 DDR_B_BA1 DDR_B_BA0 <24>
BB10 AH9 DDR_B_BA1 <24>
DDR_B_D30 BC7 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 AR9 DDR_B_BG0
DDR_B_D31 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <24>
BB7
DDR_B_D32 AA11 DDR1_DQ_31/DDR0_DQ_63 AJ9 DDR_B_MA0
DDR_B_D33 DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 DDR_B_MA1 DDR_B_MA0 <24>
AA10 AK6 DDR_B_MA1 <24>
DDR_B_D34 AC11 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 AK5 DDR_B_MA2
AC10 AL5 DDR_B_MA3 <24>
DDR_B_D36 AA7 DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 AL6 DDR_B_MA4
DDR_B_D37 DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 DDR_B_MA5 DDR_B_MA4 <24>
AA8 AM6 DDR_B_MA5 <24>
DDR_B_D38 AC8 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 AN7 DDR_B_MA6
DDR_B_D39 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 DDR_B_MA7 DDR_B_MA6 <24>
AC7 AN10 DDR_B_MA7 <24>
DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7
DDR_B_D40 W8 DDR4(IL)/LP3-DDR4(NIL) AN8 DDR_B_MA8
W7 AR11 DDR_B_MA9 <24>
DDR_B_D42 V10 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 AH7 DDR_B_MA10
V11 AN11 DDR_B_MA11 <24>
DDR_B_D44 W11 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 AR10 DDR_B_MA12
W10 AF9 DDR_B_MA13 <24>
DDR_B_D46 V7 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 AR7 DDR_B_BG1
DDR_B_D47 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR_B_ACT# DDR_B_BG1 <24>
V8 AT9 DDR_B_ACT# <24>
DDR_B_D48 R11 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT#
DDR_B_D49 P11 DDR1_DQ_48/DDR1_DQ_48 AJ7 DDR_B_PAR
DDR_B_D50 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR_B_ALERT# DDR_B_PAR <24>
P7 AR8 DDR_B_ALERT# <24>
DDR_B_D51 R8 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT#
DDR_B_D52 R10 DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL)
DDR_B_D53 P10 DDR1_DQ_52/DDR1_DQ_52 BN9 DDR_B_DQS#0
DDR_B_D54 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 DDR_B_DQS#1 DDR_B_DQS#0 <24>
R7 BL9 DDR_B_DQS#1 <24>
3 DDR_B_D55 P8 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 BG9 DDR_B_DQS#2 3
L11 BC9 DDR_B_DQS#3 <24>
DDR_B_D57 M11 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 AC9 DDR_B_DQS#4
L7 W9 DDR_B_DQS#5 <24>
DDR_B_D59 M8 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 R9 DDR_B_DQS#6
L10 M9 DDR_B_DQS#7 <24>
DDR_B_D61 M10 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7
DDR_B_D62 M7 DDR1_DQ_61/DDR1_DQ_61 BP9 DDR_B_DQS0
DDR_B_D63 DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 DDR_B_DQS1 DDR_B_DQS0 <24>
L8 BJ9 DDR_B_DQS1 <24>
DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 BF9 DDR_B_DQS2
DDR1_DQSP_2/DDR0_DQSP_6 DDR_B_DQS3 DDR_B_DQS2 <24>
AW11 LP3/DDR4 BB9 DDR_B_DQS3 <24>
AY11 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 AA9 DDR_B_DQS4
NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 DDR_B_DQS5 DDR_B_DQS4 <24>
AY8 V9 DDR_B_DQS5 <24>
AW8 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 P9 DDR_B_DQS6
NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 DDR_B_DQS7 DDR_B_DQS6 <24>
AY10 L9 DDR_B_DQS7 <24>
AW10 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7
AY7 NC/DDR1_ECC_5 AW9
AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9 For ECC DIMM
For ECC DIMM NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8
RC3 1 2 121_0402_1% SM_RCOMP0 G1 BN13 +0.6V_VREFCA

+0.6V_VREFCA
RC4 1 2 75_0402_1% SM_RCOMP1 H1 DDR_RCOMP_0 DDR_VREF_CA BP13
RC5 1 2 100_0402_1% SM_RCOMP2 J2 DDR_RCOMP_1 2 OF 13 DDR0_VREF_DQ BR13 +0.6V_B_VREFDQ
DDR_RCOMP_2 DDR1_VREF_DQ +0.6V_B_VREFDQ
Trace Width/Space: 15 mil/ 25 mil CFL-H_BGA1440
Max Trace Length: 500 mil
4 4
2017/12/18
Compal Secret Data
2018/09/01 Title
CFL-H(3/8)DIMMB
Custom

A B C D E
A B C D E
PEG&DMI
To DGPU
1 To DGPU PEG Lane Reversed
1
PEG Lane Reversed CFL-H

UC1C
CC1 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P15 E25 B25 PEG_CTX_GRX_P15 0.22U_0201_6.3V6K 2 1VGA@ CC2
<25> PEG_CRX_C_GTX_P15 PEG_CRX_GTX_N15 PEG_RXP_0 PEG_TXP_0 PEG_CTX_GRX_N15 0.22U_0201_6.3V6K PEG_CTX_C_GRX_P15 <25>
<25> PEG_CRX_C_GTX_N15 CC3 VGA@ 1 2 0.22U_0201_6.3V6K D25 A25 2 1VGA@ CC4
PEG_RXN_0 PEG_TXN_0 PEG_CTX_C_GRX_N15 <25>
<25> PEG_CRX_C_GTX_N14 CC6 VGA@ 1 2 0.22U_0201_6.3V6K F24 C24 2 1VGA@ CC12
<25> PEG_CRX_C_GTX_P9 PEG_CRX_GTX_N9 PEG_RXP_6 PEG_TXP_6 PEG_CTX_GRX_N9 PEG_CTX_C_GRX_P9 <25>
<25> PEG_CRX_C_GTX_N9 CC27 VGA@ 1 2 0.22U_0201_6.3V6K D19 A19 0.22U_0201_6.3V6K 2 1VGA@ CC28
<25> PEG_CRX_C_GTX_N8 CC31 VGA@ 1 2 0.22U_0201_6.3V6K F18 C18 0.22U_0201_6.3V6K 2 1VGA@ CC32
CC33 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P7 D17 A17 PEG_CTX_GRX_P7 0.22U_0201_6.3V6K 2 1VGA@ CC34
2
<25> PEG_CRX_C_GTX_N7 CC35 VGA@ 1 2 0.22U_0201_6.3V6K E17 B17 0.22U_0201_6.3V6K 2 1VGA@ CC36 2
CC37 VGA@ 1 2 0.22U_0201_6.3V6K PEG_CRX_GTX_P6 F16 C16 PEG_CTX_GRX_P6 0.22U_0201_6.3V6K 2 1VGA@ CC38
<25> PEG_CRX_C_GTX_N6 CC39 VGA@ 1 2 0.22U_0201_6.3V6K E16 B16 0.22U_0201_6.3V6K 2 1VGA@ CC40
+VCCIO
RC6 1 2 24.9_0402_1% PEG_RCOMP G2
PEG_RCOMP
Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil
3 DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0 3
<15> DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_RXP_0 DMI_TXP_0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 <15>
<15> DMI_CRX_PTX_N0 E8 A8 DMI_CTX_PRX_N0 <15>
DMI_RXN_0 DMI_TXN_0
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
<15> DMI_CRX_PTX_N1 F6 B6 DMI_CTX_PRX_N1 <15>
DMI_RXN_1 DMI_TXN_1
To PCH DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2 To PCH
<15> DMI_CRX_PTX_N2 E5 A5 DMI_CTX_PRX_N2 <15>
DMI_RXN_2 DMI_TXN_2
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
<15> DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_RXP_3 3 OF 13 DMI_TXP_3 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 <15>
<15> DMI_CRX_PTX_N3 J9 B4 DMI_CTX_PRX_N3 <15>
DMI_RXN_3 DMI_TXN_3
CFL-H_BGA1440
4 4
2017/12/18
Compal Secret Data
2018/09/01 Title
PEG/DMI
Custom

A B C D E
A B C D E
CFL-H
UC1E
PCH_CPU_BCLK_P B31 BN25 CFG0 CFG0 RC7 1 @ 2 1K_0402_5%

<16> PCH_CPU_BCLK_P PCH_CPU_BCLK_N BCLKP CFG_0
<16> PCH_CPU_BCLK_N A32 BN27 CFG2 RC8 1 2 1K_0402_5%
BCLKN CFG_1 BN26 CFG2 CFG4 RC9 1 2 1K_0402_5%
PCH_CPU_PCIBCLK_P D35 CFG_2 BN28 CFG5 RC10 1 @ 2 1K_0402_5%
<16> PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N PCI_BCLKP CFG_3
<16> PCH_CPU_PCIBCLK_N C36 BR20 CFG4 CFG6 RC11 1 @ 2 1K_0402_5%
PCI_BCLKN CFG_4 BM20 CFG5 CFG7 RC12 1 @ 2 1K_0402_5%
PCH_CPU_24M_CLK_P E31 CFG_5 BT20 CFG6
<16> PCH_CPU_24M_CLK_P PCH_CPU_24M_CLK_N CLK24P CFG_6
571391_CFL_H_PDG_Rev0p5 <16> PCH_CPU_24M_CLK_N D31 BP20 CFG7
CLK24N CFG_7 BR23
1. The total Length of Data and Clock (from CPU to each VR) must be equal (± 0.1 inch).
2. Route the Alert signal between the Clock and the Data signals. CFG_8 BR22
1 1
3. Place those resistors close CPU side. CFG_9 BT23 The CFG signals have a default value of '1' if not terminated on the board.
CFG_10 BT22 CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted
CFG_11 BM19 * 1 = (Default) Normal Operation;
CFG_12 BR19 0 = Stall.
Sensitive CFG_13 BP19 CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.
CPU_SVID_ALERT# BH31 CFG_14 BT19 1 = Normal operation
CPU_SVID_CLK BH32 VIDALERT# CFG_15 * 0 = Lane numbers reversed.
<56,57> CPU_SVID_CLK CPU_SVID_DAT VIDSCK CFG[4]: eDP enable:
BH29 BN23
H_PROCHOT#_R BR30 VIDSOUT CFG_17 BP23 1 = Disabled.
PROCHOT# CFG_16 BP22 * 0 = Enabled.
DDR_PG_CTRL BT13 CFG_19 BN22 CFG[6:5]: PCI Express* Bifurcation:
DDR_VTT_CNTL CFG_18 00 = 1 x8, 2 x4 PCI Express*
01 = reserved
XDP_BPM#0 10 = 2 x8 PCI Express*
BR27 TC1 TP@ 11 = 1 x16 PCI Express*
BPM#_0 BT27 XDP_BPM#1 *
Sensitive BPM#_1 TC2 TP@
BM31 XDP_BPM#2 CFG[7]: PEG Training:
BPM#_2 TC3 TP@
EC_VCCST_PG H13 BT30 XDP_BPM#3 * 1 = (default) PEG Train immediately following RESET# de assertion.
VCCST_PWRGD BPM#_3 TC4 TP@ 0 = PEG Wait for BIOS for training.
H_CPUPW RGD BT31 *CFG Pin Use CMC debug on DDX03 R02 Schematic.
<19> H_CPUPW RGD H_PLTRST_CPU# PROCPWRGD CPU_XDP_TDO
<18> H_PLTRST_CPU# BP35 BT28
H_PM_SYNC_R BM34 RESET# PROC_TDO BL32 CPU_XDP_TDI CPU_XDP_TDO <19>
<18> H_PM_SYNC_R H_PM_DOW N PM_SYNC PROC_TDI CPU_XDP_TMS CPU_XDP_TDI <19>
BP31 BP28
H_PECI PM_DOWN PROC_TMS CPU_XDP_TCK0 CPU_XDP_TMS <19>
BT34 BR28
<18,39> H_PECI H_THERMTRIP# PECI PROC_TCK CPU_XDP_TCK0 <19> To be confirm
RC17 1 @ 2 0_0402_5% J31
<18> PCH_THERMTRIP#_R THERMTRIP# CPU_XDP_TRST#
BP30
PROC_TRST# XDP_PREQ# CPU_XDP_TRST# <22>
TP@ TC5 SKTOCC# BR33 BL30 TC19 TP@
BN1 SKTOCC# PROC_PREQ# BP27 XDP_PRDY#
PROC_SELECT# PROC_SELECT# PROC_PRDY# TC20 TP@
2
should be unconnected on CFL processor CATERR# BM30 2
TP@ TC6
EDS1.2 8/21 CATERR# BT25 CFG_RCOMP 1 RC18 2 49.9_0402_1% XDP_PREQ#
CFG_RCOMP XDP_PRDY# XDP_PREQ# <22>
AT13
XEMC@ AW13 ZVM# XDP_PRDY# <22>
0.1U_0402_10V6K 1 2 CC65 H_CPUPW RGD MSM# Trace Width/Space: 4 mil/ 12 mil
AU13 Max Trace Length: 600 mil
EMC@ AY13 RSVD1
1000P_0402_50V7K 1 2 CC66 H_PROCHOT#_R RSVD2
5 OF 13
XEMC@ +1.05VS_VCCSTG
0.1U_0402_10V6K 1 2 CC67 H_THERMTRIP# CFL-H_BGA1440 Place to CPU side
EMC@ RC76 2 CMC@ 1 51_0402_5% CPU_XDP_TMS
1000P_0402_50V7K 1 2 CC68 EC_VCCST_PG
RC77 2 CMC@ 1 51_0402_5% CPU_XDP_TDI
RC78 2 CMC@ 1 51_0402_5% CPU_XDP_TDO

Near CPU side
follow 1050 Request +3VS Place to CPU side
+1.2V_VDDQ
8/21 RC79 2 CMC@ 1 51_0402_5% CPU_XDP_TCK0
1
+1.05V_VCCST
RH1 1 2 1K_0402_5% H_THERMTRIP# RC23 RC80 2 @ 1 51_0402_5% PCH_JTAG_TCK1
CC69 PCH_JTAG_TCK1 <19>
UC3 330K_0402_5%
1 5 2 1 RC81 2 @ 1 51_0402_5% CPU_XDP_TRST#
NC VCC
2
DDR_PG_CTRL 2 0.1U_0402_10V6K
A 4 SM_PG_CTRL
Y SM_PG_CTRL <52>
3
3 +1.05VS_VCCSTG GND 3
PU 330K follow CRB
74AUP1G07GW _TSSOP5
8/21
1
RC21
1K_0402_5%
SVID
2
RC14 1 2 499_0402_1% H_PROCHOT#_R

<39,50> H_PROCHOT#
+1.05V_VCCST
+1.05V_VCCST
1
RC22
1K_0402_5%
RC19 RC20
56_0402_1% 100_0402_1%
2
RC15 1 2 60.4_0402_1% EC_VCCST_PG

<39,47> EC_VCCST_PG_R
RC16 1 2 20_0402_5% H_PM_DOW N RC13 1 2 220_0402_5% CPU_SVID_ALERT#

<18> H_PM_DOW N_R <56,57> CPU_SVID_ALERT#_R
4 4
1
CPU_SVID_DAT
<56,57> CPU_SVID_DAT
RH2
@ 13_0402_5%
2
2017/12/18
Compal Secret Data
2018/09/01 Title
CFL-H(5/8)CFG,SVID
Custom

A B C D E
A B C D E
GT
32000mA(Hexa Core GT2) +VCC_CORE +VCC_CORE +VCC_CORE CFL-H +VCC_CORE
+VCC_GT CFL-H +VCC_GT CFL-H UC1J
UC1K UC1I
AT14
VCCGT1 VCCGT80
BD35 AA13
VCC1 VCC64
AH13 128000mA(Hexa Core GT2) K14
VCC1 VCC64
W35
AT31 BD36 AA31 AH14 L13 W36
AT32 VCCGT2 VCCGT81 BE31 AA32 VCC2 VCC65 AH29 L14 VCC2 VCC65 W37
AT33 VCCGT3 VCCGT82 BE32 AA33 VCC3 VCC66 AH30 N13 VCC3 VCC66 W38
AT34 VCCGT4 VCCGT83 BE33 AA34 VCC4 VCC67 AH31 N14 VCC4 VCC67 Y29
AT35 VCCGT5 VCCGT84 BE34 AA35 VCC5 VCC68 AH32 N30 VCC5 VCC68 Y30
AT36 VCCGT6 VCCGT85 BE35 AA36 VCC6 VCC69 AJ14 N31 VCC6 VCC69 Y31
1 1
AU14 VCCGT9 VCCGT88 BE38 AB29 VCC9 VCC72 AJ31 N36 VCC9 VCC72 Y34
AU29 VCCGT10 VCCGT89 BF13 AB30 VCC10 VCC73 AJ32 N37 VCC10 VCC73 Y35
AU30 VCCGT11 VCCGT90 BF14 AB31 VCC11 VCC74 AJ33 N38 VCC11 VCC74 Y36
AU31 VCCGT12 VCCGT91 BF29 AB32 VCC12 VCC75 AJ34 P13 VCC12 VCC75
AU32 VCCGT13 VCCGT92 BF30 AB35 VCC13 VCC76 AJ35 P14 VCC13
AU35 VCCGT14 VCCGT93 BF31 AB36 VCC14 VCC77 AJ36 P29 VCC14
AU36 VCCGT15 VCCGT94 BF32 AB37 VCC15 VCC78 AK31 P30 VCC15
AU37 VCCGT16 VCCGT95 BF35 AB38 VCC16 VCC79 AK32 P31 VCC16
AU38 VCCGT17 VCCGT96 BF36 AC13 VCC17 VCC80 AK33 P32 VCC17
AV29 VCCGT18 VCCGT97 BF37 AC14 VCC18 VCC81 AK34 P33 VCC18
AV30 VCCGT19 VCCGT98 BF38 AC29 VCC19 VCC82 AK35 P34 VCC19
AV31 VCCGT20 VCCGT99 BG29 AC30 VCC20 VCC83 AK36 P35 VCC20
AV32 VCCGT21 VCCGT100 BG30 AC31 VCC21 VCC84 AK37 P36 VCC21
AV33 VCCGT22 VCCGT101 BG31 AC32 VCC22 VCC85 AK38 R13 VCC22
AV34 VCCGT23 VCCGT102 BG32 AC33 VCC23 VCC86 AL13 R31 VCC23
AW14 VCCGT26 VCCGT105 BG35 AC36 VCC26 VCC89 AL31 R34 VCC26
AW31 VCCGT27 VCCGT106 BG36 AD13 VCC27 VCC90 AL32 R35 VCC27
AW32 VCCGT28 VCCGT107 BH33 AD14 VCC28 VCC91 AL35 R36 VCC28
AW35 VCCGT31 VCCGT110 BH36 AD33 VCC31 VCC94 AL38 T29 VCC31
AW36 VCCGT32 VCCGT111 BH37 AD34 VCC32 VCC95 AM13 T30 VCC32
AW37 VCCGT33 VCCGT112 BH38 AD35 VCC33 VCC96 AM14 T31 VCC33
AW38 VCCGT34 VCCGT113 BJ16 AD36 VCC34 VCC97 AM29 T32 VCC34
AY29 VCCGT35 VCCGT114 BJ17 AD37 VCC35 VCC98 AM30 T35 VCC35
AY30 VCCGT36 VCCGT115 BJ19 AD38 VCC36 VCC99 AM31 T36 VCC36
2 AY31 VCCGT37 VCCGT116 BJ20 AE13 VCC37 VCC100 AM32 T37 VCC37 2
AY32 VCCGT38 VCCGT117 BJ21 AE14 VCC38 VCC101 AM33 T38 VCC38
AY35 VCCGT39 VCCGT118 BJ23 AE30 VCC39 VCC102 AM34 U29 VCC39
AY38 VCCGT42 VCCGT121 BJ27 AE35 VCC42 VCC105 AN13 U32 VCC42
BA13 VCCGT43 VCCGT122 BJ37 AE36 VCC43 VCC106 AN14 U33 VCC43
BA14 VCCGT44 VCCGT123 BJ38 AE37 VCC44 VCC107 AN31 U34 VCC44
BA29 VCCGT45 VCCGT124 BK16 AE38 VCC45 VCC108 AN32 U35 VCC45
BA30 VCCGT46 VCCGT125 BK17 AF29 VCC46 VCC109 AN33 U36 VCC46
BA31 VCCGT47 VCCGT126 BK19 AF30 VCC47 VCC110 AN34 V13 VCC47
BA36 VCCGT52 VCCGT131 BK26 AF35 VCC52 VCC115 AP13 V34 VCC52
BB13 VCCGT53 VCCGT132 BK27 AF36 VCC53 VCC116 AP30 V35 VCC53
BB14 VCCGT54 VCCGT133 BL15 AF37 VCC54 VCC117 AP31 V36 VCC54
BB31 VCCGT55 VCCGT134 BL16 AF38 VCC55 VCC118 AP32 V37 VCC55
BB32 VCCGT56 VCCGT135 BL17 AG14 VCC56 VCC119 AP35 V38 VCC56
BB33 VCCGT57 VCCGT136 BL23 AG31 VCC57 VCC120 AP36 W13 VCC57
BB36 VCCGT60 VCCGT139 BL26 AG34 VCC60 VCC123 K13 W30 VCC60
BB37 VCCGT61 VCCGT140 BL27 AG35 VCC61 VCC124 W31 VCC61
BB38 VCCGT62 VCCGT141 BL28 AG36 VCC62 W32 VCC62 10 OF 13
BC29 VCCGT63 VCCGT142 BL36 VCC63 VCC63
BC30 VCCGT64 VCCGT143 BL37 CFL-H_BGA1440
BC31 VCCGT65 VCCGT144 BM15
3 BC32 VCCGT66 VCCGT145 BM16 AG37 VCCSENSE 3
VCCGT67 VCCGT146 VCC_SENSE VCCSENSE <56>
BC35 BM17 9 OF 13 AG38 VSSSENSE
VCCGT68 VCCGT147 VSS_SENSE VSSSENSE <56>
BC36 BM36
BC37 VCCGT69 VCCGT148 BM37 CFL-H_BGA1440
BC38 VCCGT70 VCCGT149 BN15
VCCGT71 VCCGT150
1. Vcc_SENSE/ Vss_SENSE Trace Length Match < 25 mils
BD13 BN16 2. Maintain 25-mil separation distance away from any other dynamic signals.
BD14 VCCGT72 VCCGT151 BN17
BD32 VCCGT76 VCCGT155 BP15
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
BR15 VCCGT160 VCCGT165 BT16
VCCGT163 VCCGT168
AH37 VSSGT_SENSE
11 OF VSSGT_SENSE VSSGT_SENSE <56>
13 AH38 VCCGT_SENSE
VCCGT_SENSE VCCGT_SENSE <56>
CFL-H_BGA1440
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils
2. Maintain 25-mil separation distance away from any other dynamic signals.
4 4
2017/12/18
Compal Secret Data
2018/09/01 Title
CFL-H(6/8)VCC_CORE/GT
Custom

A B C D E
A B C D E
+1.2V_VDDQ_CPU
Max: 3300mA
+VCC_SA CFL-H +1.2V_VDDQ_CPU +1.2V_VDDQ_CPU +1.2V_VDDQ +1.2V_VDDQ_CPU

UC1L 3.3A
@ JPC1
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
+VCC_SA J30 AA6 1 2
VCCSA1 VDDQ1 1 2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
Max: 11100mA K29 AE12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
K30 VCCSA2 VDDQ2 AF5 JUMP_43X118
VCCSA3 VDDQ3
CC70
CC71
CC72
CC73
CC74
CC75
CC76
CC77
CC78
CC79
CC80
CC81
CC82
CC83
CC84
CC85
K31 AF6
K32 VCCSA4 VDDQ4 AG5 @ JPC2
K33 VCCSA5 VDDQ5 AG9 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1
K34 VCCSA6 VDDQ6 AJ12 1 2
K35 VCCSA7 VDDQ7 AL11 JUMP_43X118
L31 VCCSA8 VDDQ8 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12 571483_CFL_H_RVP_CRB_TDK_Rev0p5
L36 VCCSA11 VDDQ11 AR6 +1.2V_VDDQ_CPU: 10uF * 12 22uF * 4
L37 VCCSA12 VDDQ12 AT12
VCCSA13 VDDQ13 PLACE CAP BACKSIDE
L38 AW6
M29 VCCSA14 VDDQ14 AY6
M30 VCCSA15 VDDQ15 J5
M31 VCCSA16 VDDQ16 J6
M32 VCCSA17 VDDQ17 K12 +1.2V_VDDQ +1.2V_VCCPLL_OC
M33 VCCSA18 VDDQ18 K6 +VCCIO
M34 VCCSA19 VDDQ19 L12 RC24 1 @ 2 0_0402_5%
+VCC_IO M35 VCCSA20 VDDQ20 L6
Max: 6400mA VCCSA21 VDDQ21
1U_0201_6.3V6M
1U_0201_6.3V6M
M36 R6
VCCSA22 VDDQ22
10U_0402_6.3V6M
T6 1 1
+VCCIO VDDQ23
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
W6 1 1 1 1 @
VDDQ24
CC86
CC87
Y12
VDDQ25
CC88
CC89
CC90
CC91
AG12
G15 VCCIO1 +1.2V_VCCPLL_OC 2 2
G17 VCCIO2 +1.2V_VCCPLL_OC 2 2 2 2
G19 VCCIO3 BH13 Max: 130mA
G21 VCCIO4 VCCPLL_OC1 BJ13
H15 VCCIO5 VCCPLL_OC2 G11 +1.05V_VCCST
H16 VCCIO6 VCCPLL_OC3
H17 VCCIO7 H30 Max: 60mA +1.05VS_VCCSTG
H19 VCCIO8 VCCST 571483_CFL_H_RVP_CRB_TDK_Rev0p5 571483_CFL_H_RVP_CRB_TDK_Rev0p5
2 H20 VCCIO9 H29 Max: 20mA +1.2V_VCCPLL_OC: 1uF * 2 +0.95VS_VCCIO: 10uF * 12 22uF * 4 2
H21 VCCIO10 VCCSTG2
VCCIO11 +1.05V_VCCSFR
PLACE CAP BACKSIDE
H26 G30
H27 VCCIO12 VCCSTG1
J15 VCCIO13 H28 Max: 150mA
J16 VCCIO14 VCCPLL1 J28
J17 VCCIO15 VCCPLL2
J19 VCCIO16 +1.05V_VCCST +1.05V_VCCSFR
J20 VCCIO17 M38 VCCSA_SENSE
VCCIO18 VCCSA_SENSE VSSSA_SENSE VCCSA_SENSE <57>
J21 M37 RC25 1 @ 2 0_0402_5%
VCCIO19 VSSSA_SENSE VSSSA_SENSE <57>
J26 150mA
VCCIO20 VCCIO_SENSE
1U_0201_6.3V6M
1U_0201_6.3V6M
J27 H14
VCCIO21 VCCIO_SENSE VSSIO_SENSE VCCIO_SENSE <55>
J14 1 1
12 OF 13 VSSIO_SENSE VSSIO_SENSE <55>
CC92
CC93
CFL-H_BGA1440
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils 2 2
2. Maintain 25-mil separation distance away from any other dynamic signals.
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCST: 1uF * 1 571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05V_VCCSFR: 1uF * 1
PLACE CAP BACKSIDE PLACE CAP BACKSIDE
+1.05VS_VCCSTG
3 3
1U_0201_6.3V6M
1
CC94
2
571483_CFL_H_RVP_CRB_TDK_Rev0p5
+1.05VS_VCCSTG: 1uF * 1
4 4
2017/12/18
Compal Secret Data
2018/09/01 Title
CFL-H(7/8)VCCSA/VCCIO/VDDQ
Custom

A B C D E
A B C D E
CFL-H
CFL-H CFL-H UC1H CFL-H
UC1F UC1G BN4 F15 UC1M
A10 AK4 AW5 BJ15 BN7 VSS_325 VSS_409 F17
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BP12 VSS_326 VSS_410 F19
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP14 VSS_327 VSS_411 F2 E2
VSS_3 VSS_84 VSS_165 VSS_246 VSS_328 VSS_412 Impedance Spectrum Tool Trigger TP@ TC7
IST_TRIG E3 RSVD_TP5
A18 AL14 AY34 BJ25 BP18 F21 TP@ TC8
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 BP21 VSS_329 VSS_413 F23 E1 IST_TRIG
VSS_5 VSS_86 VSS_167 VSS_248 VSS_330 VSS_414 TP@ TC9 RSVD_TP4
A22 AL34 BA10 BJ30 BP24 F25 TP@ TC10 D1
A24 VSS_6 VSS_87 AL4 BA11 VSS_168 VSS_249 BJ31 BP25 VSS_331 VSS_415 F27 RSVD_TP3
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP26 VSS_332 VSS_416 F29 BR1 BK28
VSS_8 VSS_89 VSS_170 VSS_251 VSS_333 VSS_417 TP@ TC11 RSVD_TP1 RSVD11
1 A28 AL8 BA37 BJ33 BP29 F3 TP@ TC12 BT2 BJ28 1
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP33 VSS_334 VSS_418 F31 RSVD_TP2 RSVD10
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP34 VSS_335 VSS_419 F36 BN35
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP7 VSS_336 VSS_420 F4 RSVD15
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BR12 VSS_337 VSS_421 F5 J24
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR14 VSS_338 VSS_422 F8 H24 RSVD28
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR18 VSS_339 VSS_423 F9 BN33 RSVD27
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR21 VSS_340 VSS_424 G10 BL34 RSVD14
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR24 VSS_341 VSS_425 G12 RSVD13
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR25 VSS_342 VSS_426 G14 N29
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR26 VSS_343 VSS_427 G16 R14 RSVD30
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR29 VSS_344 VSS_428 G18 AE29 RSVD31
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR34 VSS_345 VSS_429 G20 AA14 RSVD2
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR36 VSS_346 VSS_430 G22 AP29 RSVD1
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR7 VSS_347 VSS_431 G23 AP14 RSVD5
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BT12 VSS_348 VSS_432 G24 A36 RSVD4
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT14 VSS_349 VSS_433 G26 VSS_A36
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT18 VSS_350 VSS_434 G28 A37
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT21 VSS_351 VSS_435 G4 VSS_A37
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT24 VSS_352 VSS_436 G5 PCH_TRIGOUT_R H23
VSS_28 VSS_109 VSS_190 VSS_271 VSS_353 VSS_437 <22> PCH_TRIGOUT_R CPU_TRIGOUT PROC_TRIGIN
AD11 AP8 BC6 BL33 BT26 G6 RC26 1 2 30_0402_5% J23
VSS_29 VSS_110 VSS_191 VSS_272 VSS_354 VSS_438 <22> CPU_TRIGOUT_R PROC_TRIGOUT
AD12 AP9 BD10 BL35 BT29 G8
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT32 VSS_355 VSS_439 G9 F30
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT5 VSS_356 VSS_440 H11 RSVD24
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 C11 VSS_357 VSS_441 H12
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C13 VSS_358 VSS_442 H18 E30
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C15 VSS_359 VSS_443 H22 RSVD23
AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C17 VSS_360 VSS_444 H25
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C19 VSS_361 VSS_445 H32 B30 BL31
2 AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C21 VSS_362 VSS_446 H35 C30 RSVD7 RSVD12 AJ8 2
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C23 VSS_363 VSS_447 J10 RSVD21 RSVD3 G13
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C25 VSS_364 VSS_448 J18 RSVD25
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C27 VSS_365 VSS_449 J22 G3
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C29 VSS_366 VSS_450 J25 J3 RSVD26 C38
VSS_42 VSS_123 VSS_204 VSS_285 VSS_367 VSS_451 RSVD29 RSVD22 TC13 TP@
AF2 AR36 BE4 BM25 C31 J32 C1 TC14 TP@
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C37 VSS_368 VSS_452 J33 RSVD20 BR2
VSS_44 VSS_125 VSS_206 VSS_287 VSS_369 VSS_453 RSVD17 TC15 TP@
AF4 AR38 BE6 BM27 C5 J36 BR35 BP1 TC16 TP@
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C8 VSS_370 VSS_454 J4 BR31 RSVD19 RSVD16 B38
VSS_46 VSS_127 VSS_208 VSS_289 VSS_371 VSS_455 RSVD18 RSVD8 TC17 TP@
AG11 AR5 BF33 BM29 C9 J7 BH30 B2 TC18 TP@
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 D10 VSS_372 VSS_456 K1 RSVD9 RSVD6
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D12 VSS_373 VSS_457 K10 13 OF 13
VSS_49 VSS_130 VSS_211 VSS_292 VSS_374 VSS_458 Add for Corner NCTF testing
AG30 AT6 BG12 BM35 D14 K11
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D16 VSS_375 VSS_459 K2 CFL-H_BGA1440
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D18 VSS_376 VSS_460 K3
AG8 VSS_52 VSS_133 AU12 BG37 VSS_214 VSS_295 BM6 D20 VSS_377 VSS_461 K38
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D22 VSS_378 VSS_462 K4
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D24 VSS_379 VSS_463 K5
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D26 VSS_380 VSS_464 K7
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D28 VSS_381 VSS_465 K8
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D3 VSS_382 VSS_466 K9
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D30 VSS_383 VSS_467 L29
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D33 VSS_384 VSS_468 L30
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D6 VSS_385 VSS_469 L33
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D9 VSS_386 VSS_470 L34
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 E34 VSS_387 VSS_471 M12
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E35 VSS_388 VSS_472 M13
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E38 VSS_389 VSS_473 N10
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E4 VSS_390 VSS_474 N11
3 AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E9 VSS_391 VSS_475 N12 3
AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 N3 VSS_392 VSS_476 N2
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N33 VSS_393 VSS_477 BT8
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N34 VSS_394 VSS_478 BR9
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N4 VSS_395 VSS_479
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N5 VSS_396 A3
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N6 VSS_397 VSS_A3 A34
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N7 VSS_398 VSS_A34 A4
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N8 VSS_399 VSS_A4 B3
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N9 VSS_400 VSS_B3 B37
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 P12 VSS_401 VSS_B37 BR38
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P37 VSS_402 VSS_BR38 BT3
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 M14 VSS_403 VSS_BT3 BT35
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M6 VSS_404 VSS_BT35 BT36
AK30 6 OF VSS_161
VSS_80 13 W34 BJ14 VSS_2427 OF VSS_323
13 T14 N1 VSS_405 VSS_BT36 BT4
VSS_81 VSS_162 VSS_243 VSS_324 F11 VSS_406 VSS_BT4 C2
CFL-H_BGA1440 CFL-H_BGA1440 F13 VSS_4078 OF 13VSS_C2 D38
VSS_408 VSS_D38
CFL-H_BGA1440
4 4
2017/12/18
Compal Secret Data
2018/09/01 Title
CFL-H(8/8)GND/RSVD
Custom

A B C D E
A B C D E
CNP-H
UH1B
DMI_CTX_PRX_N0 K34 J3 USB20_N1
<10> DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI0_RXN USB2N_1 USB20_P1 USB20_N1 <42>
<10> DMI_CTX_PRX_P0 J35 J2 USB3 MB
DMI_CRX_PTX_N0 DMI0_RXP USB2P_1 USB20_N2 USB20_P1 <42>
<10> DMI_CRX_PTX_N0 C33 N13
DMI_CRX_PTX_P0 DMI0_TXN USB2N_2 USB20_P2 USB20_N2 <41>
<10> DMI_CRX_PTX_P0 B33 N15 TYPE C
DMI_CTX_PRX_N1 DMI0_TXP USB2P_2 USB20_N3 USB20_P2 <41>
<10> DMI_CTX_PRX_N1 G33 K4
DMI_CTX_PRX_P1 DMI1_RXN USB2N_3 USB20_P3 USB20_N3 <44>
<10> DMI_CTX_PRX_P1 F34 K3
<10> DMI_CRX_PTX_N1 C32 M10 USB2 (SUB/B)
<10> DMI_CRX_PTX_P1 B32 L9
DMI_CTX_PRX_N2 DMI1_TXP USB2P_4 USB20_N5 USB20_P4 <44>
<10> DMI_CTX_PRX_N2 K32 M1
DMI_CTX_PRX_P2 DMI2_RXN USB2N_5 USB20_P5 USB20_N5 <33>
<10> DMI_CTX_PRX_P2 J32 L2 Camera
<10> DMI_CRX_PTX_N2 C31 K7
1 <10> DMI_CRX_PTX_P2 B31 K6 TS 1
DMI_CTX_PRX_N3 DMI2_TXP USB2P_6 USB20_P6 <33>
<10> DMI_CTX_PRX_N3 G30 L4
DMI_CTX_PRX_P3 F30 DMI3_RXN USB2N_7 L3 +3VALW _PCH_PRIM
<10> DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI3_RXP USB2P_7 USB20_N8
<10> DMI_CRX_PTX_N3 C29 G4
<10> DMI_CRX_PTX_P3 B29 G5 FingerPrint RPH1
DMI3_TXP USB2P_8 USB20_P8 <46> USB_OC0#
A25 M6 8 1
B25 RSVD USB2N_9 N8 USB_OC1# 7 2
P24 RSVD USB2P_9 H3 USB_OC2# 6 3
R24 RSVD USB2N_10 H2 USB_OC3# 5 4
C26 RSVD USB2P_10 R10
B26 RSVD USB2N_11 P9 10K_0804_8P4R_5%
F26 RSVD USB2P_11 G1
G26 RSVD USB2N_12 G2
B27 RSVD USB2P_12 N3
C27 RSVD USB2N_13 N2
L26 RSVD USB2P_13 E5 USB20_N14
RSVD USB2N_14 USB20_P14 USB20_N14 <37>
M26 F6 BT FOR CNVI follow 571906_CNL_PCH_TA_WW11.pdf
RSVD USB2P_14 USB20_P14 <37>
D29
E28 RSVD AH36 USB_OC0#
RSVD GPP_E9/USB2_OC0# USB_OC1# USB_OC0# <40>
K29 AL40 USB_OC1# <42>
M29 RSVD GPP_E10/USB2_OC1# AJ44 USB_OC2#
RSVD GPP_E11/USB2_OC2# AL41 USB_OC3# +3VALW
G17 GPP_E12/USB2_OC3# AV47
F16 PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# AR35
A17 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# AR37
1
B17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AV43
R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
PCIE2_RXN/USB31_8_RXN USB2_RCOMP RH3
P21 F4 RH4 1 2 113_0402_1%
PCIE2_RXP/USB31_8_RXP USB2_COMP USB2_VBUS_SENSE 10K_0402_5%
B18 F3 RH5 1 @ 2 0_0402_5%
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13
2
2 GPD_7 2
K18 PCIE2_TXP/USB31_8_TXP RSVD1 G3 USB2_ID 1 2 0_0402_5%
PCIE3_RXN/USB31_9_RXN USB2_ID
RH6 @ STRAP
J18
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD_7
1
C19 PCIE3_TXN/USB31_9_TXN GPD7
PCIE3_TXP/USB31_9_TXP RH7
N18 G45
PCIE4_RXN/USB31_10_RXN PCIE24_TXP 10K_0402_5%
R18 G46
PCIE4_RXP/USB31_10_RXP PCIE24_TXN @
D20 Y41
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40
2
F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48
PCIE5_RXN PCIE23_TXP X'tal Input:
G20 G49 High: Differential
B21 PCIE5_RXP PCIE23_TXN W44 Low: Single ended
A22 PCIE5_TXN PCIE23_RXP W43
K21 PCIE5_TXP PCIE23_RXN H48
J21 PCIE6_RXN PCIE22_TXP H47
D21 PCIE6_RXP PCIE22_TXN U41
C21 PCIE6_TXN PCIE22_RXP U40 The 30 HSIO lanes on PCH-H supports the following configurations:
B23 PCIE6_TXP PCIE22_RXN F46 1. Up to 24 PCIe* Lanes
C23 PCIE7_TXP PCIE21_TXP G47
— A maximum of 16 PCIe* Ports (or devices) can be enabled
PCIE7_TXN PCIE21_TXN ‧ When a GbE Port is enabled, the maximum number of PCIe* Ports (or
J24 R44 devices) that can be enabled reduces based off the following:
L24 PCIE7_RXP PCIE21_RXP T43 Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
F24 PCIE7_RXN PCIE21_RXN — PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
G24 PCIE8_RXN Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
PCIE8_RXP 21-24 (PCIe* Controller #6) can be individually configured
B24 2. Up to 6 SATA Lanes
C24 PCIE8_TXN 2 OF 13 — A maximum of 6 SATA Ports (or devices) can be enabled
PCIE8_TXP — SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
Rev1.0 — SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19
CNP-H_BGA874 3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled
4. Up to 4 GbE Lanes
3 — A maximum of 1 GbE Port (or device) can be enabled 3
5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
devices
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “ PC I Express * (PCIe*) ” chapt er f or t he P CH PCI e* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support
6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.
4 4
2017/12/18
Compal Secret Data
2018/09/01 Title
PCH(1/8)DMI/PCIE/USB2
Custom

A B C D E
A B C D E
PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf CNP-H
XTAL_24M_PCH_OUT XTAL_24M_PCH_OUT_R
remove TP as C5PRH UH1G
1 EMC@ 2 BE33
RH11 33_0402_1% GPP_A16/CLKOUT_48
PCH_CPU_24M_CLK_P D7 Y3
<11> PCH_CPU_24M_CLK_P PCH_CPU_24M_CLK_N CLKOUT_CPUNSSC_P CLKOUT_ITPXDP# TP@ TH2
C6 Y4 TP@ TH3
XTAL_24M_PCH_IN 1 EMC@ 2 XTAL_24M_PCH_IN_R <11> PCH_CPU_24M_CLK_N CLKOUT_CPUNSSC# CLKOUT_ITPXDP_P
1 2
RH8 1M_0402_5% RH9 33_0402_1% PCH_CPU_BCLK_P B8 B6 PCH_CPU_PCIBCLK_N
<11> PCH_CPU_BCLK_P PCH_CPU_BCLK_N CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK# PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N <11>
C8 A6
<11> PCH_CPU_BCLK_N CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK_P <11>
YH1
24MHZ_18PF_XRCGB24M000F2P51R0 XTAL_24M_PCH_OUT_R U9 AJ6 CLK_PEG_VGA#
XTAL_24M_PCH_IN_R XTAL_OUT CLKOUT_PCIE_N0 CLK_PEG_VGA CLK_PEG_VGA# <25>
1 U10 AJ7 DGPU 1
XTAL_IN CLKOUT_PCIE_P0 CLK_PEG_VGA <25>
3 1
3 1 XCLK_BIASREF CLK_PCIE_LAN#
33P_0402_50V8J
18P_0402_50V8J
RH10 1 2 60.4_0402_1% T3 AH9
NC NC XCLK_BIASREF CLKOUT_PCIE_N1 CLK_PCIE_LAN CLK_PCIE_LAN# <36>
AH10 GLAN
PCH_RTCX1 CLKOUT_PCIE_P1 CLK_PCIE_LAN <36>
CH5
CH6
XCLK_BIASREF (PDG) BA49
4 2 Trace Width/Space: 15mil /15 mil PCH_RTCX2 BA48 RTCX1 AE14 CLK_PCIE_W LAN#
Max Trace Length: 1000 mil RTCX2 CLKOUT_PCIE_N2 CLK_PCIE_W LAN CLK_PCIE_W LAN# <37>
8/24 AE15 NGFF WL+BT(KEY E)
VGA_CLKREQ# CLKOUT_PCIE_P2 CLK_PCIE_W LAN <37>
BF31
LAN_CLKREQ# BE31 GPP_B5/SRCCLKREQ0# AE6 CLK_PCIE_NGFF#
<36> LAN_CLKREQ# W LAN_CLKREQ# GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CLK_PCIE_NGFF CLK_PCIE_NGFF# <35>
<37> W LAN_CLKREQ# AR32 AE7 M2 SSD
SSD_CLKREQ# GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_NGFF <35>
<35> SSD_CLKREQ# BB30
BA30 GPP_B8/SRCCLKREQ3# AC2
PCH_RTCX1 AN29 GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 AC3
AE47 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4
PCH_RTCX2 AC48 GPP_H0/SRCCLKREQ6# AB2
AE41 GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 AB3
1 2 AF48 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5
RH12 10M_0402_5% AC41 GPP_H3/SRCCLKREQ9# W4
remove no use srcclkreq AC39 GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 W3
AE39 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6
AB48 GPP_H6/SRCCLKREQ12# W7
YH2
1 2 AC44 GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 W6
AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7
GPP_H9/SRCCLKREQ15#
10P_0402_50V8J
10P_0402_50V8J
1 1 AC14
V2 CLKOUT_PCIE_N8 AC15
32.768KHZ_9PF_X1A000141000200
V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8
CLKOUT_PCIE_P15
CH7
CH8
U2
2 2 T2 CLKOUT_PCIE_N9 U3
T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9
2 CLKOUT_PCIE_P14 AC9 2
Trace Space: 15 mil AA1 CLKOUT_PCIE_N10 AC11
Max Trace Length: 1000 mil Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
CLKOUT_PCIE_P13 AE9
use same part w C5MMH AC7 CLKOUT_PCIE_N11 AE11
+3VS CLKOUT_PCIE_N12 CLKOUT_PCIE_P11
AC6
CLKOUT_PCIE_P12 7 OF 13 R6 REFCLK_CNV
CLKIN_XTAL REFCLK_CNV <37>
CNP-H_BGA874 Rev1.0
1
RPH2
8 1 LAN_CLKREQ# RH14
7 2 VGA_CLKREQ# 10K_0402_5%
W LAN_CLKREQ# VGA_CLKREQ# <25>
6 3
5 4 SSD_CLKREQ#
2
10K_0804_8P4R_5%
CNP-H
UH1M
AW13 BD4 CLK_CNV_PRX_DTX_N

GPP_G0/SD_CMD CNV_WR_CLKN CLK_CNV_PRX_DTX_P CLK_CNV_PRX_DTX_N <37>
For DDX03 R02 BE9 BE3 CLK_CNV_PRX_DTX_P <37>
BF8 GPP_G1/SD_DATA0 CNV_WR_CLKP
BF9 GPP_G2/SD_DATA1 BB3 CNV_PRX_DTX_N0
XTAL Frequency Select GPP_G3/SD_DATA2 CNV_WR_D0N CNV_PRX_DTX_P0 CNV_PRX_DTX_N0 <37>
BG8 BB4
+1.8VALW _PRIM GPP_G4/SD_DATA3 CNV_WR_D0P CNV_PRX_DTX_N1 CNV_PRX_DTX_P0 <37>
remove SD signal from PCH BE8 BA3
GPP_G5/SD_CD# CNV_WR_D1N CNV_PRX_DTX_P1 CNV_PRX_DTX_N1 <37>
BD8 BA2
GPP_G6/SD_CLK CNV_WR_D1P CNV_PRX_DTX_P1 <37>
AV13
GPP_G7/SD_WP BC5 CLK_CNV_PTX_DRX_N
3 CNV_BRI_PTX_DRX CNV_WT_CLKN CLK_CNV_PTX_DRX_P CLK_CNV_PTX_DRX_N <37> 3
RH15 1 2 4.7K_0402_5% AP3 BB6 CLK_CNV_PTX_DRX_P <37>
AP2 GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP
AN4 GPP_I12/M2_SKT2_CFG1 BE6 CNV_PTX_DRX_N0
This signal has a weak internal pull-down 20K. STRAP GPP_I13/M2_SKT2_CFG2 3.3V CNV_WT_D0N CNV_PTX_DRX_N0 <37>
AM7 BD7 CNV_PTX_DRX_P0
0 = 38.4/19.2MHz XTAL frequency selected.
1 = 24MHz XTAL frequency selected. (DDX03)
remove CPU_C10_GATE# GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P BG6 CNV_PTX_DRX_N1 CNV_PTX_DRX_P0 <37>
CNV_WT_D1N CNV_PTX_DRX_P1 CNV_PTX_DRX_N1 <37>
Notes: AV6 BF6
1. The internal pull-down is disabled after RSMRST# GPP_J0/CNV_PA_BLANKING CNV_WT_D1P CNV_W T_RCOMP CNV_PTX_DRX_P1 <37>
AY3 BA1 RH16 1 2 150_0402_1%
de-asserts.
AR13 GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP
2. This signal is in the primary well. GPP_J11/A4WP_PRESENT PCIE_RCOMPN
AV7 B12 RH17 1 2 100_0402_1%
AW3 GPP_J10 PCIE_RCOMPN A13 PCIE_RCOMPP
AT10 GPP_J_2 1.8V PCIE_RCOMPP BE5 SD_RCOMP_1P8 RH18 1 2 200_0402_1%
+1.8VALW _PRIM CNV_BRI_PTX_DRX AV4 GPP_J_3 SD_1P8_RCOMP BE4 SD_RCOMP_3P3 RH19 1 2 200_0402_1%
VCCPSPI Select <37> CNV_BRI_PTX_DRX CNV_BRI_PRX_DTX AY2 GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP BD1
checked CRB
<37> CNV_BRI_PRX_DTX CNV_RGI_PTX_DRX GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P81 GPPJ_RCOMP_1P8 RH20 1
BA4 BE1 2 200_0402_1%
<37> CNV_RGI_PTX_DRX CNV_RGI_PRX_DTX GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82
AV3 BE2
<37> CNV_RGI_PRX_DTX GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPPJ_RCOMP_1P83
@ GPP_J9 AW2
RH21 1 2 4.7K_0402_5% GPP_J9 GPP_J8/CNV_MFUART2_RXD
AU9 Y35
The signal has a weak internal pull-down 20K GPP_J9/CNV_MFUART2_TXD RSVD2 Y36
0 = VCCPSPI is connected to 3.3V rail
STRAP RSVD3
1 = VCCPSPI is connected to 1.8V rail
Note: If VCCPSPI is connected to 1.8V rail, this pin BC1
+1.8VALW _PRIM 13 OF 13 RSVD1 AL35
strap must be a ‘ 1’ fo r th e prope r functionalit y TP@ TH4
of the SPI (Flash) I/Os TP
#571483_CFL_H_RVP_CRB_TDK_Rev0p5
CNP-H_BGA874 Rev1.0
Recommend external test point
+1.8VALW _PRIM RH181 1 CNVI@ 2 20K_0402_1% CNV_BRI_PRX_DTX
M.2 CNV Mode Select
RH182 1 CNVI@ 2 20K_0402_1% CNV_RGI_PRX_DTX
571391_CFL_H_PDG_Rev0p71
To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add
RH22 2 1 10K_0402_5% CNV_RGI_PTX_DRX a weak pull up resistor to the SoC pin with a recommended value of 20K ohm.
4 4
STRAP
RH23 2 @ 1 10K_0402_5%
An external pull-up or pull-down is required.
0 = Integrated CNVi enable.
1 = Integrated CNVi disable.
Pulled down by CRF CNVi RGI_DT pin Security Classification
2017/12/18
Compal Secret Data
2018/09/01 Title
PCH(2/8)CLK/CNVI/SD
Custom

A B C D E
A
CNP-H
UH1E
AL13
GPP_I5/DDPB_CTRLCLK AR8
no follow naming GPP_I6/DDPB_CTRLDATA
AT6 AN13
HDMI_HPD_PCH AN10 GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK AL10
<25,34> HDMI_HPD_PCH GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA
AP9 AL9
AL15 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3
can remove if no use DP GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA AN40
08/18 GPP_F23/DDPF_CTRLDATA AT49
GPP_F22/DDPF_CTRLCLK
AP41
EDP_HPD AN6 GPP_F14/PS_ON#
<25,33> EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4
remove PCH DP SCLK/SDATA M45
GPP_K23/IMGCLKOUT1 L48
GPP_K22/IMGCLKOUT0 T45
GPP_K21 T46
5 OF 13 GPP_K20 AJ47
DDP[B..F]CTRLDATA GPP_H23/TIME_SYNC0
This signal has a weak internal Pull-down. CNP-H_BGA874 Rev1.0
remove CIO_PLUG_EVENT#
0 = Port B~D is not detected. intel critical net recommend
1 = Port B,C,D is detected. (Default)
Notes: RH198 1 2 100K_0201_5%
1. The internal Pull-down is disabled after
PCH_PWROK de-asserts. CNP-H
2. This signal is in the primary well. UH1A PLT_RST# CH9 1 2 100P_0402_50V8J
1 @ 2 EC_PME#_R BE36 AV29 PLT_RST#
<36,39> EC_PME# GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# PLT_RST# <25,39,45>
RH24 0_0402_5% XEMC@
R15 Y47
R13 RSVD2 GPP_K16/GSXCLK Y46 GPIO Serial Expander (GSX) is the capability
* wait confirm CG7 RSVD1 GPP_K12/GSXDOUT provided by the PCH to expand the GPIOs
PDG P348 quad mode support PH1K CRB connect GND Y48
GPP_K13/GSXSLOAD W46 on a platform that needs more GPIOs than the
CRB PU 20k GPP_K14/GSXDIN ones provided by the PCH.
+3VALW _SPI #571182_CFL_PCH_EDS_Rev1.0 recommend 100k RH186 1 @ 2 0_0402_5% AL37 AA45
#571391_CFL_H_PDG_Rev0p71 AN35 VSS GPP_K15/GSXSRESET#
TH6 TP@ TP
RH25 2 1 1K_0402_5% PCH_SPI_IO2 PCH_SPI_SI AU41 AL47
PCH_SPI_SO BA45 SPI0_MOSI GPP_E3/CPU_GP0 AM45
RH26 2 1 1K_0402_5% PCH_SPI_IO3 PCH_SPI_CS#0 AY47 SPI0_MISO GPP_E7/CPU_GP1 BF32 TP_INT# 2 1 +3VS
PCH_SPI_CLK SPI0_CS0# GPP_B3/CPU_GP2 TYPEC_1P5A DH1 EC_TP_INT# <39,45>
AW47 BC33
SPI0_CLK GPP_B4/CPU_GP3 TYPEC_1P5A <40>
AW48 RB751V-40_SOD323-2
RH27 2 1 1K_0402_5%PCH_SPI_SI SPI0_CS1# AE44 TP_INT# RH28 2 1 100K_0402_5%
PCH_SPI_IO2 AY48 GPP_H18/SML4ALERT# AJ46
+3VALW _PCH_PRIM PCH_SPI_IO3 BA46 SPI0_IO2 GPP_H17/SML4DATA AE43
AT40 SPI0_IO3 GPP_H16/SML4CLK AC47 GPP_H15
RH29 2 1 100K_0402_5% GPP_H15 STRAP SPI0_CS2# GPP_H15/SML3ALERT# AD48
BE19 GPP_H14/SML3DATA AF47
#571182_CNL_PCH_H_EDS_V1_Rev0.7 GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK GPP_H12
External pull-up is required. Recommend 100K if pulled BF19 AB47
GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# GPP_H12 <20> +RTCVCC
up to 3.3V or 75K if pulled up to 1.8V. BF18 AD47
571007_CFL_MOW_Archive_WW22_2017 BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA AE48
STUFF R on GPP_H15 BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 SM_INTRUDER# 1M_0402_5% 2 1 RH30
GPP_D21/SPI1_IO2 INTRUDER#
CNP-H_BGA874 Rev1.0 RVP: 330K
A 1 M pull-up is used on the customer reference
1 board (CRB). This is needed to reduce leakage 1
from Coin Cell Battery in G3 state.
PCH_SPI_CLK RH195 1 @ 2 100K_0201_5%
intel critical net recommend
SPI ROM ( 16MByte )

+3VALW _SPI
+3VALW _SPI
CH10 0.1U_0201_10V6K
UH2 PCH_SPI_CS#0
1 2 1 @ 2
PCH_SPI_CS#0 1 8 RH31 4.7K_0402_5% PCH PLTRST Buffer RH32 1 @ 2 0_0402_5%
PCH_SPI_SO_0_R 2 /CS VCC 7 PCH_SPI_IO3_0_R
PCH_SPI_IO2_0_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_CLK_0_R +3VS
4 /WP(IO2) CLK 5 PCH_SPI_SI_0_R
GND DI(IO0)
W 25Q128FVSIQ_SO8 1
CH11 2
P/N: SA00005VV20 0.1U_0402_10V6K
PCH_SPI_SI_0_R RH107 1 2 49.9_0402_1% PCH_SPI_SI
5
PCH_SPI_SO_0_R RH108 1 2 49.9_0402_1% PCH_SPI_SO UH3
@ @ PCH_SPI_IO3_0_R RH109 1 2 49.9_0402_1% PCH_SPI_IO3 PLT_RST# 1
P
PCH_SPI_CLK_0_R 1 2 1 2 PCH_SPI_CLK_0_R RH110 1 2 49.9_0402_1% PCH_SPI_CLK B 4
PCH_SPI_IO2_0_R PCH_SPI_IO2 Y PLT_RST_BUF# <35,36,37>
RH111 1 2 49.9_0402_1% 2
A
G
RH33 CH12
0_0402_5% 68P_0402_50V8J sch checklist 0.7 TC7SH08FU_SSOP5
3
1 device 15 ohm / 2 device 33 ohm
note : 1050 Use 8M rom
2017/12/18
Compal Secret Data
2018/09/01 Title
PCH(3/8)DDC/SPI
Custom

A
A B C D E
#571391_CFL_H_PDG_Rev0p5
‧ eSPI clock and eSPI data mismatched: <500 mils.
‧ eSPI clock and eSPI chip select mismatched: <500 mils.
‧ eSPI signal maximum 9 Vias
* If DATA signals are entirely routed on MS, stuff the resistor with 15 Ohm.
CNP-H
UH1F
F9 BB39 LPC_AD0
<42> USB3_PTX_DRX_N1 USB31_1_TXN 1.8V GPP_A1/LAD0/ESPI_IO0 LPC_AD1 LPC_AD0 <39,45>
F7 AW37 LPC Bus check straps
<42> USB3_PTX_DRX_P1 USB31_1_TXP (eSPI) GPP_A2/LAD1/ESPI_IO1 LPC_AD2 LPC_AD1 <39,45>
USB3 MB <42> USB3_PRX_DTX_N1 D11 AV37
USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 LPC_AD3 LPC_AD2 <39,45>
<42> USB3_PRX_DTX_P1 C11 BA38 LPC : +3.3V
USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 LPC_AD3 <39,45>
C3
<41> USB3_PTX_DRX_N2 USB31_2_TXN LPC_FRAME#
D4 BE38
<41> USB3_PTX_DRX_P2 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# TPM_SERIRQ LPC_FRAME# <39,45>
1 USB3 Type C <41> USB3_PRX_DTX_N2 B9 AW35 TPM_SERIRQ <39,45> 1
C9 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# BA36 LPC_PIRQA#
<41> USB3_PRX_DTX_P2 USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39
C17 GPP_A0/RCIN#/ESPI_ALERT1# BF38 ESPI_RST#
USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST# <39>
C16
G14 USB31_6_TXP BB36 CLK_LPC RH35 2 1 22_0402_5%
USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_LPC_TPM CLK_LPC_R <39>
F14 BB34 RH36 2 TPM@ 1 22_0402_5%
USB31_6_RXP GPP_A10/CLKOUT_LPC1 CLK_LPC_TPM_R <45>
C15
<44> USB3_PTX_DRX_N5 USB31_5_TXN
B15 T48
<44> USB3_PTX_DRX_P5 USB31_5_TXP GPP_K19/SMI#
USB3 SUB <44> USB3_PRX_DTX_N5 J13 T47
K13 USB31_5_RXN GPP_K18/NMI#
<44> USB3_PRX_DTX_P5 USB31_5_RXP
G12 AH40
<41> USB3_PTX_DRX_P3 USB31_3_TXP GPP_E6/SATA_DEVSLP2 SSD_DEVSLP1
F11 AH35
<41> USB3_PTX_DRX_N3 USB31_3_TXN GPP_E5/SATA_DEVSLP1 SSD_DEVSLP1 <35>
USB3 Type C <41> USB3_PRX_DTX_P3 C10 AL48
B10 USB31_3_RXP GPP_E4/SATA_DEVSLP0 AP47
<41> USB3_PRX_DTX_N3 USB31_3_RXN GPP_F9/SATA_DEVSLP7 AN37 1A modify
C14 GPP_F8/SATA_DEVSLP6 AN46
<44> USB3_PTX_DRX_P4 USB31_4_TXP GPP_F7/SATA_DEVSLP5
B14 AR47
<44> USB3_PTX_DRX_N4 USB31_4_TXN GPP_F6/SATA_DEVSLP4
USB3 SUB <44> USB3_PRX_DTX_P4 J15 AP48
K16 USB31_4_RXP 6 OF 13 GPP_F5/SATA_DEVSLP3
<44> USB3_PRX_DTX_N4 USB31_4_RXN
+3VS
CNP-H_BGA874 Rev1.0
TPM_SERIRQ 2 1 RH37
CNP-H
1A modify 10K_0402_5%
2 UH1C 2
CL_CLK AR2 G36 PCIE_PRX_DTX_N9
TH10 TP@ CL_DATA CL_CLK PCIE9_RXN PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 <35> LPC_PIRQA#
For Intel CLINK TH11 TP@ AT5 F36 1 2 RH38
CL_RST# AU4 CL_DATA PCIE9_RXP C34 PCIE_PTX_DRX_N9 PCIE_PRX_DTX_P9 <35>
TH12 TP@ CL_RST# PCIE9_TXN PCIE_PTX_DRX_P9 PCIE_PTX_DRX_N9 <35>
M.2 SSD PCIE L3 10K_0402_5%
D34
P48 PCIE9_TXP PCIE_PTX_DRX_P9 <35>
V47 GPP_K8
V48 GPP_K9 K37 PCIE_PRX_DTX_N10
W47 GPP_K10 PCIE10_RXN J37 PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 <35>
GPP_K11 PCIE10_RXP C35 PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 <35>
PCIE10_TXN PCIE_PTX_DRX_P10 PCIE_PTX_DRX_N10 <35>
M.2 SSD PCIE L2
L47 B35
L46 GPP_K0 PCIE10_TXP PCIE_PTX_DRX_P10 <35>
U48 GPP_K1 F44 PCIE_PRX_DTX_N15
U47 GPP_K2 PCIE15_RXN/SATA2_RXN E45 PCIE_PRX_DTX_P15 PCIE_PRX_DTX_N15 <37>
GPP_K3 PCIE15_RXP/SATA2_RXP PCIE_PTX_DRX_N15 .1U_0402_16V7K PCIE_PRX_DTX_P15 <37> NGFF
N48 B40 1 2 CH1
N47 GPP_K4 PCIE_15_SATA_2_TXN C40 PCIE_PTX_DRX_P15 .1U_0402_16V7K 1 2 CH2
PCIE_PTX_C_DRX_N15 <37> WL+BT(KEY E)
P47 GPP_K5 PCIE15_TXP/SATA2_TXP PCIE_PTX_C_DRX_P15 <37>
R46 GPP_K6 L41
1A modify GPP_K7 PCIE16_RXN/SATA3_RXN M40
C36 PCIE16_RXP/SATA3_RXP B41
<35> PCIE_PTX_DRX_P11 B36 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN C41
<35> PCIE_PTX_DRX_N11 F39 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP
M.2 SSD PCIE L1 <35> PCIE_PRX_DTX_P11 PCIE11_RXP/SATA0A_RXP SATA_PRX_DTX_N4
G38 K43
<35> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN K44 SATA_PRX_DTX_P4 SATA_PRX_DTX_N4 <43>
AR42 PCIE17_RXP/SATA4_RXP A42 SATA_PTX_DRX_N4 SATA_PRX_DTX_P4 <43>
GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN SATA_PTX_DRX_P4 SATA_PTX_DRX_N4 <43>
HDD
AR48 B42
DGPU_PRSNT# AU47 GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP SATA_PTX_DRX_P4 <43>
AU46 GPP_F13/SATA_SDATAOUT0 P41
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN R40
3 PCIE_PTX_DRX_N14 PCIE18_RXP/SATA5_RXP 1A modify 3
CH3 2 1 .1U_0402_16V7K C39 C42
<36> PCIE_PTX_C_DRX_N14 PCIE_PTX_DRX_P14 PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN
CH4 2 1 .1U_0402_16V7K D39 D42
<36> PCIE_PTX_C_DRX_P14 PCIE_PRX_DTX_N14 D46 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP
GLAN <36> PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14 PCIE14_RXN/SATA1B_RXN +3VS
C47 AK48 1A modify
<36> PCIE_PRX_DTX_P14 PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED#
B38 AH41
C38 PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0 AJ43
C45 PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1 AK47 SATA_GP1 <35>
C46 PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2 AN47 RH187 1 PBA@ 2 10K_0402_5%
PCIE13_RXP/SATA0B_RXP GPP_F0/SATAXPCIE3/SATAGP_3 AM46
E37 GPP_F1/SATAXPCIE4/SATAGP4 AM43 SATA_GP5 SATA_GP1 RH39 2 1 10K_0402_5%
<35> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5 TP@ TH13
D38 AM47
<35> PCIE_PTX_DRX_N12 J41 PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6 AM48
M.2 SSD PCIE L0 <35> PCIE_PRX_DTX_P12 PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7 M.2 SSD PCIE/SATA select pin
H42
<35> PCIE_PRX_DTX_N12 PCIE12_RXN/SATA1A_RXN AU48 PCH_BKL_PW M
GPP_F21/EDP_BKLTCTL PCH_BKL_PW M <25,33>
B44 AV46 ENBKL
PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN PCH_ENVDD ENBKL <25,39>
1A modify A44 AV44
PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN PCH_ENVDD <25,33>
R37 #571391_CFL_H_PDG_Rev0p5.pdf
R35 PCIE20_RXP/SATA7_RXP AD3 PCH_THERMTRIP# RH40 1 2 620_0402_5%
PCIE20_RXN/SATA7_RXN THRMTRIP# PCH_PECI PCH_THERMTRIP#_R <11>
D43 AF2 RH41 1 @ 2 13_0402_5% H_PECI
PCIE19_TXP/SATA6_TXP PECI H_PM_SYNC H_PECI <11,39>
C44 AF3 RH42 1 2 30_0402_5% H_PM_SYNC_R
+3VALW _PCH_PRIM PCIE19_TXN/SATA6_TXN PM_SYNC H_PLTRST_CPU# H_PM_SYNC_R <11>
N42 AG5
PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# H_PM_DOW N_R H_PLTRST_CPU# <11>
M44 AE2
PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOW N_R <11>
1
CNP-H_BGA874 Rev1.0
RH43
10K_0402_5% UMA@ XEMC@
H_PECI 0.1U_0402_10V6K 1 2 CH50
2
4 4
DGPU_PRSNT#
1
RH44
10K_0402_5% VGA@
GPP_F13
DGPU_PRSNT#
2017/12/18
Compal Secret Data
2018/09/01 Title
DIS,Optimus 0 PCIE/SATA/USB3/eSPI
2
UMA 1 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom

A B C D E
A B C D E
+1.2V_VDDQ
<39> ME_EN 1 @ 2
2
RPH7 RH45 0_0402_5%
1 8 HDA_RST# RH46
<38> HDA_RST#_R HDA_BIT_CLK
<38> HDA_BIT_CLK_R 2 7 470_0402_1%
3 6 HDA_SDOUT
<38> HDA_SDOUT_R HDA_SYNC
<38> HDA_SYNC_R 4 5
1
DRAM_RESET# 1 2
DDR_DRAMRST#_R <23,24>
33_0804_8P4R_5% RH47 0_0402_5%
2 1 @
1 CH13 1U_0402_6.3V6K 1
100K_0201_5% 2 1RH196 HDA_BIT_CLK CNP-H
100K_0201_5% 2 1RH197 HDA_RST# UH1D
HDA_BIT_CLK BD11 BF36
HDA_SDIN0 BE11 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AV32 PM_CLKRUN#
intel critical net recommend <38> HDA_SDIN0 HDA_SDOUT BF12 HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN# PM_CLKRUN# <45>
HDA_SYNC BG13 HDA_SDO/I2S0_TXD BF41 LAN_DISABLE_N
HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC TP@ TH14
del RF reserve cap on HDA HDA_RST# BE10 BD42 SLP_W LAN#
HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# TP@ TH15
BF10
BE12 HDA_SDI1/I2S1_RXD BB46 DRAM_RESET#
BD12 I2S1_TXD/SNDW2_DATA DRAM_RESET# BE32 PCH_VRALERT#
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33 TYPEC_3A
GPP_B1/GSPI1_CS1#/TIME_SYNC1 LAN_GPO TYPEC_3A <40>
BE29
RH48 1 CPU_DISPA_SDO GPP_B0/GSPI0_CS1# PCH_GPP_K17 LAN_GPO <36>
2 30_0402_5% AM2 R47 TP@ TH19
<7> CPU_DISPA_SDO_R CPU_DISPA_SDI_R HDACPU_SDO GPP_K17/ADR_COMPLETE PCH_GPP_B11
AN3 AP29 TP@ TH20
<7> CPU_DISPA_SDI_R RH49 1 CPU_DISPA_BCLK HDACPU_SDI GPP_B11/I2S_MCLK SYS_PW ROK
2 30_0402_5% AM3 AU3 SYS_PW ROK <39,47>
<7> CPU_DISPA_BCLK_R HDACPU_SCLK SYS_PWROK
FOR Jefferson Peak RESET pin is glitch free,it AV18 BB47 W AKE#
AW18 GPP_D8/I2S2_SCLK WAKE# BE40 PM_SLP_A#
is recommended that a pull-down resistor of 75K CLKREQ_CNV# BA17 GPP_D7/I2S2_RXD GPD6/SLP_A# BF40 SLP_LAN# TP@ TH37
ohm on GPP_D5(CNV_RF_RESET#) <37> CLKREQ_CNV# CNV_RF_RESET# GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# PM_SLP_S0# TP@ TH21
BE16 BC28
<37> CNV_RF_RESET# GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# PM_SLP_S3# PM_SLP_S0# <39>
<38> PCH_DMIC_DATA0 BF15 BF42
BD16 GPP_D20/DMIC_DATA0/SNDW4_DATA 1.8V GPD4/SLP_S3# BE42 PM_SLP_S4# PM_SLP_S3# <39,47>
<38> PCH_DMIC_CLK0 GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# PM_SLP_S5# PM_SLP_S4# <39,47>
+RTCVCC TH22 TP@ AV16 BC42 TP@ TH23
AW15 GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5#
TH24 TP@ GPP_D17/DMIC_CLK1/SNDW3_CLK
PCH_SRTCRST# BE45 SUSCLK
RH50 1 2 20K_0402_1% GPD8/SUSCLK PM_BATLOW # SUSCLK <35,37>
BF44
GPD0/BATLOW# BE35 SUSACK#_R
CH18 1 2 1U_0402_6.3V6K PCH_RTCRST# GPP_A15/SUSACK# TP@ T207
2 BE47 BC37 1 @ 2 2
<39> PCH_RTCRST# PCH_SRTCRST# RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK SUSPW RDNACK <39>
CLR ME BD46 RH51 0_0402_5%
SRTCRST#
Delay 18~25 ms
PCH_PW ROK AY42 BG44 LAN_W AKE#
PCH_RTCRST# <39,47> PCH_PW ROK EC_RSMRST# PCH_PWROK GPD2/LAN_WAKE# AC_PRESENT_R AC_PRESENT
RH52 1 2 20K_0402_1% <39> EC_RSMRST# BA47 BG42 1 @ 2 AC_PRESENT <39>
RSMRST# GPD1/ACPRESENT BD39 SLP_SUS# RH53
SLP_SUS# PBTN_OUT#_R TP@ 0_0402_5% --No Support Deep Sx
PBTN_OUT#
BE46 1 2
@ T208 PBTN_OUT# <39>
CH19 1 2 1U_0402_6.3V6K PCH_DPW ROK AW41 GPD3/PWRBTN# AU2 SYS_RESET# RH54 0_0402_5%
PCH_SMBALERT# BE25 DSW_PWROK SYS_RESET# AW29 PCH_SPKR
ECLR CMOS <20> PCH_SMBALERT# PCH_SMBCLK GPP_C2/SMBALERT# GPP_B14/SPKR H_CPUPW RGD PCH_SPKR <20,38>
JCMOS1 1 @ 2 0_0603_5% Delay 18~25 ms BE26 AE3
PCH_SMBDATA GPP_C0/SMBCLK CPUPWRGD H_CPUPW RGD <11>
BF26
PCH_SML0ALERT# BF24 GPP_C1/SMBDATA AL3 XDP_ITP_PMODE
<20> PCH_SML0ALERT# PCH_SML0CLK GPP_C5/SML0ALERT# ITP_PMODE CPU_XDP_TCK0 TP@ T209
BF25 AH4 CPU_XDP_TCK0 <11>
PCH_SML0DATA BE24 GPP_C3/SML0CLK PCH_JTAGX AJ4 CPU_XDP_TMS
PCH_SML1ALERT# BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 CPU_XDP_TDO CPU_XDP_TMS <11>
<20> PCH_SML1ALERT# PCH_SML1CLK BF27 GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO AH2 CPU_XDP_TDI CPU_XDP_TDO <11> Connect CPU & PCH
+3VALW _DSW GPP_C6/SML1CLK PCH_JTAG_TDI CPU_XDP_TDI <11>
PCH_SML1DATA BE27 4 OF 13 AJ3 PCH_JTAG_TCK1
GPP_C7/SML1DATA PCH_JTAG_TCK PCH_JTAG_TCK1 <11>
CNP-H_BGA874 Rev1.0
RH55 2 1 1K_0402_5% W AKE#
RH56 2 1 8.2K_0402_5% PM_BATLOW # +3VALW _DSW PM_SLP_S3# RH193 1 2 100K_0201_5%

PM_SLP_S4# RH194 1 2 100K_0201_5%
RH57 2 @ 1 100K_0402_5% AC_PRESENT_R
RPH8
RH58 2 @ 1 100K_0402_5% PBTN_OUT#_R 8 1 PCH_PW ROK intel critical net recommend
7 2 LAN_W AKE#
+3VS 6 3 EC_RSMRST#
3 5 4 EC_RSMRST# 1 @ 2 PCH_DPW ROK 3
RH59 0_0402_5%
10K_0804_8P4R_5%
5
G
QH7B +3VALW _PCH_PRIM

2N7002KDW _SOT363-6
2 1 SYS_RESET#
PCH_SMBCLK D_CK_SCLK
(DDR,G-Sensor)
3 4 RH183 10K_0402_5%
S
D_CK_SCLK <23,24,43>
D
+3VS POP on 1A version

2
G
QH7A
2N7002KDW _SOT363-6 100K_0402_5% 1 @ 2 RH184 SYS_PW ROK
RH60 2 1 8.2K_0402_5% PM_CLKRUN#
PCH_SMBDATA 6 1D_CK_SDATA
S
D_CK_SDATA <23,24,43> PCH_DPW ROK

100K_0402_5% 1 @ 2 RH61
D
RH191 2 1 2.2K_0402_5% D_CK_SCLK XEMC@

RH192 2 1 2.2K_0402_5% D_CK_SDATA 0.1U_0402_10V6K 1 2 CH20 SYS_RESET# +3VALW _PCH_PRIM
XEMC@ PCH_VRALERT# RH62 2 @ 1 10K_0402_5%

PCH_SML1CLK 1 @ 2 0.1U_0402_10V6K 1 2 CH21 SYS_PW ROK
+3VALW _PCH_PRIM EC_SMB_CK2 <25,39,40,44>
RH189 0_0402_5%
RPH11 PCH_SML1DATA
(EC, VGA) XEMC@
PCH_PW ROK
1 @ 2 0.1U_0402_10V6K 1 2 CH22
PCH_SMBCLK EC_SMB_DA2 <25,39,40,44>
8 1 RH190 0_0402_5%
7 2 PCH_SMBDATA XEMC@
6 3 PCH_SML1CLK 0.1U_0402_10V6K 1 2 CH51 EC_RSMRST#
5 4 PCH_SML1DATA
4 4
2.2K_0804_8P4R_5%
From ESD Team Request
1 2 PCH_SML0CLK Near PCH side
RH63 499_0402_1%
1 2 PCH_SML0DATA

RH64 499_0402_1%
Security Classification Compal Secret Data
Issued Date 2017/12/18 2018/09/01 Title
Deciphered Date
PCH(5/8)PMU/HDA/SMBUS/DMIC
Custom

A B C D E
A B C D E
+3VALW _PCH_PRIM
RPH12
1 8 I2C_1_SCL CNP-H
2 7 I2C_1_SDA UH1K
3 6 I2C_0_SCL
4 5 I2C_0_SDA GSPI1_MOSI BA26 BA20 VGA_ID1
BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20 VGA_ID2
EC_SCI# AU26 GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK BB16 PROJECT_ID0
2.2K_0804_8P4R_5% <39> EC_SCI# GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO PROJECT_ID1
AW26 AN18
+3VS GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
GSPI0_MOSI BE30 BF14
RH66 2 @ 1 10K_0402_5% EC_SCI# GC6_FB_EN3V3 RH67 1 @ 2 0_0402_5% GC6_FB_EN BD29 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18
<25> GC6_FB_EN3V3 TS_EN GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN
BF29 BF17
<33,39> TS_EN GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL
1 RH68 2 1 49.9K_0402_1% UART_2_PRXD_DTXD BB26 BE17 SUB_DET 1
GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA
RH69 2 1 49.9K_0402_1% UART_2_PTXD_DRXD
check for remove (PCH or Both) BB24
check needed? DGPU_AC_DETECT BE23 GPP_C9/UART0A_TXD
<39,50> DGPU_AC_DETECT GPP_C8/UART0A_RXD
RH70 2 @ 1 49.9K_0402_1% UART_2_PRTS_DCTS AP24
GPU_EVENT# BA24 GPP_C11/UART0A_CTS#
CG11 connect to GPP_B15 <25> GPU_EVENT# GPP_C10/UART0A_RTS#
RH71 2 @ 1 49.9K_0402_1% UART_2_PCTS_DRTS AG45
BD21 GPP_H20/ISH_I2C0_SCL AH46
RH72 1 VGA@ 2 10K_0402_5% DGPU_PW R_EN AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA
DGPU_HOLD_RST# AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AH47
<25> DGPU_HOLD_RST# DGPU_PW R_EN GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL
AU24 AH48
<25,29> DGPU_PW R_EN GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
RH73 1 VGA@ 2 10K_0402_5% DGPU_HOLD_RST# UART_2_PCTS_DRTS AV21
UART_2_PRTS_DCTS AW21 GPP_C23/UART2_CTS#
UART_2_PTXD_DRXD BE20 GPP_C22/UART2_RTS# AV34
<37> UART_2_PTXD_DRXD UART_2_PRXD_DTXD GPP_C21/UART2_TXD GPP_A23/ISH_GP5
BD20 AW32
+3VALW _PCH_PRIM <37> UART_2_PRXD_DTXD GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BA33
I2C_1_SCL BE21 GPP_A21/ISH_GP3 BE34 G_INT
<45> I2C_1_SCL I2C_1_SDA GPP_C19/I2C1_SCL GPP_A20/ISH_GP2 CODEC_ID
<Touch PAD><45> BF21 BD34
GPP_H12 I2C_1_SDA I2C_0_SCL GPP_C18/I2C1_SDA GPP_A19/ISH_GP1
RH74 1 @ 2 4.7K_0402_5% BC22 BF35
GPP_H12 <17> I2C_0_SDA GPP_C17/I2C0_SCL GPP_A18/ISH_GP0
BF23 BD38
This signal has a weak internal pull-down. GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
0 = Master Attached Flash Sharing (MAFS) enabled (Default)
STRAP
BE15
1 = Slave Attached Flash Sharing (SAFS) enabled.
BE14 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
11 OF 13
Notes: GPP_D23/ISH_I2C2_SCL/I2C3_SCL
1. This signal is in the primary well.
Rev1.0
FOR 4 DMIC @256 +3VALW _PCH_PRIM
Warning: This strap must be configured to ‘ 0’ if th e CNP-H_BGA874
eSPI or LPC strap is configured to ‘ 0’
CODEC_ID RH188 1 256@ 2 1K_0402_5%

2 2
CODEC_ID / GPP_A19
+3VALW _PCH_PRIM 0 = 2 DIMC @255 (Default)
1 = 4 DIMC @256
RH112 1 @ 2 4.7K_0402_5% FOR 40 PIN SUB/B

PCH_SMBALERT# <19> +1.8VALW _PRIM
SMBALERT# / GPP_C2 has a weak internal Pull-down.
0 = Disable Intel ME (TLS) (Default)
1 = Enable Intel ME (TLS) SUB_DET RH185 1 @ 2 1K_0402_5%
RH113 1 @ 2 4.7K_0402_5%
PCH_SML0ALERT# <19>
SML0ALERT# / GPP_C5 has a weak internal Pull-down.
0 = LPC is selected (for EC 9022).
1 = eSPI is selected
+1.8VALW _PRIM
+1.8VALW _PRIM
RH114 1 2 150K_0402_1% VGA_ID1 RH84 1 @ 2 1K_0402_5%
PCH_SML1ALERT# <19> PROJECT_ID0 RH88 1SATARD@ 2 1K_0402_5%
SML1ALERT# / GPP_B23 has an internal pull-down. RH85 1 2 10K_0402_5%
0 = Disable IntelR DCI-OOB (Default) RH89 1SATANRD@2 10K_0402_5% +3VS
*1 = Enable IntelR DCI-OOB
STRAP
VGA_ID2 RH86 1 @ 2 1K_0402_5%
2
PROJECT_ID1 RH90 1 2 1K_0402_5% GSEN@
+3VS RH87 1 2 10K_0402_5% RH78
3 RH91 1 @ 2 10K_0402_5% 3
10K_0402_5%
RH77 1 @ 2 4.7K_0402_5% GSPI0_MOSI STRAP
1
G_INT
The signal has a weak internal Pull-down. G_INT <43>
0 = Disable “ No Reboot” mode . (Default)
1 = Enable “ No Reboot” mod e (PC H wil l disabl e th e Project_ID1 Project_ID0
2
TCO Timer system reboot feature). This function is pop for avoid floating Project ID RH79
useful when running ITP/XDP.
Notes: 1.0 Modify GPP_D10 GPP_D9 GPP_D12 GPP_D11 @ 100K_0402_5%
1. The internal Pull-down is disabled after
PCH_PWROK is high.
Reserved 0 0 DH53F(1060 WO RD) 0 0
1
Reserved 0 1 DH53F(1060 W RD) 0 1
Reserved 1 0 * DH5VF(1050 WO RD) 1 0
@ GSPI1_MOSI
RH80 1 2 150K_0402_1% STRAP for 8 Layer 1 1 * DH5VF(1050 W RD) 1 1
※no t e: 00 /01 us edf or 1050
This Signal has a weak internal Pull-down.
0: SPI (Default)
SCI capability is available on all GPIOs
1: LPC
Notes: EVT PCH GPIOs that can be routed to generate SMI# or NMI:
1. The internal Pull-down is disabled after PCH_PWROK is high.
10 used for 1060 EVT ‧ GPP_B14, GPP_B20, GPP_B23
‧ GPP_C[23:22]
‧ GPP_D[4:0]
‧ GPP_E[8:0]
PCH_SPKR ‧ GPP_I[3:0]
RH83 2 @ 1 100K_0402_5% ‧ GPP_G[7:0] (support SMI# only).
PCH_SPKR <19,38>
Top Swap Override STRAP The voltage of all GPIO pads in each GPP group is determined by the voltage supplied to the group (either 3.3V or 1.8V),
0 = Disable “ Top Swap” mode. (Default
) except for GPP_I and GPD group, (which are 3.3V only), and GPP_J group (which is 1.8V only).
1 = Enable “ Top Swap” mode
.
4 The internal Pull-down is disabled after PCH_PWROK is high. All GPIOs have programmable internal pull-up/pull-down resistors which are off by default. 4
The internal pull-up/pull-down for each GPIO can be enabled by BIOS programming.
2017/12/18
Compal Secret Data
2018/09/01 Title
PCH(6/8)GPIO/I2C/UART/STRAP
Custom

A B C D E
A B C D E
GPIO Group Voltage
GPPA 3.3V
+1.05VALW_PCH_PRIM
+1.05VALW CNP-H +3VALW_PCH_PRIM
+1.05VALW_PCH_PRIM UH1H GPPB
5.95A AA22 AW9 0.182A GPPC 3.3V
@ JPH1 AA23 VCCPRIM_1P051 VCCPRIM_3P32
1 2 5.95A AB20 VCCPRIM_1P052 BF47 +VCCRTCEXT
1 2 HSIO for DMIU/USB3.1/PCIE=4162mA VCCPRIM_1P053 DCPRTC1 +VCCRTCEXT GPPD 3.3V
AB22 BG47 +VCCRTCEXT * 1.8V
VCCPRIM_1P054 DCPRTC2
1U_0402_6.3V6K
JUMP_43X79 1 AB23
AB27 VCCPRIM_1P055 V23 0.095A +3VALW_SPI
VCCPRIM_1P056 VCCPRIM_3P35
GPPE
CH23
AB28 3.3V
0.1U_0402_10V6K
AB30 VCCPRIM_1P057 AN44 0.05A 1 GPPF
2 AD20 VCCPRIM_1P058 VCCSPI +RTCVCC
CH24
AD23 VCCPRIM_1P059 BC49
1 GPPG 3.3V 1
AD27 VCCPRIM_1P0510 VCCRTC1 BD49
VCCPRIM_1P0511 VCCRTC2 2
AD28
AD30 VCCPRIM_1P0512 AN21 0.145A GPPH 3.3V
AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8 GPPK
+1.05VALW_VCCMPHY AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7 0.97A
+1.05VALW_VCCMPHY AF30 VCCPRIM_1P0517 VCCPRIM_3P34
@ JPH2
VCCPRIM_1P0518
GPPI 3.3V Only
1 2 6.6A AC35 0.262A
1 2 6.6A U26 VCCPGPPHK1 AC36
JUMP_43X79 U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35 0.174A GPPJ 1.8V Only
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36
VCCPRIM_1P0525 VCCPGPPEF2 +1.8VALW_PRIM
22U_0402_6.3V6M
1U_0402_6.3V6K
1 1 V27
V28 VCCPRIM_1P0526 AN24 0.14A GPD 3.3V Only
VCCPRIM_1P0527 VCCPGPPD +1.8VALW_PRIM
CH25
CH26
V30 AN26
+1.05VALW_PCH V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26 0.343A
2 2 VCCPRIM_1P0529 VCCPGPPBC2
0.0012A AD31 AN32 0.101A
VCCPRIM_1P0514 VCCPGPPA
4.7U_0402_6.3V6M
1U_0402_6.3V6K
1 1
0.2A AE17 AT44 0.106A
VCCPRIM_1P0515 VCCPRIM_3P31
CH27
CH28
BE48
3-5MM FROM PACKAGE EDGE 0.42A W22 VCCDSW_3P31 BE49 0.113A
+3VALW_DSW
W23 VCCDUSB_1P051 VCCDSW_3P32 +3VALW_HDA 2 2
+1.05VALW_PCH +1.05V_VCCDSW VCCDUSB_1P052 BB14 0.00767A
BG45 VCCHDA AG19
RH94 1 2 0_0603_5% BG46 VCCDSW_1P051 VCCPRIM_1P83 AG20 +1.8VALW_PRIM
0.109A W31 VCCDSW_1P052 VCCPRIM_1P84 AN15 0.766A Close to BB11
+1.05VALW_VCCAZPLL VCCPRIM_MPHY_1P05 VCCPRIM_1P85 AR15
0.015A D1 VCCPRIM_1P86 BB11
E1 VCCPRIM_1P0521 VCCPRIM_1P87 +1.8V_PHVLDO +1.8VALW_PRIM
+1.05VALW_VCCAMPHYPLL 0.213A C49 VCCPRIM_1P0522 AF19 0.882A VCCPHVLDO_1P8
D49 VCCAMPHYPLL_1P051 VCCPRIM_1P81 AF20 +1.8V_PHVLDO RH95 1 @ 2 0_0402_5% (External VRM mode RH172 unmount)
pop for intel sensitive net (1.0) VCCAMPHYPLL_1P052 VCCPRIM_1P82
E49
+1.05VALW_PCH +1.05VALW_PCH +1.05V_VCCDSW VCCAMPHYPLL_1P053 AG31 0.193A
+1.05VALW_XTAL VCCPRIM_1P0520 +1.05VALW_PCH
0.00428A P2 AF31 0.0895A
VCCA_XTAL_1P051 VCCPRIM_1P0519 +1.05VALW_PCH
P3 AK22
0.169A W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23 +1.24V_VCCLDOSRAM_IN +1.24V_PRIM_DPHY
2 VCCA_SRC_1P051 VCCPRIM_1P242 +1.24V_VCCLDOSRAM_IN 2
1U_0402_6.3V6K
1 W20 Short pins AJ22,AJ23,AK22,AK23 together

0.1U_0402_10V6K
0.1U_0402_10V6K
VCCA_SRC_1P052 AJ22
1 1 VCCDPHY_1P241 +1.24V_PRIM_DPHY at surface layer from PDG Rev0.71
CH31
0.0198A C1 AJ23 Internal LDO RH96 1 @ 2 0_0402_5%

CH29
CH30
C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5

2 VCCAPLL_1P055 VCCDPHY_1P243 +1.24V_PRIM_MAR
0.0085A V19 RH174 for 571391_CFL_H_PDG_Rev0p71.pdf
2 2 VCCA_BCLK_1P05 K47 VCCMPHY_SENSE
VCCMPHY_SENSE VSSMPHY_SENSE TP@ TH27
0.021A B1 K46 TP@ TH28
For DDX03 R02
B2 VCCAPLL_1P051 VSSMPHY_SENSE
B3 VCCAPLL_1P052 8 OF 13 +1.24V_PRIM_MAR
VCCAPLL_1P053
CNP-H_BGA874 Rev1.0
place near VCCDUSB 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE EDGE
FOR W22/W23 VCCPRIM_MPHY W31
4.7U_0402_6.3V6M
1
CH32
pop for intel sensitive net (1.0)
+1.05VALW_PCH 2
+1.05VALW_PCH
+1.05VALW_PCH
1U_0402_6.3V6K
0.1U_0402_10V6K
1
1 +3VALW_PCH_PRIM
1U_0402_6.3V6K
1
+3VALW_PCH_PRIM +3VALW_PCH_PRIM
CH33
CH34
+3VALW +3VALW_PCH_PRIM +3VALW_PCH_PRIM +3VALW_SPI

CH35
2
2
0.1U_0402_10V6K
2
1U_0402_6.3V6K
1 1
0.1U_0402_10V6K
RH97 1 2 0_0805_5% RH98 1 2 0_0603_5% 1
CH38
0.1U_0402_10V6K
CH37
1
CH36
1-5MM FROM PACKAGE EDGE 1-3MM FROM PACKAGE EDGE 1-5MM FROM PACKAGE EDGE
CH39
+1.8VALW +1.8VALW_PRIM 2 2
FOR VCCAPLL C1/C2 FOR VCCA_BCLK V19 FOR VCCAPLL B1/B2/B3 +3VALW_DSW 2
@ 2
@
RH99 1 2 0_0402_5% RH100 1 2 0_0603_5%
0.1U_0402_10V6K
1
CH40
3 3
change to 0_0603 (1.0) 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE 1-3MM FROM PACKAGE
2 FOR PGPPEF AE35/AE37 FOR PGPPHK AC35/AC36 FOR VCCPRIM AY8/BB7
+1.05VALW_PCH +3VALW_HDA
+1.05VALW_VCCAZPLL
reserve for cnvi issue (1.0)
0_0402_5% 2 1RH101
+1.8VALW_PRIM +1.8VALW_PRIM
RH1021 2 0_0402_5%
1P_0402_50V8
1P_0402_50V8
1 1
1P_0402_50V8
CH41
1P_0402_50V8
CH42
0.1U_0402_10V6K
10U_0603_6.3V6M
1 1 1 1
CH44
CH43
CH52
2 2
CH53
@ @ @
2 2 2 2
@ @ reserve filter folloe CRB
8/21
1-3MM FROM PACKAGE EDGE
+1.05VALW_VCCAMPHYPLL
near AG19/AG20
RH103 1 2 0_0402_5%
1U_0402_6.3V6K
22U_0402_6.3V6M
1 1
CH46
CH45
+RTCBATT
2 2 change to 10k DH2 +RTCVCC +RTCBATT
LC filter colse to pin JRTC1
@ RH104 2 1 10K_0402_5% 2
+CHGRTC 1 1
1uF 1-3MM FROM PACKAGE EDGE 1
3 2
2
4 4
3
0.1U_0402_10V6K
BAV70W_SOT323-3 GND
1U_0402_6.3V6K
1 1 4
+1.05VALW_XTAL GND
CH48
CH47
ACES_50271-0020N-001
RH105 1 2 0_0402_5% CONN@
2 2
SP02000RO00
22U_0402_6.3V6M
1
CH49
2 Issued Date 2017/12/18 Deciphered Date 2018/09/01 Title
@
PCH(7/8)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom

A B C D E
A B C D E
CNP-H
UH1L CNP-H
CNP-H UH1J
UH1I BG3 M24 Y14
A2 AL12 BG33 VSS VSS M32 RSVD7 Y15
A28 VSS VSS AL17 BG37 VSS VSS M34 RSVD8 U37
1 1
A3 VSS VSS AL21 BG4 VSS VSS M49 RSVD6 U35
A33 VSS VSS AL24 BG48 VSS VSS M5 RSVD5
A37 VSS VSS AL26 C12 VSS VSS N12 N32
A4 VSS VSS AL29 C25 VSS VSS N16 RSVD3 R32
A45 VSS VSS AL33 C30 VSS VSS N34 RSVD4
A46 VSS VSS AL38 C4 VSS VSS N35 AH15
A47 VSS VSS AM1 C48 VSS VSS N37 RSVD2 AH14
A48 VSS VSS AM18 C5 VSS VSS N38 RSVD1
A5 VSS VSS AM32 D12 VSS VSS P26
A8 VSS VSS AM49 D16 VSS VSS P29
AA19 VSS VSS AN12 D17 VSS VSS P4 AL2 XDP_PREQ#
VSS VSS VSS VSS PREQ# XDP_PRDY# XDP_PREQ# <11>
AA20 AN16 D30 P46 AM5 XDP_PRDY# <11>
AA25 VSS VSS AN34 D33 VSS VSS R12 PRDY# AM4 CPU_XDP_TRST#
VSS VSS VSS VSS CPU_TRST# PCH_TRIGOUTRH106 1 PCH_TRIGOUT_R CPU_XDP_TRST# <11>
AA27 AN38 D8 R16 AK3 2 30_0402_5%
VSS VSS VSS VSS TRIGGER_OUT CPU_TRIGOUT_R PCH_TRIGOUT_R <14>
AA28 AP4 E10 R26 AK2
VSS VSS VSS VSS TRIGGER_IN CPU_TRIGOUT_R <14>
AA30 AP46 E13 R29
AA31 VSS VSS AR12 E15 VSS VSS R3 10 OF 13
AA49 VSS VSS AR16 E17 VSS VSS R34 CNP-H_BGA874 Rev1.0
AA5 VSS VSS AR34 E19 VSS VSS R38
AB19 VSS VSS AR38 E22 VSS VSS R4
AB25 VSS VSS AT1 E24 VSS VSS T17
AB31 VSS VSS AT16 E26 VSS VSS T18
AC12 VSS VSS AT18 E31 VSS VSS T32
AC46 VSS VSS AT32 E8 VSS VSS U12
2 AD1 VSS VSS AT34 F41 VSS VSS U15 2
AD19 VSS VSS AT45 F43 VSS VSS U17
AD2 VSS VSS AV11 F47 VSS VSS U21
AD22 VSS VSS AV39 G44 VSS VSS U24
AD25 VSS VSS AW10 G6 VSS VSS U33
AD49 VSS VSS AW4 H8 VSS VSS U38
AE12 VSS VSS AW40 J10 VSS VSS V20
AE33 VSS VSS AW46 J26 VSS VSS V22
AE38 VSS VSS B47 J29 VSS VSS V4
AE4 VSS VSS B48 J4 VSS VSS V46
AE46 VSS VSS B49 J40 VSS VSS W25
AF22 VSS VSS BA12 J46 VSS VSS W27
AG1 VSS VSS BA5 J9 VSS VSS Y10
AG22 VSS VSS BA6 K11 VSS VSS Y12
AG23 VSS VSS BB41 K39 VSS VSS Y17
AG25 VSS VSS BB43 M16 VSS VSS Y33
AG27 VSS VSS BB9 M18 VSS VSS Y38
AG28 VSS VSS BC10 M21 VSS 12 OF 13 VSS Y9
AG30 VSS VSS BC13 VSS VSS
AG49 VSS VSS BC15 CNP-H_BGA874 Rev1.0
AH12 VSS VSS BC19
AH17 VSS VSS BC24
AH33 VSS VSS BC26
AH38 VSS VSS BC31
AJ19 VSS VSS BC35
AJ20 VSS VSS BC40
AJ25 VSS VSS BC45
3 AJ27 VSS VSS BC8 3
AJ28 VSS VSS BD43
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
AK27 VSS VSS BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
AK4 VSS VSS BG25
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
CNP-H_BGA874 Rev1.0
4 4
2017/12/18
Compal Secret Data
2018/09/01 Title
PCH(8/8)GND/RSVD
Custom

A B C D E
5 4 3 2 1
CHANNEL-A BOT REVERSE TYPE

<8>
<8>
(4 mm)
DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK0
DDR_A_CLK#0
137
139
JDIMM1A
CK0(T)
CK0#(C)
REVERSE
DQ0
DQ1
8
7
DDR_A_D0
DDR_A_D1
DDR_A_CLK1 DDR_A_D2
Interleaved Memory <8> DDR_A_CLK1

138 20
DDR_A_CLK#1 140 CK1(T) DQ2 21 DDR_A_D3
<8> DDR_A_CLK#1 CK1#(C) DQ3 DDR_A_D4
4
DDR_A_CKE0 109 DQ4 3 DDR_A_D5
<8> DDR_A_CKE0 DDR_A_CKE1 110 CKE0 DQ5 16 DDR_A_D6
TOP: JDIMM1 CONN Non-ECC DIMM <8> DDR_A_D[0..15]
<8>
<8>
DDR_A_CKE1
DDR_A_CS#0
DDR_A_CS#0
DDR_A_CS#1
149
CKE1
S0#
DQ6
DQ7
DQS0(T)
17
13
DDR_A_D7
DDR_A_DQS0
DDR_A_DQS#0 DDR_A_DQS0 <8>
157 11
<8> DDR_A_D[16..31] <8> DDR_A_CS#1 S1# DQS0#(C) DDR_A_DQS#0 <8>
D
162 D
+3VS +3VS +3VS 165 S2#/C0 28 DDR_A_D8
<8> DDR_A_D[32..47] S3#/C1 DQ8 29 DDR_A_D9
DDR_A_ODT0 155 DQ9 41 DDR_A_D10
<8> DDR_A_D[48..63] <8> DDR_A_ODT0 ODT0 DQ10
1
1
1
DDR_A_ODT1 161 42 DDR_A_D11
<8> DDR_A_ODT1 ODT1 DQ11 DDR_A_D12
RD4 RD1 RD5 24
@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% JDIMM1B DDR_A_BG0 115 DQ12 25 DDR_A_D13
REVERSE <8> DDR_A_BG0 DDR_A_BG1 113 BG0 DQ13 38 DDR_A_D14
111 141 <8> DDR_A_BG1 DDR_A_BA0 150 BG1 DQ14 37 DDR_A_D15
+1.2V_VDDQ +1.2V_VDDQ <8> DDR_A_BA0
2
2
2
SA0_CHA_DIM1 SA1_CHA_DIM1 SA2_CHA_DIM1 112 VDD1 VDD11 142 DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS1
VDD2 VDD12 <8> DDR_A_BA1 BA1 DQS1(T) DDR_A_DQS#1 DDR_A_DQS1 <8>
117 147 32
118 VDD3 VDD13 148 DDR_A_MA0 144 DQS1#(C) DDR_A_DQS#1 <8>
VDD4 VDD14 <8> DDR_A_MA0 A0
1
1
123 153 DDR_A_MA1 133 50 DDR_A_D16
124 VDD5 VDD15 154 <8> DDR_A_MA1 DDR_A_MA2 132 A1 DQ16 49 DDR_A_D17
RD3 RD6 RD2
0_0402_5% 0_0402_5% 0_0402_5% VDD7 VDD17 <8> DDR_A_MA3 A3 DQ18
130 160 DDR_A_MA4 128 63 DDR_A_D19
<8> DDR_A_MA5
2
2
+3VS 136 VDD9 VDD19 DDR_A_MA6 127 A5 DQ20 45 DDR_A_D21
VDD10 <8> DDR_A_MA6 DDR_A_MA7 122 A6 DQ21 58 DDR_A_D22
255 258 <8> DDR_A_MA7 DDR_A_MA8 125 A7 DQ22 59 DDR_A_D23
VDDSPD VTT +0.6VS_VTT <8> DDR_A_MA8 DDR_A_MA9 121 A8 DQ23 55 DDR_A_DQS2
<8> DDR_A_MA9 DDR_A_MA10 A9 DQS2(T) DDR_A_DQS#2 DDR_A_DQS2 <8>
0.1U_0402_10V6K
164 257 146 53
2.2U_0402_6.3V6M
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM 2
+0.6V_DDR_VREFCA VREFCA VPP1 259 +2.5V <8> DDR_A_MA10 DDR_A_MA11 120 A10_AP DQS2#(C) DDR_A_DQS#2 <8>
2 VPP2 <8> DDR_A_MA11 DDR_A_MA12 A11 DDR_A_D24
119 70
<8> DDR_A_MA12 DDR_A_MA13 A12 DQ24 DDR_A_D25
CD1
CD2
1 99 158 71
VSS VSS <8> DDR_A_MA13 DDR_A_MA14_WE# A13 DQ25 DDR_A_D26
2 102 151 83
1 1 5 VSS VSS 103 <8> DDR_A_MA14_WE# DDR_A_MA15_CAS# 156 A14_WE# DQ26 84 DDR_A_D27
SPD ADDRESS FOR CHANNEL A : 6 VSS
VSS
VSS
VSS
106 <8>
<8>
DDR_A_MA15_CAS#
DDR_A_MA16_RAS#
DDR_A_MA16_RAS# 152 A15_CAS#
A16_RAS#
DQ27
DQ28
66 DDR_A_D28
DDR_A_D29
9 107 67
WRITE ADDRESS: 0XA0 PLACE NEAR TO PIN
10
14
VSS
VSS
VSS
VSS
167
168
<8> DDR_A_ACT#
DDR_A_ACT# 114
ACT#
DQ29
DQ30
79
80
DDR_A_D30
DDR_A_D31
READ ADDRESS: 0XA1 15
18
VSS
VSS
VSS
VSS
171
172 <8> DDR_A_PAR
DDR_A_PAR
DDR_A_ALERT#
143
116 PARITY
DQ31
DQS3(T)
76
74
DDR_A_DQS3
DDR_A_DQS#3 DDR_A_DQS3 <8>
SA0 = 0; SA1 = 0; SA2 = 0. 19
22
VSS
VSS
VSS
VSS
175
176 +1.2V_VDDQ RD7 2 <8> 1 DDR_A_ALERT#
240_0402_1% DIMM1_CHA_EVENT#
DDR_DRAMRST#_R
134
108
ALERT#
EVENT#
DQS3#(C)
174 DDR_A_D32
DDR_A_DQS#3 <8>
C
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26
VSS
VSS
VSS
VSS
180
181
<19,24> DDR_DRAMRST#_R RESET# DQ32
DQ33
173
187
DDR_A_D33
DDR_A_D34 C
STRETCH GOAL IS 2133 MT/S 27

30
VSS
VSS
VSS
VSS
184
185 <19,24,43> D_CK_SDATA
254
253 SDA
DQ34
DQ35
186
170
DDR_A_D35
DDR_A_D36
31 VSS VSS 188 <19,24,43> D_CK_SCLK SCL DQ36 169 DDR_A_D37
35 VSS VSS 189 SA2_CHA_DIM1 166 DQ37 183 DDR_A_D38
36 VSS VSS 192 SA1_CHA_DIM1 260 SA2 DQ38 182 DDR_A_D39
Layout Note: Layout Note: VSS VSS SA0_CHA_DIM1 SA1 DQ39 DDR_A_DQS4
39 193 256 179
Place near JDIMM1.257,259 Place near JDIMM1.258 40 VSS VSS 196 SA0 DQS4(T) 177 DDR_A_DQS#4 DDR_A_DQS4 <8>
43 VSS VSS 197 DQS4#(C) DDR_A_DQS#4 <8>
44 VSS VSS 201 92 195 DDR_A_D40
47 VSS VSS 202 91 CB0_NC DQ40 194 DDR_A_D41
48 VSS VSS 205 101 CB1_NC DQ41 207 DDR_A_D42
+2.5V +0.6VS_VTT 51 VSS VSS 206 105 CB2_NC DQ42 208 DDR_A_D43
10uF*2 10uF*2 VSS VSS CB3_NC DQ43 DDR_A_D44
52 209 88 191
1uF*2 1uF*1 56 VSS VSS 210 87 CB4_NC DQ44 190 DDR_A_D45
57 VSS
VSS
VSS
VSS
213 For ECC DIMM 100 CB5_NC
CB6_NC
DQ45
DQ46
203 DDR_A_D46
DDR_A_D47
1U_0402_6.3V6K
10U_0603_6.3V6M
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
10U_0603_6.3V6M
1 1 1 1 1 1 1 60 214 104 204

61 VSS VSS 217 97 CB7_NC DQ47 200 DDR_A_DQS5
VSS VSS DQS8(T) DQS5(T) DDR_A_DQS#5 DDR_A_DQS5 <8>
CD5
CD3
CD6
CD7
CD8
CD9
CD4
64 218 95 198
VSS VSS DQS8#(C) DQS5#(C) DDR_A_DQS#5 <8>
65 222
2 2 2 2 2 2 2 68 VSS VSS 223 216 DDR_A_D48
69 VSS VSS 226 12 DQ48 215 DDR_A_D49
72 VSS VSS 227 +1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_A_D50
73 VSS VSS 230 54 DM1#/DBI1# DQ50 229 DDR_A_D51
85 VSS VSS 239 DDR_DRAMRST#_R 241 DM6#/DBI6# DQ55 221 DDR_A_DQS6
VSS VSS DM7#/DBI7# DQS6(T) DDR_A_DQS#6 DDR_A_DQS6 <8>
86 243 96 219
VSS VSS DM8#/DBI8# DQS6#(C) DDR_A_DQS#6 <8>
0.1U_0402_10V6K
89 244
90 VSS VSS 247
Layout Note: VSS VSS 2
93 248 @
PLACE THE CAP near JDIMM1. 164 VSS VSS DDR_A_D56
CD10
94 251 237
98 VSS VSS 252 DQ56 236 DDR_A_D57
B VSS VSS 1 DQ57 249 DDR_A_D58 B
262 261 DQ58 250 DDR_A_D59
GND GND DQ59 232 DDR_A_D60
DQ60 233 DDR_A_D61
+0.6V_DDR_VREFCA LOTES_ADDR0206-P001A DQ61 245 DDR_A_D62
2.2uF*1 DQ62 DDR_A_D63
246
0.1uF*1 CONN@
PLACE NEAR TO SODIMM DQ63 242 DDR_A_DQS7
DQS7(T) 240 DDR_A_DQS#7 DDR_A_DQS7 <8>
2 2 DQS7#(C) DDR_A_DQS#7 <8>
CD11 CD12
0.1U_0402_10V6K 2.2U_0402_6.3V6M
Part Number:SP07001FYH0
1 1 Part Value:S SOCKET FOX_AS0A826-H4RB-7H 260P DDR4 LOTES_ADDR0206-P001A
CONN@
+1.2V_VDDQ
DIMM Side CPU Side
2
RD8 +0.6V_DDR_VREFCA +0.6V_VREFCA
Layout Note:
Place near JDIMM1 @ 2 1K_0402_1%
CD13
1
0.1U_0402_10V6K
1
1 RD9 2
VREF traces should be at least 20 mils
10uF*6 2_0402_1% wide with 20 mils spacing to other
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 2
1 signals
330uF*1
2
+1.2V_VDDQ CD15
RD10 CD14 0.022U_0402_16V7K
2
1K_0402_1% 0.1U_0402_10V6K
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
CD16
CD17
CD18
CD19
CD20
CD21
CD22
CD23
A + CD32 RD11 A
CD28
CD24
CD27
CD25
CD26
CD29
CD30
CD31
330U_D2_2V_Y 24.9_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1
@ @

DDRIV_CHA: DIMM0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. DH5VF M/B LA-F591PR01
5 4 3 2 1
5 4 3 2 1
CHANNEL-B BOT STD (4 mm)

TOP: JDIMM3 CONN Non-ECC DIMM Interleaved Memory <9> DDR_B_D[0..15]
<9>
<9>
<9>
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
137
139
138
140
JDIMM2A
CK0(T)
CK0#(C)
CK1(T)
RESERVE
DQ0
DQ1
DQ2
8
7
20
21
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
<9> DDR_B_CLK#1 CK1#(C) DQ3 4 DDR_B_D4
+3VS +3VS +3VS <9> DDR_B_D[16..31] DDR_B_CKE0 109 DQ4 3 DDR_B_D5
<9> DDR_B_CKE0 DDR_B_CKE1 110 CKE0 DQ5 16 DDR_B_D6
<9> DDR_B_D[32..47] <9> DDR_B_CKE1 CKE1 DQ6 17 DDR_B_D7
DQ7
1
1
DDR_B_CS#0 149 13 DDR_B_DQS0
D <9> DDR_B_D[48..63] <9> DDR_B_CS#0 DDR_B_CS#1 S0# DQS0(T) DDR_B_DQS#0 DDR_B_DQS0 <9> D
RD12 RD13 RD14 157 11
<9> DDR_B_CS#1 162 S1# DQS0#(C) DDR_B_DQS#0 <9>
0_0402_5% 0_0402_5% @ 0_0402_5% JDIMM2B
@ S2#/C0 DDR_B_D8
RESERVE 165 28
111 141 S3#/C1 DQ8 29 DDR_B_D9
+1.2V_VDDQ +1.2V_VDDQ
2
2
SA0_CHB_DIM3 SA1_CHB_DIM3 SA2_CHB_DIM3 112 VDD1 VDD11 142 DDR_B_ODT0 155 DQ9 41 DDR_B_D11
117 VDD2 VDD12 147 <9> DDR_B_ODT0 DDR_B_ODT1 161 ODT0 DQ10 42 DDR_B_D15
VDD3 VDD13 <9> DDR_B_ODT1 ODT1 DQ11
1
118 148 24 DDR_B_D14

VDD4 VDD14 DQ12
1
1
RD16 123 153 DDR_B_BG0 115 25 DDR_B_D10
124 VDD5 VDD15 154 <9> DDR_B_BG0 DDR_B_BG1 113 BG0 DQ13 38 DDR_B_D12
RD15 @ 0_0402_5% RD17
VDD6 VDD16 <9> DDR_B_BG1 DDR_B_BA0 BG1 DQ14 DDR_B_D13
0_0402_5% 0_0402_5% 129 159 150 37
130 VDD7 VDD17 160 <9> DDR_B_BA0 DDR_B_BA1 145 BA0 DQ15 34 DDR_B_DQS1
<9> DDR_B_BA1 DDR_B_DQS1 <9>
2
135 VDD8 VDD18 163 BA1 DQS1(T) 32 DDR_B_DQS#1

DDR_B_DQS#1 <9>
2
2
+3VS 136 VDD9 VDD19 DDR_B_MA0 144 DQS1#(C)
VDD10 <9> DDR_B_MA0 DDR_B_MA1 133 A0 50 DDR_B_D16
<9> DDR_B_MA1 DDR_B_MA2 A1 DQ16 DDR_B_D17
255 258 132 49
VDDSPD VTT +0.6VS_VTT <9> DDR_B_MA2 DDR_B_MA3 131 A2 DQ17 62 DDR_B_D19
<9> DDR_B_MA3 DDR_B_MA4 A3 DQ18 DDR_B_D20
0.1U_0402_10V6K
164 257 128 63
2.2U_0402_6.3V6M
+0.6V_DDRB_VREFCA VREFCA VPP1 259 +2.5V <9> DDR_B_MA4 DDR_B_MA5 126 A4 DQ19 46 DDR_B_D22
2 2 VPP2 <9> DDR_B_MA5 DDR_B_MA6 A5 DQ20 DDR_B_D18
127 45
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM <9> DDR_B_MA6 DDR_B_MA7 A6 DQ21 DDR_B_D23
CD33
CD34
1 99 122 58
2 VSS VSS 102 <9> DDR_B_MA7 DDR_B_MA8 125 A7 DQ22 59 DDR_B_D21
1 1 5 VSS VSS 103 <9> DDR_B_MA8 DDR_B_MA9 121 A8 DQ23 55 DDR_B_DQS2
VSS VSS <9> DDR_B_MA9 A9 DQS2(T) DDR_B_DQS2 <9>
SPD ADDRESS FOR CHANNEL B : 6
9 VSS VSS
106
107 <9> DDR_B_MA10
DDR_B_MA10
DDR_B_MA11
146
120 A10_AP DQS2#(C)
53 DDR_B_DQS#2
DDR_B_DQS#2 <9>
VSS VSS <9> DDR_B_MA11 A11
WRITE ADDRESS: 0XA4 PLACE NEAR TO PIN
10
14 VSS VSS
167
168 <9> DDR_B_MA12
DDR_B_MA12
DDR_B_MA13
119
158 A12 DQ24
70
71
DDR_B_D30
DDR_B_D25
VSS VSS <9> DDR_B_MA13 DDR_B_MA14_WE# A13 DQ25 DDR_B_D26
READ ADDRESS: 0XA3 15
18 VSS VSS
171
172 <9>
<9>
DDR_B_MA14_WE#
DDR_B_MA15_CAS#
DDR_B_MA15_CAS#
151
156 A14_WE# DQ26
83
84 DDR_B_D24
VSS VSS DDR_B_MA16_RAS# A15_CAS# DQ27 DDR_B_D28
SA0 = 0; SA1 = 1; SA2 = 0. 19
22 VSS
VSS
VSS
VSS
175
176
<9> DDR_B_MA16_RAS#
152
A16_RAS# DQ28
DQ29
66
67 DDR_B_D27
DDR_B_ACT# DDR_B_D29
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26 VSS
VSS
VSS
VSS
180
181 <9> DDR_B_ACT#
DDR_B_PAR
114
ACT# DQ30
DQ31
79
80 DDR_B_D31
DDR_B_DQS3
27 184 143 76
STRETCH GOAL IS 2133 MT/S 30 VSS
VSS
VSS
VSS
185 <9>
<9>
DDR_B_PAR
DDR_B_ALERT#
DDR_B_ALERT#
DIMM3_CHB_EVENT#
116 PARITY
ALERT#
DQS3(T)
DQS3#(C)
74 DDR_B_DQS#3 DDR_B_DQS3
DDR_B_DQS#3
<9>
<9>
31 188 2 RD18 1 134
C 35 VSS VSS 189 +1.2V_VDDQ 240_0402_1% DDR_DRAMRST#_R 108 EVENT# 174 DDR_B_D34 C
36 VSS VSS 192 <19,23> DDR_DRAMRST#_R RESET# DQ32 173 DDR_B_D35
Layout Note: Layout Note: VSS VSS DQ33 DDR_B_D36
39 193 187
Place near JDIMM3.257,259 Place near JDIMM3.258 40 VSS VSS 196 254 DQ34 186 DDR_B_D32
VSS VSS <19,23,43> D_CK_SDATA SDA DQ35 DDR_B_D39
43 197 253 170
44 VSS VSS 201 <19,23,43> D_CK_SCLK SCL DQ36 169 DDR_B_D38
47 VSS VSS 202 SA2_CHB_DIM3 166 DQ37 183 DDR_B_D37
48 VSS VSS 205 SA1_CHB_DIM3 260 SA2 DQ38 182 DDR_B_D33
+2.5V +0.6VS_VTT 51 VSS VSS 206 SA0_CHB_DIM3 256 SA1 DQ39 179 DDR_B_DQS4
10uF*2 10uF*2 VSS VSS SA0 DQS4(T) DDR_B_DQS#4 DDR_B_DQS4 <9>
52 209 177
1uF*2 1uF*1 56 VSS VSS 210 DQS4#(C) DDR_B_DQS#4 <9>
57 VSS VSS 213 92 195 DDR_B_D40
VSS VSS CB0_NC DQ40 DDR_B_D41
1U_0402_6.3V6K
10U_0603_6.3V6M
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
10U_0603_6.3V6M
1 1 1 1 1 1 1 60 214 91 194
61 VSS VSS 217 101 CB1_NC DQ41 207 DDR_B_D42
VSS VSS CB2_NC DQ42 DDR_B_D43
CD37
CD40
CD41
CD35
CD36
CD38
CD39
64 218 105 208

2 2 2 2 2 2 2 68 VSS VSS 223 87 CB4_NC DQ44 190 DDR_B_D45
69 VSS VSS 226
For ECC DIMM 100 CB5_NC DQ45 203 DDR_B_D46
73 VSS VSS 230 97 CB7_NC DQ47 200 DDR_B_DQS5
77 VSS VSS 231 95 DQS8(T) DQS5(T) 198 DDR_B_DQS#5 DDR_B_DQS5 <9>
78 VSS VSS 234 DQS8#(C) DQS5#(C) DDR_B_DQS#5 <9>
81 VSS VSS 235 216 DDR_B_D48
82 VSS VSS 238 12 DQ48 215 DDR_B_D52
85 VSS VSS 239
+1.2V_VDDQ 33 DM0#/DBI0# DQ49 228 DDR_B_D50
86 VSS VSS 243 54 DM1#/DBI1# DQ50 229 DDR_B_D55
Layout Note: VSS VSS DM6#/DBI6# DQ55 DDR_B_DQS6
98 252 241 221
PLACE THE CAP WITHIN 200 MILS VSS VSS 96 DM7#/DBI7# DQS6(T) 219 DDR_B_DQS#6 DDR_B_DQS6 <9>
FROM THE JDIMM3 262 261 DM8#/DBI8# DQS6#(C) DDR_B_DQS#6 <9>
GND GND
B LOTES_ADDR0070-P009A 237 DDR_B_D61 B

DQ56 236 DDR_B_D57
CONN@ DQ57 DDR_B_D60
+0.6V_DDRB_VREFCA 249
2.2uF*1 DQ58 DDR_B_D56
250
0.1uF*1 DQ59 232 DDR_B_D62
Part Number:SP07001CEA0 DQ60 233 DDR_B_D59
2 2 DQ61 DDR_B_D63
245
CD42 CD43
Part Value:S SOCKET FOX_AS0A826-H4SB-7H 260P DDR4 DQ62 246 DDR_B_D58
DQ63 242 DDR_B_DQS7
0.1U_0402_10V6K 2.2U_0402_6.3V6M DQS7(T) DDR_B_DQS7 <9>
1 1 +1.2V_VDDQ 240 DDR_B_DQS#7
DQS7#(C) DDR_B_DQS#7 <9>
LOTES_ADDR0070-P009A
CONN@
2
Layout Note: DIMM Side CPU Side
2
CD44
Place near JDIMM3 @ 0.1U_0402_10V6K RD19
1
1K_0402_1%
+0.6V_DDRB_VREFCA +0.6V_B_VREFDQ
1
10uF*6
1 RD20 2
+1.2V_VDDQ 1uF*8 +1.2V_VDDQ 2_0402_1%
330uF*1 VREF traces should be at least 20 mils
2 wide with 20 mils spacing to other
2
2 1
signals
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
RD21 CD45
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD51 1K_0402_1% 0.1U_0402_10V6K CD55

1
CD54
CD46
CD47
CD49
CD50
CD52
CD53
CD48
0.1U_0402_10V6K 0.022U_0402_16V7K
1 2
CD56
CD59
CD62
CD63
CD61
CD60
CD57
CD58
A A
2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
RD22
24.9_0402_1%
@ @
1
DDRIV_CHB: DIMM0
5 4 3 2 1
A B C D E
+1.8VSDGPU_AON +1.8VSDGPU_AON
RVP1
10K_0804_8P4R_5%
5
UV1A VGA_OVERT# 8 1
VGA_ALERT 7 2
VCC
AN12 Part 1 of 7 PLTRST_VGA#_1V8 1 FRM_LCK# 6 3
<10> PEG_CTX_C_GRX_P0 PEX_RX0 DGPU_VID IN B VGA_GATE ACIN_BUF
AM12 P6 4 5 4
<10> PEG_CTX_C_GRX_N0 PEX_RX0_N GPIO0 GC6_FB_EN1V8 DGPU_VID <61> OUT Y
AN14 M3 2
GND
<10> PEG_CTX_C_GRX_P1 PEX_RX1 GPIO1 GPU_EVENT#_1 VGA@ +1.8VSDGPU_MAIN IN A 1
AM14 L6 DV8 2 1 VGA@
<10> PEG_CTX_C_GRX_N1 PEX_RX1_N GPIO2 GPU_EVENT# <20>
AP14 P5 CV201
<10> PEG_CTX_C_GRX_P2 PEX_RX2 GPIO3 1.8VSDGPU_MAIN_EN
AP15 P7 RB751S40T1G_SOD523-2 @ UV12 0.01U_0402_16V7K RVP2
<10> PEG_CTX_C_GRX_N2
3
AN15 PEX_RX2_N GPIO4 L7 FRM_LCK# 1.8VSDGPU_MAIN_EN <29> NL17SZ08DFT2G_SC70-5 2 @ 10K_0804_8P4R_5%
<10> PEG_CTX_C_GRX_P3 PEX_RX3 GPIO5 DGPU_PSI GPU_EVENT#_1
AM15 M7 8 1
<10> PEG_CTX_C_GRX_N3 PEX_RX3_N GPIO6 GPU_INV_PW M DGPU_PSI <61> VRAM_VREF_CTL
AN17 N8 7 2
<10> PEG_CTX_C_GRX_P4 PEX_RX4 GPIO7 VRAM_VDD_CTL GC6_FB_EN1V8
AM17 L3 6 3
<10> PEG_CTX_C_GRX_N4 PEX_RX4_N GPIO8 VGA_ALERT VRAM_VDD_CTL <59> VGA_GATE 1.8VSDGPU_MAIN_EN
AP17 M2 5 4
<10> PEG_CTX_C_GRX_P5 PEX_RX5 GPIO9 VRAM_VREF_CTL
AP18 L1
<10> PEG_CTX_C_GRX_N5 PEX_RX5_N GPIO10
2
1 AN18 M5 DGPU_ENVDD VRAM_VREF_CTL <30,31> VGA@ 1
<10> PEG_CTX_C_GRX_P6 PEX_RX6 GPIO11 ACIN_BUF
AM18 N3 DV2 2 1
GPIO
G
<10> PEG_CTX_C_GRX_N6 PEX_RX6_N GPIO12 GPU_ENBKL DGPU_AC_DETECT <39,50> VGA_ALERT SYS_PEX_RST_MON#
AN20 M4 1 6 RV1 2 VGA@ 1 10K_0402_5%
<10> PEG_CTX_C_GRX_P7 PEX_RX7 GPIO13 GPU_ALERT <39> VGA_I2CS_SDA
AM20 N4 1 2
D
RB751S40T1G_SOD523-2 RV2 VGA@ 1.8K_0402_1%
<10> PEG_CTX_C_GRX_N7 PEX_RX7_N GPIO14 VGA_I2CS_SCL
AP20 P2 VGA@ QV5B VGA@ RV3 1 VGA@ 2 1.8K_0402_1%
<10> PEG_CTX_C_GRX_P8 PEX_RX8 GPIO15 SYS_PEX_RST_MON# DGPU_PSI
AP21 R8 PJT138KA 2N SOT363-6 RV4 2 VGA@ 1 10K_0402_5%
<10> PEG_CTX_C_GRX_N8 PEX_RX8_N GPIO16 DGPU_EDP_HPD# GPU_PEX_RST_HOLD#
AN21 M6 RV82 2 VGA@ 1 10K_0402_5%
<10> PEG_CTX_C_GRX_P9 PEX_RX9 GPIO17 ALL_GPW RGD
AM21 R1
AN23 P3
<10> PEG_CTX_C_GRX_P10 PEX_RX10 GPIO19
5
AM23 P4
<10> PEG_CTX_C_GRX_N10 PEX_RX10_N GPIO20 +1.8VSDGPU_MAIN
AP23 P1 PCH side
G
<10> PEG_CTX_C_GRX_P11 PEX_RX11 GPIO21 DGPU_CLKREQ#
AP24 P8 4 3
<10> PEG_CTX_C_GRX_N11 PEX_RX11_N GPIO22 GPU_PEX_RST_HOLD# VGA_CLKREQ# <16>
AN24 T8
D
<10> PEG_CTX_C_GRX_P12 PEX_RX12 GPIO23
5
AM24 L2 QV5A VGA@ QV2A
AN26 R4 PJT138KA 2N SOT363-6 PJT138KA 2N SOT363-6
G
<10> PEG_CTX_C_GRX_P13 PEX_RX13 GPIO25 VGA_I2CS_SCL
AM26 R5 4 3
<10> PEG_CTX_C_GRX_N13 PEX_RX13_N GPIO26 HDMI_HPD_GPU# EC_SMB_CK2 <19,39,40,44>
AP26 U3
D
VGA@
<10> PEG_CTX_C_GRX_P14 PEX_RX14 GPIO27 +1.8VSDGPU_MAIN
AP27
<10> PEG_CTX_C_GRX_N14 PEX_RX14_N
AN27
<10> PEG_CTX_C_GRX_P15 PEX_RX15 +1.8VSDGPU_MAIN
AM27 AK9
<10> PEG_CTX_C_GRX_N15 PEX_RX15_N NC
2
AL10 QV2B
NC AL9 PJT138KA 2N SOT363-6
G
NC
1
AK14 AM9 PU at EC side VGA_I2CS_SDA 1 6
<10> PEG_CRX_C_GTX_P0 PEX_TX0 NC EC_SMB_DA2 <19,39,40,44>
AJ14 AN9
D
<10> PEG_CRX_C_GTX_N0 RV131 GPU_OVERT# <39> VGA@
AH14 PEX_TX0_N NC AG10 100K_0201_5%
<10> PEG_CRX_C_GTX_P1 PEX_TX1 NC
<10> PEG_CRX_C_GTX_N1 AG14 AP8 VGA@
3
AK15 PEX_TX1_N NC AK26
<10> PEG_CRX_C_GTX_P2
6 2
AJ15 PEX_TX2 NC AJ26 5 G
D
QV1A
<10> PEG_CRX_C_GTX_N2 PEX_TX2_N NC
AL16 27MHZ_10PF_XRCGB27M000F2P18R0
PCI EXPRESS
S
PJT138KA 2N SOT363-6
AK16 PEX_TX3 VGA_OVERT# 2 G
D
VGA@ XV1
<10> PEG_CRX_C_GTX_N3 <27> VGA_OVERT#
4
AK17 PEX_TX3_N S
AJ17 PEX_TX4 QV1B XTALOUT 2 RV80 1 XTALOUT_R 1 3 XTALIN
<10> PEG_CRX_C_GTX_N4
1
AH17 PEX_TX4_N AP9 PJT138KA 2N SOT363-6 0_0402_5% 1 3
<10> PEG_CRX_C_GTX_P5 PEX_TX5 TS_VREF NC NC
AG17 VGA@ VGA@
15P_0402_50V8J
12P_0402_50V8J
<10> PEG_CRX_C_GTX_N5 PEX_TX5_N 1 1
AK18 VGA@ VGA@
<10> PEG_CRX_C_GTX_P6 PEX_TX6 2 4
<10> PEG_CRX_C_GTX_N6 AJ18 VGA@
AL19 PEX_TX6_N CV1 CV2
<10> PEG_CRX_C_GTX_P7 PEX_TX7 +1.8VSDGPU_AON 2 2
AK19
<10> PEG_CRX_C_GTX_N7 PEX_TX7_N
AK20 unused pin PH 2K to 1V8AON
<10> PEG_CRX_C_GTX_P8 PEX_TX8
AJ20 Crystals must have a max ESR of 80 ohm
<10> PEG_CRX_C_GTX_P9 AH20 R7 RV86 1 VGA@ 2 2K_0402_5%
AG20 PEX_TX9 I2CB_SCL R6 RV85 1 VGA@ 2 2K_0402_5%
2 <10> PEG_CRX_C_GTX_N9 PEX_TX9_N I2CB_SDA 2
AK21
I2C
AJ21 R2 RV5 1 VGA@ 2 2K_0402_5% +1.8VSDGPU_MAIN

<10>
<10>
PEG_CRX_C_GTX_N10
PEG_CRX_C_GTX_P11
AL22 PEX_TX10_N I2CC_SCL R3 RV6 1 VGA@ 2 2K_0402_5% RESERVE FOR DIS eDP @
RVP3
AK22 PEX_TX11 I2CC_SDA
<10> PEG_CRX_C_GTX_N11 PEX_TX11_N VGA_I2CS_SCL +GPU_PLLVDD GPU_INV_PW M
AK23 T4 +3VS 1 8
<10> PEG_CRX_C_GTX_P12 PEX_TX12 I2CS_SCL VGA_I2CS_SDA GPU_ENBKL
AJ23 T3 2 7
<10> PEG_CRX_C_GTX_N12 PEX_TX12_N I2CS_SDA DGPU_ENVDD
AH23 VGA@ 3 6
<10> PEG_CRX_C_GTX_P13 PEX_TX13 +GPU_PLLVDD
AG23 LV1 1 2 4 5
1
<10> PEG_CRX_C_GTX_P14 AK24 TAI-TECH HCB1608KF-330T30 @
PEX_TX14
0.1U_0201_10V6K
4.7U_0402_6.3V6M
22U_0603_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
AJ24 1 1 1 1 1 SM01000JX00 +1.8VSDGPU_AON RG194
<10> PEG_CRX_C_GTX_N14 PEX_TX14_N 100K_0804_8P4R_5%
AL25 CV5 CV6 CV3 CV42 CV4 10K_0402_5%
AK25
5
VGA@ VGA@ VGA@ VGA@ VGA@ +1.8VSDGPU_AON
2
AD8 2 2 2 2 2 @
G
AJ11 XS_PLLVDD +1.8VSDGPU_AON GPU_INV_PW M 4 3 QV9A
NC Near PCH_BKL_PW M <18,33>
1
AE8
D
GPU VGA@ PJT138KA 2N SOT363-6
SP_PLLVDD
1
AL13 Near Near Near RG180
<16> CLK_PEG_VGA PEX_REFCLK
AK13 AD7 AD7 AD8 AE8 VGA@ 10K_0402_5% +1.8VSDGPU_AON @
<16> CLK_PEG_VGA# DGPU_CLKREQ# PEX_REFCLK_N VID_PLLVDD
AK12 CG340 RG195
+1.8VSDGPU_AON PEX_CLKREQ_N 2 1 10K_0402_5%
CLK
2
RV7 1 VGA@ 2 10K_0402_5% H3 XTALIN HDMI_HPD_GPU# @
2
XTAL_IN H2 XTALOUT RV9 0.1U_0201_10V6K
G
XTAL_OUT
5
10K_0402_5% GPU_ENBKL 1 6 QV9B
PLTRST_VGA#_1V8 XTAL_OUTBUFF1 ENBKL <18,39>
D
AJ12 J4 2 VGA@ PJT138KA 2N SOT363-6
VCC
1
AP29 PEX_RST_N XTAL_OUTBUFF H1 XTAL_SSIN 1 2 VGA@ HDMI_HPD_PCH 1 D
PEX_TREMP PEX_TERMP XTAL_SSIN <17,34> HDMI_HPD_PCH IN B DGPU_ENVDD CLOSE UX1
1 2 RV11 4 2 RV135 1 @ 2 0_0402_5%
PLTRST_VGA#_1V8 OUT Y PCH_ENVDD <18,33>
10K_0402_5% 2 G
GND
IN A
RV10 VGA@ S VGA@
3
2.49K_0402_1% QG5 +1.8VSDGPU_AON RG193 1 @ 2 10K_0402_5%
VGA@ MESS138W -G_SOT323-3
3
GP107-ES-A1_BGA908 UG28 DGPU_EDP_HPD#
@ NL17SZ08DFT2G_SC70-5 1.0 Modify
1
D
@ 2
EDP_HPD <17,33>
QG6 G
MESS138W -G_SOT323-3 S
3
+1.8VSDGPU_AON +1.8VSDGPU_AON
2
UV11
3 VGA@ RV83 3
5
NL17SZ08DFT2G_SC70-5 10K_0402_5%
@
VCC
1VS_DGPU_PG 1 +3VS
1
IN B 4 ALL_GPW RGD
2 OUT Y
1
GND
<59> 1.35VS_DGPU_PG IN A VGA@ +3VS

CV226
1
0.1U_0201_10V6K
3
2 RV106 RV108
10K_0402_5% 10K_0402_5%
5
VGA@ VGA@ VGA@
VCC
2
2
1.8VSDGPU_MAIN 1
IN B 4GPUCORE_EN
OUT Y GPUCORE_EN <29>
3
2
GND
PJT138KA 2N SOT363-6
5
D
IN A
G
for PEX_VDD dis-charge
6
S
1.8VSDGPU_MAIN_EN 2 G
D
QV7A UV10
GC6 2.0 function
3
4
QV7B S VGA@ NL17SZ08DFT2G_SC70-5
PJT138KA 2N SOT363-6 DV4 2 1
1
DGPU_PW R_EN <20> VGA_CORE_EN <29,61>
+3VS DV3 VGA@
GC6_FB_EN3V3 2 RB751S40T1G_SOD523-2 Enable: Vh:1.5V
1 +1.8VSDGPU_AON
1.35VSDGPU_PW R_EN <29> VGA@ Vl:0.7V
1
3 VGA@ +1.8VSDGPU_AON 2 1
<60> 1VS_DGPU_PG
RV113 RV105 2
1
1
4.7K_0402_5% BAV70W _SOT323-3 2 6.2K_0402_1%

RV111 VGA@ RV12 VGA@ CV197
1
10K_0402_5% 100K_0402_1% CV199 0.1U_0201_10V6K

3 2
VGA@ GC6_FB_EN3V3 VGA@ RV102 GPU_OVERT# DV7 1 2 1 VGA@

GC6_FB_EN3V3 <20> 0.1U_0201_10V6K
1@
1.0 Modify
10K_0402_5%
6 2
D
5 G @ UV9 @ RB751S40T1G_SOD523-2 VGA@
5
S PJT138KA 2N SOT363-6 NL17SZ08DFT2G_SC70-5 VGA@ DV5 1 2

1.0VSDGPU_EN <60>
2
GC6_FB_EN1V8 2 G
D
QV8A
GND VCC
4
QV8B S VGA@ PLTRST_VGA#_1V8 1 3 RB751S40T1G_SOD523-2

PJT138KA 2N SOT363-6 IN B 4 5
D
QV6A
G
VDDS delay rename from VGA_CORE_S_EN
1
VGA@ GC6_FB_EN1V8# 2 OUT Y S PJT138KA 2N SOT363-6 1 2

IN A @ RV103 24.9K_0402_1%
1.33ms
2
4
+1.8VSDGPU_AON @ VGA@
2 2
CV227
3
6
+1.8VSDGPU_AON CV224 0.1U_0201_10V6K CV196

1
UV2 GC6_FB_EN1V8 2 G
D
0.1U_0201_10V6K 1 0.22U_0402_16V7K
4 NL17SZ08DFT2G_SC70-5 RV100 S 1@ 1 VGA@ 4
5
VGA@ 10K_0402_5%
VGA_CORE_PG <61>
1
@ QV6B @ remove DV6/RV104

VCC
PLT_RST# 1 PJT138KA 2N SOT363-6 1.A Modify

2
<17> PLT_RST# IN B PLTRST_VGA#_1V8

4
DGPU_HOLD_RST# 2 OUT Y
GND
<20> DGPU_HOLD_RST# IN A
Thermal shutdown protection marge NVVDD remove VGA_CORE_S_PG
RV16 1 VGA@ 2 100K_0402_5%
3
CV200 1 2 @ 0.1U_0201_10V6K

N17P PEG 1/7
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
A B C D E
A B C D E
GDDR5 Mode H Mapping

UV1B UV1C
<30> FBA_D[63..0] FBA_CMD[31..0] <30> <31> FBB_D[63..0] FBB_CMD[31..0] <31> DATA Bus
Part 2 of 7 Part 3 of 7
FBA_D0 L28 U30 FBA_CMD0 FBB_D0 G9 D13 FBB_CMD0 Address
FBA_D1 FBA_D0 FBA_CMD0 FBA_CMD1 FBB_D1 FBB_D0 FBB_CMD0 FBB_CMD1
0..31 32..63
M29 T31 E9 E14
FBA_D2 L29 FBA_D1 FBA_CMD1 U29 FBA_CMD2 FBB_D2 G8 FBB_D1 FBB_CMD1 F14 FBB_CMD2
CMD0 CS#
M28 R34 F9 A12
FBA_D4 N31 FBA_D3 FBA_CMD3 R33 FBA_CMD4 FBB_D4 F11 FBB_D3 FBB_CMD3 B12 FBB_CMD4
CMD1 A3_BA3
P29 U32 G11 C14
FBA_D6 R29 FBA_D5 FBA_CMD5 U33 FBA_CMD6 FBB_D6 F12 FBB_D5 FBB_CMD5 B14 FBB_CMD6
CMD2 A2_BA0
P28 U28 G12 G15
FBA_D8 J28 FBA_D7 FBA_CMD7 V28 FBA_CMD8 FBB_D8 G6 FBB_D7 FBB_CMD7 F15 FBB_CMD8
CMD3 A4_BA2
H29 V29 F5 E15
FBA_D10 J29 FBA_D9 FBA_CMD9 V30 FBA_CMD10 FBB_D10 E6 FBB_D9 FBB_CMD9 D15 FBB_CMD10
1 FBA_D11 FBA_D10 FBA_CMD10 FBA_CMD11 FBB_D11 FBB_D10 FBB_CMD10 FBB_CMD11
CMD4 A5_BA1 1
H28 U34 F6 A14
FBA_D12 G29 FBA_D11 FBA_CMD11 U31 FBA_CMD12 FBB_D12 F4 FBB_D11 FBB_CMD11 D14 FBB_CMD12
CMD5 WE#
E31 V34 G4 A15
FBA_D14 E32 FBA_D13 FBA_CMD13 V33 FBA_CMD14 FBB_D14 E2 FBB_D13 FBB_CMD13 B15 FBB_CMD14
CMD6 A7_A8
F30 Y32 F3 C17
FBA_D16 C34 FBA_D15 FBA_CMD15 AA31 FBA_CMD16 FBB_D16 C2 FBB_D15 FBB_CMD15 D18 FBB_CMD16
CMD7 A6_A11
D32 AA29 D4 E18
FBA_D18 B33 FBA_D17 FBA_CMD17 AA28 FBA_CMD18 FBB_D18 D3 FBB_D17 FBB_CMD17 F18 FBB_CMD18
CMD8 ABI#
C33 AC34 C1 A20
FBA_D20 F33 FBA_D19 FBA_CMD19 AC33 FBA_CMD20 FBB_D20 B3 FBB_D19 FBB_CMD19 B20 FBB_CMD20
CMD9 A12_RFU
F32 AA32 C4 C18
FBA_D22 H33 FBA_D21 FBA_CMD21 AA33 FBA_CMD22 FBB_D22 B5 FBB_D21 FBB_CMD21 B18 FBB_CMD22
CMD10 A0_A10
H32 Y28 C5 G18
FBA_D24 P34 FBA_D23 FBA_CMD23 Y29 FBA_CMD24 FBB_D24 A11 FBB_D23 FBB_CMD23 G17 FBB_CMD24
CMD11 A1_A9
P32 W31 C11 F17
FBA_D26 P31 FBA_D25 FBA_CMD25 Y30 FBA_CMD26 FBB_D26 D11 FBB_D25 FBB_CMD25 D16 FBB_CMD26
CMD12 RAS#
P33 AA34 B11 A18
MEMORY INTERFACE B
FBA_D28 L31 FBA_D27 FBA_CMD27 Y31 FBA_CMD28 FBB_D28 D8 FBB_D27 FBB_CMD27 D17 FBB_CMD28
CMD13 RST#
L34 Y34 A8 A17
FBA_D30 L32 FBA_D29 FBA_CMD29 Y33 FBA_CMD30 FBB_D30 C8 FBB_D29 FBB_CMD29 B17 FBB_CMD30
CMD14 CKE#
L33 V31 B8 E17
FBA_D32 AG28 FBA_D31 FBA_CMD31 R28 FBB_D32 F24 FBB_D31 FBB_CMD31 G14
FBA_D33 FBA_D32 FBA_CMD32 FBB_D33 FBB_D32 FBB_CMD32 CMD15 CAS#
AF29 AC28 G23 G20
FBA_D34 AG29 FBA_D33 MEMORY INTERFACE FBA_CMD33 R32 FBA_DEBUG0 @ TV1 FBB_D34 E24 FBB_D33 FBB_CMD33 C12 FBB_DEBUG0
FBA_D35 FBA_D34 FBA_CMD34 FBA_DEBUG1 FBB_D35 FBB_D34 FBB_CMD34 FBB_DEBUG1
@ TV2 CMD16 CS#
AF28 AC32 @ TV3 G24 C20 @ TV4
FBA_D36 AD30 FBA_D35 FBA_CMD35 FBB_D36 D21 FBB_D35 FBB_CMD35
FBA_D37 FBA_D36 FBB_D37 FBB_D36 CMD17 A3_BA3
AD29 E21
FBA_D38 AC29 FBA_D37 FBB_D38 G21 FBB_D37
AD28 F21
FBA_D40 AJ29 FBA_D39 FBB_D40 G27 FBB_D39
AK29 D27
FBA_D42 AJ30 FBA_D41 FBB_D42 G26 FBB_D41
AK28 E27
FBA_D44 AM29 FBA_D43 FBB_D44 E29 FBB_D43
FBA_D45 FBA_D44 FBB_D45 FBB_D44 CMD21 WE#
AM31 R30 F29 D12
2 FBA_D46 AN29 FBA_D45 FBA_CLK0 R31 FBA_CLKA0 <30> FBB_D46 E30 FBB_D45 FBB_CLK0 E12 FBB_CLKA0 <31> 2
FBA_D47 FBA_D46 FBA_CLK0_N FBA_CLKA0# <30> FBB_D47 FBB_D46 FBB_CLK0_N FBB_CLKA0# <31> CMD22 A7_A8
AM30 AB31 D30 E20
FBA_D48 AN31 FBA_D47 FBA_CLK1 AC31 FBA_CLKA1 <30> FBB_D48 A32 FBB_D47 FBB_CLK1 F20 FBB_CLKA1 <31>
FBA_D49 FBA_D48 FBA_CLK1_N FBA_CLKA1# <30> FBB_D49 FBB_D48 FBB_CLK1_N FBB_CLKA1# <31> CMD23 A6_A11
AN32 C31
FBA_D49 FBB_D49
A
FBA_D50 AP30 FBB_D50 C32

FBA_D51 FBA_D50 FBB_D51 FBB_D50 CMD24 ABI#
AP32 B32
FBA_D52 AM33 FBA_D51 K31 FBB_D52 D29 FBB_D51 F8
FBA_D53 FBA_D52 FBA_WCK01 FBA_WCK01 <30> FBB_D53 FBB_D52 FBB_WCK01 FBB_WCK01 <31> CMD25 A12_RFU
AL31 L30 A29 E8
FBA_D54 AK33 FBA_D53 FBA_WCK01_N H34 FBA_WCK01# <30> FBB_D54 C29 FBB_D53 FBB_WCK01_N A5 FBB_WCK01# <31>
FBA_D55 FBA_D54 FBA_WCK23 FBA_WCK23 <30> FBB_D55 FBB_D54 FBB_WCK23 FBB_WCK23 <31> CMD26 A0_A10
AK32 J34 B29 A6
FBA_D56 AD34 FBA_D55 FBA_WCK23_N AG30 FBA_WCK23# <30> FBB_D56 B21 FBB_D55 FBB_WCK23_N D24 FBB_WCK23# <31>
FBA_D57 FBA_D56 FBA_WCK45 FBA_WCK45 <30> FBB_D57 FBB_D56 FBB_WCK45 FBB_WCK45 <31> CMD27 A1_A9
AD32 AG31 C23 D25
FBA_D58 AC30 FBA_D57 FBA_WCK45_N AJ34 FBA_WCK45# <30> FBB_D58 A21 FBB_D57 FBB_WCK45_N B27 FBB_WCK45# <31>
FBA_D59 FBA_D58 FBA_WCK67 FBA_WCK67 <30> FBB_D59 FBB_D58 FBB_WCK67 FBB_WCK67 <31> CMD28 RAS#
AD33 AK34 C21 C27
FBA_D60 FBA_D59 FBA_WCK67_N FBA_WCK67# <30> FBB_D60 FBB_D59 FBB_WCK67_N FBB_WCK67# <31>
AF31 B24 CMD29 RST#
FBA_D61 AG34 FBA_D60 FBB_D61 C24 FBB_D60
FBA_D62 AG32 FBA_D61 FBB_D62 B26 FBB_D61
FBA_D63 FBA_D62 FBB_D63 FBB_D62 CMD30 CKE#
AG33 J30 C26 D6
FBA_D63 FBA_WCKB01 J31 FBB_D63 FBB_WCKB01 D7
<30> FBA_DBI[7..0] FBA_DBI0 FBA_WCKB01_N <31> FBB_DBI[7..0] FBB_DBI0 FBB_WCKB01_N CMD31 CAS#
P30 J32 E11 C6
FBA_DBI1 F31 FBA_DQM0 FBA_WCKB23 J33 FBB_DBI1 E3 FBB_DQM0 FBB_WCKB23 B6
FBA_DBI2 F34 FBA_DQM1 FBA_WCKB23_N AH31 FBB_DBI2 A3 FBB_DQM1 FBB_WCKB23_N F26
FBA_DBI3 M32 FBA_DQM2 FBA_WCKB45 AJ31 FBB_DBI3 C9 FBB_DQM2 FBB_WCKB45 E26
FBA_DBI4 AD31 FBA_DQM3 FBA_WCKB45_N AJ32 FBB_DBI4 F23 FBB_DQM3 FBB_WCKB45_N A26
FBA_DBI5 AL29 FBA_DQM4 FBA_WCKB67 AJ33 FBB_DBI5 F27 FBB_DQM4 FBB_WCKB67 A27
FBA_DBI6 AM32 FBA_DQM5 FBA_WCKB67_N FBB_DBI6 C30 FBB_DQM5 FBB_WCKB67_N
FBA_DBI7 AF34 FBA_DQM6 FBB_DBI7 A24 FBB_DQM6
FBA_DQM7 FBB_DQM7
<30> FBA_EDC[7..0] FBA_EDC0 M31 E1 GPU_BUFRST# <31> FBB_EDC[7..0] FBB_EDC0 D10
@ TV9
FBA_EDC1 G31 FBA_DQS_WP0 BUFRST_N +1.8VSDGPU_MAIN FBB_EDC1 D5 FBB_DQS_WP0
FBA_EDC2 E33 FBA_DQS_WP1 FBB_EDC2 C3 FBB_DQS_WP1
FBA_EDC3 M33 FBA_DQS_WP2 VGA@ FBB_EDC3 B9 FBB_DQS_WP2
FBA_EDC4 AE31 FBA_DQS_WP3 K27 +FB_PLLAVDD LV3 1 2 FBB_EDC4 E23 FBB_DQS_WP3 H17 +FB_PLLAVDD
FBA_EDC5 AK30 FBA_DQS_WP4 FB_REFPLL_AVDD FBB_EDC5 FBB_DQS_WP4 FBB_PLL_AVDD
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 TAI-TECH HCB1608KF-330T30 E28 1 1
FBA_EDC6 AN33 FBA_DQS_WP5 FBB_EDC6 FBB_DQS_WP5
22U_0603_6.3V6M
SM01000JX00 B30
3 FBA_EDC7 AF33 FBA_DQS_WP6 CV9 CV10 CV11 FBB_EDC7 A23 FBB_DQS_WP6 CV12 CV7 3
FBA_DQS_WP7 U27 VGA@ VGA@ VGA@ FBB_DQS_WP7 VGA@ VGA@
M30 FBA_PLL_AVDD 2 2 2 D9 2 2
H30 FBA_DQS_RN0 +GPU_PLLVDD E4 FBB_DQS_RN0
E34 FBA_DQS_RN1 B2 FBB_DQS_RN1
M34 FBA_DQS_RN2 H26 A9 FBB_DQS_RN2
AF30 FBA_DQS_RN3 GPCPLL_AVDD D22 FBB_DQS_RN3
AK31 FBA_DQS_RN4 D28 FBB_DQS_RN4
FBA_DQS_RN5 Near U27 Near FBB_DQS_RN5
AM34 K27 A30 Near
AF32 FBA_DQS_RN6 B23 FBB_DQS_RN6
FBA_DQS_RN7 FBB_DQS_RN7 H17
GP107-ES-A1_BGA908 GP107-ES-A1_BGA908
@ @
+GPU_PLLVDD +1.35VSDGPU
+1.35VSDGPU
FBA_CMD14 2 VGA@ 1
FBB_CMD14
CV195
0.1U_0201_10V6K
CV194
0.1U_0201_10V6K
CV124
0.1U_0201_10V6K
RV87 10K_0402_5% 2 VGA@ 1

FBA_CMD30 2 VGA@ 1 RV91 10K_0402_5%
1 1 1 CKE FBB_CMD30
RV88 10K_0402_5% signal 2 VGA@ 1
RV92 10K_0402_5%
VGA@
VGA@
VGA@
2 2 2 FBA_CMD13 2 VGA@ 1
RV89 10K_0402_5% FBB_CMD13 2 VGA@ 1
FBA_CMD29 2 VGA@ 1 RV93 10K_0402_5%
RST
RV90 10K_0402_5% FBB_CMD29 2 VGA@ 1
signal
Near RV94 10K_0402_5%
H26
4 4

N17P VRAM 2/7
A B C D E
A B C D E
UV1D
Part 4 of 7
AL6
IFPA_L0 +1.8VSDGPU_AON
MULTI LEVELFor N17x
AK6 AC6
AN5 IFPA_L0_N
IFPA_L1
NC
NC
AJ28 STRAPS
AM5 AJ4
AP3 IFPA_L1_N NC AJ5
AN3 IFPA_L2 NC AL11 strap0 strap1 strap2 strap3 strap4 strap5
AM6 IFPA_L2_N NC C15
IFPA_L3 NC
2
AN6 D19 RV26 RV27 RV28 RV29 RV30 RV78 RV31 RV32 RV33
IFPA_L3_N NC D20 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%
NC
NC D23 @ @ @ X76@ @ @ X76@ X76@ X76@
1 NC 1
AN8 D26
AM8 IFPB_L0 NC V32
1
AM7 IFPB_L0_N NC
AL7 IFPB_L1
AP6 IFPB_L1_N STRAP0
AP5 IFPB_L2 STRAP1 ROM_SI
AJ9 IFPB_L2_N STRAP2 ROM_SO
AH9 IFPB_L3 STRAP3 ROM_SCLK
IFPB_L3_N STRAP4
H31 STRAP5
AK1 FB_VREF
<34> GPU_DP2_P0 IFPC_L0
2
AJ1
<34> GPU_DP2_N0 IFPC_L0_N
2
AJ3 L4 VCCSENSE_VGA RV34 RV35 RV36 RV37 RV38 RV79 RV39 RV40 RV41
HDMI <34>
<34>
<34>
GPU_DP2_P1
GPU_DP2_N1
GPU_DP2_P2
AJ2
AH3
AH4
IFPC_L1
IFPC_L1_N
IFPC_L2
VDD_SENSE
L5 VSSSENSE_VGA
VCCSENSE_VGA <61> 100K_0402_5%
@
100K_0402_5%
@
100K_0402_5%
@
100K_0402_5%
@
100K_0402_5% 100K_0402_5%
X76@ X76@
100K_0402_5%
@
100K_0402_5%
@
100K_0402_5%
@
2.0 <34> GPU_DP2_N2 VSSSENSE_VGA <61>
1
AG5 IFPC_L2_N GND_SENSE
<34> GPU_DP2_P3
1
AG4 IFPC_L3
<34> GPU_DP2_N3 IFPC_L3_N
AM1
<7> GPU_EDP_TXP0 IFPD_L0
AM2
<7> GPU_EDP_TXN0
AM3 IFPD_L0_N TEST
<7> GPU_EDP_TXP1 IFPD_L1 AK11
AM4 TESTMODE RV42 1 VGA@ 2 10K_0402_5%
eDP <7>
<7>
<7>
GPU_EDP_TXN1
GPU_EDP_TXP2
GPU_EDP_TXN2
AL3
AL4
AK4
IFPD_L1_N
IFPD_L2
IFPD_L2_N
NVJTAG_SEL
JTAG_TCK
AM10
AM11
JTAG_TCK_VGA
JTAG_TDI
@ TV5
@ TV6
<7> GPU_EDP_TXP3 IFPD_L3 JTAG_TDI JTAG_TDO
AK5 AP12 @ TV7
<7> GPU_EDP_TXN3 IFPD_L3_N JTAG_TDO JTAG_TMS
AP11 @ TV8
JTAG_TMS AN11 JTAG_RST RV43 1 VGA@ 210K_0402_5%
AD2 JTAG_TRST_N
IFPE_L0
LVDS/TMDS
AD3
AD1 IFPE_L0_N
AC1 IFPE_L1
AC2 IFPE_L1_N
2 AC3 IFPE_L2 2
AC4 IFPE_L2_N SERIAL
AC5 IFPE_L3 H6
IFPE_L3_N ROM_CS_N H4 ROM_SCLK
ROM_SCLK H5 ROM_SI
AE3 ROM_SI H7 ROM_SO
AE4 IFPF_L0 ROM_SO
AF4 IFPF_L0_N
AF5 IFPF_L1
AD4 IFPF_L1_N
AD5 IFPF_L2
AG1 IFPF_L2_N
AF1 IFPF_L3 GENERAL
IFPF_L3_N
AJ6 M1 VGA_OVERT#
IFPA_AUX_SCL OVERT VGA_OVERT# <25>
AH6
IFPA_AUX_SDA_N
AK8
AL8 IFPB_AUX_SCL
IFPB_AUX_SCL_N
AG3 J2 STRAP0
<34> GPU_DP2_CTRL_CLK IFPC_AUX_SCL STRAP0
AG2 J7 STRAP1
<34> GPU_DP2_CTRL_DAT IFPC_AUX_SDA_N STRAP1 J6 STRAP2
AK3 STRAP2 J5 STRAP3
<7> GPU_EDP_AUXP IFPD_AUX_SCL STRAP3
AK2 J3 STRAP4
<7> GPU_EDP_AUXN IFPD_AUX_SDA_N STRAP4 J1 STRAP5
AB3 STRAP5
AB4 IFPE_AUX_SCL
IFPE_AUX_SDA_N K3
AF3 THERMDP K4
AF2 IFPF_AUX_SCL THERMDN
IFPF_AUX_SDA_N
3 3
GP107-ES-A1_BGA908
@
SMB_ATL_ADDR
* LOW Single GPU

High Dual GPU
DEVID_SEL
* LOW Orig. Device ID

High Support G-Sync GPUID
VGA_DEVICE
LOW 3D Device
High VGA Device
*
PCIE_CFG
* LOW Normal signal swing

High Reduce the signal amplitude
4 4
HDMI audio output

N17P STRAP 3/7
A B C D E
A B C D E
+1.35VSDGPU
Under
CHA GPU
/6*1uF+2*10uF 1*22uF+1*10uF+2*4.7uF+4*1uF
1 1 1 1 1 1 1 1 Under Near
+1.0VSDGPU
1U_0402_6.3V6K GPU GPU
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
CV18 CV19 CV20 CV21 CV22 CV23 CV24 CV26
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2 2 2
1 1 1 1 1 1 1
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
CV134 CV13 CV14 CV33 CV29 CV16 CV28
22U_0603_6.3V6M
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ CV34
2 2 2 2 2 2 2 VGA@
UV1E 2
1 1
CHB Part 5 of 7
/6*1uF+2*10uF
AA27 AG19
AA30 FBVDDQ_0 PEX_DVDD AG21
AB27 FBVDDQ_1 PEX_DVDD AG22
1 1 1 1 1 1 1 1 FBVDDQ_2 PEX_DVDD
AB33 AG24
FBVDDQ_3 PEX_DVDD
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
CV126 CV127 CV128 CV129 CV130 CV131 CV132 CV133 AC27 AH21
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ AD27 FBVDDQ_4 PEX_DVDD AH25
2 2 2 2 2 2 2 2 AE27 FBVDDQ_5 PEX_DVDD
FBVDDQ_6 1*22uF+2*10uF+2*4.7uF+4*1uF
AF27
AG27 FBVDDQ_7 AG13
B13 FBVDDQ_8 PEX_HVDD AG15 +1.8VSDGPU_MAIN
FBVDDQ_9 PEX_HVDD Under Near
B19 AG16 GPU GPU
E13 FBVDDQ_11 PEX_HVDD AG18
E19 FBVDDQ_12 PEX_HVDD AG25
FBVDDQ_14 PEX_HVDD 1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
H10 AH15 CV137 CV136 CV25 CV15 CV17 CV32 CV30 CV27 CV31
H11 FBVDDQ_15 PEX_HVDD AH18
H12 FBVDDQ_16 PEX_HVDD AH26 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
H13 FBVDDQ_17 PEX_HVDD AH27 2 2 2 2 2 2 2 2 2
GPU FBVDDQ_18 PEX_HVDD
/5*22uF+2*10uF H14 AJ27
H18 FBVDDQ_19 PEX_HVDD AK27
H19 FBVDDQ_22 PEX_HVDD AL27
1 1 1 1 1 1 1 FBVDDQ_23 PEX_HVDD
H20 AM28
POWER
FBVDDQ_24 PEX_HVDD
10U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
CV37 CV38 CV202 CV36 CV39 CV40 CV41 H21 AN28
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ H22 FBVDDQ_25 PEX_HVDD
2 2 2 2 2 2 2 H23 FBVDDQ_26
H24 FBVDDQ_27
H8 FBVDDQ_28 AH12
FBVDDQ_29 PEX_PLL_HVDD +1.8VSDGPU_MAIN
H9 1
FBVDDQ_30
0.1U_0201_10V6K
L27
M27 FBVDDQ_31 CV43
N27 FBVDDQ_32 AG12 VGA@
Place close to FBVDDQ_33 NC 2
Near
GPU P27 AG26 GPU
R27 FBVDDQ_34 NC AG7
2 T27 FBVDDQ_35 NC AN2 +1.8VSDGPU_AON 2
FBVDDQ_36 NC 2*4.7uF+1*1uF+2*0.1uF
T30
T33 FBVDDQ_37
1 1 1 1 1 1 1 FBVDDQ_38
Y27 1 1 1 1
FBVDDQ_43
10U_0603_6.3V6M
22U_0603_6.3V6M
0.1U_0201_10V6K
10U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.1U_0201_10V6K
4.7U_0402_6.3V6M
CV217 CV218 CV219 CV220 CV221 CV222 CV223
1U_0402_6.3V6K
@ @ @ @ @ @ @ J8 CV135 CV49 CV51 CV50
2 2 2 2 2 2 2 1V8_AON K8 VGA@ VGA@ VGA@ VGA@
1V8_AON L8 2 2 2 2
B16 VDD18 M8
E16 FBVDDQ VDD18
H15 FBVDDQ
H16 FBVDDQ
V27 FBVDDQ AH8
near GPU for NV update spec 1210 FBVDDQ IFPAB_PLLVDD Under Near
W27 AJ8 GPU GPU
W30 FBVDDQ IFPAB_RSET +1.8VSDGPU_MAIN
+1.35VSDGPU FBVDDQ 2*4.7uF+1*1uF+2*0.1uF
W33
FBVDDQ AF7
IFPCD_PLLVDD
2
AF8 2 1 1 1 1 1
IFPCD_RSET
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0402_6.3V6M
RV45 RG38 1K_0402_1%
1U_0402_6.3V6K
@ 0_0402_5% CV52 CV53 CV54 CV55
AB8 VGA@ VGA@ VGA@ VGA@
IFPEF_PLLVDD AD6 2 1 2 2 2 2
1
FB_VDDQ_SENSE F1 IFPEF_RSET RG182 1K_0402_1%

<59> FB_VDDQ_SENSE FB_VDDQ_SENSE
TV10@ FB_GND_SENSE F2 Under

PROBE_FB_GND
GPU Near
+1.35VSDGPU AG8
FB_CAL_PD_VDDQ IFP_IOVDD GPU
RV47 1 VGA@ 2 40.2_0402_1% J27 AG9
FB_CAL_PD_VDDQ IFP_IOVDD AG6
IFP_IOVDD AF6
FB_CAL_PU_GND IFP_IOVDD +GPU_PLLVDD
RV48 1 VGA@ 2 40.2_0402_1% H27 AC7
FB_CAL_PU_GND IFP_IOVDD AC8
IFP_IOVDD 1 1
0.1U_0201_10V6K
0.1U_0201_10V6K
1 VGA@ 2 FB_CAL_TERM_GND H25 CV215 CV216
3 RV49 60.4_0402_1% FB_CAL_TERM_GND VGA@ VGA@ 3
2 2
Under GPU
1 per ball
GP107-ES-A1_BGA908 3*4.7uF+3*1uF+6*0.1uF +1.0VSDGPU
@
1 1 1 1 1 1
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CV214 CV213 CV212 CV205 CV204 CV203
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2
Near
GPU
1 1 1 1 1 1
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
CV210 CV211 CV209 CV208 CV207 CV206
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
2 2 2 2 2 2
Under GPU 1
4 per ball 4

N17P POWER 4/7
A B C D E
A B C D E
N17P VDDS UV1F

1uF*5/4.7uF*5 (under GPU)
330uF*1/22uF*3/10uF*2/4.7uF*2 Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
AA18 GND_1 GND_101 D33
AA20 GND_2 GND_102 E10
AA22 GND_3 GND_103 E22
AB12 GND_4 GND_104 E25
UV1G AB14 GND_5 GND_105 E5
+VGA_CORE +VGA_CORE AB16 GND_6 GND_106 E7
AB19 GND_7 GND_107 F28
AA14 Part 7 of 7 P23 AB2 GND_8 GND_108 F7
AA21 VDD_1 VDDS P19 AB21 GND_9 GND_109 G10
AB13 VDD_4 VDDS AA12 A33 GND_10 GND_110 G13
1 VDD_6 VDDS GND_11 GND_111 1
AB15 AA16 AB23 G16
AB17 VDD_7 VDDS AA19 AB28 GND_12 GND_112 G19
AB18 VDD_8 VDDS AA23 AB30 GND_13 GND_113 G2
AB20 VDD_9 VDDS AC14 AB32 GND_14 GND_114 G22
AB22 VDD_10 VDDS AC21 AB5 GND_15 GND_115 G25
AC12 VDD_11 VDDS M14 AB7 GND_16 GND_116 G28
AC16 VDD_12 VDDS M21 AC13 GND_17 GND_117 G3
AC19 VDD_14 VDDS P12 AC15 GND_18 GND_118 G30
AC23 VDD_15 VDDS P16 AC17 GND_19 GND_119 G32
M12 VDD_17 VDDS W21 AC18 GND_20 GND_120 G33
M16 VDD_18 VDDS W14 AA13 GND_21 GND_121 G5
M19 VDD_20 VDDS V18 AC20 GND_22 GND_122 G7
M23 VDD_21 VDDS U17 AC22 GND_23 GND_123 K2
N13 VDD_23 VDDS T21 AE2 GND_24 GND_124 K28
N15 VDD_24 VDDS T14 AE28 GND_25 GND_125 K30
N17 VDD_25 VDDS AE30 GND_26 GND_126 K32
N18 VDD_26 AE32 GND_27 GND_127 K33
N20 VDD_27 U1 AE33 GND_28 GND_128 K5
VDD_28 VDDS_SENSE
NVVDD & NVVDDS merge GND_29 GND_129
N22 U2 confirm NV nc or not AE5 K7
POWER
P14 VDD_29 GNDS_SENSE AE7 GND_30 GND_130 M13
P21 VDD_31 +1.35VSDGPU AH10 GND_31 GND_131 M15
R13 VDD_34 +VGA_CORE AA15 GND_32 GND_132 M17
R15 VDD_36 U4 AH13 GND_33 GND_133 M18
VDD_37 XVDD GND_34 GND_134
2
R17 U5 +5VS VGA@ AH16 M20
R18 VDD_38 XVDD U6 RV116 AH19 GND_35 GND_135 M22
R20 VDD_39 XVDD U7 20_0402_5% AH2 GND_36 GND_136 N12
2
R22 U8 AH22 N14
T12 VDD_41 XVDD V1 RV115 AH24 GND_38 GND_138 N16
1
T16 VDD_42 XVDD V2 100K_0402_5% +1.35VSDGPU_R AH28 GND_39 GND_139 N19
T19 VDD_44 XVDD V3 VGA@ AH29 GND_40 GND_140 N2
6
T23 V4 D AH30 N21
1
U13 VDD_47 XVDD V5 1.35VSDGPU_PWR_EN# 2 AH32 GND_42 GND_142 N23
U15 VDD_48 XVDD V6 G AH33 GND_43 GND_143 N28
GND
3
U18 V7 D AH5 N30
U20 VDD_51 XVDD V8 5 S AH7 GND_45 GND_145 N32
<25,59> 1.35VSDGPU_PWR_EN
1
2 U22 VDD_52 XVDD W2 G QV11A AJ7 GND_46 GND_146 N33 2
V13 VDD_53 XVDD W3 2N7002KDW_SOT363-6 AK10 GND_47 GND_147 N5
V15 VDD_54 XVDD W4 S VGA@ AK7 GND_48 GND_148 N7
4
V17 VDD_55 XVDD W5 QV11B AL12 GND_49 GND_149 P13
V20 VDD_56 XVDD W7 AL14 GND_50 GND_150 P15
VDD_58 XVDD 2N7002KDW_SOT363-6 GND_51 GND_151
V22 W8 VGA@ AL15 P17
W12 VDD_59 XVDD AL17 GND_52 GND_152 P18
W16 VDD_60 AL18 GND_53 GND_153 P20
W19 VDD_62 Y1 AL2 GND_54 GND_154 P22
W23 VDD_63 XVDD Y2 +VGA_CORE AL20 GND_55 GND_155 R12
Y13 VDD_65 XVDD Y3 AL21 GND_56 GND_156 R14
Y15 VDD_66 XVDD Y4 AL23 GND_57 GND_157 R16
2
Y17 Y5 +5VS VGA@ AL24 R19
Y18 VDD_68 XVDD Y6 RV118 AL26 GND_59 GND_159 R21
Y20 VDD_69 XVDD Y7 20_0402_5% AL28 GND_60 GND_160 R23
2
Y22 Y8 AL30 T13
VDD_71 XVDD RV117 AL32 GND_62 GND_162 T15
1
100K_0402_5% +VGA_CORE_R AL33 GND_63 GND_163 T17
AA1 VGA@ AL5 GND_64 GND_164 T18
XVDD GND_65 GND_165
6
AA2 D AM13 T2
1
XVDD AA3 NVVDD_EN# 2 AM16 GND_66 GND_166 T20
XVDD AA4 G AM19 GND_67 GND_167 T22
XVDD GND_68 GND_168
3
AA5 D AM22 AG11
XVDD AA6 5 S AM25 GND_69 GND_169 T28
<25,61> VGA_CORE_EN
1
XVDD AA7 G QV10A AN1 GND_70 GND_170 T32
XVDD AA8 2N7002KDW_SOT363-6 AN10 GND_71 GND_171 T5
XVDD S VGA@ AN13 GND_72 GND_172 T7
4
QV10B AN16 GND_73 GND_173 U12
AN19 GND_74 GND_174 U14
2N7002KDW_SOT363-6 GND_75 GND_175
VGA@ AN22 U16
GP107-ES-A1_BGA908 AN25 GND_76 GND_176 U19
AN30 GND_77 GND_177 U21
@ GND_78 GND_178
AN34 U23
AN4 GND_79 GND_179 V12
AN7 GND_80 GND_180 V14
+1.8V_AON/+1.8V_MAIN
3 AP2 GND_81 GND_181 V16 3
AP33 GND_82 GND_182 V19
B1 GND_83 GND_183 V21
B10 GND_84 GND_184 V23
B22 GND_85 GND_185 W13
DVT +1.8VSDGPU_AON GND_86 GND_186
B25 W15
+1.8VALW UG27 B28 GND_87 GND_187 W17
1 14 B31 GND_88 GND_188 W18
2 VIN1 VOUT1 13 B34 GND_89 GND_189 W20
VIN1 VOUT1 +1.0VSDGPU GND_90 GND_190
10U_0603_6.3V6M
CG335 220P_0402_50V8J B4 W22

1V8_AON_EN 3 12 1 2 B7 GND_91 GND_191 W28
ON1 CT1 1 GND_92 GND_192
+1.8VSDGPU_AON +5VALW
CG334
C10 Y12
RG1791 @ 2 4 11 C13 GND_93 GND_193 Y14
VGA@
VBIAS GND GND_94 GND_194
2
10K_0402_5% CG336 220P_0402_50V8J VGA@ VGA@ C19 Y16
5 10 1 2 2 +5VS R39 C22 GND_95 GND_195 Y19
<25> 1.8VSDGPU_MAIN_EN +1.8VALW ON2 CT2 +1.8VSDGPU_MAIN GND_96 GND_196
20_0402_5% C25 Y21
6 9 C28 GND_97 GND_197 Y23
1 VGA@
VIN2 VOUT2 GND_98 GND_198
2
CG337 7 8 VGA@ C7 AH11
1
VIN2 VOUT2 GND_99 GND_199
10U_0603_6.3V6M
0.1U_0201_10V6K R214 C16

VGA@ 15 100K_0402_5% GND_OPT W32
2 GPAD 1 GND_OPT
+1.8VALW
CG338
6
EM5209VF_DFN14_2X3 D
1
GPUCORE_EN# 2 Q17A VGA@

VGA@
VGA@ 2
22U_0603_6.3V6M
G 2N7002KDW_SOT363-6
GP107-ES-A1_BGA908
1
CG339
VGA@ S @
1
3
D
GPUCORE_EN 5
<25> GPUCORE_EN
2
S
4
Q17B
2N7002KDW_SOT363-6
VGA@ remove NVDDS discharge
4
For Power down sequence 4
DV1
2 1 1V8_AON_EN
<20> DGPU_PWR_EN
RB751S40T1G_SOD523-2
VGA@
1 2
RV22 1
49.9K_0402_5% 2017/12/18 2018/09/01 Title
VGA@ CV35
0.1U_0201_10V6K
2 VGA@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N17P POWER & GND 5/7
1.0 Modify AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
A B C D E
A B C D E
MF=1
MF=0
<26> FBA_D[63:0] 2 OF 2 2 OF 2
UV4B +1.35VSDGPU UV5B
K4 A4 FBA_D0 K4 A4 FBA_D56
<26> FBA_CMD6 A8/A7 DQ0 <26> FBA_CMD26 A8/A7 DQ0
1
H5 A2 FBA_D1 H5 A2 FBA_D57
<26> FBA_CMD11 A9/A1 DQ1 FBA_D2 <26> FBA_CMD23 A9/A1 DQ1 FBA_D58
H4 B4 RV50 H4 B4
<26> FBA_CMD10 K5 A10/A0 DQ2 B2 FBA_D3 <26> FBA_CMD22 K5 A10/A0 DQ2 B2 FBA_D59
549_0402_1%
<26> FBA_CMD7 J5 A11/A6 DQ3 E4 FBA_D4 <26> FBA_CMD27 J5 A11/A6 DQ3 E4 FBA_D60
VGA@
<26> FBA_CMD9 A12/RFU#J5/NC#J5 DQ4 E2 FBA_D5 <26> FBA_CMD25 A12/RFU#J5/NC#J5 DQ4 E2 FBA_D61
RV51
2
H11 DQ5 F4 FBA_D6 931_0402_1% H11 DQ5 F4 FBA_D62
<26> FBA_CMD2 BA0/A2 DQ6 FBA_D7 FBA0_VREFC <26> FBA_CMD19 BA0/A2 DQ6 FBA_D63
1
K10 F2 1 2 K10 F2 1
<26> FBA_CMD4 K11 BA1/A5 DQ7 A11 FBA_D8 <26> FBA_CMD17 K11 BA1/A5 DQ7 A11 FBA_D48
<26> FBA_CMD3 H10 BA2/A4 DQ8 A13 FBA_D9 <26> FBA_CMD18 H10 BA2/A4 DQ8 A13 FBA_D49
VGA@
<26> FBA_CMD1 BA3/A3 DQ9 <26> FBA_CMD20 BA3/A3 DQ9
1
B11 FBA_D10 B11 FBA_D50
J4 DQ10 B13 FBA_D11 RV52 J4 DQ10 B13 FBA_D51
<26> FBA_CMD8 ABI# DQ11 FBA_D12 <26> FBA_CMD24 ABI# DQ11 FBA_D52
G3 E11 1.33K_0402_1% G3 E11
<26> FBA_CMD12 G12 RAS# DQ12 E13 FBA_D13 <26> FBA_CMD31 G12 RAS# DQ12 E13 FBA_D53
<26> FBA_CMD0 L3 CS# DQ13 F11 FBA_D14 <26> FBA_CMD21 L3 CS# DQ13 F11 FBA_D54
VGA@
<26> FBA_CMD15 <26> FBA_CMD28
2
L12 CAS# DQ14 F13 FBA_D15 L12 CAS# DQ14 F13 FBA_D55
<26> FBA_CMD5 WE# DQ15 U11 FBA_D16 <26> FBA_CMD16 WE# DQ15 U11 FBA_D40
J12 DQ16 U13 FBA_D17 J12 DQ16 U13 FBA_D41
<26> FBA_CLKA0 J11 CK DQ17 T11 FBA_D18 FBA_VREFC_R <26> FBA_CLKA1 J11 CK DQ17 T11 FBA_D42
<26> FBA_CLKA0# J3 CK# DQ18 T13 FBA_D19 <26> FBA_CLKA1# J3 CK# DQ18 T13 FBA_D43
<26> FBA_CMD14 CKE# DQ19 N11 FBA_D20 <26> FBA_CMD30 CKE# DQ19 N11 FBA_D44
+1.35VSDGPU
D2 DQ20 N13 FBA_D21 D2 DQ20 N13 FBA_D45
<26> FBA_DBI0 DBI0# DQ21 FBA_D22 <26> FBA_DBI7 DBI0# DQ21 FBA_D46
D13 M11 D13 M11
<26> FBA_DBI1 DBI1# DQ22 <26> FBA_DBI6 DBI1# DQ22
1
P13 M13 FBA_D23 P13 M13 FBA_D47
<26> FBA_DBI2 P2 DBI2# DQ23 U4 FBA_D24 <26> FBA_DBI5 P2 DBI2# DQ23 U4 FBA_D32
RV53
<26> FBA_DBI3 DBI3# DQ24 U2 FBA_D25 <26> FBA_DBI4 DBI3# DQ24 U2 FBA_D33
549_0402_1%
DQ25 DQ25
1
J2 T4 FBA_D26 D VGA@ J2 T4 FBA_D34
<26> FBA_CMD13 RESET# DQ26 FBA_D27 <26> FBA_CMD29 RESET# DQ26 FBA_D35
T2 2 RV54 T2
<25> VRAM_VREF_CTL
2
J10 DQ27 N4 FBA_D28 G 931_0402_1% RV55 VGA@ J10 DQ27 N4 FBA_D36
FBA0_ZQ1 J13 SEN DQ28 N2 FBA_D29 VGA@ 1 2 FBA1_VREFC +1.35VSDGPU 1K_0402_5% FBA1_ZQ3 J13 SEN DQ28 N2 FBA_D37
S
3
J1 ZQ DQ29 M4 FBA_D30 QV3 1 2 J1 ZQ DQ29 M4 FBA_D38
MF DQ30 M2 FBA_D31 MESS138W-G_SOT323-3 VGA@ MF DQ30 M2 FBA_D39
DQ31 DQ31
1
D4 D4
<26> FBA_WCK01 D5 WCK01 C2 <26> FBA_WCK67 D5 WCK01 C2
1.0 Modify RV56
<26> FBA_WCK01# WCK01# EDC0 C13 FBA_EDC0 <26> <26> FBA_WCK67# WCK01# EDC0 C13 FBA_EDC7 <26>
1.33K_0402_1%
EDC1 R13 FBA_EDC1 <26> P4 EDC1 R13 FBA_EDC6 <26>
P4
<26> FBA_WCK23 P5 WCK23 EDC2 R2 FBA_EDC2 <26> <26> FBA_WCK45 P5 WCK23 EDC2 R2 FBA_EDC5 <26>
VGA@
<26> FBA_WCK23# FBA_EDC3 <26> <26> FBA_WCK45# FBA_EDC4 <26>
2
WCK23# EDC3 WCK23# EDC3
1
1
X76@ X76@
VGA@ VGA@ VGA@ H5GC2H24BFR-T2C_FBGA170 VGA@ VGA@ H5GC2H24BFR-T2C_FBGA170
RV57 RV58 RV59 RV60 RV61
1K_0402_5% 121_0402_1% 1K_0402_5% 1K_0402_5% 121_0402_1%
2 2
2
2
+1.35VSDGPU
UV4A 1 OF 2 +1.35VSDGPU
UV5A 1 OF 2
C5 B5
C10 VDD VSS B10 C5 B5
D11 VDD VSS D10 C10 VDD VSS B10
G1 VDD VSS G5 D11 VDD VSS D10
G4 VDD VSS G10 FBA_CLKA0 FBA_CLKA0# +1.35VSDGPU G1 VDD VSS G5
G11 VDD VSS H1 G4 VDD VSS G10
VDD VSS VDD VSS
1
1
G14 H14 G11 H1
+1.35VSDGPU L1 VDD VSS K1 G14 VDD VSS H14
RV63 RV95
L4 VDD VSS K14 40.2_0402_1% 40.2_0402_1% L1 VDD VSS K1
VDD VSS 1 1 1 1 1 1 1 VDD VSS
L11 L5 VGA@ VGA@ L4 K14
VDD VSS VDD VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
L14 L10 CV61 CV62 CV63 CV64 CV65 CV66 CV69 L11 L5
2
2
P11 VDD VSS P10 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ L14 VDD VSS L10
1 1 1 1 1 1 1 VDD VSS 2 2 2 2 2 VDD VSS
R5 T5 2 2 P11 P10
VDD VSS 1 VDD VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.01U_0402_16V7K
CV58 CV59 CV67 CV56 CV57 CV60 CV68 R10 T10 VGA@ R5 T5
VDD VSS VDD VSS
CV190
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ R10 T10
2 2 2 2 2 2 2 B1 A1 VDD VSS
B3 VDDQ VSSQ A3 2 B1 A1
B12 VDDQ VSSQ A12 B3 VDDQ VSSQ A3
B14 VDDQ VSSQ A14 B12 VDDQ VSSQ A12
D1 VDDQ VSSQ C1 B14 VDDQ VSSQ A14
VDDQ VSSQ Close to VDDQ VSSQ
D3 C3 VRAM D1 C1
D12 VDDQ VSSQ C4 D3 VDDQ VSSQ C3
VDDQ VSSQ VDDQ VSSQ
10U_0603_6.3V6M
10U_0603_6.3V6M
Close to D14 C11 1 1 1 1 1 1 1 D12 C4
E5 VDDQ VSSQ C12 D14 VDDQ VSSQ C11
VRAM VDDQ VSSQ VDDQ VSSQ
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0402_6.3V6K
E10 C14 CV77 CV78 CV79 CV80 CV81 CV82 CV83 E5 C12
VDDQ VSSQ VDDQ VSSQ
10U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1 F1 E1 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ E10 C14

F3 VDDQ VSSQ E3 2 2 2 2 2 2 2 F1 VDDQ VSSQ E1
VDDQ VSSQ VDDQ VSSQ
1U_0402_6.3V6K
10U_0402_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
CV141 CV142 CV140 CV73 CV74 CV75 CV76 F12 E12 F3 E3

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ F14 VDDQ VSSQ E14 FBA_CLKA1 FBA_CLKA1# F12 VDDQ VSSQ E12
3 2 2 2 2 2 2 2 G2 VDDQ VSSQ F5 F14 VDDQ VSSQ E14 3
VDDQ VSSQ VDDQ VSSQ
1
1
G13 F10 G2 F5
H3 VDDQ VSSQ H2 RV96 RV62 G13 VDDQ VSSQ F10
H12 VDDQ VSSQ H13 40.2_0402_1% 40.2_0402_1% H3 VDDQ VSSQ H2
K3 VDDQ VSSQ K2 VGA@ VGA@ H12 VDDQ VSSQ H13
VDDQ VSSQ Close to VDDQ VSSQ
K12 K13 VRAM K3 K2
2
L2 VDDQ VSSQ M5 K12 VDDQ VSSQ K13

L13 VDDQ VSSQ M10 L2 VDDQ VSSQ M5
Close to VDDQ VSSQ 1 VDDQ VSSQ
0.01U_0402_16V7K
VRAM M1 N1 VGA@ 1 1 1 1 1 1 1 L13 M10

VDDQ VSSQ VDDQ VSSQ
CV191
10U_0603_6.3V6M
10U_0603_6.3V6M
M3 N3 M1 N1
VDDQ VSSQ VDDQ VSSQ
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
M12 N12 CV86 CV87 CV143 CV144 CV145 CV147 CV146 M3 N3
VDDQ VSSQ 2 VDDQ VSSQ
10U_0402_6.3V6M
1 1 1 1 1 1 1 M14 N14 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ M12 N12
N5 VDDQ VSSQ R1 2 2 2 2 2 2 2 M14 VDDQ VSSQ N14
VDDQ VSSQ VDDQ VSSQ
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
CV84 CV85 CV70 CV71 CV72 CV138 CV139 N10 R3 N5 R1

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ P1 VDDQ VSSQ R4 N10 VDDQ VSSQ R3
2 2 2 2 2 2 2 P3 VDDQ VSSQ R11 P1 VDDQ VSSQ R4
P12 VDDQ VSSQ R12 P3 VDDQ VSSQ R11
P14 VDDQ VSSQ R14 P12 VDDQ VSSQ R12
VDDQ VSSQ (3GHz and VDDQ VSSQ
T1 U1 up) P14 R14
T3 VDDQ VSSQ U3 T1 VDDQ VSSQ U1
VDDQ VSSQ Around VDDQ VSSQ
T12 U12 VRAM T3 U3
T14 VDDQ VSSQ U14 T12 VDDQ VSSQ U12
VDDQ VSSQ T14 VDDQ VSSQ U14
Around FBA0_VREFC VDDQ VSSQ
VRAM J14 A5
VREFC VPP/NC#A5 FBA1_VREFC
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
U5 1 1 1 1 1 1 1 1 J14 A5
VPP/NC#U5 VREFC VPP/NC#A5
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 A10 U5
U10 VREFD CV166 CV168 CV167 CV170 CV169 CV172 CV171 CV173 A10 VPP/NC#U5
1 VREFD 1 VREFD
CV161 CV160 CV158 CV162 CV163 CV164 CV159 CV165 CV89 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ U10
2 2 2 2 2 2 2 2 VREFD
820P_0402_50V7K
820P_0402_50V7K
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ CV88
2 2 2 2 2 2 2 2 X76@ VGA@
2 H5GC2H24BFR-T2C_FBGA170 2 X76@
H5GC2H24BFR-T2C_FBGA170
x32
x32 only
4 only 4

N17P GDDR5 CHA 6/7
A B C D E
A B C D E
MF=1
+1.35VSDGPU
<26> FBB_D[63:0] MF=0 UV7B 2 OF 2
1
UV6B 2 OF 2 K4 A4 FBB_D56
<26> FBB_CMD26 H5 A8/A7 DQ0 A2 FBB_D57
RV64
FBB_D0 <26> FBB_CMD23 A9/A1 DQ1 FBB_D58
K4 A4 549_0402_1% H4 B4
<26> FBB_CMD6 H5 A8/A7 DQ0 A2 FBB_D1 <26> FBB_CMD22 K5 A10/A0 DQ2 B2 FBB_D59
VGA@
<26> FBB_CMD11 H4 A9/A1 DQ1 B4 FBB_D2 <26> FBB_CMD27 J5 A11/A6 DQ3 E4 FBB_D60
RV65
<26> FBB_CMD10 <26> FBB_CMD25
2
K5 A10/A0 DQ2 B2 FBB_D3 931_0402_1% A12/RFU#J5/NC#J5 DQ4 E2 FBB_D61
<26> FBB_CMD7 J5 A11/A6 DQ3 E4 FBB_D4 1 2 FBB0_VREFC H11 DQ5 F4 FBB_D62
<26> FBB_CMD9 A12/RFU#J5/NC#J5 DQ4 FBB_D5 <26> FBB_CMD19 BA0/A2 DQ6 FBB_D63
1
E2 K10 F2 1
H11 DQ5 F4 FBB_D6 <26> FBB_CMD17 K11 BA1/A5 DQ7 A11 FBB_D48
VGA@
<26> FBB_CMD2 BA0/A2 DQ6 <26> FBB_CMD18 BA2/A4 DQ8
1
K10 F2 FBB_D7 H10 A13 FBB_D49
<26> FBB_CMD4 K11 BA1/A5 DQ7 A11 FBB_D8 <26> FBB_CMD20 BA3/A3 DQ9 B11 FBB_D50
RV66
<26> FBB_CMD3 H10 BA2/A4 DQ8 A13 FBB_D9 J4 DQ10 B13 FBB_D51
1.33K_0402_1%
<26> FBB_CMD1 BA3/A3 DQ9 FBB_D10 <26> FBB_CMD24 ABI# DQ11 FBB_D52
B11 G3 E11
J4 DQ10 B13 FBB_D11 <26> FBB_CMD31 G12 RAS# DQ12 E13 FBB_D53
VGA@
<26> FBB_CMD8 <26> FBB_CMD21
2
G3 ABI# DQ11 E11 FBB_D12 L3 CS# DQ13 F11 FBB_D54
<26> FBB_CMD12 G12 RAS# DQ12 E13 FBB_D13 <26> FBB_CMD28 L12 CAS# DQ14 F13 FBB_D55
<26> FBB_CMD0 L3 CS# DQ13 F11 FBB_D14 FBB_VREFC_R <26> FBB_CMD16 WE# DQ15 U11 FBB_D40
<26> FBB_CMD15 CAS# DQ14 FBB_D15 DQ16 FBB_D41
L12 F13 J12 U13
<26> FBB_CMD5 WE# DQ15 U11 FBB_D16 <26> FBB_CLKA1 J11 CK DQ17 T11 FBB_D42
J12 DQ16 U13 FBB_D17 <26> FBB_CLKA1# J3 CK# DQ18 T13 FBB_D43
+1.35VSDGPU
<26> FBB_CLKA0 J11 CK DQ17 T11 FBB_D18 <26> FBB_CMD30 CKE# DQ19 N11 FBB_D44
<26> FBB_CLKA0# J3 CK# DQ18 T13 FBB_D19 D2 DQ20 N13 FBB_D45
<26> FBB_CMD14 CKE# DQ19 <26> FBB_DBI7 DBI0# DQ21
1
N11 FBB_D20 D13 M11 FBB_D46
D2 DQ20 N13 FBB_D21 <26> FBB_DBI6 P13 DBI1# DQ22 M13 FBB_D47
RV67
<26> FBB_DBI0 DBI0# DQ21 <26> FBB_DBI5 DBI2# DQ23
1
D13 M11 FBB_D22 D 549_0402_1% P2 U4 FBB_D32
<26> FBB_DBI1 P13 DBI1# DQ22 M13 FBB_D23 2 <26> FBB_DBI4 DBI3# DQ24 U2 FBB_D33
VGA@
<26> FBB_DBI2 P2 DBI2# DQ23 U4 FBB_D24 <25> VRAM_VREF_CTL J2 DQ25 T4 FBB_D34
G RV68
<26> FBB_DBI3 <26> FBB_CMD29
2
DBI3# DQ24 U2 FBB_D25 VGA@ 931_0402_1% RESET# DQ26 T2 FBB_D35
S
3
J2 DQ25 T4 FBB_D26 QV4 1 2 FBB1_VREFC RV69 J10 DQ27 N4 FBB_D36
<26> FBB_CMD13 RESET# DQ26 T2 FBB_D27 +1.35VSDGPU FBB1_ZQ3 J13 SEN DQ28 N2 FBB_D37
MESS138W-G_SOT323-3 1K_0402_5%
J10 DQ27 N4 FBB_D28 VGA@ 1 2 J1 ZQ DQ29 M4 FBB_D38
SEN DQ28 MF DQ30
1
FBB0_ZQ1 J13 N2 FBB_D29 M2 FBB_D39
ZQ DQ29 FBB_D30
1.0 Modify DQ31
J1 M4 RV70 VGA@ D4
MF DQ30 M2 FBB_D31 <26> FBB_WCK67 D5 WCK01 C2
1.33K_0402_1%
D4 DQ31 <26> FBB_WCK67# WCK01# EDC0 C13 FBB_EDC7 <26>
<26> FBB_WCK01 D5 WCK01 C2 P4 EDC1 R13 FBB_EDC6 <26>
VGA@
<26> FBB_WCK01# FBB_EDC0 <26> <26> FBB_WCK45 FBB_EDC5 <26>
2
WCK01# EDC0 C13 P5 WCK23 EDC2 R2
EDC1 FBB_EDC1 <26> <26> FBB_WCK45# WCK23# EDC3 FBB_EDC4 <26>
P4 R13
<26> FBB_WCK23 P5 WCK23 EDC2 R2 FBB_EDC2 <26>
<26> FBB_WCK23# WCK23# EDC3 FBB_EDC3 <26>
1
1
X76@
VGA@ VGA@ H5GC2H24BFR-T2C_FBGA170
1
1
X76@ RV71 RV72

VGA@ VGA@ VGA@ H5GC2H24BFR-T2C_FBGA170 1K_0402_5% 121_0402_1%
2 2
RV73 RV74 RV75
2
2
1K_0402_5% 121_0402_1% 1K_0402_5%
2
2
+1.35VSDGPU
UV7A 1 OF 2
+1.35VSDGPU C5 B5
1 OF 2 +1.35VSDGPU C10 VDD VSS B10
UV6A
D11 VDD VSS D10
+1.35VSDGPU VDD VSS
C5 B5 G1 G5
C10 VDD VSS B10 G4 VDD VSS G10
D11 VDD VSS D10 G11 VDD VSS H1
VDD VSS 1 1 1 1 1 1 1 VDD VSS
G1 G5 G14 H14
VDD VSS VDD VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 G4 G10 CV90 CV94 CV96 CV97 CV91 CV95 CV98 L1 K1
G11 VDD VSS H1 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ L4 VDD VSS K14
VDD VSS FBB_CLKA0 FBB_CLKA0# 2 2 2 2 2 2 2 VDD VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
CV99 CV100 CV101 CV92 CV93 CV102 CV103 G14 H14 L11 L5
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ L1 VDD VSS K1 L14 VDD VSS L10
VDD VSS VDD VSS
1
2 2 2 2 2 2 2 L4 K14 P11 P10
L11 VDD VSS L5 RV76 RV77 R5 VDD VSS T5
L14 VDD VSS L10 40.2_0402_1% 40.2_0402_1% R10 VDD VSS T10
P11 VDD VSS P10 VGA@ VGA@ VDD VSS
R5 VDD VSS T5 B1 A1
2
R10 VDD VSS T10 B3 VDDQ VSSQ A3
VDD VSS Close to VDDQ VSSQ
1 VRAM B12 A12
VDDQ VSSQ
0.01U_0402_16V7K
Close to B1 A1 B14 A14
VDDQ VSSQ VDDQ VSSQ
10U_0603_6.3V6M
CV193
10U_0603_6.3V6M
VRAM B3 A3 1 1 1 1 1 1 1 D1 C1
B12 VDDQ VSSQ A12 D3 VDDQ VSSQ C3
VDDQ VSSQ 2 VDDQ VSSQ
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0402_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0402_6.3V6M
1 1 1 1 1 1 1 B14 A14 CV104 CV105 CV106 CV174 CV108 CV109 CV110 D12 C4
D1 VDDQ VSSQ C1 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ D14 VDDQ VSSQ C11
VDDQ VSSQ 2 2 2 2 2 2 2 VDDQ VSSQ
1U_0402_6.3V6K
10U_0402_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0402_6.3V6M
CV111 CV112 CV113 CV114 CV115 CV116 CV117 D3 C3 E5 C12

VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ D12 VDDQ VSSQ C4 E10 VDDQ VSSQ C14
2 2 2 2 2 2 2 D14 VDDQ VSSQ C11 F1 VDDQ VSSQ E1
E5 VDDQ VSSQ C12 F3 VDDQ VSSQ E3
VDDQ VSSQ VGA@ VDDQ VSSQ
E10 C14 F12 E12
F1 VDDQ VSSQ E1 F14 VDDQ VSSQ E14
3 F3 VDDQ VSSQ E3 FBB_CLKA1 FBB_CLKA1# G2 VDDQ VSSQ F5 3
F12 VDDQ VSSQ E12 G13 VDDQ VSSQ F10
VDDQ VSSQ
1 Close to VDDQ VSSQ
1
F14 E14 VRAM H3 H2
G2 VDDQ VSSQ F5 RV97 RV98 H12 VDDQ VSSQ H13
Close to VDDQ VSSQ VDDQ VSSQ
VRAM G13 F10 40.2_0402_1% 40.2_0402_1% K3 K2
VDDQ VSSQ VDDQ VSSQ
10U_0603_6.3V6M
10U_0603_6.3V6M
H3 H2 VGA@ VGA@ 1 1 1 1 1 1 1 K12 K13
H12 VDDQ VSSQ H13 L2 VDDQ VSSQ M5
2
VDDQ VSSQ VDDQ VSSQ

10U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 1 1 1 K3 K2 CV118 CV119 CV153 CV155 CV154 CV156 CV157 L13 M10
K12 VDDQ VSSQ K13 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ M1 VDDQ VSSQ N1
VDDQ VSSQ 1 2 2 2 2 2 2 2 VDDQ VSSQ
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.01U_0402_16V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
CV120 CV121 CV148 CV149 CV150 CV152 CV151 L2 M5 M3 N3

VDDQ VSSQ VDDQ VSSQ
CV192
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ L13 M10 M12 N12
2 2 2 2 2 2 2 M1 VDDQ VSSQ N1 M14 VDDQ VSSQ N14
M3 VDDQ VSSQ N3 2 N5 VDDQ VSSQ R1
M12 VDDQ VSSQ N12 N10 VDDQ VSSQ R3
M14 VDDQ VSSQ N14 P1 VDDQ VSSQ R4
N5 VDDQ VSSQ R1 P3 VDDQ VSSQ R11
N10 VDDQ VSSQ R3 P12 VDDQ VSSQ R12
VDDQ VSSQ Around VDDQ VSSQ
P1 R4 VGA@ VRAM P14 R14
P3 VDDQ VSSQ R11 T1 VDDQ VSSQ U1
Around VDDQ VSSQ (3GHz and VDDQ VSSQ
VRAM P12 R12 up) T3 U3
P14 VDDQ VSSQ R14 T12 VDDQ VSSQ U12
VDDQ VSSQ VDDQ VSSQ
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
T1 U1 1 1 1 1 1 1 1 1 T14 U14
T3 VDDQ VSSQ U3 VDDQ VSSQ
T12 VDDQ VSSQ U12 CV182 CV184 CV183 CV185 CV186 CV188 CV187 CV189 FBB1_VREFC J14 A5
VDDQ VSSQ VREFC VPP/NC#A5
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 1 1 1 1 T14 U14 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ U5
VDDQ VSSQ 2 2 2 2 2 2 2 2 A10 VPP/NC#U5
CV107 CV176 CV175 CV177 CV178 CV180 CV179 CV181 FBB0_VREFC J14 A5 U10 VREFD
VREFC VPP/NC#A5 1 VREFD
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ U5
2 2 2 2 2 2 2 2 VPP/NC#U5
820P_0402_50V7K
A10 CV122
U10 VREFD VGA@ X76@
VREFD 2 H5GC2H24BFR-T2C_FBGA170
1 x32
CV123 only
820P_0402_50V7K
VGA@ X76@
x32 H5GC2H24BFR-T2C_FBGA170
2
only
4 4

N17P GDDR5 CHB 7/7
A B C D E
A B C D E
remove GPAK circuit for improve HDMI layout (1.0)
1 1
2 2
3 3
4 4

N17P G-Pak sequence 8/8
A B C D E
A B C D E
SM01000EJ00 3000ma
220ohm@100mhz
LCD POWER CIRCUIT DCR 0.04
+3VS +LCDVDD +19VB_CPU +INVPW R_B+

Place closed to
UX1 W=60mils JEDP1 +LCDVDD
+3VS
1U_0402_6.3V6K
CX2
5 1 W=60mils W=60mils
IN OUT LX1 EMC@
1 1 1
2 1 1 HCB2012KF-221T30_0805
0.1U_0201_10V6K
GND 1 2 CX7 1 1 1
4 3 CX3 CX4 1 @
2 EN OC 10U_0603_6.3V6M 0.1U_0201_10V6K CX6 CX8 CX1
2 2 1
SY6288C20AAC_SOT23-5 @ CX5 1000P_0402_50V7K 0.1U_0201_10V6K 10U_0603_6.3V6M
68P_0402_50V8J EMC@ 2 2 2
<18,25> PCH_ENVDD 2
XEMC@
1
2
RX1
100K_0402_5%
2
RX3
0_0402_5%
1 @ 2 EDP_HPD_R
<17,25> EDP_HPD
LED PANEL Conn.
1
RX4 +INVPW R_B+ JEDP1
W=60mils 1
100K_0402_5% 1
2
3 2
2
4 3
5 4
PCH_BKL_PW M 6 5
2 BKOFF# 7 6 2
+LCDVDD EDP_HPD_R 8 7
9 8
10 9
PCH_BKL_PW M 1 @ 2 11 10
<18,25> PCH_BKL_PW M 11
RX10 100K_0402_5% 12
XEMC@ 13 12
CX9 1 2 220P_0402_50V7K EDP_AUXN CX20 1 2 0.1U_0201_10V6K EDP_AUXN_C 14 13
<7> EDP_AUXN EDP_AUXP CX19 EDP_AUXP_C 14
<7> EDP_AUXP 1 2 0.1U_0201_10V6K 15
XEMC@ 16 15
BKOFF# CX10 1 2 220P_0402_50V7K EDP_TXP0 CX11 1 2 0.1U_0201_10V6K EDP_TXP0_C 17 16
<39> BKOFF# <7> EDP_TXP0 EDP_TXN0 CX12 EDP_TXN0_C 17
1 2 0.1U_0201_10V6K 18
<7> EDP_TXN0 18
19
RX5 1 @ 2 10K_0402_5% EDP_TXP1 CX13 1 2 0.1U_0201_10V6K EDP_TXP1_C 20 19
<7> EDP_TXP1 EDP_TXN1 CX14 EDP_TXN1_C 20
1 2 0.1U_0201_10V6K 21
<7> EDP_TXN1 21
22
EDP_TXP2 CX15 1 2 0.1U_0201_10V6K EDP_TXP2_C 23 22
1 2 0.1U_0201_10V6K 24
<7> EDP_TXN2 24
25
EDP_TXP3 CX17 1 2 0.1U_0201_10V6K EDP_TXP3_C 26 25
1 2 0.1U_0201_10V6K 27
<7> EDP_TXN3 27
28
USB20_P6 29 28
USB Touch Screen <15>
<15>
USB20_P6
USB20_N6
USB20_N6 30 29
30
31
+TS_PW R 32 31
Touch +TS_PW R 32
+5VS +3VS 33
Screen TS_EN 33
RX6 1 @ 2 0_0603_5% 34
<20,39> TS_EN 34
+3VS 35
3 RX7 1 2 0_0603_5% USB20_N5_CAMERA 36 35 41 3
USB20_P5_CAMERA 37 36 G1 42
For 37 G2
Camera 38 43
DMIC_CLK_R 39 38 G3 44
<38> DMIC_CLK_R DMIC_DATA_R 39 G4
40 45
Camera <38> DMIC_DATA_R 40 G5
ACES_50398-04041-001
CONN@
USB20_N5 RX8 1 @ 2 0_0402_5% USB20_N5_CAMERA
<15> USB20_N5 DMIC_CLK_R SP010013I00
USB20_P5 RX9 1 @ 2 0_0402_5% USB20_P5_CAMERA
<15> USB20_P5 DMIC_DATA_R
2
DX1
YSLC05CH_SOT23-3
XEMC@
CO-LAY FOR VGA OUTPUT
+3VS
1
RG196 1 @ 2 100K_0201_5% EDP_AUXN_C
RG197 1 @ 2 100K_0201_5% EDP_AUXP_C
RG198 1 @ 2 100K_0201_5% EDP_AUXN

RG199 1 @ 2 100K_0201_5% EDP_AUXP
4 4

eDP CONN.
A B C D E
A B C D E
RPY2
HDMI_CLKN 1 8 HDMI_GND
CY22 1 2 .1U_0402_16V7K HDMI_CLKP HDMI_CLKP 2 7
<27> GPU_DP2_P3 HDMI_CLKN HDMI_TX_N0
CY24 1 2 .1U_0402_16V7K 3 6
<27> GPU_DP2_N3 HDMI_TX_P0 4 5
1 CY16 1 2 .1U_0402_16V7K HDMI_TX_P0 1
<27> GPU_DP2_P2 HDMI_TX_N0
CY17 1 2 .1U_0402_16V7K 499_0804_8P4R_1%
<27> GPU_DP2_N2
CY18 1 2 .1U_0402_16V7K HDMI_TX_P1 RPY3
<27> GPU_DP2_P1 HDMI_TX_N1 HDMI_TX_N1
CY19 1 2 .1U_0402_16V7K 1 8
<27> GPU_DP2_N1 HDMI_TX_P1 2 7
CY20 1 2 .1U_0402_16V7K HDMI_TX_P2 HDMI_TX_N2 3 6
<27> GPU_DP2_P0 HDMI_TX_N2 HDMI_TX_P2
CY21 1 2 .1U_0402_16V7K 4 5
<27> GPU_DP2_N0
499_0804_8P4R_1%
+5VS W=40mils +HDMI_5V_OUT
3
D
+3VS 5 QY2B
G UY2
2N7002KDW _SOT363-6
S 3
4
OUT
1
HDMI_CLKP RY15 1 2 6.04_0402_1% HDMI_R_CLKP 1
IN CY23
2 0.1U_0201_10V6K
GND
2
XEMC@ CY26 2
3.3P_0402_50V8
AP2330W -7_SC59-3
1
HDMI_CLKN RY14 1 2 6.04_0402_1% HDMI_R_CLKN
2 2
+HDMI_5V_OUT
HDMI_TX_P0 HDMI_R_TX_P0 RPY1
RY16 1 2 6.04_0402_1%
HDMI_CTRL_DAT 8 1
HDMI_TX_N0 RY17 1 2 6.04_0402_1% HDMI_R_TX_N0 HDMI_CTRL_CLK 7 2 +1.8VSDGPU_AON
DY2 GPU_DP2_CTRL_CLK 6 3
HDMI_R_CLKN 1 1 10 9 HDMI_R_CLKN GPU_DP2_CTRL_DAT 5 4
HDMI_R_CLKP 2 2 9 8 HDMI_R_CLKP 2.2K_0804_8P4R_5%
HDMI_TX_P1 RY18 1 2 6.04_0402_1% HDMI_R_TX_P1
HDMI_R_TX_N04 4 7 7 HDMI_R_TX_N0
HDMI_TX_N1 RY19 1 2 6.04_0402_1% HDMI_R_TX_N1
HDMI_R_TX_P05 5 6 6 HDMI_R_TX_P0
3 3
L05ESDL5V0NA-4 SLP2510P8
HDMI_TX_P2 RY20 1 2 6.04_0402_1% HDMI_R_TX_P2 XEMC@
HDMI_TX_N2 RY22 1 2 6.04_0402_1% HDMI_R_TX_N2 +HDMI_5V_OUT HDMI connector
DY3 JHDMI1
HDMI_R_TX_N11 1 10 9 HDMI_R_TX_N1 HDMI_HPD 19
18 HP_DET
HDMI_R_TX_P1 2 2 HDMI_R_TX_P1 +5V
9 8 17
+3VS +3VS HDMI_CTRL_DAT 16 DDC/CEC_GND
3 HDMI_R_TX_N24 4 HDMI_R_TX_N2 HDMI_CTRL_CLK SDA 3
7 7 15
14 SCL
Reserved
2
HDMI_R_TX_P25 5 6 6 HDMI_R_TX_P2 13
HDMI_R_CLKN 12 CEC
RY24 3 3 11 CK-
CK_shield
2
1M_0402_5% HDMI_R_CLKP 10
G
QY2A 8 HDMI_R_TX_N0 9 CK+

1
2N7002KDW _SOT363-6 8 D0-

L05ESDL5V0NA-4 SLP2510P8 HDMI_R_TX_P0 7 D0_shield
1 6 HDMI_HPD XEMC@ HDMI_R_TX_N1 6 D0+
S
<17,25> HDMI_HPD_PCH D1-

D
5
HDMI_R_TX_P1 4 D1_shield 20
D1+ GND
2
HDMI_R_TX_N2 3 21
RY11 DY1 2 D2- GND 22
RY11 design guide rev2.0 use 20K pull down. 100K_0402_5% HDMI_HPD 6 3 HDMI_CTRL_DAT HDMI_R_TX_P2 1 D2_shield GND 23
I/O4 I/O2 D2+ GND
CCM_C100042GR019M298ZL
1
CONN@
5 2
VDD GND
+1.8VSDGPU_AON ZZZ2
DC232003500
HDMI_CTRL_CLK 4 1
I/O3 I/O1 +HDMI_5V_OUT
AZC099-04S.R7G_SOT23-6
XEMC@
5
QY1A HDMI_ROYALTY
PJT138KA_SOT363-6 P/N: SC300002900, S DIO(BR) AZC199-04S.R7G SOT23-6 ESD ROYALTY HDMI W /LOGO+HDCP
G
4 3 HDMI_CTRL_CLK RO0000003HM
4 <27> GPU_DP2_CTRL_CLK 4
S
45@
2
QY1B
PJT138KA_SOT363-6
G
1 6 HDMI_CTRL_DAT
<27> GPU_DP2_CTRL_DAT Security Classification Compal Secret Data Compal Electronics, Inc.
S
3ohm/10pF Issued Date 2017/12/18 Deciphered Date 2018/09/01 Title
HDMI CONN.
A B C D E
5 4 3 2 1
+3VS +3VS_SSD_NGFF
RM1
0_1206_5%
1 @ 2
1
10U_0603_6.3V6M
0.1U_0201_10V6K
1 2
+ CM3
CM1 CM2 150U_6.3V_M_D2
2 1 2
SGA00009000
D D
+3VS_SSD_NGFF
M.2 SSD
1A modify JSSD1
1 2
3 GND 3P3VAUX 4
PCIE_PRX_DTX_N9 5 GND 3P3VAUX 6
<18> PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 7 PERn3 NC 8
<18> PCIE_PRX_DTX_P9 9 PERp3 NC 10
CM6 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N9 11 GND DAS/DSS# 12
<18> PCIE_PTX_DRX_N9 CM4 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P9 13 PETn3 3P3VAUX 14
<18> PCIE_PTX_DRX_P9 15 PETp3 3P3VAUX 16 EMC@
PCIE_PRX_DTX_N10 17 GND 3P3VAUX 18 SSD_RST#_R CM16 2 1 100P_0402_50V8J
<18> PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 19 PERn2 3P3VAUX 20
CM5 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_N10 23 GND NC 24
<18> PCIE_PTX_DRX_N10 CM7 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P10 25 PETn2 NC 26
Place close to JSSD pin 50
<18> PCIE_PTX_DRX_P10 27 PETp2 NC 28
PCIE_PRX_DTX_N11 29 GND NC 30
ESD request to reserve.
<18> PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 31 PERn1 NC 32
<18> PCIE_PTX_DRX_N11 CM9 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P11 37 PETn1 NC 38 RM2 1 @ 2 0_0402_5%
<18> PCIE_PTX_DRX_P11 PETp1 DEVSLP SSD_DEVSLP1 <18>
39 40
PCIE_PRX_DTX_P12 41 GND NC 42 RM4 1 @ 2 0_0402_5%
<18> PCIE_PRX_DTX_P12 PCIE_PRX_DTX_N12 43 PERn0/SATA-B+ NC 44
C <18> PCIE_PRX_DTX_N12 45 PERp0/SATA-B- NC 46 C
<18> PCIE_PTX_DRX_N12 CM11 1 2 0.22U_0402_16V7K PCIE_PTX_C_DRX_P12 49 PETn0/SATA-A- NC 50 SSD_RST#_R RM6 1 @ 2 0_0402_5%
<18> PCIE_PTX_DRX_P12 PETp0/SATA-A+ PERST# SSD_CLKREQ#_R PLT_RST_BUF# <17,36,37>
51 52 RM7 1 @ 2 0_0402_5% SSD_CLKREQ# <16>
53 GND CLKREQ# 54
<16> CLK_PCIE_NGFF# REFCLKN PEWake#
<16> CLK_PCIE_NGFF 55 56
57 REFCLKP NC 58
GND NC
59 60 SUSCLK_SSD RM8 1 @ 2 0_0402_5%

SSD_DET# NC SUSCLK(32kHz) SUSCLK <19,37>
61 62
63 PEDET(NC-PCIE/GND-SATA) 3P3VAUX 64
65 GND 3P3VAUX 66
GND 3P3VAUX +3VS_SSD_NGFF
67
GND 68
+3VS_SSD_NGFF GND1 69
GND2
BELLW _80159-3221
CONN@
2
RM9 @
SP070018L00 SSD_RST#_R 2 @ 1
Pull high at PCH side 10K_0402_5% RM20 10K_0402_5%
+3VS
SSD_CLKREQ#_R 2 @ 1 +3VS
1
RM21 10K_0402_5%
RM10
1 @ 2 SSD_DET#
B <18> SATA_GP1 B
0_0402_5%
reserve for Optane Memory
1
D
@ QM1 2
BSS138W -7-F_SOT323-3 G
S
3
SSD_DET#
SATA Device 0
PCIE Device 1
A A

mSATA-SSD
5 4 3 2 1
A B C D E
LAN-RTL8411B
LDO mode
W=60mil RL1 2 LDO@ 1 0_0603_5% W=60mil
+LAN_VDD +3V_LAN
W=60mil
SWR@
300mA 1.4A
IDC=1200mA
+REGOUT LL1 1 2
+3VALW +3V_LAN 2.2UH_HPC252012NF-2R2M_20%
4.7U_0402_6.3V6M
0.1U_0201_10V6K
CL28 SWR@
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
CL7
1U_0402_6.3V6K
CL8
0.1U_0201_10V6K
4.7U_0402_6.3V6M
CL10
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1
CL2
CL3
CL4
CL5
CL6
RL2 1 Using for Switch mode 1 1 1 1 1 1 1 1 1 1 1 1 1
0.1U_0201_10V6K
CL1
CL9
CL11
CL12
CL13
0_0805_5%
1 @ 2 The trace length from
SWR@
SWR@
Lx to PIN48 (REGOUT)
2 2 2 2 2 2 2 2 2 2 2 2 2 2
LDO@
60mil 60mil and from C to Lx must
UL1 < 200mils.
5 1
IN OUT
2
GND Using for Switch mode
Place near Pin 3,8,33,46 Place near Pin 20 Place near Pin 11,32,48
4 3 11/27: P/N change to SH00000RT00
EN OC The trace length
2 ( S COIL 2.2UH +-20%
SY6288C20AAC_SOT23-5 from C to
CL14 HPC252012NF-2R2M 1.3A) PIN34,35(VDDREG)
1U_0402_6.3V6K must < 200mils.
1 LAN_PWR_EN
LAN_PWR_EN <39>
PVT modify 01/06
+3V_LAN UL2 R2534, R2537, R2539, R2535, R2536
RL5 1 2 10K_0402_5% Power Manahement/Isolation change to R-short
From EC ISOLATEB 31
RL3 2 @ 1 0_0402_5% LAN_PME# 39 ISOLATEBPIN
<17,39> EC_PME# LANWAKEB
High active. Card Reader
15 SD_D0 RL6 1 @ 2 0_0402_5% SD_D0_R
EN threshold voltage min:1.2V reserve EC_PME# pull high 100K to +3VALW_EC SD_D0/MS_D1
PCI-Express 14 SD_D1 RL7 1 @ 2 0_0402_5% SD_D1_R
typ:1.6V max:2.0V CLK_PCIE_LAN SD_D1 SD_CLK SD_CLK_R
Current limit threshold 1.5~2.8A <16> CLK_PCIE_LAN
23 16 RL4 1 2 10_0402_1%
CLK_PCIE_LAN# 24 REFCLK_P SD_CLK/MS_D0 17 SD_CMD RL8 1 @ 2 0_0402_5% SD_CMD_R
<16> CLK_PCIE_LAN# REFCLK_N SD_CMD/MS_D2 SD_D3 SD_D3_R
+3V_LAN Rising time must >0.5ms and <100ms 18 RL9 1 @ 2 0_0402_5% 2
PLT_RST_BUF# 30 SD_D3/MS_D3 19 SD_D2 RL10 1 @ 2 0_0402_5% SD_D2_R
<17,35,37> PLT_RST_BUF# LAN_CLKREQ# PERSTBPIN SD_D2/MS_CLK SD_WP
29 28 CL16
+3VS <16> LAN_CLKREQ# CLKREQBPIN SD_WP/MS_BS
5P_0402_50V8C
CL15 1 2 .1U_0402_16V7K PCIE_PRX_C_DTX_P14 25 1
<18> PCIE_PRX_DTX_P14 PCIE_PRX_C_DTX_N14 HSOP XEMC@
CL17 1 2 .1U_0402_16V7K 26
<18> PCIE_PRX_DTX_N14 HSON
1
21 42 SD_CD#
<18> PCIE_PTX_C_DRX_P14 HSIP SD_CD# close to pin17
RL15 <18> PCIE_PTX_C_DRX_N14
22 43
2
1K_0402_5% HSIN MS_CD# 2
Transceiver Interface
LAN_MIDI0+ 1
2
ISOLATEB LAN_MIDI0- 2 MDIP0

LAN_MIDI1+ 4 MDIN0
MDIP1
2
LAN_MIDI1- 5 48 +3V_LAN
RL18 LAN_MIDI2+ 6 MDIN1 AVDD33 11 Protect cotact Card contact
LAN_MIDI2- 7 MDIP2 AVDD33 12
15K_0402_5% MDIN2 DVDD33
1400mA
LAN_MIDI3+ 9 32
LAN_MIDI3- 10 MDIP3 DVDD33 Write protect Write Enable
1
MDIN3
+LAN_VDD
(Lock) (Unlock)
RL14 XTLI 44 33
XTLO_R 1 2 XTLO 45 CKXTAL1 Clock DVDD10 3 Card Uninsert Open Open Open
+3V_LAN CKXTAL2 AVDD10 8
330_0402_5% 300mA
SWR mode
AVDD10 Card insert Open Close Close
Regulator and Reference
RL11 1 SWR@2 0_0402_5% +REGOUT 36 20
35 REG_OUT EVDD10
+3V_LAN VDDREG +CARD_3V3
RL13 1 LDO@2 0_0402_5% ENSWREG ENSWREG 34 800mA
46 ENSWREG_H 13
+LAN_VDD AVDD10 Card_3V3
LDO mode LAN_RST
2 RL16 1 47
2.49K_0402_1% RSET 27 +VDD33_18
DV33/18
@ T45
0.1U_0201_10V6K
4.7U_0402_6.3V6M
41
1 @ 2 GPO 38 LED0
<19> LAN_GPO LED1/GPO 1 1 1
+3V_LAN
CL20
CL21
RL17 0_0402_5% 37 LEDs
for disable PHY 40 LED3 CL22
reserve 0 ohm
@ T46 LED_CR
RL12 1 @ 2 10K_0402_5% GPO @ T47 49 @ 0.1U_0201_10V6K
E_Pad 2 2 2
YL1
25MHZ_20PF_XRCGB25M000F2P18R0
XTLO_R
Place near Pin 27
3 XTLI 3 1 3
3 1 RTL8411B-CGT_QFN48_6X6
1
NC NC
1 +CARD_3V3 Card Reader Connector
18P_0402_50V8J
10P_0402_50V8J 4 2 CL19 JSD1
CL18 Close to Card Reader CONN
2 2 6
SD_CMD_R 3 VDD
SD_CLK_R CMD
4.7U_0402_6.3V6M
0.1U_0201_10V6K
7
P/N: SJ10000UP00 (S CRYSTAL 25MHZ 10PF XRCGB25M000F2P34R0) CLK
CL23
CL24
5
LAN Connector SD Write protect inverter circuit
1 1
8 VSS1
VSS2
TL1 JRJ45 SD_D0_R 9
2 2 SD_D1_R 10 DAT0
LAN_TERMAL1 24 12 SD_WP# 2 @ 1 SD_WP SD_D2_R 1 DAT1
LAN_MIDI0+ 2 TCT1 MCT1 23 RJ45_MIDI0+ RJ45_MIDI3- 8 GND RL21 0_0402_5% SD_D3_R 2 DAT2
LAN_MIDI0- 3 TD1+ MX1+ 22 RJ45_MIDI0- PR4- 11 CD/DAT3
TD1- MX1- RJ45_MIDI3+ 7 GND 12
4 21 PR4+ +3VS GND 13
LAN_MIDI1+ 5 TCT2 MCT2 20 RJ45_MIDI1+ RJ45_MIDI1- 6 SD_WP# 11 GND
LAN_MIDI1- 6 TD2+ MX2+ 19 RJ45_MIDI1- PR2- SD_CD# 4 W/P
TD2- MX2- RJ45_MIDI2- 5 CD
PR3-
2
7 18 IC side TAITW_PSDATQ09GLBS1NN4H1
LAN_MIDI2+ 8 TCT3 MCT3 17 RJ45_MIDI2+ RJ45_MIDI2+ 4 RL20
LAN_MIDI2- TD3+ MX3+ RJ45_MIDI2- PR3+ SD_WP CONN@
9 16 100K_0402_5%
TD3- MX3- RJ45_MIDI1+ 3
10 15 PR2+ CL26
SP011611110
40mil 40mil
1
TCT4 MCT4
1
LAN_MIDI3+ 11 14 RJ45_MIDI3+ RJ45_MIDI0- 2 10P_0402_50V8J D
LAN_MIDI3- 12 TD4+ MX4+ 13 RJ45_MIDI3- PR1- 10 LANGND 2 1 RJ45_GND SD_WP# 2 QL1
TD4- MX4- RJ45_MIDI0+ 1 GND G RL19 XEMC@ CL27 XEMC@
PR1+ L2N7002WT1G_SC-70-3
1 9 Connector side S SB00001GE00 0_0402_5% 10P_0402_50V8J
3
GND
3
SD_CLK_R 1 2 1 2
2
1
4
3
MESC5V02BD03_SOT23-3
GST5009-E @
CL25 SP050006B10 RPL1 SINGA_2RJ1660-000111F DL1
0.1U_0201_10V6K 2 75_0804_8P4R_1% CONN@ EMC@ JPL1 Close to JREAD1 for EMI
4 Place close to TCT pin JUMP_43X118 4
DC234009H00
8
5
6
7
LANGND
RJ45_GND
1

LAN RTL8411H
A B C D E
A B C D E
Wireless LAN
+3VALW W=60mils +3VS_W LAN
UM1
1U_0402_6.3V6K
CM15
5 1
IN OUT
1
2
@ GND
1 1
4 3
2 <39> W LAN_ON EN OC
SY6288C20AAC_SOT23-5
IOAC@
UART_2_PRXD_R_DTXD RM42 1 UART@ 2 0_0402_5%

+3VALW +3VS_W LAN UART_2_PTXD_R_DRXD UART_2_PRXD_DTXD <20>
RM43 1 UART@ 2 0_0402_5%
UART_2_PTXD_DRXD <20>
RM44 1 @ 2 0_0805_5% Co-layout with CNVi PH +3VS at SOC side,
+3VS for win7 USB3 debug
reserve for cnvi issue (1.0)
RM11 1 NIOAC@ 2 0_0805_5%
60mil 1 1 1 1@
CM12 @ CM13 CM19
4.7U_0402_6.3V6M 0.1U_0201_10V6K CM14 4.7U_0402_6.3V6M
2 2
0.1U_0201_10V6K
2 2 reserve 1000p for cnvi issue (1.0)
KEY E +3VS_W LAN

CM18 1
@
2 1000P_0402_50V7K
JNGFF1
1 2
USB20_P14 GND_1 3.3VAUX_2 CNVI@
3 4 1 RM41 2
<15> USB20_P14 USB20_N14 USB_D+ 3.3VAUX_4
USB2 Port.14 5 6 @ T52 75K_0402_1%
<15> USB20_N14 USB_D- LED1#
7 8
2 (For BT) RM22 1 2 0_0201_5% CNV_PRX_R_DTX_N1 9 GND_7 PCM_CLK 10 CNV_RF_RESET#_R RM34 1 2 0_0201_5% 2
<16> CNV_PRX_DTX_N1 SDIO_CLK PCM_SYNC CNV_RF_RESET# <19>
<16> CNV_PRX_DTX_P1 RM23 1 2 0_0201_5% CNV_PRX_R_DTX_P1 11 12
13 SDIO_CMD PCM_OUT 14 CLKREQ_CNV#_R RM35 1 2 0_0201_5%
SDIO_DAT0 PCM_IN CLKREQ_CNV# <19>
<16> CNV_PRX_DTX_N0 RM24 1 2 0_0201_5% CNV_PRX_R_DTX_N0 15 16 @ T53
RM25 1 2 0_0201_5% CNV_PRX_R_DTX_P0 17 SDIO_DAT1 LED2# 18
<16> CNV_PRX_DTX_P0 SDIO_DAT2 GND_18
19 20
RM26 1 2 0_0201_5% CLK_CNV_PRX_R_DTX_N 21 SDIO_DAT3 UART_WAKE 22 UART_2_PRXD_R_DTXD RM36 1 CNVI@ 2 0_0402_5%
<16> CLK_CNV_PRX_DTX_N SDIO_WAKE UART_TX CNV_BRI_PRX_DTX <16>
RM27 1 2 0_0201_5% CLK_CNV_PRX_R_DTX_P 23
<16> CLK_CNV_PRX_DTX_P SDIO_RST
24 UART_2_PTXD_R_DRXD RM37 1 CNVI@ 2 0_0402_5%
UART_RX CNV_RGI_PRX_R_DTX CNV_RGI_PTX_DRX <16>
25 26 RM38 1 2 0_0201_5%
PCIE_PTX_C_DRX_P15 GND_33 UART_RTS CNV_BRI_PTX_R_DRX CNV_RGI_PRX_DTX <16>
27 28 RM39 1 2 0_0201_5% CNV_BRI_PTX_DRX <16>
<18> PCIE_PTX_C_DRX_P15 PCIE_PTX_C_DRX_N15 PET_RX_P0 UART_CTS E51TXD_P80DATA_R
29 30 RM12 2 @ 1 0_0402_5%
<18> PCIE_PTX_C_DRX_N15 PET_RX_N0 CLink_RST E51RXD_P80CLK_R E51TXD_P80DATA <39>
31 32 RM13 2 @ 1 0_0402_5%
NGFF WL+BT (KEY E) (link to PICE Port 3)
PCIE X1
<18> PCIE_PRX_DTX_P15
PCIE_PRX_DTX_P15
PCIE_PRX_DTX_N15
33
35
GND_39
PER_TX_P0
CLink_DATA
CLink_CLK
34
36
E51RXD_P80CLK <39>
<18> PCIE_PRX_DTX_N15 PER_TX_N0 COEX3

37 38
CLK_PCIE_W LAN 39 GND_45 COEX2 40
<16> CLK_PCIE_W LAN CLK_PCIE_W LAN# REFCLK_P0 COEX1 SUSCLK_R
41 42 RM14 1 @ 2 0_0402_5%
<16> CLK_PCIE_W LAN# REFCLK_N0 SUSCLK(32KHz) W L_RST#_R SUSCLK <19,35>
(From PCH CLKOUT2) 43 44 RM15 1 @ 2 0_0402_5%
W LAN_CLKREQ# GND_51 PERST0# BT_ON PLT_RST_BUF# <17,35,36>
PCIE CLK <16> W LAN_CLKREQ# 45 46
W LAN_PME# CLKREQ0# W_DISABLE2# W L_OFF# BT_ON <39>
47 48
<39> W LAN_PME# PEWAKE0# W_DISABLE1# W L_OFF# <39>
49 50
RM28 1 2 0_0201_5% CNV_PTX_R_DRX_N1 51 GND_57 I2C_DAT 52
<16> CNV_PTX_DRX_N1 RSVD/PCIE_RX_P1 I2C_CLK
RM29 1 2 0_0201_5% CNV_PTX_R_DRX_P1 53 54 RM40 0_0201_5%
<16> CNV_PTX_DRX_P1 RSVD/PCIE_RX_N1 I2C_IRQ REFCLK_CNV_R
55 56 1 2 REFCLK_CNV <16>
RM30 1 2 0_0201_5% CNV_PTX_R_DRX_N0 57 GND_63 RSVD_64 58
<16> CNV_PTX_DRX_N0 RSVD/PCIE_TX_P1 RSVD_66 For CNVi Feature
RM31 1 2 0_0201_5% CNV_PTX_R_DRX_P0 59 60
<16> CNV_PTX_DRX_P0 RSVD/PCIE_TX_N1 RSVD_68
61 62 1 XEMC@
3 RM32 1 2 0_0201_5% CLK_CNV_PTX_R_DRX_N 63 GND_69 RSVD_70 64 CM17 3
<16> CLK_CNV_PTX_DRX_N RSVD_71 3.3VAUX_72
RM33 1 2 0_0201_5% CLK_CNV_PTX_R_DRX_P 65 66 0.1U_0201_10V6K
<16> CLK_CNV_PTX_DRX_P RSVD_73 3.3VAUX_74
67
GND_75 68 2 For ESD req reserve LC filter
69 GND1 close PCH
GND2
BELLW _80152-3221
CONN@
SP070013E00 E51TXD_P80DATA_R
1
2 1 W LAN_PME# RM19
+3VS_W LAN
RM16 10K_0402_5% 100K_0402_5%
2
reserve for BT_ON OD pull high (1.0)
BT_ON 1 @ 2 +3VS_W LAN

8.2K_0402_5% RM45
4 4
https:/ / Dr-Bios.com
M.2 Key E (WLAN)
A B C D E
A B C D E
DMIC3 Conn. (support on 256)

HD Audio Codec 2000mA 600ohm@100MHz
+3VS
DCR 0.1
+VDDA
40mil +5VS_PVDD
LA1 JDMIC1
FBMA-L11-201209601LMA20T_2P 1
1 2 LA7 DMIC_DATA34 2 1
DMIC_CLK 2 1 DMIC_CLK34 3 2
PN : SM01000EE00 +VDDA +5VS
40mil +VDDA 4 3
1 1 1 256@ BLM15PX221SN1D_2P
+5VS_AVDD 4
10U_0402_6.3V6M
CA1
0.1U_0201_10V6K
CA2
0.1U_0201_10V6K
CA3
JPA1 @ SM01000Q500 5
RA1 @ 1 2 6 G5
20mil 0_0603_5% G6
2 2 2 1 2 JUMP_43X39 ACES_50273-0040N-001
SP02000TI00
DA4
1 1 1 1 (output = 300 mA) DMIC_CLK34 1
0.1U_0201_10V6K
CA4
0.1U_0201_10V6K
CA5
10U_0402_6.3V6M
CA6
6 3
I/O4 I/O2
2 2 2 +3VS GND
near Pin41 near Pin46 down size for female gaming(1.0)
5 2
VDD GND
GNDA GND
4 1 DMIC_DATA34
CA7 1 2 0.1U_0201_10V6K
near Pin26 +1.8VS I/O3 I/O1
near Pin9 AZC099-04S.R7G_SOT23-6

CA8 1 2 10U_0603_6.3V6M XEMC@
+3VS +1.8VS_VDDA 1 @ 2
1 @ 2 +3VS_DVDDIO RA3 0_0402_5%
1 1
0.1U_0201_10V6K
CA11
10U_0402_6.3V6M
CA12
RA2 0_0402_5%
+3VS
20mil +3VS_DVDD
2 2
Int. Speaker Conn.
1 @ 2 GNDA
RA4 0_0402_5% 1 1
0.1U_0201_10V6K
CA10
10U_0603_6.3V6M
CA9
40mil JSPK1
SPKR+ EMC@1 LA2 2 HCB1608KF-121T30_0603 SPK_R+ 1
SPKR- EMC@1 LA3 2 HCB1608KF-121T30_0603 SPK_R- 2 1
2 2 HDA_BIT_CLK_R SPKL+ EMC@1 LA4 2 HCB1608KF-121T30_0603 SPK_L+ 3 2
near Pin1 Place near Pin40 SPKL- EMC@1 LA5 2 HCB1608KF-121T30_0603 SPK_L- 4 3
5 4
2
41
46
26
40
6 G1
9
10P_0402_50V8J 2 1 CA27 DMIC_CLK UA1 RA5
G2
0_0402_5%
DVDD
DVDD-IO
PVDD1
PVDD2
AVDD1
AVDD2
XEMC@ ACES_50278-00401-001
Reserved for RF SP02000RR00
1
XEMC@ @ JPA2
LINE1_L 22 43 SPKL- 1 2 GND CONN@
LINE1_R LINE1-L(PORT-C-L) SPK-OUT-L- 2 1 2
21 42 SPKL+
LINE1-R(PORT-C-R) SPK-OUT-L+ CA13 JUMP_43X79
24 45 SPKR+ 22P_0402_50V8J @ JPA3
2 23 LINE2-L(PORT-E-L) SPK-OUT-R+ 44 SPKR- 1 1 2 2
+MICBIAS LINE2-R(PORT-E-R) SPK-OUT-R- XEMC@ 1 2
31 JUMP_43X79
30 LINE1-VREFO-L 32 HP_LEFT
LINE1-VREFO-R HPOUT-L(PORT-I-L) 33 HP_RIGHT GND GND
+3VS RING2 17 HPOUT-R(PORT-I-R)
2 1 SENSE_A SLEEVE 18 MIC2-L(PORT-F-L) /RING
40mil MIC2-R(PORT-F-R) /SLEEVE 10 HDA_SYNC_R
RA13 100K_0402_1%
DMIC_DATA 2 SYNC 6 HDA_BIT_CLK_R HDA_SYNC_R <19>
DMIC_CLK 3 GPIO0/DMIC-DATA BCLK 5 HDA_SDOUT_R HDA_BIT_CLK_R <19>
GPIO1/DMIC-CLK SDATA-OUT 8 HDA_SDIN0_AUDIO 1 2 HDA_SDOUT_R <19>
<39> EC_MUTE#
47
PDB
SDATA-IN RA10 33_0402_5%
DMIC_DATA34
HDA_SDIN0 <19>
Digital MIC
48 1 256@ 2 single net
1 255@ 2 RESETB 11 SPDIF-OUT/GPIO2 RA45 0_0402_5%
<19> HDA_RST#_R
RA42 0_0402_5% RESETB 16 1 2 BEEP#_R MIC BOM upload by Audio Team
MONO_IN 12 MONO-OUT 1U_0402_6.3V6K
PCBEEP +MIC2_VREFO 256@ CA28
Close codec SENSE_A
RA12 2 1 200K_0402_1% 13 29
<44> HP_PLUG# HP/LINE1 JD(JD1) MIC2-VREFO
14
RA17 2 @ 1 20K_0402_5% 15 MIC2/LINE2 JD(JD2)
SPDIFO/FRONT JD(JD3)/GPIO3 7 CA14 1 2 10U_0402_6.3V6M
1 LDO3-CAP GND
37 39 CA16 1 2 10U_0603_6.3V6M TO eDP cable
CA15 35 CBP LDO2-CAP 27 CA17 1 2 10U_0402_6.3V6M DMIC_DATA 2 1 DMIC_DATA_R
GNDA CBN LDO1-CAP down size for female gaming(1.0) DMIC_DATA_R <33>
1U_0402_6.3V6K 10mil RA14 1 2 100K_0402_5% RA7 0_0402_5%
2
3V_1.8V_PVDD CODEC_VREF GNDA PCH_DMIC_DATA0 2
36 28 CA18 @1 2 10U_0402_6.3V6M <19> PCH_DMIC_DATA0 @ 1
CPVDD VREF RA8 33_0402_5%
CA20 1 2 2.2U_0402_6.3V6M
3V_5V_STB 20 PCH_DMIC_CLK0 2 @ 1
+3VS_DVDD VD33 STB <19> PCH_DMIC_CLK0
CA21 @1 2 0.1U_0201_10V6K RA9 33_0402_5%
1 255@ 2 3V_1.8V_PVDD CA19 1 2 19 34 CPVEE
GNDA MIC CAP CPVEE DMIC_CLK DMIC_CLK_R
1U_0402_6.3V6K
CA22
RA36 0_0402_5% 1 2 1
+1.8VS 10U_0402_6.3V6M LA6 EMC@ BLM15PX221SN1D_2P DMIC_CLK_R <33>
GNDA
1 256@ 2 SM01000Q500
RA37 0_0402_5% RA19 2 @ 1 0_0402_5% 4 25 change PN to SM01000Q500
3 49 DC DET AVSS1 38 2 3
+3VALW Thermal PAD AVSS2
1 255@ 2 3V_5V_STB
RA16 0_0402_5% ALC255-CG_MQFN48_6X6
+5VALW
GND SA000082700
1 256@ 2 GNDA
RA35 0_0402_5%
for ALC256 co-lay I2C for Co-lay ALC256 Headphone Out

+MIC2_VREFO
TO IO/B
RA15 1 2 2.2K_0402_5% SLEEVE SLEEVE <44>
RA18 1 2 2.2K_0402_5% RING2 RING2 <44>
+3VS_DVDD
HP_LEFT RA20 1 @ 2 0_0603_5% HPOUT_L_1 HPOUT_L_1 <44>

1
1
256@ HP_RIGHT RA21 1 @ 2 0_0603_5% HPOUT_R_1
HPOUT_R_1 <44>
RA41 256@
3.3K_0402_5% RA44
3.3K_0402_5% LINE1_L CA23 1 2 4.7U_0402_6.3V6M
2
RA22 2
22K_0402_5% 255@ CA25 MONO_IN LINE1_R CA24 1 2 4.7U_0402_6.3V6M
1U_0402_6.3V6K
2 1 BEEP#_R 1 2 MONO_IN RA25 1 @ 2 0_0402_5% RA26 1 @ 2 0_0402_5%
<39> BEEP#
RESETB +MICBIAS DA3
2
RA27 1 RA29 1 @ 2 0_0402_5% RA30 1 @ 2 0_0402_5% 2 2 RA23 1

22K_0402_5% XEMC@ 4.7K_0402_5%
100P_0402_50V8J
CA26
4 2 1 RA24 1 4
<19,20> PCH_SPKR 4.7K_0402_5% RA31 1 @ 2 0_0402_5% RA32 1 @ 2 0_0402_5%
2 3 2 RA28 1
1
4.7K_0402_5%
RA33 1 @ 2 0_0402_5% RA34 1 @ 2 0_0402_5% BAT54A-7-F_SOT23-3
SCSBAT54100
GND
GND GNDA GND GNDA
HD Audio Codec ALC255
A B C D E
A B C D E
Board ID
+3VLP_EC
+3VLP_EC +3VLP_ECA
2
+3VLP LB1
JPB1 FBMA-L11-160808-800LMT_0603 RB1
1 2 1 2 +3VLP_ECA 100K_0402_1%
1 2 Ra
JUMP_43X39
1
AD_BID
0.1U_0201_10V6K
0.1U_0201_10V6K
@ 1 1 1
CB1
CB2
CB3
2
RB3 1
+3VLP_EC @ RB2 0.1U_0201_10V6K RB3 @ CB4
1 For Power consumption 2 2 2 1
0_0402_5% 20K_0402_1% Rb 0.1U_0201_10V6K
Measurement VX15@ V15@
RB4 1 @ 2 47K_0402_5% EC_PME# ECAGND 240K_0402_1% 2
ECAGND <49>
1
+3VLP_LPC
SD000001B80
change board ID to 1A
111
125
22
33
96
67
9
UB1
ESPI Bus Pin : 1~5.7.8.10.12.14
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
VCC0
LPC Bus Pin : 3~5.7.8.10.12.13
Analog Board ID definition,
Please see page 3.
For turn off internal LPC module of KB9032 SUSPWRDNACK 1 21 EC_VCCST_PG_R
<19> SUSPWRDNACK CHG_CTL3 GATEA20/GPIO00 EC_VCCST_PG/GPIO0F EC_VCCST_PG_R <11,47>
2 23 BEEP#
<42> CHG_CTL3 TPM_SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 FAN_PWM1 BEEP# <38>
XEMC@
1 2 100P_0402_50V8J PLT_RST# <18,45> TPM_SERIRQ LPC_FRAME# 4 SERIRQ EC_FAN_PWM/GPIO12 27 FAN_PWM2 FAN_PWM1 <46>
CB5 PWM Output
<18,45> LPC_FRAME# LPC_AD3 5 LPC_FRAME# AC_OFF/GPIO13 FAN_PWM2 <46>
<18,45> LPC_AD3 LPC_AD2 LPC_AD3 near SOC PCH_RTCRST# <19>
7
<18,45> LPC_AD2 LPC_AD2
1
CB6 1 2 100P_0402_50V8J AC_IN LPC_AD1 8 63 BATT_TEMP D
<18,45> LPC_AD1 LPC_AD0 10 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 64 CHG_CTL1 BATT_TEMP <49,50> EC_CLR_CMOS 2
LPC & MISC QB6
<18,45> LPC_AD0 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 65 ADP_I CHG_CTL1 <42>
G L2N7002WT1G_SC-70-3
ADP_I/AD2/GPIO3A ADP_I <49,50>
1
XEMC@ XEMC@ CLK_LPC_R 12 66 AD_BID
AD Input S SB00001GE00
3
2 1 2 1 CLK_LPC_R <18> CLK_LPC_R PLT_RST# 13 CLK_PCI_EC AD_BID/AD3/GPIO3B 75 WLAN_PME# RB26
<17> PLT_RST# EC_RST# PCIRST#/GPIO05 AD4/GPIO42 EC_PME# WLAN_PME# <37>
CB7 RB6 37 76 10K_0402_5%
<46> EC_RST# EC_SCI# 20 EC_RST# AD5/GPIO43 EC_PME# <17,36>
22P_0402_50V8J 33_0402_5%
<20> EC_SCI# WLAN_ON 38 EC_SCI#/GPIO0E
<37> WLAN_ON
2
CLKRUN#/GPIO1D
68 LAN_PWR_EN
<45> KSI[0..7] DA0/GPIO3C EC_TP_INT# LAN_PWR_EN <36>
DA Output EN_DFAN1/DA1/GPIO3D 70
55 71 VR_PWRGD EC_TP_INT# <17,45>
KSI0
KSI1 56 KSI0/GPIO30 DA2/GPIO3E 72 KBL_EN
+3VLP_EC 57 KSI1/GPIO31 DA3/GPIO3F KBL_EN <45>
KSI2
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
EC_SMB_CK1 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A USB_EN EC_MUTE# <38> SYS_PWROK_R
RB10 1 2 2.2K_0402_5% KSI4 59 84 1 @ 2 SYS_PWROK <19,47>
2 1 2 2.2K_0402_5% EC_SMB_DA1 60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85 EC_TYPEC_EN# USB_EN <44> 2
RB11 KSI5 RB7 0_0402_5%
61 KSI5/GPIO35 PSCLK2/GPIO4C 86 CHG_EN EC_TYPEC_EN# <40>
KSI6 PS2 Interface
62 KSI6/GPIO36 PSDAT2/GPIO4D 87 TP_CLK CHG_EN <42>
KSI7
<45> KSO[0..17] 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_DATA TP_CLK <45>
KSO0
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <45> +3VS
KSO1 40
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 ENBKL
43 KSO3/GPIO23 ENKBL/GPXIOA00 98 TP_PWR_EN ENBKL <18,25> GPU_ALERT 1 VGA@ 2 10K_0402_5%
KSO4 RB9
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 ME_EN TP_PWR_EN <45>
KSO5
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH ME_EN <19> GPU_OVERT# RB12 1 VGA@ 2 10K_0402_5%
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <49>
KSO8 47 KSO7/GPIO27
SPOK_3V RB72 KSO8/GPIO28 SPI Device Interface SPOK_5V
1 2 0_0402_5% KSO9 48 119
49 KSO9/GPIO29 MISO/GPIO5B 120 BT_ON SPOK_5V <51>
KSO10
KSO10/GPIO2A MOSI/GPIO5C EC_CLR_CMOS BT_ON <37> +3VLP_EC
KSO11 50 SPI Flash ROM SPICLK/GPIO58 126
SPOK_5V RB73 1 2 0_0402_5% SPOK_3V5V KSO12 51 KSO11/GPIO2B 128 FP_PWR_EN
@
KSO12/GPIO2C SPICS#/GPIO5A FP_PWR_EN <46> EC Internal PU
KSO13 52
KSO14 53 KSO13/GPIO2D LID_SW# RB13 1 2 100K_0402_1%
KSO15 54 KSO14/GPIO2E 73 GPU_ALERT
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 SYS_PWROK_R GPU_ALERT <25>
KSO16 81 74
KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89
KSO17/GPIO49 GPIO50 BATT_BLUE_LED# BATT_4S <50> add for 4C Batt (1.0)
90
For abnormal shutdown BATT_CHG_LED#/GPIO52 91 CAPS_LED# BATT_BLUE_LED# <44>
For Thermal Portect Shutdown
EC_SMB_CK1 CAPS_LED#/GPIO53 PWR_LED# CAPS_LED# <45>
77 GPIO 92
SPOK_3V5V EC_RSMRST# <49,50> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 BATT_AMB_LED# PWR_LED# <44>
1 2 78 93
<49,50> EC_SMB_DA1 79 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 95 BATT_AMB_LED# <44>
DB2 RB751V-40_SOD323-2 SYSON DB1
<19,25,40,44> EC_SMB_CK2 80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 VR_ON SYSON <47,52,54>
RB751V-40_SOD323-2
<19,25,40,44> EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 127 CHG_ILMSEL VR_ON <47,55,56,57> 1 2 3V_EN
MAINPWON
1 2 PCH_PWROK DPWROK_EC/GPIO59 CHG_ILMSEL <42> 3V_EN <51>
PU at CPU side SM Bus 1
DB3 RB751V-40_SOD323-2 RB14
PM_SLP_S3# 6 100 EC_RSMRST# CB8 3V_EN_R 1 2 RB15 1 2
<19,47> PM_SLP_S3# ESPI_RST# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 DGPU_AC_DETECT EC_RSMRST# <19>
.1U_0402_16V7K 1M_0402_5%
1 2 EC_VCCST_PG_R <18> ESPI_RST# SPOK_3V 15 GPIO07 GPXIOA04 102 VCIN1_ADP_PROCHOT DGPU_AC_DETECT <20,25,50> 2
XEMC@ 1K_0402_5%
<51,54> SPOK_3V TP_EN 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 VCOUT1_PROCHOT VCIN1_ADP_PROCHOT <49>
DB4 RB751V-40_SOD323-2
<45> TP_EN TS_EN GPIO0A VCOUT1_PROCHOT#/GPXIOA06
17 104 MAINPWON
<20,33> TS_EN WL_OFF# 18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 MAINPWON <46,49,51>
3 BKOFF# 3
<37> WL_OFF# AC_PRESENT 19 GPIO0C BKOFF#/GPXIOA08 106 THERMAL_ALERT# BKOFF# <33>
<19> AC_PRESENT GPU_OVERT# AC_PRESENT/GPIO0D GPIO GPO GPXIOA09 3V_EN_R THERMAL_ALERT# <44>
25 107
<25> GPU_OVERT# FAN_SPEED1 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 PM_SLP_S0#
28 108
VCOUT1_PROCHOT <46> FAN_SPEED1 FAN_SPEED2 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 PM_SLP_S0# <19>
29
<46> FAN_SPEED2 E51TXD_P80DATA 30 FANFB1/GPIO15
<37> E51TXD_P80DATA EC_TX/GPIO16
2
E51RXD_P80CLK 31 110 AC_IN

<37> E51RXD_P80CLK PCH_PWROK 32 EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 112 EC_ON AC_IN <50>
RB19
<19,47> PCH_PWROK PWR_SUSP_LED# 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <51>
@ 0_0402_5% ON/OFFBTN#
<44> PWR_SUSP_LED# NUM_LED# SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 LID_SW# ON/OFFBTN# <45>
36 GPI 115
<45> NUM_LED# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 LID_SW# <44>
SUSP# FOLLOW TD
SUSP# <47,50,52,55>
1
SUSP#/GPXIOD05 117 SW_PROCHOT# @ RB74

DGPU_AC_DETECT SW_PROCHOT# GPXIOD06 118 EC_PECI 1 2 0_0402_5%
PBTN_OUT# PECI/GPXIOD07 H_PECI <11,18> VR2_HOT#
122 RB16 33_0402_1% 1 2
<19> PBTN_OUT# PM_SLP_S4# PBTN_OUT#/GPIO5D VR2_HOT# <57>
@ @ 123 124
<19,47> PM_SLP_S4# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +3VLP_EC
QB1A QB1B @ RB17
3
6
AGND
2N7002KDW_SOT363-6 D D 2N7002KDW_SOT363-6 0_0402_5%

GND
GND
GND
GND
GND
VCOUT1_PROCHOT 2 5 VCOUT1_PROCHOT 1 2 VR_HOT#

G G VR_HOT# <56>
KB9022QD_LQFP128_14X14 @ RB18
11
35
113
24
94
ECAGND 69
S S 0_0402_5%
CO-LAY with KB9032QA (SA000080J00) 20mil
4
1
H_PROCHOT# 1 2 SW_PROCHOT#
2 BATT_TEMP <11,50> H_PROCHOT#
CB9 1
100P_0402_50V8J
LB2 2 1
FBMA-L11-160808-800LMT_0603
2015/1/9 acer require:

reserved protact circuit when
remove CNVI detect pin on EC(1.0) adaptor 107% happen
RB78 2 @ 1 0_0402_5% VR_PWRGD

<56> VCCCORE_VR_PWRGD
4 4
RB77 2 @ 1 1K_0402_5%
<57> VCCSA_VR_PWRGD
check VR_PWRGD IS
AND BY CORE_PWRGD & SA_PWRGD

EC ENE-KB9012A4/KB9022
A B C D E
5 4 3 2 1
+3.3V_CC +3.3V_CC
+5VALW +5V_CC
US2
2
TYPEC@ CS90 2 1
0.1U_0402_10V6K 6 1 20 mils RS103 RS105
IN OUT 10K_0402_5% 10K_0402_5%
RS156 2 TYPEC@1 100K_0402_5% 5 2 1 TYPEC@ TYPEC@ TYPEC@
SET GND CS101
1
RS155 1 TYPEC@2 1K_0402_5% 4 3 0.1U_0201_10V6K CUR_MODE0 CUR_MODE1
+3VALW EN(/EN) FLAG
2
2
D 1 D
1
@ G527ATP1U_TSOT23-6 RS106
CS124 TYPEC@ 10K_0402_5%
2.2U_0402_6.3V6M SA00006Y700 RS104 @
2 10K_0402_5%
1
@
2
0.2A OCP for VCONN!
Initial Current mode selection
+3VALW +3.3V_CC
CUR_MODE0 CUR_MODE1 MODE
H L Default Current
RS1 1 2 0_0603_5% L H Medium current
1.0 Modify H H High current
+USB3_VCCC RSET
US3 +5V_CC
TYPEC@
1
1
RS101 1 10 RS113 RS109 RS110
C 39K_0402_1% GPIO2(INT#) VCONN 6.2K_0402_5% 8.2K_0402_5% 4.3K_0402_5% C
TYPEC@ 2 9 +3.3V_CC CS91 1 2 2.2U_0402_6.3V6M TYPEC@ TYPEC@ TYPEC@
CUR_DR VDD33 TYPEC@
2
3 2
8 +1.8V_CC CS92 1 2 1U_0402_6.3V6K
VBUS_DC 179F_SMB_DA2 3 VDD18 TYPEC@ D
179F_SMB_CK2 4 SI0(SDA) 5
SI1(SCL) TYPEC_3A <19>
1
11 G
VBUS_DC CC1 CC1_VCONN <41>
RS102 7 12 CC2_VCONN <41>
CUR_MODE0 14 VBUS_DC CC2 S QS4B TYPEC@
3.01K_0402_1%
4
CUR_MODE0
6
TYPEC@ CUR_MODE1 15 QS4A D 2N7002KDW _SOT363-6
CUR_MODE1 16 TYPEC@ 2 TYPEC_1P5A <17>
2
CC_EN 5 2N7002KDW _SOT363-6 G

CC_SEL VBUS_EN_179
TYPC_CONN_DET
13 checked bios
S
1
1
6 17
GND EPAD
Scaled input TYPEC@
for detection of VBUS DC levels RS116
EJ179F_QFN16_4X4 10K_0402_5%
G518 MOS Current Limit
2
1.0 Modify GPP_B1 GPP_B4 RSET(kΩ ) MODE limit point
(TYPEC_3A) (TYPEC_1P5A)
Remove INT#, L L 6.2 0.9A 1.09A
platform doesn't monitor it
L H 3.53 1.5A 1.92A
CC_SEL
report CC1 or CC2 is connection H L 2.54 2A 2.67A
B
CC_EN *H H 1.94 3A 3.5A B
power path control "low active" +5VALW
+USB3_VCCC
150U_D2_6.3VM_R17M
EC need change to low active +3.3V_CC
1
1
0.1U_0402_10V6K
CS96
CS95
0.1U_0402_25V6
CS97 @
+
1 1 1
22U_0805_25V6M
CS98 @
22U_0805_25V6M
CS99 @
TYPEC@
TYPEC@
2 2
1
@ @ US11 2 2 2
+3.3V_CC RS108 RS107 TYPEC@
4.7K_0402_5% 4.7K_0402_5% 6 1
IN OUT
+5VALW
2
RSET 5 2
SET GND
5
1
G
QS1B @ VBUS_EN_179 4 3 1 @ 2
EN FLAG USB_OC0# <15>
PU on SOC side
@ RS111 Initial Current mode selection
100K_0402_5% SY6861B1ABC_TSOT23-6 RS112 1
179F_SMB_CK2
4 3 footprint : G518 0_0402_5% VBUS_EN_179 EC_TYPEC_EN# V BUS
S
<19,25,39,44> EC_SMB_CK2
2
D
CS100
PN : SA0000BDN00(SILERGY SY6861B1)
6
2N7002KDW _SOT363-6
<39> EC_TYPEC_EN#
D
2
0.1U_0201_10V6K L H 0
2
3
2
G 2N7002KDW _SOT363-6 D L L 0
G
EC need change to low act i ve QS3A @ 5

S G pop for intel sensitive net H H 0
1
A 179F_SMB_DA2 (1.0) A
1 6 S QS3B @ H L 1
S
<19,25,39,44> EC_SMB_DA2
4
D
2N7002KDW _SOT363-6
2N7002KDW _SOT363-6
@ QS1A
RS114 2 @ 1 0_0402_5%
2017/12/18
Compal Secret Data
2018/09/01 Title
RS115 2 @ 1 0_0402_5%
CC+USB TYPE C
Custom

5 4 3 2 1
5 4 3 2 1
Change to 0201 for placement. 1A modify

D
USB3.0 (Port 3) D
RS64 1 @ 2 0_0201_5% USB3_PTX_L_DRX_P2 CS58 1 2 0.22U_0402_16V7K USB3_PTX_C_DRX_P2

<18> USB3_PTX_DRX_P2 For ESD request
RS65 1 @ 2 0_0201_5% USB3_PTX_L_DRX_N2 CS59 1 2 0.22U_0402_16V7K USB3_PTX_C_DRX_N2 DS3 EMC@ DS6 EMC@
<18> USB3_PTX_DRX_N2 USB3_PTX_L_DRX_P2 USB3_PTX_L_DRX_P2 USB20_P2_L USB20_P2_L
1 9 1 9
USB3_PRX_DTX_P2 RS74 1 @ 2 0_0201_5% USB3_PRX_L_DTX_P2
<18> USB3_PRX_DTX_P2 USB3_PTX_L_DRX_N2 USB3_PTX_L_DRX_N2 USB20_N2_L USB20_N2_L
2 8 2 8
USB3_PRX_DTX_N2 RS76 1 @ 2 0_0201_5% USB3_PRX_L_DTX_N2
<18> USB3_PRX_DTX_N2 CC1_VCONN CC1_VCONN USB3_PRX_L_DTX_N3 4 USB3_PRX_L_DTX_N3
4 7 7
TBTA_SBU1 5 6 TBTA_SBU1 USB3_PRX_L_DTX_P3 5 6 USB3_PRX_L_DTX_P3
1A modify
USB3.0 (Port 4)
RS82 1 @ 2 0_0201_5% USB3_PTX_L_DRX_P3 CS60 1 2 0.22U_0402_16V7K USB3_PTX_C_DRX_P3 3 3
<18> USB3_PTX_DRX_P3
RS83 1 @ 2 0_0201_5% USB3_PTX_L_DRX_N3 CS61 1 2 0.22U_0402_16V7K USB3_PTX_C_DRX_N3 TVW DF1004AD0_DFN9 TVW DF1004AD0_DFN9
<18> USB3_PTX_DRX_N3
USB3_PRX_DTX_P3 RS84 1 @ 2 0_0201_5% USB3_PRX_L_DTX_P3 SC300003Z00 SC300003Z00
<18> USB3_PRX_DTX_P3 DS4 DS5
EMC@ EMC@
USB3_PRX_DTX_N3 RS85 1 @ 2 0_0201_5% USB3_PRX_L_DTX_N3 1 9 CC2_VCONN 1 9 CC2_VCONN
<18> USB3_PRX_DTX_N3
2 8 TBTA_SBU2 2 8 TBTA_SBU2
USB3_PTX_L_DRX_N3 4 7 USB3_PTX_L_DRX_N3 USB3_PRX_L_DTX_N2 4 7 USB3_PRX_L_DTX_N2
USB3_PTX_L_DRX_P3 5 6 USB3_PTX_L_DRX_P3 USB3_PRX_L_DTX_P2 5 6 USB3_PRX_L_DTX_P2
C C
DLM0NSN900HY2D_4P
USB20_P2 2 1 USB20_P2_L 3 3
<15> USB20_P2 2 1
TVW DF1004AD0_DFN9 TVW DF1004AD0_DFN9
USB20_N2 3 4 USB20_N2_L
<15> USB20_N2 3 4 SC300003Z00 SC300003Z00
LS10 EMC@
SM070005U00
add topology for intel ECN_Update (1.0) +USB3_VCCC +USB3_VCCC
USB3_PRX_L_DTX_P2 CS102 1 2 0.33U_0402_10V6K USB3_PRX_C_DTX_P2

JTYPEC1
USB3_PRX_L_DTX_N2 CS103 1 2 0.33U_0402_10V6K USB3_PRX_C_DTX_N2 A1 B12
GND GND
USB3_PTX_C_DRX_P2 A2 B11 USB3_PRX_C_DTX_P2
SSTXP1 SSRXP1
1
USB3_PTX_C_DRX_N2 A3 B10 USB3_PRX_C_DTX_N2

RS119 RS120 0.1U_0402_25V6 2 1 CS84 SSTXN1 SSRXN1
220K_0402_5% 220K_0402_5% A4 B9 CS87 1 2 0.1U_0402_25V6
B VBUS VBUS B
A5 B8 TBTA_SBU2
<40> CC1_VCONN
2
CC1 SBU2
1
CS13
10U_0805_25V6K USB20_P2_L A6 B7 USB20_N2_L
USB20_N2_L A7 DP1 DN2 B6 USB20_P2_L
2
DN1 DP2
3
TBTA_SBU1 A8 B5
SBU1 CC2 CC2_VCONN <40>
DS19 EMC@ 0.1U_0402_25V6 2 1 CS86 A9 B4 CS85 1 2 0.1U_0402_25V6
MESC5V02BD03_SOT23-3 VBUS VBUS
USB3_PRX_L_DTX_P3 CS104 1 2 0.33U_0402_10V6K USB3_PRX_C_DTX_P3 USB3_PRX_C_DTX_N3 A10 B3 USB3_PTX_C_DRX_N3
USB3_PRX_C_DTX_P3 A11 SSRXN2 SSTXN2 B2 USB3_PTX_C_DRX_P3
USB3_PRX_L_DTX_N3 CS105 1 2 0.33U_0402_10V6K USB3_PRX_C_DTX_N3 SSRXP2 SSTXP2
A12 B1
GND GND
1
1
RS121 RS122 1 5
220K_0402_5% 2 GND GND 6
220K_0402_5% GND GND
3 7
4 GND GND 8
2
GND GND
LOTES_AUSB0249-P001A
CONN@
Follow intel #575549 for ESD/EOS protection.

A A
CC1_VCONN & CC2_VCONN need 20miil trace width.

2017/12/18
Compal Secret Data
2018/09/01 Title
CC+USB TYPE C
Custom

5 4 3 2 1
A B C D E
USB3.0 /2.0 CMC

<18> USB3_PTX_DRX_P1 1 2 USB3_PTX_C_DRX_P1 RS86 1 @ 2 0_0402_5% USB3_PTX_L_DRX_P1
CS2 .1U_0402_16V7K
<18> USB3_PTX_DRX_N1 1 2 USB3_PTX_C_DRX_N1 RS89 1 @ 2 0_0402_5% USB3_PTX_L_DRX_N1

1 CS3 .1U_0402_16V7K DLM0NSN900HY2D_4P 1
U2DP1 2 1 U2DP1_L
2 1
USB3_PRX_DTX_P1 RS90 1 @ 2 0_0402_5% USB3_PRX_L_DTX_P1
<18> USB3_PRX_DTX_P1 U2DN1_L +USB3_VCCA
U2DN1 3 4
3 4
USB3_PRX_DTX_N1 1 2 0_0402_5% USB3_PRX_L_DTX_N1 LS1 EMC@
<18> USB3_PRX_DTX_N1
RS91 @ W=100mils
SM070005U00
1 2
EMC@
CS5 + CS6
150U_D2_6.3VM_R17M .1U_0402_16V7K
SGA00009000 1
2
USB3.0 Conn.
ESD request U2DN1_L
1
2
JUSB1
VBUS
DS1 EMC@ U2DP1_L 3 D-
USB3_PTX_L_DRX_P1 1 9 USB3_PTX_L_DRX_P1 4 D+
DS2 EMC@ USB3_PRX_L_DTX_N1 5 GND
USB3_PTX_L_DRX_N1 2 8 USB3_PTX_L_DRX_N1 6 3 U2DN1_L USB3_PRX_L_DTX_P1 6 SSRX- 10
I/O4 I/O2 7 SSRX+ GND 11
USB3_PRX_L_DTX_P1 4 7 USB3_PRX_L_DTX_P1 +USB3_VCCA USB3_PTX_L_DRX_N1 8 GND GND 12
USB3_PTX_L_DRX_P1 9 SSTX- GND 13
USB3_PRX_L_DTX_N1 5 6 USB3_PRX_L_DTX_N1 5 2 SSTX+ GND
VDD GND ACON_TARB5-9V1391
CONN@
2 2
3 4 1 U2DP1_L DC23300NH00
I/O3 I/O1
TVW DF1004AD0_DFN9 AZC099-04S.R7G_SOT23-6
SC300003Z00
USB Host Charger 0904 vendor recommend

+5VALW
RS8 1 @ 2 0_1206_5%
22U_0603_6.3V6M
.1U_0402_16V7K
1 1
CS9
CS7
@ CHG@
2 2 US12 +USB3_VCCA
CHG@
+5VALW _CHG 1 12
VIN VOUT
3 2 3
<15> USB20_N1 DM_OUT
RS11 3
<15> USB20_P1 DP_OUT
0_0402_5% 10 U2DP1
USB_OC1# 2 @ 1 13 DP_IN 11 U2DN1
<15> USB_OC1# FAULT# DM_IN
CHG_ILMSEL 4
1 <39> CHG_ILMSEL ILIM_SEL
CS8 CHG_EN 5 15
0.1U_0201_10V6K
<39> CHG_EN EN ILIM_L 16
0831 Reserve ILIM_L R as vendor recommend
+5VALW @ 2 ILIM_HI
1
CHG_CTL1 6
<39> CHG_CTL1 CHG_CTL2 CTL1
22.1K_0402_1%
39K_0402_1%
7 9
CHG_CTL3 CTL2 NC
RS12
RS13
CHG@ 8 14
CHG_CTL2 <39> CHG_CTL3 CTL3 GND
RS14 1 2 10K_0402_5% 17
Thermal Pad CHG@ @
2
@ SLGC55544CVTR_TQFN16_3X3
RS15 1 2 10K_0402_5% CHG_ILMSEL
0911 Rerserve PU, vendor suggest to EC control

if future need support SDP2 ILM R vaule
Ios(mA)=50250/R(Kohm)
ILIM_Hi=2273mA
ILIM_L=1288mA(reserve)
4 USB Host Charger Truth Table 4
CHG_EN CTL1 CTL2 CTL3 ILIM_SEL MODE Current Limit Note

Setting
0 0 1 0 1 SDP1-OFF ILIM_H Port power off
1 0 1 0 1 SDP1 ILIM_H Data Lines Connected
1 0 1 1 1 DCP ILIM_H Data Lines Disconnected
Auto THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 Conn/USB Charger
1 1 1 1 1 CDP ILIM_H Data Lines Connected DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
A B C D E
A B C D E
SATA Re-Driver and cable HDD Conn.
B_EQ1
A_EQ2
A_EQ1
co-lay w/o re-driver
DEW
+3VS
RO24 1
0_0402_5%
2 SATA_PTX_C_DRX_P4_NRD
SATANRD@
CO1
2 1
FFC JHDD1
Type
1 RO23 1 2 SATA_PTX_C_DRX_N4_NRD 14 1
0_0402_5% SATANRD@ 0.01U_0402_16V7K UO1 +5VS 13 GND
20
19
18
17
16
SATARD@ PS8527CTQFN20GTR2A_TQFN20_4X4 GND
SATARD@ RO4 1 2 0_0805_5% +5VS_HDD 12
VDD2
B_EQ1
A_EQ2
A_EQ1
DEW
SATARD@ 11 12
SATARD@ 10 11
CO4 2 1 SATA_PTX_C_DRX_P4 0.01U_0402_16V7K 1 15 RDSATA_PTX_DRX_P4 G_INT2_R 9 10
<18> SATA_PTX_DRX_P4 A_INP A_OUTP 9
<18> SATA_PTX_DRX_N4 CO5 2 1 SATA_PTX_C_DRX_N4 0.01U_0402_16V7K 2 14 RDSATA_PTX_DRX_N4 JHDD_P8 8
3 A_INN A_OUTN 13 B_EQ2 7 8
CO8 2 1 SATA_PRX_C_DTX_N4 0.01U_0402_16V7K 4 GND1 B_EQ2 12 RDSATA_PRX_DTX_N4 RDSATA_PRX_C_DTX_P4 6 7
<18> SATA_PRX_DTX_N4 B_OUTN B_INN RDSATA_PRX_C_DTX_N4 6
CO9 2 1 SATA_PRX_C_DTX_P4 0.01U_0402_16V7K 5 11 RDSATA_PRX_DTX_P4 5
<18> SATA_PRX_DTX_P4 B_OUTP B_INP 5
SATARD@ 21 4
GND2 RDSATA_PTX_C_DRX_N4 4
REXT
VDD1
B_DE
A_DE
SATARD@ 3
RDSATA_PTX_C_DRX_P4 2 3
EN
RO22 1 2SATA_PRX_C_DTX_N4_NRD 1 2
0_0402_5% SATANRD@ 1
6
7
8
9
10
RO21 1 2SATA_PRX_C_DTX_P4_NRD ACES_51625-01201-001
0_0402_5% SATANRD@ SATARD@ +3VS +5VS_HDD CONN@
RO7 2 1 +3VS SP010028W00
+3VS
0.1U_0201_10V6K
SATARD@
4.99K_0402_1% 1 @ JPO1 100mils
B_DE
A_DE
CO10
1 2
1 RO9 @ 2 1 2
10U_0603_6.3V6M
CO12
4.7K_0402_5% JUMP_43X79 1 1
Cable Type
1
+3VS 2 @ JPO2
1 2 CO11 CO13
RO6 1 @ 2 4.7K_0402_5% A_DE 1 2 0.1U_0201_10V6K 0.1U_0201_10V6K JHDD2
2
JUMP_43X79 2 @ 2 @ 1
RO8 1 @ 2 4.7K_0402_5% B_DE 2 1
+3VS 3 2
B_EQ1
USE 8527 re-driver GND GND
3
2 RO10 1 @ 2 4.7K_0402_5% 4 2
SA00007JU10 5 4
RO11 1 @ 2 4.7K_0402_5% A_EQ1 6 5
7 6
RO12 1 @ 2 4.7K_0402_5% A_EQ2 8 7
+5VS_HDD 9 8
RO13 1 @ 2 4.7K_0402_5% B_EQ2 10 9
11 10
RO14 1 @ 2 4.7K_0402_5% DEW G_INT2 1 @ 2 G_INT2_R 12 11
RO5 0_0402_5% JHDD_P8 13 12
14 13
RO15 1 @ 2 4.7K_0402_5% A_DE RDSATA_PRX_DTX_P4 CO7 1 2 0.01U_0402_16V7K RDSATA_PRX_C_DTX_P4 15 14
SATARD@ RDSATA_PRX_C_DTX_N4 16 15
RO16 1 @ 2 4.7K_0402_5% B_DE RDSATA_PRX_DTX_N4 CO6 1 2 0.01U_0402_16V7K 17 16
SATARD@ RDSATA_PTX_C_DRX_N4 18 17
RO17 1 @ 2 4.7K_0402_5% B_EQ1 RDSATA_PTX_DRX_N4 CO3 1 2 0.01U_0402_16V7K RDSATA_PTX_C_DRX_P4 19 18
SATARD@ 20 19
RO18 1 SATARD@
2 4.7K_0402_5% A_EQ1 RDSATA_PTX_DRX_P4 CO2 1 2 0.01U_0402_16V7K 21 20
SATARD@ 22 G1
RO19 1 SATARD@
2 4.7K_0402_5% A_EQ2 23 G2
SATA_PRX_C_DTX_P4_NRD CO16 1 2 0.01U_0402_16V7K 24 G3
RO20 1 SATARD@
2 4.7K_0402_5% B_EQ2 SATANRD@ G4
SATA_PRX_C_DTX_N4_NRD CO14 1 2 0.01U_0402_16V7K ACES_50406-02071-001
SATANRD@ CONN@
SATA_PTX_C_DRX_N4_NRD CO17 1 2 0.01U_0402_16V7K SP010016L00
SATANRD@
SATA_PTX_C_DRX_P4_NRD CO18 1 2 0.01U_0402_16V7K
SATANRD@
3 3
co-lay w/o re-driver
+3VS
1
RZ1
10K_0402_5%
GSEN@
UZ1
G-Sensor +3VS
GSEN@
2
1 CZ1 1 2 10U_0603_6.3V6M
8 Vdd_IO
4 CS 14 1 2 GSEN@
<19,23,24> D_CK_SCLK SCLSPC Vdd
6 CZ2 0.1U_0201_10V6K
<19,23,24> D_CK_SDATA SDA/SDI/SDO
+3VS RZ2 1 @ 2 10K_0402_5% 7
RZ3 1 GSEN@ 2 10K_0402_5% SDO/SA0 11 G_INT
INT1 G_INT2 G_INT <20>
16 9
15 ADC1 INT2
13 ADC2 10 INT1/2 all High Active
ADC3 RES
2
3 NC 5
NC GND 12
GND
LIS3DHTR_LGA16_3X3
GSEN@
4 4
LIS3DH
SA0 ->0, Address is 0011 000 (0x30h)
SA0 ->1, Address is 0011 001 (0x32h)

HDD/ Re-Driver/ G-sensor
A B C D E
A B C D E
JIO2
JIO3
To USB/B FPC BTB CONN HPOUT_L_1
HPOUT_R_1
1
2 1
2
<38>
<38>
HPOUT_L_1
HPOUT_R_1
HPOUT_L_1
HPOUT_R_1
1
2 1
2
SLEEVE 3 <38> SLEEVE SLEEVE 3
DLM0NSN900HY2D_4P RING2 4 3 RING2 4 3
To Hall sensor/B
USB20_P3 USB20_L_P3 HP_PLUG# 4 <38> RING2 HP_PLUG# 4
2 1 5 <38> HP_PLUG# 5
<15> USB20_P3 2 1 5 5
GNDA 6 GNDA 6
SUB_PIN7 7 6 SUB_PIN7 7 6
USB20_N3 3 4 USB20_L_N3 8 7 8 7
<15> USB20_N3 3 4 USB20_L_P3 8 USB20_L_P3 8 +3VLP
9 9
LS11 EMC@ USB20_L_N3 10 9 USB20_L_N3 10 9
1 1
11 10 11 10 JHS1
SM070005U00 USB20_L_P4 12 11 USB20_L_P4 12 11 1
USB20_L_N4 13 12 USB20_L_N4 13 12 LID_SW # 2 1
13 13 <39> LID_SW# 2
14 14 3
BATT_AMB_LED# 15 14 BATT_AMB_LED# 15 14 4 3
DLM0NSN900HY2D_4P BATT_BLUE_LED# 15 <39> BATT_AMB_LED# BATT_BLUE_LED# 15 4
16 <39> BATT_BLUE_LED# 16
USB20_P4 1 2 USB20_L_P4 PWR_SUSP_LED# 17 16 PWR_SUSP_LED# 17 16 5
<15> USB20_P4 1 2 PW R_LED# 17 <39> PW R_SUSP_LED# PW R_LED# 17 GND
18 <39> PW R_LED# 18 6
19 18 19 18 GND
USB20_N4 4 3 USB20_L_N4 USB_EN 20 19 USB_EN 20 19 ACES_51524-0040N-001
<15> USB20_N4 4 3 20 <39> USB_EN 20
+5VALW 21 +5VALW 21 CONN@
EMC@ LS12 22 21 22 21
23 22 23 22 SP010022M00
SM070005U00 24 23 24 23
25 24 25 24
26 25 26 25
27 26 27 26
28 GND 28 27
GND USB3_PRX_DTX_N4 29 28
<18> USB3_PRX_DTX_N4 USB3_PRX_DTX_P4 29
ACES_51522-02601-001 <18> USB3_PRX_DTX_P4 30
CONN@ 31 30
USB3_PTX_DRX_N4 32 31
SP01001AO00 <18> USB3_PTX_DRX_N4 USB3_PTX_DRX_P4 33 32
<18> USB3_PTX_DRX_P4 33
34
USB3_PRX_DTX_N5 35 34
<18> USB3_PRX_DTX_N5 USB3_PRX_DTX_P5 35
<18> USB3_PRX_DTX_P5 36 41
37 36 G1 42
USB3_PTX_DRX_N5 38 37 G2 43
<18> USB3_PTX_DRX_N5 USB3_PTX_DRX_P5 38 G3
2
<18> USB3_PTX_DRX_P5 39 44 2
40 39 G4 45
40 G5
pop for 40 pin SUB/B ACES_50398-04041-001
CONN@
SP010013I00
R227 1 @ 2 0_0402_5% SUB_PIN7
+3VALW
R228 1 2 0_0402_5%
THERMAL SENSOR
3 3
+3VS
+3VS +3VS Thermal sensor SMBus address

-->100-1_100xb : 0x4C
(x=0)Write Address(0x98h)
0.1U_0201_10V6K
1
+3VS
CF4
(x=1)Read Address(0x99h)
1
TMS@
RF9
RF10 2
2.2K_0402_5%
5
1
TMS@ 2.2K_0402_5% TMS@ UF1 SA000067P00
G
QF1B TMS@ 1 8 TMS_SMB_CLK RF8 TMS@

2
2N7002KDW _SOT363-6 VDD SCLK 10K_0402_5%

H_THERMDA 2 7 TMS_SMB_DATA
3 4 TMS_SMB_CLK D+ SDATA
<19,25,39,40> EC_SMB_CK2
S
2
1 2 TMS@ H_THERMDC 3 6 THERMAL_ALERT#
D
D- ALERT#
2
TMS@ CF11 2200P_0402_50V7K THERMAL_ALERT# <39>

G
QF1A +3VS 1 2 CPU_THERM# 4 5

2N7002KDW _SOT363-6 RF6 TMS@ 10K_0402_5% THERM# GND
6 1 TMS_SMB_DATA NCT7718W _MSOP8

<19,25,39,40> EC_SMB_DA2
S
D
TMS@
4 4

FUN/B & LED/B
A B C D E
A B C D E
KSI[0..7]
KB Conn.
KSI[0..7] <39>
ON/OFF BTN KSO[0..17]

KSO[0..17] <39>
<39> CAPS_LED#
+5VS
RK1
RK3
1
1 @
2
2
1K_0402_5%
0_0402_5%
1
2
JKB1
1
30
29 GND2
JKB2
KB
<39> NUM_LED#
RK4
RK2
1
1
@ 2
2
0_0402_5%
1K_0402_5%
3
4
5
2
3
4
5
28
ON/OFFBTN# 27
KSO0 26
GND1
28
27
26
BackLight
R17 PVT modify ON/OFFBTN# 6 KSO1 25
+3VLP 100K_0402_5% KSO0 7 6 KSO2 24 25
2 1 KSO1 8 7 KSO3 23 24
KSO2 9 8 KSO4 22 23
KSO3 10 9 KSO5 21 22 +5VS JBL1
1 10 21 1
<39> ON/OFFBTN# ON/OFFBTN# KSO4 11 KSO6 20 U4 1
KSO5 12 11 KSO7 19 20 5 1 +5VS_BL 2 1
KSO6 13 12 KSO8 18 19 IN OUT 3 2
KSO7 14 13 KSO9 17 18 2 4 3
@ SW1 KSO8 15 14 KSO10 16 17 GND 4
EVQPLDA15_4P KSO9 16 15 KSO11 15 16 1 @ 2 4 3 5
Test Only 1 3 KSO10 17 16 KSO12 14 15 <39> KBL_EN EN OC 6 GND
R18 0_0402_5% 1
KSO11 18 17 KSO13 13 14 SY6288C20AAC_SOT23-5 GND
BOT 2 4 KSO12 19 18 KSO14 12 13 C32 @ ACES_51524-0040N-001
KSO13 20 19 KSO15 11 12 0.1U_0201_10V6K CONN@
KSO14 21 20 KSO16 10 11 2
SP010022M00
6
5
KSO15 22 21 KSO17 9 10
KSO16 23 22 KSI0 8 9
KSO17 24 23 KSI1 7 8
KSI0 25 24 KSI2 6 7
KSI1 26 25 KSI3 5 6
KSI2 27 26 33 KSI4 4 5
KSI3 28 27 GND 34 KSI5 3 4
KSI4 29 28 GND KSI6 2 3
KSI5 30 29 KSI7 1 2
KSI6 31 30 1
KSI7 32 31
32 ACES_85201-2805
CONN@
ACES_50596-03201-P01
CONN@ SP01000GO00
TPM Touch Pad +3V_PTP

2 2
+3V_PTP +3VALW 2 @ 1
+3VALW
0_0402_5% RK5
+3VS
2 @ 1
0_0402_5% RK6
UK1
+3VALW +3VALW_TPM +3VS +3VS_TPM +3V_PTP
4.7U_0402_6.3V6M
1 5 @ CK1
OUT IN 0.1U_0201_10V6K JTP1
1
CK2
R19 1 2 0_0603_5% R20 1 2 0_0603_5% 2 2 2 1 1
GND 1
2
TP_CLK 2
TP_DATA 2
0.1U_0201_10V6K
C36
10U_0603_6.3V6M
0.1U_0201_10V6K
C37
0.1U_0201_10V6K
10U_0603_6.3V6M
0.1U_0201_10V6K
C38
3 4 CK3 3
1 1 1 1 1 1 2 OC EN EC PS2 3
C33
C34
C35
1U_0402_6.3V6K RK7 4
SY6288C20AAC_SOT23-5 1 10K_0402_5% I2C_1_SDA_R 5 4
I2C_1_SCL_R 6 5
near PCH I2C
1
2 TPM@ 2 TPM@ 2 TPM@ 2 2
TPM@ 2
TPM@ TPM@ EC_TP_INT# EC_TP_INT# 7 6
pin1 <17,39> EC_TP_INT# TP_EN 8 7
<39> TP_PWR_EN <39> TP_EN 8
9
10 GND
GND
TP_PWR_EN follow SYSON behavior
near ACES_51524-00801-001
CONN@
pin8,14,22
SP01001A910
BADD SELECTION +3V_PTP +3V_PTP
* 1 AEh(write),
AFh(read)
1
+3V_PTP
1
2
RK8 RK9
G
QK1A 2.2K_0402_5% 2.2K_0402_5%
1
U5 TPM@ +3VALW_TPM 2N7002KDW_SOT363-6
2
1 RK10 RK11
2
29 VSB +3VS_TPM 6 1 I2C_1_SCL_R 4.7K_0402_5% 4.7K_0402_5%
S
3 30 XOR_OUT/SDA/GPIO0 8 <20> I2C_1_SCL 3
D
3 SCL/GPIO1 VDD1 14 1 @ 2
2
0_0402_5% 1 @ 2 R21 TPM_BADD 6 GPX/GPIO2 VDD2 22 RK12 0_0402_5%
GPIO3/BADD VDD3
5
LPC_AD0 24 2 TP_CLK
G
<18,39> LPC_AD0 LPC_AD1 21 LAD0/MISO NC1 7 TP_DATA TP_CLK <39>
QK1B
<18,39> LPC_AD1 LPC_AD2 18 LAD1/MOSI NC2 10 TP_DATA <39>
2N7002KDW_SOT363-6
<18,39> LPC_AD2 LPC_AD3 15 LAD2/SPI_IRQ# NC3 11
<18,39> LPC_AD3 LAD3 NC4 25 3 4 I2C_1_SDA_R
<20> I2C_1_SDA
S
CLK_LPC_TPM_R 19 NC5 26
D
<18> CLK_LPC_TPM_R LPC_FRAME# 20 LCLK/SCLK NC6 31 1 2
<18,39> LPC_FRAME# PLT_RST# 17 LFRAME#/SCS# NC7 @ 0_0402_5%
RK13
<17> PLT_RST# TPM_SERIRQ 27 LRESET#/SPI_RST#/SRESET# 9
<18,39> TPM_SERIRQ PM_CLKRUN# 13 SERIRQ GND1 16
<19> PM_CLKRUN# CLKRUN#/GPIO4/SINT# GND2
28 23
LPCPD# GND3 32
4 GND4 33
5 PP PGND 12
TEST Reserved
NPCT650LA0YX_QFN32_5X5
SERIRQ PH 10K to +3VS at PCH side P/N:SA00008ELC0 (S IC NPCT650ABBYX QFN 32P TPM2.0 FW 1.3.1.0)
CLKRUN# PH 10K to +3VS at PCH side
LPCPD# had internal PH XEMC@ XEMC@
CLK_LPC_TPM_R R22 1 2 33_0402_5% C39 1 2 22P_0402_50V8J
4 4

KB & TP & TPM Connector
A B C D E
+5VS
1 @ 2 +VCC_FAN1
Screw
1 1
RF4
RF7
1 @
0_0603_5%
2 +VCC_FAN2
0_0603_5%
40mil Hole
CF6 CF5
1000P_0402_50V7K 10U_0603_6.3V6M @ H1 @ H2 @ H3 @ H4 @ H5 @ H7 @ H8 @ H9 @ H6 @ H23 @ H24
2 2 H_3P0 H_3P0 H_2P5 H_3P0 H_3P0 H_4P0 H_6P4 H_4P0 H_4P0 H_3P2 H_3P2
@ @
FD1 FD2
1
@ @
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
@ H14 @ H15 @ H21 @ H22 @ H12 @ H13 @ H25 @ H26
H_6P0 H_3P7 H_3P7 H_3P7 H_3P7 H_3P7 H_3P7 H_3P7 @ H27 @ H28 @ H29 FD3 FD4
+3VS FAN Conn H_2P7x2P0N H_2P7x2P0N H_2P0N
@ @
1
1
1
FIDUCIAL_C40M80 FIDUCIAL_C40M80
1
2
RF3
10K_0402_5% CF13
4.7U_0603_10V6K
1 JFAN1
2
+VCC_FAN1 1
2 1
<39> FAN_SPEED1 FAN_PWM1 3 2
<39> FAN_PWM1
1 4 3
CF7 5 4
1000P_0402_50V7K 6 G1
XEMC@ G2
2 ACES_50278-00401-001
CONN@
SP02000RR00
+3VS
1
RF5
1
Finger Print
10K_0402_5% CF12
4.7U_0603_10V6K
2 JFAN2 +3VALW FP@
2
+VCC_FAN2 1 RK14 1 2 0_0402_5%

2 1
<39> FAN_SPEED2 FAN_PWM2 3 2 +5VALW
<39> FAN_PWM2
1 4 3 RK15 1 @ 2 0_0402_5%
CF10 5 4
1000P_0402_50V7K 6 G1 2
+FP_VCC
XEMC@ G2 FP@
2 ACES_50278-00401-001 CK4 UK2
CONN@ 1U_0402_6.3V6K 5 1
1 IN OUT
SP02000RR00 2
1
FP@
GND CK5
FP_PWR_EN 4 3 4.7U_0402_6.3V6M
<39> FP_PWR_EN EN OC 2
SY6288C20AAC_SOT23-5
FP@
DK1 FPEMC@
6 3 USB20_P8_L
I/O4 I/O2
+3VLP 1 @ 2 1 @ 2 USB20_N8_L
MAINPWON <39,51> <15> USB20_N8
R23 0_0402_5% RK16 0_0402_5%
Reset Circuit USB20_P8_L +FP_VCC
5
VDD GND
2
1 @ 2 <15> USB20_P8 1 @ 2
EC_RST# <39>
2
R24 0_0402_5% RK17 0_0402_5%

R25
4 1 USB20_N8_L
10K_0402_5% I/O3 I/O1
AZC099-04S.R7G_SOT23-6
1
Q1A D
BI_GATE# 2
BI_GATE PH to +RTCVCC at PWR G
side 2N7002KDW_SOT363-6
S +FP_VCC
1
1
JFP1
PIN ETU801 FA577E-1200
3
Q1B D C40 8
BI_GATE 5 0.1U_0201_10V6K USB20_P8_L 7 8 10
<49> BI_GATE G 2 USB20_N8_L 6 7 G2 9 1 +FP_VCC(5V) +FP_VCC(3V)
5 6 G1
S
2N7002KDW_SOT363-6
4 5 2 USBP D+
4
3 4
2 3 3 USBN D-
1 2
1 4 GND GND
ACES_51522-00801-001
CONN@ 5 NC NC
BI SW 6 NC NC
SP01001AE00
@ 7 NC
Reset Button
3 SW2 1
8 NC
SW3
BI_GATE 1 2 BI_GATE
BI_S <49>
4 2
3 4 ATE-2-V-TR_4P
H : 3.8mm
SKRPABE010_4P
Release : Battery Off
SN10000CV00 Push : Battery ON
change PN to SN10000CV00

FAN & FP & Screw Hole
A B C D E
System DC inferface For Power ON/Off Sequence

@
CQ2 1 2 0.1U_0201_10V6K UQ1 @ JPQ2 PM_SLP_S3
1 14 +5VS_OUT 1 2 +3VALW
+5VALW VIN1 VOUT1 1 2 +5VS
2
2 13
G
VIN1 VOUT1
1
JUMP_43X118
SUSP# RQ1 1 2 0_0402_5% 5VS_ON 3 12 1 2 R37 Q10A
ON1 CT1 CQ1 1000P_0402_50V7K 100K_0402_5% 2N7002KDW_SOT363-6
4 11 1 6
S
+5VALW VBIAS GND EC_VCCST_PG_R <11,39>
D
1 1
2
RQ2 2 1 0_0402_5% 3VS_ON 5 10 1 2 MOW14, For tCPU28 200us(max)
ON2 CT2 CQ3 1000P_0402_50V7K SLP_S3# to VCCST_PWRGD deassertion
5
@ 6 9 @ JPQ1
G
+3VALW VIN2 VOUT2 +3VS_OUT 1
CQ4 1 2 0.1U_0201_10V6K 7 8 2
VIN2 VOUT2 1 2 +3VS
Q10B
15 JUMP_43X118 2N7002KDW_SOT363-6
GPAD Q11A 4 3
S
VR_ON <39,55,56,57>
D
EM5209VF_DFN14_2X3 2N7002KDW_SOT363-6 D
+3VALW +5VALW +3VS_OUT +5VS_OUT 2 MOW14, For tPLT17 200us(max)
<19,39> PM_SLP_S3# G SLP_S3# to IMVP VR_ON deassertion
5
G
2 2 2 2
@ @ S
1
CQ7 CQ8 CQ5 CQ6 Q11B
1U_0402_6.3V6K 1U_0402_6.3V6K 0.1U_0201_10V6K 0.1U_0201_10V6K 2N7002KDW_SOT363-6
1 1 1 1 4 3 SUSP#
D
MOW14, For tPLT18 200us(max)
SLP_S3# to VCCIO VR disable
2
Place CQ7 close UQ1 pin 1&2
G
@
Place CQ8 close UQ1 pin 6&7 Q12A
2N7002KDW_SOT363-6
1 6
S
SYS_PWROK <19,39>
D
5
G
+3VALW @
+5VALW +0.6VS_VTT +5VALW +1.2V_VDDQ Q12B
2N7002KDW_SOT363-6
1
4 3
S
PCH_PWROK <19,39>
2
D
R38
2
@ R27 @ R28 R30 R29 100K_0402_5%
100K_0402_5% 100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @
2
2 PM_SLP_S4 2
1
1
discharge Q13A
5
SUSP discharge SYSON# 2N7002KDW_SOT363-6 D
G
trace 20 mils 2
trace 20 mils <19,39> PM_SLP_S4# G Q13B
2N7002KDW_SOT363-6
6
Q7A D D Q7B S 4 3 SYSON
S
1
3
D
2 5 SUSP Q8B D D Q8A MOW14, For tPLT15 200us(max)
<39,52,55> SUSP# G G SYSON 5 2 SYSON# SLP_S4# to VDDQ ramp down
<39,52,54> SYSON G G
@ @
2N7002KDW_SOT363-6 S S 2N7002KDW_SOT363-6
1
4
1
2N7002KDW_SOT363-6 S S 2N7002KDW_SOT363-6
1
R32 @ @
10K_0402_5% P/N: SB00000EO00 footprint use SB00000ZU00
@
2
+1.05VALW TO +1.05V_VCCST /+1.8VALW TO +1.8VS +1.05VALW TO +1.05VS_VCCSTG

+1.05VALW
@ +1.05V_VCCST
2
CQ15 1 2 0.1U_0201_10V6K UQ2
3 1 14 +1.05V_VCCST_OUT RQ5 1 2 0_0603_5% CQ12 3
+1.05VALW VIN1 VOUT1
2 13 1U_0402_6.3V6K
VIN1 VOUT1 1 UC4
SYSON RQ4 1 2 0_0402_5% EN_1.0V_VCCSTU 3 12 1 2 1
ON1 CT1 CQ14 1000P_0402_50V7K +5VALW 2 VIN1 +1.05VS_VCCSTG
4 11 VIN2
+5VALW VBIAS GND +1.05VS_VCCSTG_OUT
7 6 RQ6 1 2 0_0603_5%
SUSP# RQ8 1 2 0_0402_5% EN_1.8VS 5 10 1 2 +1.8VS VIN thermal VOUT
ON2 CT2 CQ16 1000P_0402_50V7K 3
+1.8VS_OUT VBIAS 2
+1.8VALW 6 9 RQ9 1 2 0_0603_5%
@ 7 VIN2 VOUT2 8 SUSP# RQ3 2 1 0_0402_5% EN_1.0V_VCCSTG 4 5 CQ10
CQ20 1 2 0.1U_0201_10V6K VIN2 VOUT2 ON GND
0.1U_0201_10V6K
15 1
GPAD 1
@
EM5209VF_DFN14_2X3 CQ13 AOZ1334DI-01_DFN8-7_3X3
0.1U_0201_10V6K
2
+1.0VS_VCCSTG: 60mA
R ON = 4.4m ohm
VDROP= 11mV
Delay time: 9.3us
+1.05VALW +1.05V_VCCST_OUT +1.8VS_OUT

+1.8VALW
2 2 2
2
CQ11 CQ9 CQ22
1U_0402_6.3V6K CQ24 0.1U_0201_10V6K 0.1U_0201_10V6K
1 1 1
1U_0402_6.3V6K
1
4 4


DC Interface
A B C D E
A B C D E
change PL101、PL102 from

1 +19V_ADPIN EMI@ PL101 +19V_VIN SM01000P200 to comm part 1
FBMA-L11-201209-800LMA50T
SM01000U600
1 2
20160216 3PIN'+' 3PIN'-' EMI@ PL102
1
FBMA-L11-201209-800LMA50T
@ ACES_50299-00601-001 PR102
4.7_1206_5% 1 2 PR103
1 4.7_1206_5%
1
1
2
2
2 3 PC102 EMI@ EMI@ PC104
3 4 100P_0402_50V8J 1000P_0402_50V7K
2
7 4 5
G7 5
1
8 6 EMI@ PC103 EMI@ PC105
G8 6 0.1U_0603_25V7K 0.1U_0603_25V7K
PJP101
2
2 2
@ PR101
0_0402_5%
1 2
+3VLP +CHGRTC
3 3
4 4
2016/07/18
Compal Secret Data
2017/06/14 Title
DCIN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom
C5MMH M/B LAE911P 0.1

A B C D E
A B C D E
+3VLP
1
1 1
@ PC205
1
0.1U_0603_25V7K
2
@ PR215
PR207 100_0402_1% 21.5K_0402_1% @ PR214
MB:Battery Con Put BOT Side
100K_0402_1%
1 2 26.7K_0402_1%
EC_SMB_DA1 <39,50>
PR213
PR205 100_0402_1%
2
1
1 2
EC_SMB_CK1 <39,50>
@ PU201
1 8
Battery Bot Side @ VCC TMSNS1
(Common Part)
PR202 2 7 2 1
<45,47> SL200002H00
2
200K_0402_1% GND RHYST1
PIN1 GND
1
1 2 MAINPWON 3 6 @ PR216
+3VLP <39,51> MAINPWON OT1 TMSNS2
100K_0402_1%_NCP15WF104F03RC
PIN2 GND @ PJP201
1 4 5 2 1
14K_0402_1%
@
PIN3 SMD 1 2
2 3
1 2
BATT_TEMP <39,50>
OT2 RHYST2
1
EC_SMB_DA1-1
PH202
G718TM1U_SOT23-8 @ PR218
PIN4 SMC
2
3 4 EC_SMB_CK1-1 PR203 1K_0402_1% 10K_0402_1%
4 5
PIN5 TEMP BATT_TS
100K_0402_1%_NCP15WF104F03RC
@
5 6 BATT_B/I
PIN6 BI 6 7
PH203
(Common Part)
2
7 8
PIN7 Batt+ 8 9 +RTCVCC SL200002H00
PIN8 Batt+ GND 10
GND 2016/09/26
PIN9 GND PH3 Near VGA.
PIN10 GND
CVILU_CI9908M2HR0-NH Change thePQ201 from
1
SP020017H00 PR212 SB00000QO00 to SB00001GD00,
100K_0402_5%
CVILU_CI9908M2HR0-NH
1
2 D 2
2 PQ201
<46> BI_GATE G LBSS139LT1G 1N SOT-23-3
S
3
+12.6V_BATT+
EMI@ PL201
FBMA-L11-201209-800LMA50T
1 2
+12.6V_BATT BI_S <46>
EMI@ PL202 When PR204=16.9K
1
FBMA-L11-201209-800LMA50T
1 2 PR217 For KB9022
0_0402_5% OTP Active Recovery
2
VCIN0_PH(V) 89'C, 1V 56'C, 2V
1
PC201 EMI@ PC202 EMI@
1000P_0402_50V7K 0.01U_0402_25V7K
2
PH202(ohm) 7.3092K 26.11K
+3VLP_ECA
PR206
10K_0402_1%
1 2
ADP_I <39>
1
3 3
PR204
18.7K_0402_1%
VCIN1_ADP_PROCHOT <39>
2
VCIN0_PH <39>
1
PC203 must close to EC pin
1
PR208
10K_0402_1% PH201
2
@ PC203
100K_0402_1%_NCP15WF104F03RC
2
0.1U_0402_25V6
1
2
T202@ PH201 is Common Part SL200002H00
T201@
ECAGND <39>
T202 T201 must close to PH201
ADP_I=20*I(adapter)*0.01
4
I(adapter)=adapter(W)*95%/19 4
2016/07/18
Compal Secret Data
2017/06/14 Title
BATTERY CONN/OTP
Custom
C5MMH M/B LA-E911P 0.1

A B C D E
5 4 3 2 1
Module model information

ISL95520_Hybrid_Boost_V2.mdd
Protection for reverse input
Vgs = 20V
Vds = 60V
Id = 250mA
1
D D D
2 PQ301
G L2N7002WT1G_SC70-3
S max Power loss 0.22W for 90W;0.12W for 65W system;0.05W for 45W +19VB
3
1 2 1 2 CSR rating: 1W
VCSIP-VCSIN spec < 81mV
PR301 PR302
1M_0402_1% 3M_0402_5%
PQ310 +19V_P1 PQ311

Need check the SOA for inrush EMB04N03H_EDFN5X6-8-5 AON7380_DFN3X3-8-5
+19V_P2
PR303
+19VB_CHG
1 1 0.005_1206_1% EMI@ PL704
2 2 FBMA-L11-201209-800LMA50T
5 3 3 5 1 4 1 2
+19V_VIN
EMI@
EMI@
EMI@
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_25V7K
2 3
10U_0805_25V6K
10U_0805_25V6K
CSIP_CHG_R
4
1
CSIN_CHG_R
PC302
PC303
PC305
PC304
PC324
@ PC322 @ PJP1
2
2
2
1 2 1 2
1 2
1000P_0402_25V JUMP_43X118
1
0_0402_5%
2_0402_5%
Co-lay jump and ISN choke.
PR304
PR305
1
PR306 @
2
499K_0402_1%
PC306
2
4.02K_0402_1%
4.02K_0402_1%
1 2 PQ312
AON7380_DFN3X3-8-5
1
1
0.1U_0402_25V6 2
5 3
C PR309 C
PC307 0.22U_0603_25V7K
Range:2V~3.5V 100_0402_1%
4
PR307
PR308
20*49.9/(392+49.9)=2.55V
1 2 +12.6V_BATT
66.5K_0402_1%
CMSRC_CHG
1
2200P_0402_50V7K
@ PC308
1
PC301
PR310
ASGATE_CHG
1
1 2
2
BGATE_CHG
2
OPCN_CHG 2
0.1U_0402_25V7K
CSIN_CHG
CSIP_CHG
OPCP_CHG
VBAT_CHG
0x3CH <BIT9> PSYS current gain
1 VDD_CHG
Rs1 = 10mΩ and Rs2 = 5mΩ o r Rs 1 = 10m Ω a nd R s2 = 10Ω

m PQ305
BIT0 = 1.14uA/W
AON7506_DFN33-8-5
BIT1 = 0.285uA/W
=========================================================
100K_0402_1%
support Turbo boost : 2200P Support max charge 3.5A
32
31
30
29
28
27
26
25
Rs1 = 20mΩ and Rs2 = 10mΩ or Rs 1 = 20m Ω a nd R s2 = 20Ω
m PU301
BIT0 = 2.28uA/W no support Turbo boost : 0.1u Choke 4.7uH SH00000YC00 (Common Part) Power loss: 0.245W
PR311
CSIP
ASGATE
QPCP
BGATE
CSIN
CMSRC
OPCN
VBAT
BIT1 = 0.57uA/W PC309 4 (Size:6.6 x 7.3 x 3 mm) CSR rating: 1W
Ipsys = KPSYS  x 
( VAD P x IAD P + VBA T x IBA T) PR312 0.47U_0402_16V4Z (DCR:28m~33m) VCSPP-VCSON spec < 81mV
ACIN_CHG 1 24 BST_CHG 1 2 BST_CHG_R
1 2
R_Psys = 1.2V / Ipsys
2
ACIN BOOT PR315

KPSYS = 1.14uA/W UG_CHG
adapter wattage = 45W 2 23 0_0603_5% PL301 0.01_1206_1%
3
2
1
<39> AC_IN ACOK UGATE 4.7UH_PCMB063T-4R7MS_8A_20% +12.6V_BATT
Battery wattage = 40Wh
1
2 0_0402_5% EC_SMB_DA1_R 3 LX_CHG +17.4V_BATT_CHG 1

158K_0402_1%
@ PR314 1 22 1 2 4
Ipsys = 1.14 x (45+40) = 96.9uA <39,49> EC_SMB_DA1 SDA PHASE
PR313
R_Psys = 1.2V / 96.9uA = 12.3K-ohm. 2 0_0402_5% EC_SMB_CK1_R 4 LG_CHG
4.7_1206_5%
@ PR316 1 21 2 3
<39,49> EC_SMB_CK1 SCL LGATE
1
=====================================
EMI@ PR320
PQ306
VDDP_CHG
5
adapter wattage = 65W @ PR317 1 2 0_0402_5% 5 20
2
<11,39> H_PROCHOT# PROCHOT# VDDP
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
Battery wattage = 40Wh
AON7506_DFN33-8-5
1
VDD_CHG
1
2 1K_0402_1%AMON_ISL95520 6
1
Ipsys = 1.14 x (65+40) = 119.7uA PR318 1 19 1 2
<39> ADP_I AMON VDD
PC311
PC312
PC310
R_Psys = 1.2V / 96.9uA = 10K-ohm.
2
PR321 1 2 1K_0402_1%BMON_ISL95520 7 18 PR319 4.7_0402_5%
2
2
BMON DCIN
680P_0402_50V7K
**Design Notes** 4
BATGONE
Close to EC. 8 17 PC313 PC314
For 45W/65W /90W system, 2S/3S/4S battery NC NTC
EMI@ PC315
CCLIM 1U_0201_6.3V6K 1U_0201_6.3V6K
2
2
ACLIM
B Maximum Charging current 3.5A
COMP
1
PROG
B
AGND
CSON
CSOP
FSET
PR323
1
Maximum Battery discharge power 55W 100K_0402_1%
3
2
1
1
1
0_0402_5%
#Register Setting PC316 PC317
2
PR322
0.1U_0402_25V6 0.1U_0402_25V6 PD1

1. 0X3DH bit10 set 0 (default 1) to enable turbo boost function
33
16
10
11
12
13
14
15
Follow adapter and ISL88739AHRZ-T_QFN32_4X4
PR324 10_1206_5% 3
+19V_VIN
2
2. Disable turbo when AC only battery wattage in 1 2 1
2
#Circuit Design Close to Vsys current source. @ 2
2
2
FSET_CHG
EC.
PC318
1U_0603_25V6
1. ACLIM and CCLIM are devider voltage control. Base on CPU Core VR design. VF = 0.38V For 4S per cell 4.35V battery
The resistor is pop on CPU VR schematic. S SCH DIO BAS40CW SOT-323
1
2. Use 7X7 choke and 3X3 H/L side MOSFET
1
Charge current 3A PR325
ACIN_CHG
Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W) VDD_CHG 10K_0402_1% +12.6V_BATT
Power density : 0.61 (23X16) VDD=5V
2
#Protect function
1
CCLIM_CHG
1. ACOVP : VCC voltage > 24V
200K_0402_1%
4S_BATT@ PR338
2. SMBus timeout : 0X3DH bit15 set 0 (default 0) to enable 175s(default).
1
ACLIM_CHG 2M_0402_1%
3. ACOC : OX3CH bit4 set1 release adapter limit function (default:Enable).
PR328
PR329
PROG_CHG CSOP_CHG 1 2 CSOP_CHG_R
4. CHGOCP : based on charge current setting 200K_0402_1%
2
5. BATOVP : 4.6V/Cell COMP_CHG
0_0402_5%
PR330 2_0402_5%
2
1
6. BATLOWV : No.
@ PR331 PR333=0 ohm, Fs=500KHZ ~ +/- 15%
7. TSHUT : 150C +3VS PC319
1
1
100_0402_1%
76.8K_0402_1% 0.1U_0402_25V6
2
PR332
1 2
CSON_CHG CSON_CHG_R
1
150K_0402_1%
560P_0402_50V7K
1 2
1
PR333
PR335
OCCP setting @ PR334 0_0402_5%
1
PR336 135W@
PC320
@ PQ309 4S_BATT@
2
2
1
D
232K_0402_1%
PQ315
2
1
AC_IN
1
0.015U_0402_25V7K
@VGA@ @VGA@ 2 PR337 @ 4S_BATT@ PR339 LTC015EUBFS8TL_UMT3F

2
PR340 PR341 G 75K_0402_1% @ BATT_TEMP <39,49> 100K_0402_1%

1
PC321
10K_0402_1% 10K_0402_1% S 1 2 2
3
<39> BATT_4S
L2N7002WT1G_SC70-3 BATGONE(BATT_TEMP)
2
logic high: above 2.4V

2
2
2
Hybrid boost power mode logic low: under 0.8V

Cell = 4s 4S_BATT@
3
1
<20,25,39> DGPU_AC_DETECT PQ316 D
2
<39,52,55> SUSP# G
A A
ICClimit : 7.73A
6
D Delta I : 1.44A L2N7002WT1G_SC70-3 S
3
2 1C charge current :6.48A
G
@VGA@ @VGA@ @VGA@
PQ314 PQ313B S PQ313A Battery current limimed by CCLIm ~ 3.89A.
1
1
RUM001L02_VMT3 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 Adapter current limimed by ACLIm ~ 4.33A.

(PR779 and PQ741 are for change ACLIm when AC in)
3
D
H_PROCHOT# 2 AC_IN 5 (Rs1 = 10mΩ and Rs2 = 5mΩ o r Rs 1 = 20m Ω a nd R s2 = 10mΩ).
G CC_LIM = VccLIM / 64 x Rs2
=============================================================
S (Rs1 = 10mΩ and Rs2 = 10mΩ o r Rs 1 = 20m Ω a nd R s2 = 20mΩ ). 2016/07/18 2017/06/14 Title
PWR_CHARGER
4
CC_LIM = VccLIM / 32 x Rs2

3
============================================================= THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AC_LIM = Vac_LIM / 32 x Rs1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
5 4 3 2 1
A B C D E
PR402
499K_0402_1%
ENLDO_3V5V 1 2
+19VB
1
150K_0402_1%
PR404
EN1 and EN2 dont't floating
2
@EMI@ PL401
FBMA-L11-201209-800LMA50T
1 2 PU401
1 +19VB SY8286BRAC_QFN20_3X3 @ PR401 PC401 1
@ PJ403 0_0603_5% 0.1U_0603_25V7K
+19VB_3V BST_3V
2200P_0402_50V7K
1 2 1 2 1 2 Choke 1.5uH SH000016800 (Common Part)
1 2
(Size:4.9 x 5.2 x 3 mm)
10U_0805_25V6K
10U_0805_25V6K
EMI@ PC406
@EMI@ PC403
EMI@ PC404
0.1U_0402_25V6
0.1U_0402_25V6
JUMP_43X79
(DCR:20m~25m)
1
1
1
@ PC432
PC405
BS
IN
IN
IN
IN
PL402
2
2
2
LX_3V6 20 LX_3V 1 2
LX LX +3VALWP
7 19 1.5UH_PCMB053T-1R5MS_6A_20%
GND LX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
1
8 18
+3VALWP GND GND
@ PC407
PC408
PC409
@ PC410
PC429
PC430
@EMI@
9 17 PR405
+3VLP
2
PG LDO 4.7_1206_5%
1 3V_SN
10 16
2
NC NC
1
PC411
OUT
EN2
EN1
21 4.7U_0402_6.3V6M
NC
FF
2
PR406 GND @EMI@
100K_0402_5% PC412
11
12
13
14
15
680P_0402_50V7K
2
3.3V LDO 150mA~300mA Vout is 3.234V~3.366V
SPOK_3V
<39,54> SPOK_3V
ENLDO_3V5V PC402 PR403
1000P_0402_25V8J1K_0402_5%
3V_FB 1 2 1 2
<39> 3V_EN
@EMI@ PL403
2 FBMA-L11-201209-800LMA50T 2
+19VB 1 2 +19VB_5V
PU402 @ PR408 PC418
@ PJ404 SY8288CRAC_QFN20_3X3 0_0603_5% 0.1U_0603_25V7K
1 2 +19VB_5V BST_5V 1 2 1 2
1 2
Choke 1.5uH SH000016700 (Common Part)
1
JUMP_43X79 (Size:7.3 x 6.6 x 3 mm)
BS
IN
IN
IN
IN
(DCR:14m~15m)
LX_5V 6
2200P_0402_50V7K
10U_0603_25V6M
10U_0805_25V6K
EMI@ PC431
0.1U_0402_25V6
0.1U_0402_25V6
20
LX LX PL404
7 19 LX_5V 1 2
GND LX +5VALWP
1
1
1
1
PC414
EMI@ PC416
PC415
@EMI@ PC417
8 18 PC419 4.7U_0402_6.3V6M 1.5UH_9A_20%_7X7X3_M

GND GND
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 SPOK_5V_R
2
2
2
+3VLP
1
1
9 17 1 2
PG VCC
PC420
PC421
@ PC422
PC423
@ PC425
PC424
10 16 @EMI@
2
2
NC NC PR409
OUT
LDO
EN2
EN1
1
21 4.7_1206_5%
FF
GND
2
PR414 @ PR413
11
12
13
14
15
100K_0402_5% 0_0402_5% VL
1 5V_SN
2
5V LDO 150mA~300mA
2
SPOK_5V 1
<39> SPOK_5V
PC427 @EMI@ Vout is 4.998V~5.202V
ENLDO_3V5V PC426
4.7U_0402_6.3V6M
2
680P_0402_50V7K
2
5V_EN
3 3
PC413 PR407
1000P_0402_25V8J 1K_0402_5%
5V_FB 1 2 1 2
PR410
2.2K_0402_5%
1 2
<39> EC_ON @ PR411
0_0402_5% @ PJ401
1 2 +3VALWP 1 2 +3VALW
<39,46,49> MAINPWON 1 2
JUMP_43X118
5V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
@ PJ402
1
PR412
PC428
+5VALWP 1 2 +5VALW
1 2
JUMP_43X118
2
2
4 4
2016/07/18
Compal Secret Data
2017/06/14 Title
3.3VALWP/5VALWP
Custom

A B C D E
A B C D E
1 1
@ PJ503
JUMP_43X79 Pin19 need pull separate from +1.35VP.
1 2
1 2 +19VB_1.2VP If you have +1.35V and +0.675V sequence question, 0.6Volt +/- 5%
@EMI@ PL501 you can change from +1.35VP to +1.35VS. TDC 0.7A
FBMA-L11-201209-800LMA50T
1 2 +19VB_1.2VP PR502 Peak Current 1A
+19VB 2.2_0603_5%
BST_1.2VP_R 1 2 BST_1.2VP
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
+1.2VP
1
1
EMI@ PC510
@EMI@ PC502
EMI@ PC503
PC504
PC505
change PL501 from UG_1.2VP +0.6VSP
2
2
SM01000C000 to comm
part SM01000P200 LX_1.2VP
10U_0603_6.3V6M
10U_0603_6.3V6M
5
1
PC506
1
1
PC508
PC507
0.1U_0603_25V7K
16
17
18
19
20
2
PU501
2
2
2 2
VLDOIN
PHASE
UGATE
BOOT
VTT
4 21
PAD
Choke 1uH SH00000YE00 (Common Part) LG_1.2VP 15 1
(Size:6.86 x 6.47 x 3 mm) LGATE VTTGND
(DCR:6.2m~7.2m Ohm) PQ503 IOCP
1
2
3
AON7408L 1N DFN 14 2
PL502 PR503 PGND VTTSNS
1UH_PCMC063T-1R0MN_11A_20% 16.5K_0402_1%
1 2 LX_1.2VP 1 2 CS_1.2VP 13 3
+1.2VP PC509 CS RT8207PGQW _W QFN20_3X3 GND
1
5 1U_0201_6.3V6K
1 2 12 4 VTTREF_1.2VP
@EMI@ PR504 PR505 VDDP VTTREF
4.7_1206_5% 5.1_0603_5%
1 2 VDD_1.2VP 11 5
PC523
PC521
PC525
PC522
PC524
PC520
+5VALW +1.2VP
1 2
VDD VDDQ
1
PGOOD
4 PC516
1 1 1 1 1 1
TON
1
1
@EMI@ PC518 0.033U_0402_16V7K
FB
S5
S3
2
680P_0402_50V7K PC517
2
PQ502 1U_0201_6.3V6K PR511

22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
2
3
10
6
2 2 2 2 2 2 AON7506_DFN33-8-5 2.2_0402_1%
FB_1.2VP
TON_1.2VP
EN_1.2VP
+5VALW Frequency PR506
EN_0.6VSP
6.19K_0402_1%
PR507 1 2 +1.2VP
470K_0402_1%
+19VB_1.2VP 1 2
3 3
Vout=0.75V* (1+Rup/Rdown)
1
H/S AON7408 Rds(on) :typ:27m Ohm, max:34m Ohm
Idsm(TA=25)=7.5A, Idsm(TA=70)=5.5A =0.75*(1+(6.19/10))
@ PR501 PR508
0_0402_5% 10K_0402_1% =1.214V 1.2%
L/S SI7716 Rds(on) :typ:13.5m Ohm, max:16.5m Ohm 1 2
2
Idsm(TA=25)=16A, Idsm(TA=70)=9.5A <39,47,54> SYSON
1
@ PC501
Choke: 7x7x3 0.1U_0402_10V7K
=0.75*(1+(8.2/10))
Rdc=6.2mohm(Typ), 7.2mohm(Max) =1.365V 1.1%
2
Switching Frequency: 530kHz @ PR509
Ipeak=7A, Imax=4.9A 0_0402_5%
1 2
<39,47,50,55> SUSP#
VFB=0.607V, Vout=1.214V @ PJ501
@ PR510 JUMP_43X118
0_0402_5% +1.2VP 1 2 +1.2V_VDDQ
1 2 1 2
<11> SM_PG_CTRL
1
@ PC519 @ PJ502
JUMP_43X39
0.1U_0402_10V7K 1 2
+0.6VSP +0.6VS_VTT
2
1 2
4 Mode Level +0.675VSP VTTREF_1.35V 4

S5 L off off
S3 L off on
S0 H on on
Note: S3 - sleep ; S5 - power off Security Classification
2016/07/18
Compal Secret Data
2017/06/14 Title
DDR4
Custom

A B C D E
A B C D E
@EMI@ PL601 +19VB_1VALW

1 1
FBMA-L11-201209-800LMA50T EN pin don't floating @EMI@ PR605 @EMI@ PC602
1 2 4.7_1206_5% 680P_0402_50V7K @ PJ601
If have pull down resistor at HW side, pls delete PR702 1 2 SNUB_1VALW 1 2 JUMP_43X118
PU601 1 2
+19VB_1VALW +1.05VALWP 1 2 +1.05VALW
+19VB 1
1 2
2 2
IN PG
9 @ PR606
0_0603_5%
PC603
0.1U_0603_25V7K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
@ PJ602 3 1 BST_1VALW 1 2 BST_1VALW_R 1 2 PL602
2200P_0402_50V7K
IN BS
1
JUMP_43X39 1UH_11A_20%_7X7X3_M
EMI@ PC607
EMI@ PC604
@EMI@ PC605
PC606
LDO_3V LX_1VALW
4
IN LX
6 1 2
+1.05VALWP
220U_B2_4VM_R35M
2
2
2
5 19 Choke 1uH SH00000YE00 (Common Part) 1
15.4K_0402_1%
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
1
1
(Size:6.86 x 6.47 x 3 mm)
1
1
1
@ PR607 7 20 +
PR608
PC608
PC609
PC610
PC611
PC612
@ PC615
0_0402_5% GND LX (DCR:6.2m~7.2m Ohm)
8 14 FB_1VALW Rup
2
GND FB 2
2
2
ILMT_1VALW 18 17 LDO_3V
change PL601 GND VCC
SM01000C000 to comm
1
1
EN_1VALW 11 10
EN NC
part SM01000P200 PC613 FB = 0.6V
1
@ PR609 ILMT_1VALW 13 12 2.2U_0402_6.3V6M
2
ILMT NC PR610
0_0402_5%
15 16
+3VALW Rdown
2
BYP NC 20K_0402_1%
21
2
PAD
SY8288RAC_QFN20_3X3 Pin 7 BYP is for CS.
1
The current limit is set to 6A, 8A or 12A when this pin Common NB can delete +3VALW and PC15
PC614
is pull low, floating or pull high 1U_0402_6.3V6K
2
=0.6*(1+(15.4/20))
Vout=1.062V
2 2
PR611
0_0402_5%
1 2
+1.8_PG <54>
@ PR603
10K_0402_1%
EN_1VALW 1 2
+3VALW
1
@ PC601
PR601
0.22U_0402_10V6K
2
1M_0402_1%
2
3 3
4 4
2016/07/18
Compal Secret Data
2017/06/14 Title
1V
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

A B C D E
A B C D E
@ PR7123
0_0402_5%
EN_1.8V 1 2
SPOK_3V <39,51>
1
1 1
PR7124 @ PC7118
0.1U_0402_16V7K
2
1M_0402_1%
2
PR7126
100K_0402_5%
2 1
+3VALW PU7105 Choke 1uH SH00000YG00 (Common Part)
9
<53> +1.8_PG 1 PGND 8 (Size:3.8 x 3.8 x 1.9 mm)
FB SGND (DCR:20m~25m)
+3VALW VIN_1.8V 2 7
PG EN PL7103
3 6 LX_1.8V 1 2
@ PJ7108 IN LX 1UH_2.8A_30%_4X4X2_F +1.8VALWP
1 2 4 5
20.5K_0402_1%
68P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 2 PGND NC
1
@EMI@ PR7125
4.7_0603_5%
1
PR7122
PC7123
JUMP_43X79
1
1
SY8003ADFC_DFN8_2X2
Rup
PC7125
@ PC7126
PC7119
1
PC7127
2
2
2
2
2
22U_0603_6.3V6M
2
FB_1.8V
680P_0402_50V7K
1
1
FB=0.6V PR7121
@EMI@ PC7124
Note:Iload(max)=3A
10K_0402_1%
Rdown Vout=0.6V* (1+Rup/Rdown)
2
Vout=0.6V*(1+20.5/10)
=1.83V (x1.017)
2 2
@ PJ7107
JUMP_43X79
1 2
+1.8VALWP 1 2 +1.8VALW
+3VALW
@ PJ7103
+5VALW JUMP_43X79
1 2
+2.5VP 1 +2.5V
2
2
PJ7105
2
JUMP_43X79
@
1
1
PC7210
1U_0402_6.3V6K
VIN_2.5V
2
1
FB=0.8V
PC7108 PU7102 Note:Iload(max)=3A
4.7U_0402_6.3V6M G9661MF11U_SO8
2
4 5
@ PR7110 VIN_2.5V 3 VPP NC 6
0_0402_5% 2 VIN VO 7 +2.5VP
GND
3 <39,47,52> SYSON 1 2 EN_2.5V 1 VEN ADJ 8 3
22U_0603_6.3V6M
22U_0603_6.3V6M
0.01U_0402_25V7K
POK GND
1
PR7115
PC7109
0.1U_0402_16V7K
9
1
1
Rup
@ PC7110
PC7111
1
PR7113 21.5K_0402_1%
PC7107
2
2
2
1M_0402_5%
2
FB_2.5V
2
1
PR7116
10K_0402_1%
Rdown Vout=0.8V* (1+Rup/Rdown)
Vout=0.8V* (1+(21.5/10)) = 2.52V (x1.008)
4 4
2016/07/18
Compal Secret Data
2017/06/14 Title
1.5VS/2.5V
C

A B C D E
5 4 3 2 1
EMI@ PR7203 EMI@ PC7203 @ PJ7201

4.7_1206_5% 680P_0402_50V7K 1 2
1 2 SNB_+VCCIOP 1 2 +VCCIOP 1 2 +VCCIO
JUMP_43X118
EMI@ PL7201
FBMA-L11-201209-800LMA50T
D D
1 2 Choke 0.68uH SH00000Z300 (Common Part)
@ PJ7202 PU7201 (Size:4.85 x 4.7 x 2.8 mm)
1 2 +VCCIOP_B+ 2 9 PR7202 PC7202 (DCR:11m~12m)
+19VB 1 2 IN PG 0_0603_5% 0.1U_0603_25V7K Real Voltage=0.95V
JUMP_43X39 3 1 +VCCIOP_BST 1 2+VCCIOP_BST_R 1 2 PL7202
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
IN BS
1
0.68UH_7.9A_20%_5X5X3_M
PC7207
@EMI@ PC7217
PC7208
+VCCIOP_LX
4
IN LX
6 1 2
+VCCIOP
1
5 19
PC7219
330P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
IN LX
1
1
1
7 20
EMI@
Note:Iload(max)=5.5A
PC7204
@ PC7205
PC7206
PC7211
PC7212
PC7214
10_0402_1%
2
GND LX @
PR7212
8 14 +VCCIOP_FB
IOCP=7A~8A(typ)
2
2
2
GND FB
2
PR7214
1K_0402_1%
18 17 +VCCIOP_LDO_3V
2
GND VCC
1
+VCCIOP_EN 11 10 PC7218 @
EN NC 2.2U_0402_6.3V6M
1
+VCCIOP_ILMT 13 12 FB = 0.6V Rup
2
ILMT NC 1 2 =0.6*(1+(12k/20.5k))
15 16
+3VALW BYP NC PR7218 =0.951V --- (x1.001)
1
21 12K_0402_1%
1U_0402_6.3V6K
PAD
PC7209
20.5K_0402_1%
1
SY8288RAC_QFN20_3X3
Rdown
2
PR7215
Pin 7 BYP is for CS.
Common NB can delete +3VALW and PC15
2
@ PR7209
0_0402_5%
VCCIO_SENSE_R 1 2 VCCIO_SENSE
+VCCIOP_LDO_3V VCCIO_SENSE <13>
@ PR7210
0_0402_5%
1
@ PR7207 1 2 VSSIO_SENSE
VSSIO_SENSE <13>
C 0_0402_5% C
@ PR7213 VR_ON 1 2
0_0402_5% <39,47,56,57> VR_ON
2
+VCCIOP_ILMT PR7208
1K_0402_5%
1
SUSP# 1 2 +VCCIOP_EN
@ <39,47,50,52> SUSP#
PR7217
0.1U_0402_25V6
1M_0402_5%
1
1
PC7201
check delay time with HW
PR7201
0_0402_5%
2
2
2
B B
A A

C5MMH M/B LAE911P
C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0VS_VCCIO
5 4 3 2 1
5 4 3 2 1
+19VB_CPU EMI@ PL8103

90A for ICCMAX=2.2V 76A for ICCMAX=2.2V +19VB_CPU FBMA-L11-201209-800LMA50T
+VREF +VREF 1 2
EMI@ PL8102 +19VB
PC8104 PC8105 PC8106 PC8107 FBMA-L11-201209-800LMA50T
100U_25V_NC_6.3X6
33U_D1_25VM_R6M
33U_D1_25VM_R6M
confirm with power sequence, EMI@ EMI@ 1 1 @ 1 @
1
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
it need behind +5VS. 1 2
PC8108
PC8116
PC8118
+ + +
PR8102 PR8103
2
30.1_0402_1%
8.45K_0402_1% 2 2 2
7.5K_0402_1%
4.02K_0402_1%
1
1
+19VB_CPU +19VB_CPU
2
NTC1P NTCGT1P
PR8104
PR8105
1
1
PR8106 PR8101 PC8101
PH8102 PH8101 100_0402_1% 2.2_0603_1% 0.1U_0603_25V7K
2
1 2 BOOST_VCC1 1 2BOOST_VCC1_R
1 2 Ta=70=>Id=17.5A Choke 0.15uH SH00000X700
100K_0402_1%_B25/50 4250K 10K_0402_1%_B25/50 3370K
Rdson=8.2~10.5 mohm (Size:6.59 x 6.6 x 3.0 mm)
8.66K_0402_1%
8.66K_0402_1%
0.22U_0402_25V6K
PQ8101
1
@ PR8111
2.2_0402_1%
2.2_0402_1%
2
PU8102 (DCR:0.9m +-7%)
2
PC8109 NTC1N NTCGT1N 0_0402_5%
PR8107
PR8109
PR8110
PC8110
PR8108
1 2 +VCC_CORE
G1
D1
VSSGT_SENSE <12> VCC_UG1
Fs=400k, LL=1.8m for Core 0.22U_0402_25V6K 4 3 PL8101
2
BOOT UGATE 0.15UH_MMD06CZER15MG_37A_20%
2 RTCPU_TSEN_R 2
2 RTCPU_TSENA_R 2
5 2 VCC_PHASE1 7 VCC_PHASE1 1 4
Fs=400k, LL=2.1m for GT PWM PHASE D2/S1
PR8115
1.8K_0402_1%
5.76K_0402_1%
1
1
D SET1 ICCMAX=128A, OCP=120%, DVIDT=35.7mV. 100_0402_1% PR8112 EN1 1 6 2 3 D
EN PGND
+1.05V_VCCST 1 2 5.1_0402_1%
G2
PR8113
PR8114
S2
S2
S2
57.6K_0402_1%
57.6K_0402_1%
VCC_LG1
1
1
SET2 Ramp=133%, DVIDW=9us, QRT=25mV, QRW=44% 1 2 8 7
+5VALW VCC LGATE 9
PR8119
PR8118
0.47U_0402_16V4Z
3
1
1
@ PR8120 GND AON6962_DFN5X6D-8-7 @EMI@
SET3 Zero LL disable, VR address Core=0, GT=1.
1
220K_0402_5%_B25/50 4700K
220K_0402_5%_B25/50 4700K
PR8116 PR8117 0_0402_5% PR8121
1
402K_0402_1% 442K_0402_1% 1 2 PC8112 RT9610CGQW _W DFN8_2X2 4.7_1206_5%
SETA1 ICCMAX=32A, OCP=120%, DVIDT=60mV. VSSSENSE <12>
2
2
PC8111
@ PR8122 1U_0201_6.3V6K
1
SETA2 Ramp=133%, DVIDW=9us, QRT=25mV, QRW=44%
PH8103
PH8104
200_0402_1%
2
2
1K_0402_1%
PR8123
SNUB_VCC1
Core offset function disable, GT offset PR8126
2
RTCPU_TONSETA RTCPU_TONSET
100_0402_1% PR8125 PC8113
RTCPU_TSEN
100K_0402_1%
function disable, PSYS disable.
RTCPU_TSENA 1
1
1 2 200_0402_1% 0.47U_0402_6.3V6K
0_0402_5%
VR_HOT# <39>
2
1
1
+VREF @ PR8129 1 2 1 2
PR8124
1_0402_1%
SCLK_CPU
0_0402_5% @EMI@
PR8127
SDIO_CPU RTCPU_PS4 1
2
2 EN1 PC8114 @ PR8131
2
ALERT_CPU
PR8130 680P_0402_50V7K 0_0402_5%
+19VB_CPU
RTCPU_IBIAS 2
0_0402_5% 1 2
2
RTCPU_EN 1 2
PR8128
VSSGT_SENSE_R VR_ON <39,47,55,57>
10K_0402_1%
13.3K_0402_1%
3.01K_0402_1%
13.3K_0402_1%
1
VSSSENSE_R
1
1
1
Ta=70=>Id=30A AISP1 AVcore1

8.2K_0402_1% 5.1K_0402_1%
+VREF
PR8134
@ PU8101 PC8119 PC8120 PC8121 PC8117

Rdson=2.8~3.5 mohm
PR8135
PR8133
PR8132
PR8136
RT3607CEGQW _W QFN56_6X6 EMI@ EMI@
1
1
1
1
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0402_25V6
57
42
20
21
22
31
16
23
26
25
24
27
32
13
2
2
2
1
PC8115
VREF
VR_HOT
ALERT
VDIO
GND
TSEN
IMON
TSENA
IMONA
IBIAS
NC
EN
RGND
VCLK
RGNDA
2
2
2
2
1
1
1U_0201_6.3V6K
PR8143
0_0402_5%
2K_0402_1%
24.9_0402_1%
26.7K_0402_1%
2
@ PR8139 0_0402_5%
PR8140
PR8137
PR8138
PR8141
2 1 56
NC 52 RTCPU_PW M1
@ PR8142 0_0402_5%
@ 2 1 44 PWM1 PR8144 PC8122
2
2
NC 51 RTCPU_PW M2
2.2_0603_1% 0.1U_0603_25V7K Ta=70=>Id=17.5A
RTCPU_TONSET 55 PWM2 BOOST_VCC2 1 2BOOST_VCC2_R
1 2
RTCPU_SET1 TONSET 53 RTCPU_PW M3 Rdson=8.2~10.5 mohm
RTCPU_SET2 RTCPU_TONSETA 43 PWM3
RTCPU_SET3 TONSETA 50 RTCPU_PW M4 PQ8102
RTCPU_SETA1 RTCPU_PS4 PWM4 PU8103
2
49
RTCPU_SETA2 PS4 30
G1
D1
RTCPU_SET1 14 NC 4 3 VCC_UG2
PL8306
SET1 5 PR8150 BOOT UGATE 0.15UH_MMD06CZER15MG_37A_20%
402_0402_1%
768_0402_1%
3.4K_0402_1%
1.02K_0402_1%
300_0402_1% 3.16K_0402_1%
RTCPU_SET2 AISP1 VCC_PHASE2 VCC_PHASE2

1
1
1
15 ISEN1P 680_0402_1% 5 2 7 1 4
SET2 4 RTCPU_ISEN1N 1 2 PWM PHASE D2/S1
PR8148
PR8149
PR8147
RTCPU_SET3 ISEN1N AVcore1

17 PR8151 EN2 1 6 2 3
PR8145
PR8146
SET3 5.1_0402_1% EN PGND
G2
S2
S2
S2
RTCPU_SETA1 18 6 1 2 8 7 VCC_LG2
PR8152
GND AISP2 +5VALW
2
2
2
SETA1 ISEN2P 680_0402_1% VCC LGATE 9
3
RTCPU_ISEN2N GND
1
7 1 2 AON6962_DFN5X6D-8-7 @EMI@
412_0402_1%
RTCPU_SETA2 19 ISEN2N AVcore2

1
1
1
PR8158
PR8155
PR8153
PR8154
0_0402_5%
0_0402_5%
0_0402_5%
SETA2 PC8123 RT9610CGQW _W DFN8_2X2 4.7_1206_5%

PR8156
PR8157
2 PR8159 1U_0201_6.3V6K
AISP3
1
ISEN3P 680_0402_1%
200_0402_1%
2
RTCPU_VSENA 33 3 RTCPU_ISEN3N 1 2
@ @ @
PR8160
RTCPU_VSENA AVcore3
2
2
2
VSENA ISEN3N SNUB_VCC2
C RT3607CE 9
AISP4 PR8162 200_0402_1%
PR8161 PC8124
0.47U_0402_6.3V6K C
2
1
ISEN4P 680_0402_1% @ PR8163 1 2 1 2
RTCPU_VSEN 12 8 RTCPU_ISEN4N 1 2
RTCPU_VSEN AVcore4 0_0402_5% @EMI@
VSEN ISEN4N RTCPU_PS4 1 2 EN2 PC8125 @ PR8164
2
680P_0402_50V7K 0_0402_5%
47 RTCPU_PW MA1 1 2
RTCPU_VSEN RTCPU_COMP 11 PWMA1
@ PR8165 PR8166 PR8167 COMP 46
0_0402_5% 10K_0402_1% 23.2K_0402_1% 10 PWMA2
Ta=70=>Id=30A AISP2 AVcore2
ISENA3N
ISENA2N
ISENA1N
ISENA3P
ISENA2P
ISENA1P
FB
PGOOD
COMPA
2 1 2 1 2 1 48
<12> VCCSENSE PWMA3 Rdson=2.8~3.5 mohm
VCC
DVD
FBA
RTCPU_FB +19VB_CPU
NC
PR8168 PC8126 PC8127

100_0402_1% 330P_0402_50V8J 82P_0402_50V8J
2 1 2 1 2 1 +19VB_CPU
+VCC_CORE
45
28
RTCPU_COMPA 34
35
54
29
40
41
36
37
RTCPU_ISENA1N 39
38
AISPGT1
PC8130 PC8131 PC8132 PC8133
510K_0402_1%
RTCPU_DVD
RTCPU_VCC
1
RTCPU_FBA
VCCCORE_VR_PWRGD EMI@ EMI@
1
1
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0402_25V6
1
PR8171
PR8169
680_0402_1%
2
2
@ PR8170 2 1
AVGT1
2
0_0402_5%
RTCPU_VCC
100K_0402_1%
RTCPU_VCC
2
1
PR8174 PC8135 Ta=70=>Id=17.5A

1
PC8134 2.2_0603_1% 0.1U_0603_25V7K

PR8172
10_0603_1%
BOOST_VCC3 2BOOST_VCC3_R Rdson=8.2~10.5 mohm

1
PC8136 1 1 2
PR8173
0.1U_0402_50V7K
2
2
2.2U_0402_6.3V6M PQ8103
PU8104
2
2
RTCPU_VSENA
2
@ PR8175 PR8177 PR8176
G1
D1
4 3 VCC_UG3
0_0402_5% 10K_0402_1% 16.9K_0402_1% PL8305
2 1 2 1 2 1 BOOT UGATE 0.15UH_MMD06CZER15MG_37A_20%
<12> VCCGT_SENSE VCC_PHASE3 VCC_PHASE3
5 2 7 1 4
PR8178 PC8137 PC8138 PWM PHASE D2/S1
+5VALW
100_0402_1% 270P_0402_50V7K 68P_0402_50V8J PR8179 EN3 1 6 2 3
2 1 2 1 2 1 5.1_0402_1% EN PGND
G2
S2
S2
S2
+VCC_GT VCCCORE_VR_PWRGD <39> 1 2 8 7 VCC_LG3
+5VALW VCC LGATE 9
3
GND
1
AON6962_DFN5X6D-8-7 @EMI@
100K_0402_1%
1
1
PR8181
PC8139 RT9610CGQW _W DFN8_2X2 4.7_1206_5%
1U_0201_6.3V6K
PR8180
1
200_0402_1%
2
PR8182
2
SNUB_VCC3
Reserved for RF Team Request
PR8183 PC8140
200_0402_1% 0.47U_0402_6.3V6K
2
1
+1.05V_VCCST confirm with power sequence, @ PR8184 1 2 1 2
it need behind +5VS. 0_0402_5% @EMI@
RTCPU_PS4 1 2
@RF@ PC8142 +3VALW EN3 PC8141 @ PR8185
2
2.2P_0402_50V8C PR96and PR98 pull high resistor are pop at the end of VR 680P_0402_50V7K 0_0402_5%
1 2 SVID. 1 2
Other VR is unpop.
B B
PR8186 @ PR8187 PR8188 PC8143 Ta=70=>Id=30A AISP3 AVcore3
+19VB_CPU
Rdson=2.8~3.5 mohm
0.1U_0402_25V6
1
1
1
1
100_0402_1%
100_0402_1%
45.3_0402_1%
ENABLE
Upper Threshold > 0.8V
2
Lower Threshold < 0.3V PC8146 PC8147 PC8148 PC8149

2
2
EMI@ EMI@
1
1
1
1
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
@
SCLK_CPU PR8189 1 2 49.9_0402_1%
CPU_SVID_CLK <11,57>
2
2
2
2
ALERT_CPU 2 0_0402_5%
@ PR8190 1
CPU_SVID_ALERT#_R <11,57>
SDIO_CPU
PR8191 1 2 10_0402_1%
CPU_SVID_DAT <11,57> PR8192 PC8150 Ta=70=>Id=17.5A
2.2_0603_1% 0.1U_0603_25V7K
BOOST_VCC4 1 2BOOST_VCC4_R
1 2 Rdson=8.2~10.5 mohm
Ta=70=>Id=30A
Rdson=2.8~3.5 mohm PQ8104
PU8105
2
+19VB_CPU
G1
D1
4 3 VCC_UG4
H/S AON6380 Rds(on) :typ:8.2mOhm, max:10.5mOhm BOOT UGATE
PL8106
0.15UH_MMD06CZER15MG_37A_20%
VCC_PHASE4 VCC_PHASE4
Idsm(TA=25)=22A, Idsm(TA=70)=17.5A 5
PWM PHASE
2 7
D2/S1
1 4
PC8151 PC8152 PC8153 PC8154 PC8155 PC8156 PR8193 EN4 1 6 2 3

EMI@ EMI@ 5.1_0402_1% EN PGND
G2
S2
S2
S2
VCC_LG4
1
1
1
1
1
10U_0805_25V6K
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
1 2 8 7
L/S AON6314 Rds(on) :typ:2.8mOhm, max:3.5mOhm +5VALW VCC LGATE 9
3
Idsm(TA=25)=37A, Idsm(TA=70)=30A
1
GND AON6962_DFN5X6D-8-7 @EMI@
2
2
2
2
2
1
PR8194
PC8157 RT9610CGQW _W DFN8_2X2 4.7_1206_5%
1U_0201_6.3V6K
1
200_0402_1%
2
PR8196 PC8158 Ta=70=>Id=17.5A
PR8195
2.2_0603_1% 0.1U_0603_25V7K SNUB_VCC4
BOOST_VCCGT1 1 2BOOST_VCCGT1_R
1 2 Rdson=8.2~10.5 mohm PR8197 PC8159
200_0402_1% 0.47U_0402_6.3V6K
2
1
PQ8105 @ PR8198 1 2 1 2
PU8106 +VCC_GT
1
0_0402_5% @EMI@
RTCPU_PS4 1 2 PC8160 @ PR8199
EN4
G1
D1
2
4 3 VCCGT_UG1 PL8107 680P_0402_50V7K 0_0402_5%
BOOT UGATE 0.15UH_MMD06CZER15MG_37A_20% 1 2
RTCPU_PW MA1 5 2 VCCGT_PHASE1 7 VCCGT_PHASE1 1 4
PWM PHASE D2/S1
PR8200 EN5 1 6 2 3 Ta=70=>Id=30A AISP4 AVcore4
5.1_0402_1% EN PGND
G2
S2
S2
S2
1 2 8 7 VCCGT_LG1 Rdson=2.8~3.5 mohm

+5VALW VCC LGATE 9
6
GND AON6962_DFN5X6D-8-7 @EMI@

1
PR8201
PC8161 RT9610CGQW _W DFN8_2X2 4.7_1206_5%
1U_0201_6.3V6K
2
1
182_0402_1%
A A
2
PR8202
SNUB_VCCGT1
PR8203 PC8163
182_0402_1% 0.47U_0402_6.3V6K
2
1
@ PR8204 1 2 1 2
0_0402_5% @EMI@
RTCPU_PS4 1 2 PC8162
EN5 @ PR8205
2
680P_0402_50V7K 0_0402_5%
1 2
AISPGT1 AVGT1

RT3607CE
5 4 3 2 1
5 4 3 2 1
PR902 and PR904 pull high resistor are pop at the end of VR SVID.
+1.05V_VCCST Other VR is unpop.
SVID_ALERT# pull high resistor is at HW side.
1
Confirm HW side.
Don't double pull high. @ PR8302 +1.05V_VCCST confirm with power sequence,
D
it need behind +5VS. D
1K_0402_5%
2
<39> VR2_HOT#
100_0402_1%
0.1U_0402_25V6
0.47U_0402_6.3V6K
1
PR8304
PC8303
PR8303
VREF_VCCSA
1
PC8302
45.3_0402_1%
2
14K_0402_1% 30.9K_0402_1%
2
1
VR_HOT# 90 degreeC PR8306
PR8305
49.9_0402_1%
ALERT# 87.3 degreeC
1
1 2 CPU_SVID_CLK <11,56>
PR8307
PH8302 @ PR8308
2
100K_0402_1%_B25/50 4250K 1_0402_1% 0_0402_5%
1 2 1 2 CPU_SVID_ALERT#_R <11,56>
2
1
PR8309
PR8311
59K_0402_1%
1
10_0402_1% Choke 7x7x4 7x7x3
1 2
PR8310
PR8313 PR8314 CPU_SVID_DAT <11,56> Size and DCR 0.67m +-5%0.9m +-5%
1
48.7K_0402_1%
200_0402_1%
10K_0402_1%
2
TSEN_VCCSA_R
2 1 2 1 +19VB_CPU
PR8312
7.32K_0402_1%
2
1
PR813 68.1K 73.2K
PR8315
Vboot=0V IMON
1
VREF_VCCSA
PR841 0 1.1K
2200P_0402_50V7K
2.4K_0402_1%
PR8316
EMI@ PC8308
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
@EMI@ PC8307
2
1
ALERT#_VCCSA
PC8304
PC8305
PR832 10K
TSEN_VCCSA
VREF_VCCSA
VCLK_VCCSA
IMON_VCCSA
SDIO_VCCSA
22K_0402_1%
COMP
3.6K_0402_1%
22.6K_0402_1%
2
1
1
@ PC8306
2K_0402_1%
PR833 40.2K 37.4K
2
1
1
+19VB_CPU
PR8318
PR8317
PR8319
PR8320
0.1U_0402_25V6 PR8321 EN: high > 0.7V, Low < 0.3V
2
0_0402_5% PR828 604 665
VCCSA_VR_EN 1 2 VR_ON <39,47,55,56>
2
PR8322 ISEN PR830 243 549
2
1
SET1 connect to 5V is into test mode. 2.2_0805_1%
16
18
17
2
120_0402_1%
The output is 1.05V. PR831 10K 1K

1
1
0_0402_5%
PR8326
300_0402_1%
VRHOT#
VCLK
VDIO
ALERT#
TSEN
IMON
VREF
EN
UG_VCCSA
PR8324
PR8325
PC8309 PR8301
C C
0.22U_0402_25V6K 2.2_0603_5% PH802 10K(3370K) 1K(3650K)
2
1 2 13 BOOST_VCCSA 1 2BOOST_VCCSA_R
@ VIN
2
PSYS_VCCSA 19 PU8301
0.22U_0402_16V7K
PSYS
4
SET1_VCCSA
PC8301
RT3601EAGQW _W QFN28_4X4
SET2_VCCSA PL8301 +VCC_SA
G1
D1
D1
D1
SET3_VCCSA 0.24UH_22A_20%_ 7X7X3_M
1.78K_0402_1%
7.68K_0402_1%
2
28
PR8329
300_0402_1% 20K_0402_1%
1
SET1 LX_VCCSA 9 10 LX_VCCSA 1 4

PR8327
PR8328
27 D2/S1 D1
SET2 14 AISP1_R 2 3
26 PWM
@EMI@ PR8330
Local sense, for debug only. PQ8301
G2
S2
S2
S2
SET3
1
AONH36334_DFN3X3A8-10
4.7_1206_5%
Trace is form output cap that is near choke.
1 2
1 2
1 2
1
11 LG_VCCSA PR8331
5
LGATE 576_0603_1%
100_0402_1%
2.2K_0402_1%
10 LX_VCCSA
PR8332
PR8333
PR8334
PC8310
PR8335 PHASE 0.47U_0402_6.3V6K
2
100_0402_1% VSEN_VCCSA 25 9 UG_VCCSA 1 2
1 SNUB_VCCSA 2
2 1 VSEN UGATE PR8336 PR8337
+VCC_SA
2
2
2
8 BOOST_VCCSA LG_VCCSA 255_0402_1% 10K_0402_1%

BOOT 1 2AVcore1_NTC 1 2
AVcore1_VCCSA
@ PR8339 @ PR8340
@EMI@ PC8311
0_0402_5% 0_0201_5%
680P_0402_50V7K
2AVcore1_NTC_R
AISP1_VCCSA
2 1 1 1 2
<13> VCCSA_SENSE COMP_VCCSA 23
@ PR8341 @ PR8342 PR8343 PR8344 PR8345 COMP
0_0402_5% 0_0402_5% 10K_0402_1% 300_0402_1% 47.5K_0402_1% FB_VCCSA 24 PH8301
2 1 2 1 2 1 2 1 2 1 FB 10K_0402_1%_B25/50 3370K
2
29
GND
1
RGND_VCCSA 22
PC8312 PC8314
RGND
For NTC trace routing only.
@ PC8313 330P_0402_50V8J 100P_0402_50V8J
0.1U_0402_25V6 2 1 1 2
VR_READY
2
ISEN1N
ISEN1P
DRVEN
1
PVCC
VCC
@ PC8315
0.1U_0402_25V6
2
@ PR8346
7
+VCC_VCCSA1
12
15
21
20
B 0_0402_5% B
2 1
<13> VSSSA_SENSE
+5VALW
1U_0201_6.3V6K
1
AISP1_VCCSA
PC8317
@ PC8316
100_0402_1%
<39> VCCSA_VR_PW RGD

PR8347
0.1U_0402_25V6
2
2
1
AVcore1_VCCSA
PR8348
0.1U_0402_25V6
2
Confirm HW side. 100K_0402_5%

22_0402_1%
1
1
PC8319
PR8349
Don't double pull high.

PC8318
2
2.2U_0603_10V6K
2
2
2
Local sense, for debug only.

+3VALW
+5VALW
VCCSENSE and VSSSENSE need have
a 100ohm at HW Side
A A

RT3601EA VCC_SA
Size Document Number Rev
5 4 3 2 1
A
B
C
D
2 1 2 1 2 1 2 1 2 1 2 1 2 1 +VCC_CORE
2
1
+
PC9139 PC9124 PC9114 PC9093 PC9067 PC9039 PC9009 PC9002

1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 220U_D2_2V_Y
+VCC_CORE
2
1
+
2 1 2 1 2 1 2 1 2 1 2 1 2 1
5
5
PC9003
PC9140 PC9125 PC9115 PC9094 PC9068 PC9040 PC9010 220U_D2_2V_Y
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
+
2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC9004
PC9141 PC9126 PC9116 PC9095 PC9069 PC9041 PC9011 220U_D2_2V_Y
2 1
2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC9154
PC9142 PC9127 PC9117 @ PC9096 PC9070 PC9042 PC9012 22U_0603_6.3V6M
2 1
2 1 2 1 2 1 2 1 2 1 2 1 2 1
PC9150
@ PC9143 PC9128 PC9118 @ PC9097 PC9071 PC9043 PC9013 22U_0603_6.3V6M
2 1
2 1 2 1 2 1 2 1 2 1 2 1
PC9156
@ PC9144 PC9129 PC9119 PC9072 PC9044 PC9014 22U_0603_6.3V6M
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1
2 1 2 1 2 1 2 1 2 1 2 1
PC9155
2 1
2 1 2 1 2 1 2 1 2 1 2 1
PC9153
2 1
2 1 2 1 2 1 2 1 2 1 2 1
PC9152
2 1
4
4
2 1 2 1 2 1 2 1 2 1 2 1
PC9151
2 1 2 1 2 1 2 1
+VCC_GT
PC9098 PC9077 PC9049 PC9019

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
PC9099 PC9078 PC9050 PC9020

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
@ PC9100 PC9079 PC9051 PC9021

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
2
1
+
@ PC9101 PC9080 PC9052 PC9022 PC9007

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 220U_D2_2V_Y
+VCC_GT
2 1 2 1 2 1 2 1
@ PC9102 PC9081 PC9053 PC9023

1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1
2 1 2 1 2 1 2 1 PC9162
22U_0603_6.3V6M
@ PC9103 PC9082 PC9054 PC9024
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1
3
3
2 1 2 1 2 1 2 1 PC9158
22U_0603_6.3V6M
@ PC9104 PC9083 PC9055 PC9025
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1
2 1 2 1 2 1 2 1 PC9157
22U_0603_6.3V6M
@ PC9105 PC9084 PC9056 PC9026
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1
Issued Date
@
2 1 2 1 2 1 2 1 PC9160
22U_0603_6.3V6M
@ PC9106 PC9085 PC9057 PC9027
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1
2 1 2 1 2 1 2 1 PC9163
22U_0603_6.3V6M
@ PC9107 PC9086 PC9058 PC9028
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1
@
PC9159
22U_0603_6.3V6M
2 1
PC9161
22U_0603_6.3V6M
2016/07/18
2 1
PC9164
22U_0603_6.3V6M
2 1
PC9165
22U_0603_6.3V6M
2 1
2
2
Compal Secret Data
PC9166
Deciphered Date
22U_0603_6.3V6M
+VCC_SA
2 1 2 1
@
PC9108 PC9087
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
PC9134 PC9109 PC9088

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

2017/06/14
2 1 2 1 2 1
@
@ PC9135 PC9110 PC9089

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
@ PC9136 PC9111 PC9090

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Title
Date:
2 1 2 1 2 1
Custom
@ PC9137 PC9112 PC9091

1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
@ PC9138 PC9113 PC9092

Size Document Number
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

Thursday, February 22, 2018
1
1
C5MMH M/B LAE911P
Sheet
58
of
67
R ev
0.1
A
B
C
D
A B C D E
+19VB
VGA_EMI@ PL1301
FBMA-L11-201209-800LMA50T
TYP MAX 1 2
H/S_AON6428 Rds(on) = 11.3m Ohm , 14.5m Ohm
L/S_AON6794 Rds(on) = 2.8m Ohm , 3.5m Ohm +19VB_1.35VSDGPUP 1
1 2
2
10U_0805_25V6K
10U_0805_25V6K
@ PJ1301
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
1
1
1 JUMP_43X79 1
VGA_EMI@ PC1302
@VGA_EMI@ PC1303
VGA@ PC1304
VGA@ PC1310
VGA_EMI@ PC1312
5
<25> 1.35VS_DGPU_PG VGA@ PQ1301
2
AON6380 1N DFN5X6-8
VGA@ PR1312 4
1 2
+3VS 10K_0402_5%
PU1301 VGA@
IOCP RT8237EZQW (2)_W DFN10_3X3 VGA@ PR1302 VGA@ PC1305 Choke 0.82uH SH00000FH00/SH00000YJ00
3
2
1
0_0603_5% 0.1U_0603_25V7K
VGA@ PR1301 1 10 BST_1.35VSDGPUP 1 2 1 2 (Size:6.95 x 6.6 x 2.8 mm)
PR1303 VGA@ 69.8K_0402_1% PGOOD BOOT (DCR:6.7m~8m Ohm)
1K_0402_1% 1 2ILMT_1.35VSDGPUP 2 9 HGATE_1.35VSDGPUP VGA@ PL1302
CS UGATE 0.82UH PCMC063T-R82MN 13A_20%
1.35VS_DGPU_EN LX_1.35VSDGPUP
<29> 1.35VSDGPU_PW R_EN
2 1 3
EN PHASE
8 1 2
+1.35VSDGPUP
4 7
VGA@ PC1306
0.1U_0402_16V7K
FB VCC +5VALW
5
1
1
@VGA@
1
5 6 LGATE_1.35VSDGPUP
220U_D2 SX_2VY_R9M
220U_D2 SX_2VY_R9M
1M_0402_1% RF LGATE PR1305 1 1
2
PR1304 11
PC1301
PC1311
TP 4.7_1206_5%
+ +
VGA_EMI@
2
1
4
2
1
VGA@ VGA@
SNB_1.35VSDGPUP
1
PR1306 PC1307 2 2
1U_0402_6.3V6K
VGA@
VGA@
Frequency 200K_0402_1% VGA@ PR1314
2
2 VGA@ PQ1303 100_0402_1%
2
3
2
1
AON6314 1N DFN5X6-8
Rrf=470K ->290KHz
2
Rrf=200K ->340KHz VGA@ PC1313 VGA@ PR1315
1
680P_0402_50V7K 49.9_0402_1%
Rrf=100K ->380KHz 1 2 1 2 PC1308
680P_0402_50V7K
2
VGA_EMI@
1
VGA@ PR1307
1.35VS_DGPU_FB 2 1 1 2
PR1310 VGA@ FB_VDDQ_SENSE <28>
90.9K_0402_1% 18.7K_0402_1% @VGA@ PR1313 0_0402_5%
1
2
VGA@
PR1308
1
D
VGA@ 20K_0402_1%
1 2 2 PQ1302
VFB=0.704V
2
<25> VRAM_VDD_CTL L2N7002W T1G_SC70-3

G
1
PR1309 S
3
VGA@ PR1311 0_0402_5%

@VGA@ PC1309
0.1U_0402_16V7K
1
10K_0402_1% @VGA@
Vout=0.704V* (1+(18.7/20))=1.36 0.97%
2
Vout=0.704V* (1+(18.7/(20//93.1)))=1.5 0.03% @ PJ1302

Vout=0.704V* (1+(18.7/(20//90.9)))=1.524 1.62% +1.35VSDGPUP 1
1 2
2 +1.35VSDGPU
Vout=0.704V* (1+(18.7/(20//88.7)))=1.548 3.23% JUMP_43X118
3 Rds on 2.8 / 3.5mohm 3

Change the output voltage from 1.35V to 1.5V @ PJ1303
Rlimt=69.8K 1
1 2
2
JUMP_43X118
4 4
2016/07/18
Compal Secret Data
2017/06/14 Title
VRAM
A3

A B C D E
@ PJ1401
JUMP_43X79
1 2
+1.0VSDGPUP 1 2 +1.0VSDGPU
1 1
VGA@ PC1402 Choke 1uH SH00000YG00 (Common Part)

22U_0603_6.3V6M
(Size:3.8 x 3.8 x 1.9 mm)
1 2 VGA@ PU1401 (DCR:20m~25m)
SY8032ABC_SOT23-6
@ PJ1402 VGA@ PL1401
JUMP_43X79 1UH_2.8A_30%_4X4X2_F
1 2 VIN_1.0VSDGPUP 4 3 LX_1.0VSDGPUP 1 2
+3VALW 1 2 IN LX +1.0VSDGPUP
5 2
<25> 1VS_DGPU_PG PG GND Rup
VGA@ PC1401
68P_0402_50V8J
VGA@ PR1401 6 1 VGA_EMI@
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
FB EN
1
1 2 PR1402
+3VS
1
4.7_0603_5% VGA@
VFB=0.6V
@VGA@ PC1406
VGA@ PC1403
VGA@ PC1407
VGA@ PR1406 4.7K_0402_5% PR1403
2
0_0402_5% 13.7K_0402_1% Vout=0.6V* (1+Rup/Rdown)
2
1 2 EN_1.0VSDGPUP
<25> 1.0VSDGPU_EN =0.6V* (1+13.7/20)
SNUB_1.0VSDGPUP
2
Vout=1.011V
1
FB_1.0VSDGPUP
VGA@ PR1404 VGA@ PC1404
1M_0402_1% 0.1U_0402_16V7K
Rdown
1
2
VGA@
PR1405
1
VGA_EMI@ 20K_0402_1%
PC1405
2
680P_0402_50V7K
2
Note:
When design Vin=5V, please stuff snubber
2
to prevent Vin damage 2
3 3
4 4
2016/07/18
Compal Secret Data
2017/06/14 Title
1.05VSDGPU
C

A B C D E
5 4 3 2 1
+19VB_NVVDD
<62> NVVDD_ISUMP1 NVVDD_ISUMP2 <62>
PC1201
0.1U_0402_25V6
1 2
1
0_0402_5%
2
0.1U_0402_25V6
PR1205
PR1202
PR1203
20K_0402_1%
20K_0402_1%
PC1202
2
layout 上 :
91K_0402_1%
2
@ 請將 Tota l DC R sensin g 的compon en t
PR1206
@
1
PR1201 放靠近Control le r .
PR1207 for OCP setting
10.7K_0402_1%
1
2
10K_0402_5% NTC_La NTC_Lb
PR1207
2 1 @ PR1208 @ PR1209
1 2 1 2 2 1
NVVDD_ISUMN1 <62>
PR1210 1_0402_1%
2
D 0_0402_5% 0_0402_5% D
PC1203 PC1217 2 1
NVVDD_ISUMN2 <62>
0.01U_0402_16V7K @ 0.1U_0402_25V6 1 2 PR1211 1_0402_1%
1 2 1 2 @ PR1212 0_0402_5%
For N17P-G1, TDP 50W
2 1 2 1 1 2
PR1214 PR1215
@ PC1204 0.1U_0402_25V6 NVVDD1
0_0402_5% 0_0402_5% 1 2 TDC = 45+13=58A
2
1 2 2 1
PR1218
PC1206 PR1216 PR1217 @ PC1205 0.1U_0402_25V6 NTC_La NTC_Lb Peak Current = 106+18=124A
1 2
0.015U_0402_16V7K 2.4K_0402_1%
1 2
0_0402_5% 1 2
@
PH1201 OCP = 148A
Close to PU1201 PC1207 0.1U_0402_10V6K 1 2
GPU_PROG3
GPU_PROG1
GPU_PROG2
1
@ PC1208
0_0402_5% 0_0402_5% 0.1U_0402_25V6 2 1 470K_0402_5%_B25/50 4700K
PR1220
2
<27> VCCSENSE_VGA PR1219 1K_0402_1%
PR1221
0_0402_5%
EAP
CSPSUM
VINMON
1 2
Close to PL1301
COMP
1
+VGA_CORE
PC1209
SS
2 1 @ 0.1U_0402_10V6K
CSNSUM
1
2
PR1222
100_0402_5% PR1262
@ 0_0402_5% @ PC1212
1 2 1 2
24
23
22
21
20
19
18
17
0.1U_0402_25V6
PROG3
PROG1
PROG2
VINMON
IMON
COMP
EAP
SS
2
PR1223
1 layout 上 : 請將 RSE N1 ~ 4
<27> VSSSENSE_VGA
PR1224 1K_0402_1% 25
FB CSPSUM
16 放靠近 C o n t r o l l e r.
0_0402_5% PR1243 100K_0402_5%
1 2 FBRTN 26 15
2 1 FBRTN CSNSUM PR1225 2.2K_0402_1%
2 1 GPU_TP1 27 14 ISEN1 2 1
TP1 ISEN1 GPU_PH1
PR1228 +5VS 2 1 PR1226 2.2K_0402_1%
100_0402_5% GPU_TP2 28 PU1201 13 ISEN2 2 1
TP2 ISEN2 GPU_PH2
FBRTN PR1247 100K_0402_5% UP9511QQKI_WQFN32_4X4 PR1264
C
GPU_LPC 29 12 2 1 C
LPC ISEN3 5VCC
1 2 100K_0402_5%
+3VALW NVVDD1_ENP
PR1263 30 11
10K_0402_5% EN ISEN4
1
GPU_PSI 5VCC
31 PIN 30 LOW動作 . 5VCC 10
24.9K_0402_1%
PSI 2.2_0603_1% +5VS

DMN53D0LDW-7 2N SOT363-6
DMN53D0LDW-7 2N SOT363-6
PR1231
PR1230
32
PGOOD PWM1
9 5VCC 2 1 請教 A U TO
6
REFADJ
PHASE的設定
PWM4
PWM3
PWM2
REFIN
1U_0402_6.3V6K
VREF
33
PQ1201A
PQ1201B
FSW
2
GND
PC1214
VID
<25,29> VGA_CORE_EN
2 5
PWM1
1
2
@ PR1232
4
1
0_0402_5%
GPU_FSW
1 2
REFADJ
+3VS PR1239 +5VS
PWM2
GPU_VID 2 1 GPU_PWM1 <62>
@ PR1233 0_0402_5%
0_0402_5%
2
2
2 1
33K_0402_5%
43K_0402_5%
36K_0402_5%
10K_0402_5%
51K_0402_5%
+1.8VS PR1245
R1
PR1234
PR1242
PR1246
PR1248
PR1244
2 1 GPU_PWM2 <62>
1
DGPU_PSI <25> @ PR1235 0_0402_5%

6.19K_0402_1%
2 1
PR1236
1
1
0_0402_5% @
Fsw=300kHz
GPU_PROG1
GPU_PROG2
GPU_PROG3
1 2
2
GPU_LPC
@
PR1237 0_0402_5%
PR1238
PWMVID 的 RC BOM
100K_0402_5% 請根據GPU 's conf ig R3
REFIN
1 2 PR1241
+3VS
設定 PR1240
2 1
2
@
0_0402_5%
8.2K_0402_5%
8.2K_0402_5%
1
2
1 2 4.32K_0402_1%
PR1251
PR1252
PR1255
PR1257
0_0402_5%
309_0402_1% 16.5K_0402_1%
<25> VGA_CORE_PG
PR1249
<25> DGPU_VID
0_0402_5% R4
1
B B
@
2
1
@
1
R5
PR1256
R2 PR1258
2
2 1
4700P_0402_50V7K
20.5K_0402_1%
1
PC1215
Cold Boot = 4-phase

C
0.01U_0402_16V
Warm Boot = 4-phase

2
2
PC1216
1
FBRTN
A A

PWR_VGA_UP9511P
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC. C5MMH M/B LAE911P
5 4 3 2 1
1 2 3 4 5
+19VB
EMI@ PL1502
FBMA-L11-201209-800LMA50T
1 2 +19VB_NVVDD
EMI@ PL1503
FBMA-L11-201209-800LMA50T
VGA_CORE
1 2 Vboot=0.8V
TDC=58A
Peak Current=124A
A
OCP=148A A
+5VS
FSW=300kHz
Dr.MOS SIC632 TYP MAX
0_0402_5%
@ PR1502
H/S Rds(on) = 4.8mohm ,5.76mohm
+5VS L/S Rds(on) = 1.3mohm ,1.56mohm
1
PR1503
10K_0402_1%
PR1504 PU1501 1 2
1K_0402_1% 1 28
<61> GPU_PWM1 2 1 2 PW M CGND 27
+5VS 3 ZCD_EN# GL 26 PR1506
VCIN DSBL#
2
0_0402_5%
4 25 2.2_0603_1%
5 CGND THW n 24 2 1
@ PR1505
6 BOOT VDRV 23
PR1501 NC PGND Choke 0.22uH SH00000QZ00
1
1U_0402_6.3V6K
PC1502
7 22
PHASE GL
1
1U_0603_16V7
PC1503
1 2 8 21
1
9 VIN SW 20 GPU_PH1
2
PC1501 10 VIN SW 19 PL1501
2
0_0402_5% 1 2 11 PGND SW 18 0.22UH_MMD-10DZ-R22MES1L__35A_20% +VGA_CORE
+19VB_NVVDD 12 SW SW 17 GPU_PH1 1 4
0.1U_0402_50V7K 13 SW SW 16
14 SW SW 15 2 3
SW SW
SIC632CDT1GE3_POWERPAK31_5X5
PC1504
PC1505
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
10U_0603_25V6M
10U_0603_25V6M
1
1
PC1506
PC1507
PC1508
PC1509
B EMI@ B
1
PC1510
PC1511
PR1507
4.7_1206_5%
2
2
@EMI@
EMI@
2
<61> NVVDD_ISUMP1
2
@ @
GPU_SNB1
<61> NVVDD_ISUMN1
1
EMI@
PC1512
680P_0402_50V7K
2
+5VS
2
@ PR1508
0_0402_5%
+5VS
1
PR1509
PR1510 PU1502 1 2
C C
1K_0402_1% 1 28
<61> GPU_PWM2 2 1 2 PW M CGND 27 10K_0402_1%
+5VS 3 ZCD_EN# GL 26 PR1512
VCIN DSBL#
2
0_0402_5%
4 25 2.2_0603_1%
5 CGND THW n 24 2 1
@ PR1511
PR1513 BOOT VDRV

6 23
NC PGND
1
1U_0402_6.3V6K
PC1513
1 2 7 22
PHASE GL
1
1U_0603_16V7
PC1515
8 21
1
PC1514 9 VIN SW 20 GPU_PH2

2
0_0402_5% 1 2 10 VIN SW 19 PL1504
2
11 PGND SW 18 0.22UH_MMD-10DZ-R22MES1L__35A_20% +VGA_CORE
+19VB_NVVDD 0.1U_0402_50V7K 12 SW SW 17 GPU_PH2 1 4
13 SW SW 16
14 SW SW 15 2 3
SW SW
1
SIC632CDT1GE3_POWERPAK31_5X5 EMI@
PC1516
PC1517
10U_0603_25V6M
10U_0603_25V6M
PR1514
2200P_0402_50V7K
10U_0805_25VAK
10U_0805_25VAK
0.1U_0402_25V6
4.7_1206_5%
1
1
1
PC1518
PC1519
PC1521
PC1520
<61> NVVDD_ISUMP2
2
2
2
GPU_SNB2
EMI@
@EMI@
1
EMI@
PC1522
680P_0402_50V7K
2
<61> NVVDD_ISUMN2
D D

PWR_+NVVDD1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C5MMH M/B LAE911P
1 2 3 4 5
D
0.1
Rev
C5MMH M/B LAE911P

67
of
63
Sheet
VGA DECOUPLING
1
1
Thursday, February 22, 2018
Document Number
Date:
Title
Size
VGA@ @VGA@ @VGA@ VGA@ VGA@

PC1714 PC1768 PC1743 PC1756 PC17992
2017/06/14
22U_0603_6.3V6M 22U_0603_6.3V6M 4.7U_0402_6.3V6M 1U_0402_6.3V6K 10U_0603_6.3V6M MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
2
1 2 1 2 1 2 1 2 1 2
VGA@ @VGA@ VGA@ VGA@ VGA@
PC1713 PC1767 PC1742 PC1755 PC17991
22U_0603_6.3V6M 22U_0603_6.3V6M 4.7U_0402_6.3V6M 1U_0402_6.3V6K 10U_0603_6.3V6M
1 2 1 2 1 2 1 2 1 2
@VGA@ VGA@ VGA@ VGA@ VGA@ 560U_2.5V_M
PC1712 PC1766 PC1741 PC1754 PC1799
VGA@ PC1774
+
1
1 2 1 2 1 2 1 2 1 2
Deciphered Date
VGA@ VGA@ @VGA@ VGA@ VGA@ 220U_D2 SX_2VY_R9M
PC1711 PC1726 PC1740 PC1753 PC1728
Compal Secret Data

VGA@ PC1777
+
1
1 2 1 2 1 2 1 2 1 2
@VGA@ VGA@ VGA@ VGA@ VGA@ 220U_D2 SX_2VY_R9M
PC1710 PC1725 PC1739 PC1752 PC1727
@VGA@ PC1776
+
1
1 2 1 2 1 2 1 2 1 2
+VGA_CORE
2016/07/18
4.7uF_0402 X 20(+7@)
22uF_0603 X 27(+8@)
22uF_0805 X 0(+3@)
3
3
220uF_D2 X 3(+1@)
10uF_0603X 16
1uF_0402 X 14
560uF_OS X 2
Issued Date
+VGA_CORE
VGA@ VGA@ 560U_2.5V_M VGA@

PC1751 PC1779 PC1780
VGA@ PC1772
4.7U_0402_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
+
1
2
1 2 1 2 2 1
@VGA@ @VGA@ VGA@ VGA@ 220U_D2 SX_2VY_R9M 22U_0603_6.3V6M
PC1724 PC1738 PC1750 PC1778
VGA@ PC1773 VGA@ PC1796
4.7U_0402_6.3V6M 4.7U_0402_6.3V6M 4.7U_0402_6.3V6M 10U_0603_6.3V6M
+
1
2
1 2 1 2 1 2 1 2 2 1
4
4
VGA@ @VGA@ @VGA@ VGA@ VGA@ 220U_D2 SX_2VY_R9M 22U_0603_6.3V6M
PC1709 PC1723 PC1737 PC1749 PC1765
1U_0402_6.3V6K 4.7U_0402_6.3V6M 4.7U_0402_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
+
1
2
1 2 1 2 1 2 1 2 1 2 2 1
VGA@ VGA@ VGA@ @VGA@ VGA@ 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1708 PC1722 PC1736 PC1748 PC1764
1 2 1 2 1 2 1 2 1 2 2 1 2 1
VGA@ VGA@ VGA@ VGA@ VGA@ 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1707 PC1721 PC1735 PC1747 PC1763
VGA@ PC1797 @VGA@ PC1793
1 2 1 2 1 2 1 2 1 2 2 1 2 1
VGA@ VGA@ VGA@ VGA@ @VGA@ 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1706 PC1720 PC1734 PC1775 PC1762
VGA@ PC1786 @VGA@ PC1792
1 2 1 2 1 2 1 2 1 2 2 1 2 1
PC1705 PC1719 PC1733 PC1770 PC1761
1 2 1 2 1 2 1 2 1 2 2 1 2 1
PC1704 PC1718 PC1732 PC1769 PC1760
1 2 1 2 1 2 1 2 1 2 2 1 2 1
PC1703 PC1717 PC1731 PC1746 PC1759
1 2 1 2 1 2 1 2 1 2 2 1 2 1
PC1702 PC1716 PC1730 PC1745 PC1758
1 2 1 2 1 2 1 2 1 2 2 1 2 1
5
5
VGA@ @VGA@ VGA@ VGA@ @VGA@ 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1701 PC1715 PC1729 PC1744 PC1757
1 2 1 2 1 2 1 2 1 2 1 2 1 2
+VGA_CORE
A
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1 for PWR

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
Change the PQ310 from AON6366E (SB00001D800) to EMB04N03H (SB00001C500).
Change the PQ311、P Q31 2 fro m AON6366E ( SB00001 D800) to AON7380 ( SB00001 G M00).
01 Design Update Solution Change 0.2 50 Change the PC302、PC303 、 PC310、 PC3
1 1 、PC 312 f rom 1 0U_0603_ 25V ( SE00 000X2 00) t o 1 0U_0805_ 25V ( SE00 000Q
K00). 10/13 A2
Delete the PC323 10U_0603_25V (SE00000X200).
02 Design Update Solution Change 0.2 53 Change the PR603 (10K_0402_1%, SD034100280) from pop to un-pop. 10/13 A2
Change the PR7126 (100K_0402_5%, SD028100380) from un-pop to pop.
D D
03 Design Update Solution Change 0.2 54 Change the PR7126.2 net from +3VS to +3VALW. 10/13 A2
04 Design Update Solution Change 0.2 63 Change the PC1748、PC1 761、 PC1710、PC1 71 2、PC1767、 PC 1768 ( 22U_0603_6 . 3V, SE0 0000M000) from po p to un-pop. 10/13 A2
Change the PC315、PC1 308 、 PC1512、PC1 5 2
05 Design Update Down size for SNB MLCC 0.2 5 0 、5 9、 62 from 680P_50V_K_X7R_0603 (SE025681K80) to 680P_50V_K_X7R_0402 (SE074681K80). 10/13 A2
06 Design Update Solution Change 0.2 59 Change the PQ1302 from 2N7002KW (SB000009Q80) to L2N7002WT1G (SB00000ST00). 10/13 A2
07 Design Update Down size for MLCC 0.2 59 Change the PC1307 from 1U_6.3V_M_X5R_0603 (SE107105M80) to 1U_6.3V_K_X5R_0402 (SE000000K80). 10/13 A2
Change the PC102 from 100P_50V_J_NPO_0603 (SE024101J80) to 100P_50V_J_NPO_0402 (SE071101J80).
08 Design Update Down size for EMI MLCC 0.2 48 Change the PC104 from 1000P_50V_K_X7R_0603 (SE025102K80) to 1000P_50V_K_X7R_0402 (SE074102K80). 10/13 A2
Change the PC1747、P C1 759 、 PC1 74 9、 P C1 7
58、 P C1764、 P C
1 766、 P C
17
3 10/13 A2
09 Design Update Down size for MLCC 0.2 63 from 22U_6.3V_M_X5R_0805(SE000000I10) to 22U_6.3V_M_X5R_0603 (SE00000M000).
Change the PH8103、P H81 04 fro m 1 50K_5 %_0402_B25/50_4500K ( SL200002K00) to 220K_5 %_0402_B25/50_4700K ( SL200002I00).
10 Design Update Solution Change 0.2 56 Change the PR8109、P R811 0 fro m 8. 87K_0402_1 %( SD0348871 80) to 8. 66K_0402_1 %( SD0348661 80). 10/23 A2
Change the PR8118、P R811 9 fro m 93. 1 K_0402_1 %( SD034931 280) to 57. 6K_0402_1 %( SD034576280).
C 11 雷雷雷 Down size for Jump 0.2 53 Change the PJ602 from 43X79 to 43X39. 10/23 A2 C
Change the PC8113、PC81 24 、 PC81 4

0、 PC8159、PC8 1 6
3
12 Design Update Solution Change 0.2 5 6 、5 7 from 0.47U_16V_Z_Y5V_0402 (SE000002F80) to 0.47U_6.3V_K_X5R_0402 (SE124474K80). 10/25 A2
Change the PC8310 from 0.47U_25V_K_X5R_0402 (SE00000WA00) to 0.47U_6.3V_K_X5R_0402 (SE124474K80).
13 Design Update Solution Change 0.2 58 Add the location PC9164、PC91 65
、 PC91 66 and pop, 2 2U_6. 3V _M_X5R_0603 ( SE0000 0M000). 10/26 A2
Change the PR8114 from 6.81K_0402_1% (SD034681180) to 5.76K_0402_1% (SD034576180). 10/27 A2
14 Design Update CPU transient test result 0.2 5 6 、5 7、 58 Change the PR8113 from 2.49K_0402_1% (SD034249180) to 1.8K_0402_1% (SD00000R580).
Change the PR8117 from 560K_0402_1% (SD034560380) to 442K_0402_1% (SD034442300).
Change the PR8116 from 510K_0402_1% (SD00000RK80) to 402K_0402_1% (SD034402380).
Change the PR8141 from 100_0402_1% (SD034100080) to 8.2K_0402_1% (SD000004100).
Change the PR8149 from 1.05K_0402_1% (SD00000J480) to 3.16K_0402_1% (SD000006580).
Change the PR8176 from 20K_0402_1% (SD034200280) to 16.9K_0402_1% (SD034169280).
Change the PR8310 from 63.4K_0402_1% (SD03463K280) to 59K_0402_1% (SD034590280).
Change the PR8319 from 24.9K_0402_1% (SD034249280) to 22K_0402_1% (SD034220280).
Change the PR8325 from 0_0402_5% (SD028000080) to 300_0402_1% (SD034300080).
Change the PR8328 from 22K_0402_1% (SD034220280) to 20K_0402_1% (SD034200280).
B Change the PC8312 from 270P_0402_50V7K (SE074271K80) to 330P_0402_50V8J (SE000006I80). B

Change the PR8336 from 42.2_0402_1% (SD00000ZN00) to 255_0402_1% (SD034255080).
Change the PR8134 from 121K_0402_1% (SD034121380) to 13.3K_0402_1% (SD034133280).
Change the PR8138 from 49.9K_0402_1% (SD034499280) to 26.7K_0402_1% (SD034267280).
Change the PR8147 from 3.32K_0402_1% (SD034332180) to 768_0402_1% (SD00000TT80).
Change the PC9110、PC91 08 fro m 22 U_0603_6. 3V6 M ( SE00000 M000) to un- pop.
Change the PC9112、PC911 3 fro m un- pop to 22 U_0603_6. 3V6 M ( SE00000 M000).
Change the PC8126 from 330P_0402_25V8J (SE00000FD80) to 330P_0402_50V8J (SE000006I80).
Change the PR8173 from 0_0603_5% (SD013000080) to 10_0603_1% (SD014100A80).
Change the PC8137 from 330P_0402_25V8J (SE00000FD80) to 270P_0402_50V7K (SE074271K80).
Change the PC9159、PC91 60 fro m 22 U_0603_6. 3V6 M( SE00000 M000) to un- pop.
Change the PC9057、PC9058 fro m un- pop to 22 U_0603_6. 3V6 M( SE00000 M000).
Change the PR1303 from 10K_0402_1% (SD034100280) to 1K_0402_1% (SD034100180). 11/02 A2
15 Design Update Power sequence 0.2 5 9 、6 0 Change the PR1401 from 10K_0402_5% (SD028100280) to 4.7K_0402_5% (SD028470180).
16 Design Update Solution Change 0.2 61 Change the PU1201 from UP9511P (SA00009SW00) to UP9511Q (SA0000BK300). 11/08 A2
Change the PR1243、P R1 247 fro m 1 0K_0402_5 % ( SD0281 00280) to 1 00K_0402_5 % ( SD0281 00380).
17 Design Update Solution Change 0.2 5 2 、5 6、 57 Change the PC8317、PC509 、 PC517 fr om 1 U_0402_1 0V6K( SE0000 0QL10) to 1 U_0201 _6. 3V6K ( SE00000YB00). 11/08 A2
Change the PC8112、PC811 5、 PC81 2 3、 PC8139、PC8 1 57、PC8161 fr o m 1 U_0402_25V6K ( SE000010V00) t o 1 U_0201 _6. 3V6K ( SE00000YB00).
A A
18 Design Update Solution Change 0.2 5 0 、5 6 Change the PR340、P Q31 4 、 PQ31 3 A、 PQ313B、 PR 32 7、 P Q3 07、 PQ30 8 fro m p op to un -po p.
Change the PR326 from un-pop to 0_0603_5% (SD013000080) 11/14 A2
Change the PR310 from 51.1K_0402_1% (SD034511280) to 52.3K_0402_1% (SD034523280)
Change the PC8147 from Security Classification Compal Secret Data Compal Electronics, Inc.
10U_0805_25V_X5R Issued Date 2016/01/29 Deciphered Date 2017/06/14 Title
(SE00000QK00) to un-pop THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR
Custom
DH53F M/B LA-E951P 0.1

5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 2 of 2 for PWR

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
19 Design Update Solution Change 1.0 50 Change the PC313、PC31 4 fro m 1 U_1 6V_X5R_0402( SE00000 OU00) to 1 U_6. 3V_X5R_0201 ( SE00000YB00). 12/15 C
Change the PR304、P R31 、
4 PR316、 PR3
22、 PR 334、PR81 1 1、 P
R81 20、PR8128、P R81 39
、 PR81 4
2、 PR8143、PR81 53、 PR 8 1 5 4、
5 0 、5 5 PR8155、P R81 65
、 P R81 7
0、 PR8175、 P R8
1 90、 P R
81 29、 PR81 63、PR8184、P R81 98 、 P R820 4、 P R8308、 P R8
3 26 、 P R 83 39 、
20 Design Update Solution Change 1.0 5 6 、5 7 12/15 C
PR8341、P R8342、 PR8346、 PR3
1 7、 PR 333 f r o m 0_040 2_5 %( SD0280000 80) to R-shor .t
21 Design Update Solution Change 1.0 50 Change the PC305、PC324 fro m 0. 1 U_0402_25V7K( SE00000 W21 0) to 0. 1 U_0402_25V6 ( SE00000G880). 12/18 C
D D
22 Design Update Solution Change 1.0 56 Change the PC8101、PC81 22、 PC81 3
5、 PC8150、PC8158 f r om 0. 1 U_0603_50V7K( SE0251 04K80) 12/18 C
to 0.1U 25V K X7R 0603 (SE042104K80).
23 Design Update SW2 un-pop 1.0 49 Change the PR217 from un-pop to 0_0402_5%(SD028000080). 12/18 C
24 Design Update Solution Change 1.0 50 Change the PR326、P R7202 fro m 0_0603_5 %( SD01 3000080) to R-short. 12/18 C
25 Design Update Solution Change 1.0 56 Add PC8116、PC811 8, 33 U_D1 _25V M_R6 M( SGA0000 A400), and un- pop. 12/19 C
Delete location PR326、P R327
、 P Q30
7、 P Q3
0
8
26 Design Update 4S_BATT 1.0 50 Add location PR338->2M_0402_1% (SD034200480)、P R339->1 00K_0402_1 %( SD0341 00380) 12/20 C
Add location PQ315->LTC015EUBFS8TL(SB000011K00)、P Q31 6-> 2 N7002K W1 N S OT323- 3 ( SB00000ST00)
27 Design Update Solution Change 1.0 50 Change the PC309 from 0.22U_0603_25V(SE000005Z80) to 0.47U_0402_16V(SE000002F80). 12/21 C
28 Design Update ACIN_CHG 1.0 50 Change the PR306 from 392K_0402_1%(SD034392380) to 499K_0402_1%(SD034499380). 12/25 C
Change the PR310 from 52.3K_0402_1%(SD034523280) to 66.5K_0402_1%(SD034665280).
29 Design Update Power sequence 1.0 60 Change the PR1406 from 10K_0402_1%(SD034100280) to 0_0402_5%(SD028000080). 12/27 C
Change the Jump PJ7202、P J1 301 fro m short to open.
C C
Change the bead PL7201、PL1 301 fro m un- pop to pop 0805_5 A ( S M01 000 U600).
30 Design Update 3valw interfere 1.0 5 5 、5 9 Change the PR7203 from un-pop to pop 4.7_1206_5% (SD001470B80) 01/10 C
Change the PC7203 from un-pop to pop 680pF_0402_50V (SE074681K80)
31 Design Update Solution Change 1.A 55 Change the PR7202 from R-short to 0_0603_5%(SD013000080). 01/12 C
B B
A A
2016/01/29
Compal Secret Data
2017/06/14 Title
PIR
Custom
C5MMH M/B LA-E911P 0.1

5 4 3 2 1
A B C D E
Version change list (P.I.R. List) Page 1 of 1 for HW
Item Page Title Date Issue Description Solution Description Phase Rev.
1 29 Design Update 9/27 power source optimization DGPU1.8V power source change to 1.8VALW A2 0.2
1 1
2 39 Design Update 9/27 version upgrade Change board ID to DVT (V15_ID1/VX15_ID11) A2 0.2
Add RM44 for +3VALW to +3VS_WLAN

3 37 Design Update 10/17 CNVI power request A2 0.2
RH186/RH47/RH103/RH105/RH97/RH98/RH99/RH100/
RD3/RD6/RD2/RD15/RD13/RD17/RM22/RM23/RM24/
0 ohm part count reduce RM25/RM26/RM27/RM28/RM29/RM30/RM31/RM32/
Design Update 10/19 A2 0.2
4 RM33/RM34/RM35/RM38/RM39/RM40/RS1/RS8/RS16/
R19/R20/RQ5/RQ9/RQ6
5
Design Update 10/19 USB common voltage footprint update LS1/LS10 change footprint to "MURAT_DLM0NSN900HY2D_4P"
41,42 A2 0.2
CV75, Cv83, CV86, Cc88, CV87, Cv83, Cv73, Cv82,Cv108, Cv119, Cv118, Cv110,
6 for cost, change 10uF_0402 to 0603 Cv120, Cv121, Cv114, Cv115 , CC75, Cc73, Cc80, CC74,CC76, CC78, CC79, CX1
Design Update 10/24 A2 0.2
CX3, CA6, CA8, CA9, CA16, CA17, CC71, CC72, CC81, CC89, CC90,
7 44 Design Update 10/25 USB CMC move to M/B add L11/ L12 for USB2.0 CMC A2 0.2
2
add PU 100K RB78 for CNVI card detect 2
CNVI device detact issue reserved RB79 PD 0ohm for CNVI card detect
8 39 Design Update 10/26 EC add PIN89 GPIO50 as CNVI_DET# A2 0.2
add PIN 19 CNVI_DET#
9 38 Design Update 10/26 for reserve 4 dmic Change JDMIC1 to 4pin : SP02000TI00 A2 0.2
10 43 Design Update 11/02 SATA HDD redriver EQ tuning UNPOP RO17 for redriver EQ A2 0.2
change RV105 to 8.2K (vga_core_en)

RV12 change to 100k_1% (1.35VSDGPU_PWR_EN)
11 25 Design Update 11/02 NV vga sequence tuning RV113 change to 4.7k_5% A2 0.2
PR1303 change to 1k
PR1401 change to 4.7k
12 43 Design Update 11/06 co-lay no HDD re-driver circuit add CO14/CO16~18/RO21~24 for no re-driver. A2 0.2
45 Design Update 11/13 for factory request, don't include SW1 in bom unpop SW1 and control by SMT memo A2 0.2
3 3
13
replace level shift by 0 ohm on Type-C circuit unpop QS1/RS107/RS108 POP RS114/RS115
14 40 Design Update 11/13 A2 0.2
24Mhz Keep 33 18 /1M

15 Design Update 11/13 fine tune crystal frequency 25Mhz Keep 10 18 /330
27Mhz CV1 change to 15PF (15 12 /0) A2 0.2
32.768Khz change CH7/CH8 to 10PF (10 10 /10M)
16 Design Update 12/14 0 OHM change to R-short change RC17/RH5/RH6/RH94/RH96/RV125/RM2/RB19/RB76/RO4 PVT 1.0
/RS114/RS115 to R-short
peci issue, can't get system temperature UNPOP RH41
17 18 Design Update 12/14 PVT 1.0
18 46 Design Update 12/14 unpop SW2(BI SW) PVT 1.0

4
19 39 Design Update 12/16 channge board ID to ver1.0 (V series 15k/ vx series 200k) PVT 1.0
4
add RS116 on VBUS_EN_179

20 40 Design Update 12/18 change typeC VCONN sol to G527 change US2 to SA00006Y700, add RS156/RS155/CS101/CS124 PVT 1.0
2017/12/18
Compal Secret Data
2018/09/01 Title
PIR-HW1
Custom

A B C D E
A B C D E
Version change list (P.I.R. List) Page 1 of 1 for HW
Item Page Title Date Issue Description Solution Description Phase Rev.
21 37 Design Update 12/18 BT lost issue reserve RM45 for pull up BT_ON to +3VS_WLAN PVT 1.0
1
22 25 Design Update 12/20 vga sequence tuning change RV105 to 6.2k / RV103 to 24.9k PVT 1.0 1
23 21 Design Update 12/20 intel sensitive net pop CH29 & CH34 PVT 1.0
24 45 Design Update 12/21 intel ECN_Update Change RS64,RS65,RS74,RS76,RS82~RS85 to 0201 size. PVT 1.0
Add CS102~CS105,RS119~RS122.
37 reserve CM18 on CNV_RF_RESET#
25 Design Update 12/22 CNVI lost issue PVT 1.0
21 add CH52 0.1U on +1.8VALW_PRIM
reserve CM19 4.7uF on +3VS_WLAN

37
26 Design Update 12/26 CNVI lost issue reserve CH53_10uF on +1.8VALW_PRIM PVT 1.0
21
change RH100 R-short to 0_0603
27 38 Design Update 12/26 charmeleon down z-high on wi-fi card area change CA6/CA17 to 0402 package PVT 1.0
remove GPAK circuit for improve HDMI layout PVT 1.0

2
28 32 Design Update 12/26 improve HDMI layout del U18/CV225/RV126/RV125/CG341/CG342 2
29 change PCIE port from 17-20 to 12-9

18, 35 Design Update 01/11 improve optone layout for HM370 change from SSD_DEVSLP4 to SSD_DEVSLP1 PVT 1A
change from SATA_GP4 to SATA_GP1
30 18 Design Update 01/11 HDD port change to SATA0B PVT 1A
31 32 Design Update 01/11 JTYPEC1.A2/A3/B2/B3 change to NET NAME PVT 1A
32 7 Design Update 02/22 change PN for MP chip UC1/UH1/UV1/ change to MP part number
PVT 1A
33 19 Design Update 02/22 PVT memo improve POP RH183 Remove CQ7/CQ8 PVT 1A
3 3
4 4
2017/12/18
Compal Secret Data
2018/09/01 Title
PIR-HW1
Custom

A B C D E

Compal LA-F951P DH5VF DH7VF DH53F DH73F REV 1A (1.0) - Acer Nitro AN515-52

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Compal LA-F951P DH5VF DH7VF DH53F DH73F REV 1A (1.0) - Acer Nitro AN515-52

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A

Vxl 5/DH53F MB Schematic Document

Date : Thursday, February 22, 2018 ISheet 1 of 67

BOM Option Table

I5QP89 PG1 4G 32HDMI

+19VB -> +19V_CPU

DH5VF_EVT Power Sequence AC mode

Plug in Power On S3 S3 Resume Power Off

PM_SLP_S3# → 19.22ms 100.5us

2 SYSON → 72.1us → 152.8us

+1.05V_VCCST → 275.9us → 88.37us

+1.2V_VDDQ → 692.9us → 367.6us

+1.05VS_VCCSTG → 8.378us → 55.47us → 8.502us

+5VS → 877.7us → 618.5us → 906.0us

+3VS → 630.4us → 8.679ms → 656.1us

+1.8VS → 412us → 347.6us → 424.9us 446.2us

EC_VCCST_PG → 25.34ms → 0us → 25.25ms 0us

Date: Thursday, February 22, 2018 Sheet 5 of 67

EC_SMB_CK1 100 ohm EC_SMB_CK1-1 I2CC_SDA

KB9022 0 ohm EC_SMB_CK1_CHGR

Security Classification Compal Secret Data Compal Electronics, Inc.

CO-LAY FOR VGA OUTPUT

<27> GPU_EDP_TXP0 RG183 1 @ 2 0_0201_5%

RG191 1 @ 2 0_0201_5% EDP_AUXP

K36 D29 EDP_TXP0

Cannon Lake PCH SKU

Date: Thursday, February 22, 2018 Sheet 7 of 67

Date: Thursday, February 22, 2018 Sheet 8 of 67

<24> DDR_B_D[0..63] DDR CHANNEL B

RC3 1 2 121_0402_1% SM_RCOMP0 G1 BN13 +0.6V_VREFCA

Date: Thursday, February 22, 2018 Sheet 9 of 67

PEG Lane Reversed CFL-H

Date: Thursday, February 22, 2018 Sheet 10 of 67

PCH_CPU_BCLK_P B31 BN25 CFG0 CFG0 RC7 1 @ 2 1K_0402_5%

RC78 2 CMC@ 1 51_0402_5% CPU_XDP_TDO

RC14 1 2 499_0402_1% H_PROCHOT#_R

RC15 1 2 60.4_0402_1% EC_VCCST_PG

RC16 1 2 20_0402_5% H_PM_DOW N RC13 1 2 220_0402_5% CPU_SVID_ALERT#

Date: Thursday, February 22, 2018 Sheet 11 of 67

Date: Thursday, February 22, 2018 Sheet 12 of 67

+VCC_SA CFL-H +1.2V_VDDQ_CPU +1.2V_VDDQ_CPU +1.2V_VDDQ +1.2V_VDDQ_CPU

PLACE CAP BACKSIDE PLACE CAP BACKSIDE

Date: Thursday, February 22, 2018 Sheet 13 of 67

Date: Thursday, February 22, 2018 Sheet 14 of 67

Date: Thursday, February 22, 2018 Sheet 15 of 67

PCH-H XTAL_IN/OUT POR is 24MHz for 571697_CNL_MOW_WW16_2017.pdf CNP-H

AW13 BD4 CLK_CNV_PRX_DTX_N

Date: Thursday, February 22, 2018 Sheet 16 of 67

PCH_SPI_CLK RH195 1 @ 2 100K_0201_5%

intel critical net recommend

SPI ROM ( 16MByte )

note : 1050 Use 8M rom

Date: Thursday, February 22, 2018 Sheet 17 of 67

Date: Thursday, February 22, 2018 Sheet 18 of 67

RH55 2 1 1K_0402_5% W AKE#

RH56 2 1 8.2K_0402_5% PM_BATLOW # +3VALW _DSW PM_SLP_S3# RH193 1 2 100K_0201_5%

QH7B +3VALW _PCH_PRIM

+3VS POP on 1A version

D_CK_SDATA <23,24,43> PCH_DPW ROK

RH191 2 1 2.2K_0402_5% D_CK_SCLK XEMC@

XEMC@ PCH_VRALERT# RH62 2 @ 1 10K_0402_5%

Compal Electronics, Inc.

Date: Thursday, February 22, 2018 Sheet 19 of 67

CODEC_ID RH188 1 256@ 2 1K_0402_5%