Lecture 7

Chapter 4.8 – 4.12

 4.8 Magnitude Comparator
• A Magnitude Comparator is a combinational
circuit that compares two numbers A and B
and determines their relative magnitudes
– Outputs indicate:
• A>B
• A=B
• A<B
 4.8 Magnitude Comparator
• To compare two n-bit requires 22n truth table
entries
– n = 4 requires 22*4 = 256 table entries
• Upon inspection, a comparator possesses a
certain amount of regularity
– Consider two numbers A and B, with four digits each
• A = A 3 A2 A1 A 0
• B = A 3B 2B 1B 0
– The two number are equal when each pair of
significant digits are equal:
• A3 = B3, A2 = A2, A1 = B1, A0 = A0
 4.8 Magnitude Comparator
• As the numbers are binary, the equality of
each pair can be expressed logically with an
exclusive-NOR function:
xi = AiBi + A’iB’i for i= 0:3
where xi = 1 only if the pair in position i are equal
A B XNOR
A
0 0 1
0 1 0
(A ⊕ B)’ 1 0 0
1 1 1
B
 4.8 Magnitude Comparator
• A > B, B > A
– To determine if A is greater or less than B, inspect
the relative magnitudes of the pairs, starting with
the most significant pair
• If A =1 and B = 0, A > B
• If B = 1 and A = 0, B > A
Thus:
(A > B) = A3B3’ + x3A2B2’ + x3x2A1B1’ + x3x2x1A0B0’
(A < B) = A3’B3 + x3A2’B2 + x3x2A1’B1 + x3x2x1A0’B0
4.8 Magnitude Comparator
 4.9 Decoders
• A decoder is a combinational circuit that
converts binary information from n inputs to a
maximum of 2n unique output lines
• The decoders presented here are called n-to-
m line decoders
 4.9 Decoders
• Consider the truth table for a three-to-eight
line decoder:
– Each output represents one of the minterms of
the three inputs
4.9 Decoders
 4.9 Decoders
• Constructing decoders using NAND gates
– More economical to generate the decoder
minterms in their complemented form
• A two-to-four decoder with enable using
NAND gates:
 4.9 Decoders
• A decoder with enable input can function as a
demultiplexer
– A circuit that receives information from a single
line and directs it to 2n possible outputs, the
selection of a specific output controlled by the
combination of n select lines
– Consider two 3-to-eight decoders:
• When w = 0, the top decoder is
enabled and lower disabled
and the upper eight outputs
generate minterms 0000 to 0111
 4.9 Decoders
• Combinational Logic Implementation
– A decoder generates the 2n minterms of n input
variables
• Adding an external OR gate generates the familiar sum-
of-products form
– Recall any Boolean function can be expressed in a
sum-of-minterms form
– Thus, any combinational circuit with n inputs and
m outputs can be implemented with an n-to-2n
decoder and m OR gates
 4.9 Decoders
• Combinational Logic Implementation (cont.)
– Consider the truth table for the full adder

S(x, y, z) = Σ(1, 2, 4, 7)
C(x, y, z) = Σ(3, 5, 6, 7 )
 4.9 Decoders
• Combinational Logic Implementation (cont.)
– As there are three inputs and a total of eight
minterms, we need a three-to-eight decoder

S(x, y, z) = Σ(1, 2, 4, 7)
C(x, y, z) = Σ(3, 5, 6, 7 )
 4.9 Decoders
• Combinational Logic Implementation (cont.)
– A long list of minterms will require an OR gate
with a large number of inputs or several OR gates
cascaded together (large propagation delay)
– A function having k minterms can be expressed in
its complemented form F’ with 2n – k minterms.
• If the number of minterms in the function is greater
than 2n/2, then F’ can be expressed with fewer
minterms
 4.10 Encoders
• An encoder performs the inverse operation of
a decoder
– An encoder has 2n (or fewer) inputs and n outputs
– The outputs lines, taken as an aggregate, generate
the desired binary code corresponding to the
input value
 4.10 Encoders
• Consider an octal to binary encoder whose truth table is
given below:

• The encoder can implemented using three OR gates

whose inputs are taken directly from the truth table
x = D4 + D5 + D6 +D7
y = D2 + D3 + D6 +D7
z = D1 + D3 + D5 +D7
Note: Only one input can be active at a time
Need priority encoder
 4.10 Encoders
• Priority Encoders
– If two or more inputs are equal to a 1 at the same time, the input with
the highest predetermined priority will take precedence
– In table 4.8, the higher the subscript number, the higher the input
priority
• D3 is the highest, so when set, others are don’t cares
– V is the valid bit indicator
• Set when one or more inputs are 1s
• Outputs are not inspected when V = 0
 4.10 Encoders
• Priority Encoders (Table 4.8 cont.)
 4.11 Multiplexers
• A multiplexer is a combinational circuit that
routes binary information from one of many
inputs to a single output based on the select
value
– Acts an electronic switch Similar to the black
three terminal switch
• (Single Pole, Double Throw) in your kit

– Requires one select line

• Single Throw, Four Throw

– Requires two select lines

– Block diagram shown as wedge shaped symbol,

visually suggesting how multiple inputs are directed to
a single output
– Often labeled “MUX”
 4.11 Multiplexers

Two-to-one line mux

Four-to-one line mux

4.11 Multiplexers

Quadruple two-to-one line mux

 4.11 Multiplexers
• Boolean Function Implementation
– Section 4.9 showed that a decoder can be used to
implement Boolean functions by adding an
external OR gate
– Examination of a multiplexer shows that it is
essentially a decoder with an internal OR gate
– The minterms of a function are generated using
the selection inputs of a mux with the individual
minterms selected by the data inputs
– Thus a n variable Boolean function can be
implemented with a n – 1 selection mux
 4.11 Multiplexers
• Consider:
F(x, y, z) = Σ(1, 2, 6, 7)
– This function can be implemented with a four-to-one line mux
• Apply:
x to S1
y to S0
• The data input values are determined from the function truth
table
 4.11 Multiplexers
• Consider:
F(A, B, C, D) = Σ(1, 3, 4, 11, 12, 13, 14, 15)
– This function can be implemented with a four-to-one line mux
• Apply:
A to S2, B to S1, C to S0, D/D’ (and 1/0) to inputs
 4.11 Multiplexers
• Three-State Gates
– A digital circuit that exhibits three states:
• 0, 1, and tri-state (a.k.a. high impedance)
– Single Pole, Single Throw
– Like the blue DIP switches in your kit
• The tri-state state behaves like an open circuit, which
means the output appears disconnected
• Any conventional logic gate (AND, NAND, etc.) can be
constructed to tri-state the output
– Buffer or Inverter most commonly used
 4.11 Multiplexers
• Three-State Gates
– A mux can be constructed using three state gates
 4.11 Multiplexers
• Transmission Gates
– Another digital circuit that exhibits three states:
• 0, 1, and tri-state (a.k.a. high impedance)
– Single Pole, Single Throw
– Like the blue DIP switches in your kit
• The tri-state state behaves like an open circuit, which
means the output appears disconnected
• No drive capability as with Tri-State Gates
• Can also be used to make a mux (and other cells)
• Must use both PMOS and NMOS
Otherwise output drops by Vth depending on value and device
 4.12 HDL Models Of Comb. Circuits
• The logic of a module can be described in any
one or combination of the following modeling
styles:
– Gate level: Uses instantiations of predefined and
user defined primitive gates
– Dataflow: Uses continuous assignment statements
with the keywords wire/assign
– Behavioral: Uses procedural assignment
statements with the keyword always
4.12 HDL Models Of Comb. Circuits
• Gate Level Modeling
– A circuit is specified by its logic gates and
interconnects
• Four values assigned to output(s):
– Logic values: 0, 1
– Unknown: x
» Assigned when the logic value is ambiguous
• Flip-Flop prior to reset or data clocked in
• Bus contention: two or more drivers on net
– Hi-Impedance: z
» Assigned when nothing driving net
• Tri-state
• Wire inadvertently left unconnected
 4.12 HDL Models Of Comb. Circuits
/*
module ripple_carry_4_bit_adder(Sum, C4, A, B, C0); // Verilog 1995
output [3:0] Sum;
output C4;
input [3:0] A, B;
input C0;
*/
module ripple_carry_4_bit_adder (output [3:0] Sum, output C4,
input [3:0] A, B, input C0); // Verilog 2001, 2005
wire C1, C2, C3;
// Instantiate chain of full adders
full_adder FA0(Sum[0], C1, A[0], B[0], C0),
FA1(Sum[1], C2, A[1], B[1], C1),
FA2(Sum[2], C3, A[2], B[2], C2),
FA3(Sum[3], C4, A[3], B[3], C3);
endmodule
 4.12 HDL Models Of Comb. Circuits
• Three-State Gates
– High impedance is symbolized by z in Verilog
• If checking for high impedance, must use === or !==
– The gates are instantiated with the statement:
• gateName optionalUniqueName(output, input, control)

buffer when control = 1 buffer when control = 0

z when control = 0 z when control = 0

inv when control = 1 inv when control = 0

z when control = 0 z when control = 0
 4.12 HDL Models Of Comb. Circuits
// Mux with three-state output
module mux_tri(m_out, A, B, select); Verilog 1995
output m_out;
input A, B, select;
tri m_out;

bufif1(m_out, A, select);
bufif0(mout_B, select);
endmodule
 4.12 HDL Models Of Comb. Circuits
• Dataflow Modeling:
– Bitwise operators perform a bit wise operation on two operands.
• They take each bit in one operand and perform the operation with the
corresponding bit in the other operand.
• If one operand is shorter than the other, it will be extended on the left side
with zeroes to match the length of the longer operand.
– For a logical operation, a vector is tested for equality to 0. If it is, then its Boolean
value is defined as "false", otherwise "true"
• Logical operator evaluation stops as soon as result is known
• Expressions connected by && and || are evaluated from left to right
• The result is a scalar value:
– False if relation is 0
– True if relation is 1
– Unknown (x) if any of the operands has x
– If the operands are scalar, the bitwise and logical will be identical
– Be careful with bitwise versus logical operators:
~(1010) = 01010 but !(1010) = 0
– Reduction bitwise AND useful to check if value is all 1s:
&(1010) = 0, &(1111) = 1
– Reduction bitwise OR useful to check if value is all 0s:
|(1010) = 1, |(0000) = 0
 4.12 HDL Models Of Comb. Circuits
module operands();
For a logical operation, a vector is tested for equality to 0.
reg [3:0] A = 4'b1010;
If it is, then its Boolean value is defined as "false", otherwise "true"
reg [3:0] B = 4'b1111;
reg [3:0] C = 4'b0000;
reg [3:0] D = 4'b0101;
initial begin
$display("~A = %4b", ~A);
$display("!A = %4b", !A);
$display("&A = %4b", &A);
$display("A & B = %4b", A&B);
$display("A && B = %4b", A&&B);
$display("A * B = %4b", A*B);
$display("A | B = %4b", A|B);
$display("A || B = %4b", A||B);
$display("A + B = %4b", A+B);
$display("A & C = %4b", A&C);
$display("A && C = %4b", A&&C);
$display("A * C = %4b", A*C);
$display("A | C = %4b", A|C);
$display("A || C = %4b", A||C);
$display("A + C = %4b", A+C);
end
endmodule
 4.12 HDL Models Of Comb. Circuits

// Gate Level description of two-to-four decoder // Dataflow description of two-to-four decoder

module decoder_2x4_gates (D, A, B, enable); module decoder_2x4_df (

output [0:3] D; output [0:3] D,
input A, B; input A, B,
input enable; enable
);
wire A_not, B_not, enable_not;
assign D[0] = !((!A) && (!B) && (!enable)),
not D[1] = !((!A) && B && (!enable)),
G1 (A_not, A), D[2] = !(A && B && (!enable)),
G2 (B_not, B), D[3] = !(A && B && (!enable));
G3 (enable_not, enable);
nand endmodule
G1 (D[0], A_not, B_not, enable_not),
G2 (D[1], A_not, B, enable_not),
G3 (D[2], A, B_not, enable_not),
G3 (D[3], A, B, enable_not);
endmodule
4.12 HDL Models Of Comb. Circuits
module ripple_carry_4_bit_adder (
output [3:0] Sum, module binary_adder (
output C4, output [3:0] Sum,
input [3:0] A, B, output C_out,
input C0 input [3:0] A, B,
); input C0
);
wire C1, C2, C3;
// Instantiate chain of full adders assign {C_out, Sum} = A + B + C_in;
full_adder FA0(Sum[0], C1, A[0], B[0], C0), endmodule
FA1(Sum[1], C2, A[1], B[1], C1),
FA2(Sum[2], C3, A[2], B[2], C2),
FA3(Sum[3], C4, A[3], B[3], C3);
endmodule
 4.12 HDL Models Of Comb. Circuits
// Dataflow description of four-bit comparator
module mag_compare (
output A_lt_B, A_eq_B, A_gt_B,
input [3:0] A, B
);

assign A_lt_B = (A<B);

assign A_GT_B = (A > B);
assign A_eq_B = (A == B);
endmodule
 4.12 HDL Models Of Comb. Circuits
• Conditional Operator:
– The conditional operator take three operands:
• condition ? true_expression : false_expression;
• The condition is evaluated
– If the result is logic 1, the true_expression is evaluated and
used to assign a value to the left hand side of the equation
– If the result is logic 0, the false_expression is evaluated and
used to assign a value to the left hand side of the equation

// Dataflow description of Conditional operator can be used for tri-state buffer modeling.
// two-to-one multiplexer assign data_out = (enable) ? data_reg : 8'bz;
module mux_2x1_df (
output m_out,
input A, B, select
Conditional operator can be nested
); assign out = sel[1] ? (sel[0] ? In3: in2) : (sel[0] ? In1 : in0);

assign m_out = select ? A : B;

endmodule
 4.12 HDL Models Of Comb. Circuits
• Behavioral Modeling
– Behavioral descriptions use the keyword always, followed by optional
event control expression and a list of procedural assignment
statements
• The event control expression specifies when the statements will
execute
• The target output of a procedural assignment statement must of
the reg type
// Behavioral description of two-to-one multiplexer
module mux_2x1_beh (
output reg m_out,
input A, B, select
);
always @(A or B or select)
if(select)
m_out = A;
else
m_out = B;
endmodule
4.12 HDL Models Of Comb. Circuits

// Behavioral description of four-to-one multiplexer

module mux_4x1_beh (
output reg m_out,
input in_0, in_1, in_2, in_3,
input [1:0] select
);
always @(in_0, in_1, in_2, in_3, select)
case(select)
1’d0: m_out = in_0;
1’d1: m_out = in_1;
1’d2: m_out = in_2;
1’d3: m_out = in_3;
endcase
endmodule
 4.12 HDL Models Of Comb. Circuits
• Writing a Simple Test Bench:
– repeat(x)
• Repeats x times the statements to “;”
– $display”<format>”, exp1, exp2, …);
format indication:
%b %B binary
%c %C character (low 8 bits)
%d %D decimal %0d for minimum width field
%e %E E format floating point %15.7E %f
%F F format floating point %9.7F %g
%G G general format floating point
%h %H hexadecimal
%l %L library binding information
%m %M hierarchical name, no expression
%o %O octal %s %S string, 8 bits per character, 2´h00 does not print
%t %T simulation time, expression is $time
%u %U unformatted two value data 0 and 1
%v %V net signal strength
%z %Z unformatted four value data 0, 1, x, z
escape sequences, quoted characters in strings:
n newline
\t tab
\\ backslash
\" quote
\ddd octal
%% percent
 4.12 HDL Models Of Comb. Circuits
$write // same as $display except no automatic insertion of newline
$strobe // same as $display except waits until all events finished
$monitor // same as $display except only displays if an expression changes
$monitoron // only one $monitor may be active at ant time,
$monitoroff // turn current $monitor off
$displayb // same as $display using binary as default format
$writeb // same as $write using binary as default format
$strobeb // same as $strobe using binary as default format
$monitorb // same as $monitor using binary as default format
$displayo // same as $display using octal as default format
$writeo // same as $write using octal as default format
$strobeo // same as $strobe using octal as default format
$monitoro // same as $monitor using octal as default format
$displayh // same as $display using hexadecimal as default format
$writeh // same as $write using hexadecimal as default format
$strobeh // same as $strobe using hexadecimal as default format
$monitorh // same as $monitor using hexadecimal as default format
 Homework
• Ten points each
– 4.33
– 4.38
– 4.40
– 4.41
– 4.44
– 4.56