Computer Organization & Design, CNE211_ 2018 Tutorial 2 Dr.

Jamel Baili

Question1: Assume the execution of the following three consecutive instructions on a CPU:
Load [520]
ADD [521]
Store [521]
If the load instruction is in memory location [400], fill each of the Program Counter (PC), Memory,
Accumulator (AC), and Instruction Register (IR) in each step.

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 Computer Organization & Design, CNE211_ 2018 Tutorial 2 Dr. Jamel Baili

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Question 2:
Consider the execution of a program which results in the execution of 2 million instructions on a 400MHz
processor. The program consists of four major types of instructions. The instruction mix and the CPI for each
instruction type are given below based on the result of a program trace experiment:
Instruction Type CPI Instruction
Arithmetic and logic 1 60%
Load/store with cache hit 2 18%
Branch 4 12%
Memory reference with cache 8 10%

What is the MIPS rate on this processor?

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 Computer Organization & Design, CNE211_ 2018 Tutorial 2 Dr. Jamel Baili

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Question3:
A benchmark program is run on a 40 MHz processor. The executed program consists of 100,000 instruction
executions, with the following instruction mix and clock cycle count:
Instruction Type Instruction Count Cycles per Instruction
Integer 45000 1
Data transfer 32000 2
Floating point 15000 2
Control transfer 8000 2
Determine the effective CPI, MIPS rate, and execution time for this program.
Ans.

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Question 4:
Consider two different machines, with two different instruction sets, both of which have a clock rate of 200
MHz. The following measurements are recorded on the two machines running a given set of benchmark
programs:
Instruction Count
Instruction Type (millions) Cycles per Instruction
Machine A
Arithmetic and logic 4 1
Load and store 8 3
Branch 2 4
Others 4 3
Machine B
Arithmetic and logic 10 1
Load and store 8 3
Branch 2 4
Others 4 3
a) Determine the effective CPI, MIPS rate, and execution time for each machine.
b) Comment on the results.
Ans. (a)

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 Computer Organization & Design, CNE211_ 2018 Tutorial 2 Dr. Jamel Baili

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(b) Although machine B has a higher MIPS than machine A, it requires a longer CPU time to execute the
same set of benchmark programs. (Different instruction count and instruction sets).

Question 5:
Consider the execution of a program which results in the execution of 2 million instructions on a 400-MHz
processor. The program consists of four major types of instructions. The instruction mix and the CPI for each
instruction type are given below based on the result of a program trace experiment:
Instruction Type CPI Instruction Mix

Arithmetic and logic 1 50%

Load/store with cache hit 5 20%
Branch 3 10%
Memory reference with cache miss 2 20%
a) What is the MIPS rate on this processor?
b) If a CPU design enhancement improves the CPI of (Load/store with cache hit instructions) from 5 to
2, what is the resulting performance improvement from this enhancement (speedup)?
Ans.
Before improvement:
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After improvement:

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 Computer Organization & Design, CNE211_ 2018 Tutorial 2 Dr. Jamel Baili

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Question 6:
Computer A has an overall CPI of 1.5 and can be run at a clock rate of 800MHz. Computer B has a CPI of 3
and can be run at a clock rate of 900 Mhz. We have a particular program we wish to run. When compiled for
computer A, this program has exactly 150,000 instructions.
a) How many instructions would the program need to have when compiled for Computer B, in order for the
two computers to have exactly the same execution time for this program?
b) If a CPU design enhancement improves the CPI of Computer A so that the speed up is 1.5, what is the new
CPI?
c) If a CPU design enhancement improves the CPI of Computer B to be 2.5, what is the speed up?

Answer Key

a) (CPUTime)A = (Instruction count)A * (CPI)A * (Clock cycle Time)A

= (150,000)*(1.5)/(800*106)
(CPUTime)B = (Instruction count)B * (CPI)B * (Clock cycle Time)B
= (Instruction count)B*(3)/(900*106)
Since (CPUTime)A = (CPUTime)B,

-We have to solve for (Instruction count)B and get 84375

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