IKI10230

Pengantar Organisasi Komputer

Bab 7: Control Unit
Sumber:
1. Hamacher. Computer Organization, ed-5.
2. Materi kuliah CS152/1997, UCB.

28 Mei 2003
Bobby Nazief (nazief@cs.ui.ac.id)
Qonita Shahab (niet@cs.ui.ac.id)

bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/

1
Pengendalian Eksekusi Instruksi:
Hardwired Control

2
Prosesor: Control & Datapath

Computer
Processor Memory Devices
(active) (passive)
Control Input
(“brain”) (where
programs,
data
Datapath live when
(“brawn”) Output
running)

3
Review: Organisasi Prosesor (Single-bus)
Control lines

Instruction
PC Control
Decoder
Address Unit
lines
MAR IR
Memory
bus Data
lines
MDR R0

R(n-1) Datapath
Add Unit
ALU Sub
control
lines
ALU
XOR
Carry-in

Z TEMP

4
Interaksi Control ↔ Datapath

Instruction
IR Control

Conditions
MARin ADD
Control
PCout Riin Signals

Datapath

STEP CONTROL SIGNALS

1. PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
2. Zout, PCin, WMFC
3. MDRout, IRin
4. R3out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, Add, Zin
7. Zout, R1in, End
5
Organisasi Unit Pengendali

CLK Control Step

Clock
Counter

• • •

Status

•••
Flags
Decoder/
• • •

IR
Encoder
Condition

•••
Codes

• • •

Control Signals

6
Pemisahan Decoder & Encoder

Clock CLK Control Step Reset

Counter
• • •

Step Decoder

T1 T2 • • • Tn

LDI Status

•••
LD Flags

Instruction
• • •

IR • • • Encoder
Decoder
Condition

•••
INSn Codes

Run • • •
End

Control Signals

7
Contoh Struktur Encoder untuk sinyal Zin

ADD BR ° Fungsi Logika:

T6 T5 Zin = T1 + T6 • ADD + T5 • BR + …

° Zin akan terjadi pada:

T1 • T1: untuk setiap instruksi
• • • • (instruksi berikut: PC+1)
• T5: untuk instruksi ADD
• T6: untuk instruksi BR

Zin

8
Interaksi Memori ↔ [Control,Datapath]

Ideal Control
Instruction Control Signals Conditions
Instruction
Memory
Rd Rs Rt
5 5 5
Instruction
Address
A Data
32 Data
Next Address

Rw Ra Rb Address
32 32 Ideal Out

ALU
PC

Registers Data
B Data In Memory

Clk Clk
32
Clk

Datapath

9
Pengendalian Eksekusi Instruksi:
Microprogrammed Control

10
 Microprogramming
° Control is the hard part of processor design
°Datapath is fairly regular and well-organized
°Memory is highly regular
°Control is irregular and global

Microprogramming:
-- A Particular Strategy for Implementing the Control Unit of a
processor by "programming" at the level of register transfer
operations

Microarchitecture:
-- Logical structure and functional capabilities of the hardware as
seen by the microprogrammer

Historical Note:
IBM 360 Series first to distinguish between architecture & organization
Same instruction set across wide range of implementations, each with
different cost/performance
11
Microinstructions
STEP CONTROL SIGNALS
1. PCout, MARin, Read, Clear Y, Carry-in to ALU, Add, Zin
2. Zout, PCin, WMFC
3. MDRout, IRin
4. R3out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, Add, Zin
7. Zout, R1in, End

Carry-in
in
MDRout

Clear Y

WMFC
MARin
PCout

Read
R1out

R3out
PCin

Add
R1in

End
IRin

Zout
Yin

Zin
1 0 0 1 1 0 0 0 0 0 1 0 1 1 1 1 0 0
2 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0
3 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
4 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0
5 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0
6 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0
7 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1

12
 Organisasi Microprogrammed Control Unit

Starting
IR Address
Generator

Clock µPC
MDRout
MARin
PCout

R1out

R3out
PCin

R1in
IRin

Yin

1 0 0 1 1 0 0 0 0 0 1 0 1 1 1 1 0 0
Control
2 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0Store
1 0 Control
3 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Word
4 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0
5 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0
6 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0
7 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1
13
 Organisasi µProgrammed Control Unit: Branching

Status Flags
Starting
IR Address Condition Codes
Generator

Clock µPC
Addr. Microinstruction
0 PCout, MARin, Read, Clear Y, Carry-in to ALU, Add, Zin
1 Zout, PCin, WMFC
2 MDRout, IRin Control
3 Branch to starting addr. of appropriate µroutine Store Control
……………………………………………………………………………. Word
25 PCout, Yin, if N=0 then branch to µinstruction 0
26 Offset-field-of-IRout, Add, Zin
27 Zout, R1in, End

14
Encoding of Microinstruction

F1 F2 F3 F4
(4 bits) (3 bits) (3 bits) (4 bits)
0000: No transfer 000: No transfer 000: No transfer 0000: ADD
0001: PCout 001: PCin 001: MARin 0001: SUB
0010: MDRout 010: IRin 010: MDRin .
0011: Zout 011: Zin 011: TEMPin .
0100: R0out 100: R0in 100: Yin .
0101: R1out 101: R1in 1111: XOR

° Most signals are not needed simultaneously

° Many are mutually exclusive:
• ALU: 1 function at a time
• Data source is unique

° Organization:
• Vertical Organization (Highly Encoded µInstruction)
• Horizontal Organization (otherwise)
15
Microprogram Sequencing: Branching Implementation

° 1 Machine Instruction
1 Set of µInstructions

• large total number of µInstruction
• large Control Store

° Many Addressing Modes
many instruction

combinations
• results in many duplications of common parts

° If the common parts are to be shared
many

branches
• results in longer execution time

Need efficient branching techniqe
Bit-ORing

16
 Microprogram Sequencing (1/2): Add src,Rdst
000
MAR  [PC]; Read; Z  [PC]+1 Start

001
PC  [Z]; WMFC

002
IR  [MDR]

003
Branch[InstDec,OR]

Indexed Autodecrement Autoincrement Register indirect

161 141 121 111
MAR  [PC]; Read; Z  [Rsrc] - 4 MAR  [PC]; Read; MAR  [Rsrc];
Z  [PC]+1 Z  [PC]+1 Read

162 142 122 112

PC  [Z]; WMFC MAR, Rsrc  [Z]; Z  [Rsrc] Branch[171]; WMFC
Read

17
 Microprogram Sequencing (2/2): Add src,Rdst
Indexed Autodecrement Autoincrement Register indirect
166 143 123 112
Branch[170,OR]; Branch[170,OR]; Branch[170,OR]; Branch[171];
WMFC WMFC WMFC WMFC

170
MAR  [MDR]; Read; WMFC

171
Y  [MDR]

172
Z  [Y] + [Rdst]
173
Rdst  [Z] End

18
 Branching in Microinstruction: Add (Rsrc)+,Rdst
Mode

OP code 0 1 0 Rsrc Rdst

11 10 8 7 4 3 0
Addr. Microinstruction
000 PCout, MARin, Read, Clear Y, Set carry-in, Add, Zin
001 Zout, PCin, WMFC
IR10,9 = 01 (autoincrement)
002 MDRout, IRin
003 µBranch {µPC ← 101; µPC5,4 ← [IR10,9]; µPC3 ← [IR10].[IR9].[IR8]}

ADD 121 Rsrcout, MARin, Read, Clear Y, Set carry-in, Add, Zin
122 Zout, Rsrcin
IR8 = 0 (direct)
123 µBranch {µPC ← 170; µPC0 ← [IR8]}, WMFC

170 MDRout, MARin, Read, WMFC

Bit
171 MDRout, Yin
ORing
172 Rdstout, Add, Zin
173 Zout, Rdstin, End 19
Microinstruction Sequencing: Organization
IR

Status Flags Condition Codes

Decoding Circuits

µAR

Control
Store

Next Address µIR

µInstruction Decoder
• • •
20
Control Signals
Encoding of Microinstruction w/ Next Address

F0 F1 F2 F3
(8 bits) (3 bits) (3 bits) (3 bits)
Address of next 000: No transfer 000: No transfer 000: No transfer
microinstruction 001: PCout 001: PCin 001: MARin
010: MDRout 010: IRin 010: MDRin
011: Zout 011: Zin 011: TEMPin
100: Rsrcout 100: Rsrcin 100: Yin
101: Rdstout 101: Rdstin

F4 ... F8 F9 F10
(4 bits) (1 bit) (1 bit) (1 bit)
0000: ADD 0: NextAdrs 0: No 0: No
action action
0001: SUB 1: InstDec
1: ORmode 1: ORindsrc
.
.
1111: XOR
21
 Content of µStore

F0 F1 F2 F3 F4 F5 F F F F F
6 7 8 9 1
0
000 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0
001 0 0 2 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0
002 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
003 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
121 1 2 2 1 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0
122 1 7 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
170 1 7 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0
171 1 7 2 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
172 1 7 3 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
173 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

22
/Etc

23
“Macroinstruction” Interpretation

User program
Main ADD plus Data
Memory SUB
AND this can change!
.
.
.
DATA one of these is
mapped into one
of these
execution
unit

CPU control AND microsequence

memory
e.g., Fetch
Calc Operand Addr
Fetch Operand(s)
Calculate
Save Answer(s)

24
 Control: Hardware vs. Microprogrammed

° Control may be designed using one of several initial representations.

The choice of sequence control, and how logic is represented, can then
be determined independently; the control can then be implemented with
one of several methods using a structured logic technique.

Initial Representation Finite State Diagram Microprogram

Sequencing Control Explicit Next State Microprogram counter

Function + Dispatch ROMs

Logic Representation Logic Equations Truth Tables

Implementation Technique PLA ROM

“hardwired control” “microprogrammed control”

25