TITLE : LAYOUT DESIGN

1.0 OBJECTIVES
1. To familiar with VLSI design software.
2. To design the layout of the basic CMOS logic circuit.
3. To simulate the functionality of the layout designed.
4. To work effectively in given task in group.

2.0 EQUIPMENT
1. Personal Computer / desktop
2. Microwind 3.1

3.0 RESULT
PART A: INVERTER

Figure 1: CMOS Inverter Layout Design

Figure 2: 2D view
 Figure 3: Voltage vs Time Simulation Graph
PART B: NOR GATE

Figure 4: Nor Automatic Layout

Figure 5: Nor Automatic Layout Timing Diagram

 Figure 6: Stick Diagram For NOR

Figure 7: NOR Manually layout

Figure 8: NOR Manually Layout Timing Diagram

PART C: COMPOUND GATE

Figure 9: Stick Diagram Of Compound

Figure 10: Compound Gate Layout

Figure 11: Compound Layout Timing Diagram

4.0 DISCUSSION
During VLSI design and fabrication lab session, the student learnt about layout design. In
part A, is to design the inverter gate. It was created by using the Microwind software. Microwind
is an integrated circuit layout tool used to draw the layout design of the masks or layers to
fabricate an integrated circuit. In this tool, different layers are represented by
a different colors and patterns. In drawing the layout, the students must follow the manufacturing
constraints, that can be defined in the design rules. The first rule that must be followed is the
length of the transistors must equal to 0.035um λ. Hence at first, the students do need to define
the value of the lamda, λ in micrometer. In drawing, one must draw the layout layer by layer. In
this inverter design, the length of the NMOS and PMOS is 0.07 µm while its width are 0.35 µm.
First, draw the PMOS transistor layout and the dimension of the transistor is 0.07 μm for length
and 0.35 μm for width. After that, the NMOS transistor layout is draw at the bottom of the
PMOS using the same dimension like PMOS. After that, selecting polysilicon from the palette,
draw the polysilicon layer exactly at the center of the diffusion. Poly should be vertical. Next,
select the N-well from the palette and draw the N-well arbitrarily. To make sure that we are
following the design rules, the students click on DRC. We can directly click on the N-well and
stretch it to a next level. The students can also perform the DRC again to see if everything is fine
before proceeding to the next step. One strange behavior of DRC is that, at the first click it points
to the error, but even if the error is not corrected, the error message goes off. To recheck, we
need to click again. One good thing about it is that, it also shows the scale. So that we can stretch
or resize accordingly. Next, select metal layer from the palette. Join the Source and Drain. Select
appropriate contact from the palette and click on the metal diffusion interface. From the palette,
the students select Vdd. Click on N-well. Again from click on Vdd and then on the source of
PMOS. Add a contact where the students had added Vdd. Apply Vss to the source of the NMOS
in the same way. The students apply the input to the inverter by selecting the clock from the
palette and click on the poly connecting both PMOS and NMOS. The students were able to see
the output. For the present layout, the output will be available at the metal which joining drain
and source of the devices. Click on the Visible Node and then click on the metal. Last but not
least, we can simulate the design and observe the output after designing the layout.
In part B, the stuednts using nor.sch file that has been designed in lab 1 using DSCH to
make verilog file. Verilog file is a standardized as IEEE 1364, is a hardware description
language (HDL) used to model electronic systems. it sometime used in verification of analog
circuits and mixed-signal circuit, but in this case the stuents using to covert stick diagram to
design layout. Using automatic layout generation procedure, the verilog file is compile using
microwind3.1. Specific size for pmos and nmos is need for better outcome 0.07 μm for length
and 0.35 μm for width. Do correction if the design rule checker DRC is detecting and error on
the design. Run the simulation after setting the clock period for both ouput and input. Noticed the
design layout is not very efficient because of the software not very compatible between DSCH
and Microwind3.1. After that, design the stick diagram for NOR circuit manually. This time
design layout manully for NOR by using MOS generator. By using MOS generator, most of the
time by designing pmos and nmos is cut because we only need simple drag from MOS generator
to design pmos and nmos. Run the simulation after doing correction if the design rule checker
DRC is detecting and error on the design. Noticed the timing diagram is same for both manual
design and automatically design.
In part C, the stick diagram of the compound gate designed in Lab 2 was drawn for
this experiment. After that, the new file was created then the layout for the compound gate
has been design by using MOS Generator. Next, the DRC was run and any violations seen
also was clean. As we can see the stick diagram of part c, stick diagrams are mean of
capturing topography and layer information using simple diagram. Stick diagrams are easy
to draw because it convey layer information through colour codes or monochrome
encoding plus no need to be drawn in an actual scale. Based on the simulation result as
shown as figure above, the graph of the output simulation was shown at the result. From
the observation of the simulation result, there are have the same value as the truth table of
compound gates. The result shows that all the digital signal follow by the truth table. The
compound gates there are two operations that have the same logic as AND or OR gates,
but with an inverted output. The NAND operation says if and only if all inputs are on, the
output will be off. The output will be on if any of the inputs are off. The NOR operation
says if any input is on, the output will be off. Notice the bubble on the output of the
schematic symbol used to indicate an inversion. The important characteristic of a CMOS
circuit is the duality that exists between its PMOS transistors and NMOS transistors. A
CMOS circuit is created to allow a path always to exist from the output to either the power
source or ground. To accomplish this, the set of all paths to the voltage source must be
the complement of the set of all paths to ground. This can be easily accomplished by
defining one in terms of the NOT of the other. Due to the De Morgan's laws based logic,
the PMOS transistors in parallel have corresponding NMOS transistors in series while the
PMOS transistors in series have corresponding NMOS transistors in parallel.
5.0 CONCLUSION
Throughout this lab session, the students have learnt how to draw the layout design for a
given specification of a CMOS inverter using the Microwind software and comes out with
Voltage Transfer Characteristic graphs which are voltage vs time simulation graph and voltage
vs voltage simulation graph. From this graphs, the students have determined and analyzed the
transfer characteristics of the inverter. In addition, the students also gain some knowledge and
skills in drawing the basic layout of the CMOS inverter, NOR gate and compound gate using the
Microwind software. As the students faced some errors while drawing the layout, the students
learnt about the design rules. Next, the students also simulate the functionality of the layout
designed. Lastly, our objectives in this lab session were achieved successfully.