Philadelphia University Student Name:

Student Number:
Faculty of Engineering Serial Number:

Final Exam, Second Semester: 2015/2016

Dept. of Computer Engineering
Course Title: Logic Circuits Date: 08/06/2016
Course No: 630211 Time Allowed: 2 hours
Dr. Ali Khawaldeh
Lecturer: No. Of Pages: 7
Dr. Qadri Hamarsheh

Instructions:
 ALLOWED: pens and drawing tools (no red colour).
 NOT ALLOWED: Papers, literatures and any handouts. Otherwise, it will lead to the non-approval of your examination.
 Shut down Telephones, and other communication devices.
Please note:
 This exam paper contains 5 questions totaling 40 marks
 Write your name and your matriculation number on every page of the solution sheets.
 All solutions together with solution methods (explanatory statement) must be inserted in the labelled position on the solution
sheets.
 You can submit your exam after the first hour.
Basic notions: The aims of the questions in this part are to evaluate the required minimal student knowledge and skills. Answers in the
pass category represent the minimum understanding of basic concepts: Digital Systems, Binary Number Systems, Boolean Algebra,
Basic Logic Gates, Boolean Expression Simplification, Karnaugh Maps, Combinational and Sequential Circuits.

Question 1 Multiple Choice (13 marks)

Identify the choice that best completes the statement or answers the question.
1) Convert hexadecimal C0B to binary.
a) 110000001100 b) 110100001011
c) 110000001001 d) 110000001011
2) Using Boolean algebra theorem gives 𝐱(𝐱 + 𝐲) equal to
a) 𝐱̅ b) 1
c) 0 d) 𝐱
3) Refer to the following figure, If S1=1 and S2= 0 what will be the logic state at the output X?

a) X=A b) X=B
c) X=C d) X=D
4) The minterms in a karnaugh map are marked with a
a) y b) x
c) 0 d) 1
5) A 6x64 line decoder can be built using:
a) six 2x4 line decoders only b) nine 2x4 line decoders only
c) seven 3x8 line decoders only d) nine 3x8 line decoders only

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6) Decoder with enable input can be used as:
a) XOR b) Demultiplexer
c) Multiplexer d) Encoder
7) The Boolean function realized by the logic circuit shown is

a) 𝐅 = Ʃ𝐦 (𝟎, 𝟏, 𝟑, 𝟓, 𝟗, 𝟏𝟎. 𝟏𝟒) b) 𝐅 = Ʃ𝐦 (𝟐, 𝟑, 𝟓, 𝟕, 𝟖, 𝟏𝟐. 𝟏𝟑)

c) 𝐅 = Ʃ𝐦 (𝟏, 𝟐, 𝟒, 𝟓, 𝟏𝟏, 𝟏𝟒. 𝟏𝟓) d) 𝐅 = Ʃ𝐦 (𝟐, 𝟑, 𝟓, 𝟕, 𝟖, 𝟗. 𝟏𝟐)
8) A sequential circuit with two JK flip-flops A and B, and one input X is specified by the following input
equations:
𝑱𝑨 = 𝑩 𝑿′ 𝑲𝑨 = 𝑨′ 𝑿′
𝑱𝑩 = 𝑨′𝑿′ KB = B X' + A' X
What are the next states of the flip-flops A and B if the present state of the flip-flops A, B and the input X
equals, 001, 101 respectively:
a) 01, 10 b) 00, 10
c) 01, 01 d) 01, 11
9) What is the function of the following circuit?

a) A four-bit memory register b) A four-bit synchronous counter

c) A four-bit shift register d) None of the above
10) In a synchronous counter, each state is clocked by the same pulse.
a) True b) False
11) Fastest operating shift register is:
a) Serial In - Serial Out
b) Serial In - Parallel Out
c) Parallel In - Serial Out
d) Parallel In - Parallel Out
12) Two 4-bit shift registers A and B with serial input (SI) and serial output (SO), the initial content of
register A and B, 1100, 1110 respectively. The SO of register A is connected to the SI of register B. The
register A shifted eight times with the serial input being 10111101. What are the content of the register A
and B after the fifth shift (T5)?
a) 1110, 0111 respectively b) 1011, 1101 respectively
c) 1110, 1110 respectively d) 1001, 1110 respectively
13) Number of clock pulses, which 5-bit ring counter needs to reach 00010 state are (initial state of the
counter 10000):
a) 3 b) 5
c) 7 d) 9

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Familiar and Unfamiliar Problems Solving: The aim of the questions in this part is to evaluate that the student has some basic
knowledge of the key aspects of the lecture material and can attempt to solve familiar and unfamiliar problems of Combinational and
Sequential Circuits and Analysis of Sequential Circuits.

Question 2 (9 marks)
a) Implement the following Boolean expression with exclusive-OR and AND gates only. (2 marks)
𝐅 = 𝐀𝐁′𝐂𝐃′ + 𝐀′𝐁𝐂𝐃′ + 𝐀𝐁′𝐂′𝐃 + 𝐀′𝐁𝐂′𝐃

Solution

b) Simplify the following expression into sum of products using Karnaugh map (2 marks)
𝐘(𝐀, 𝐁, 𝐂, 𝐃) = 𝚺𝐦(𝟎, 𝟑, 𝟒, 𝟕, 𝟖) + 𝐝(𝟏𝟎, 𝟏𝟏, 𝟏𝟐, 𝟏𝟑, 𝟏𝟒, 𝟏𝟓)

Solution

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c) Show the Truth Table for the Following function:- (2 marks)

Solution

d) Implement half adder circuit using 4:1 multiplexers only. (3 marks)

Solution

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Question 3 (5 marks)
̅
a) Draw the waveforms at outputs 𝑸 and 𝑸 for the following logic circuit, assume the initial value of 𝑸 is
logic 1: (2 marks)

CLK

time
b) Draw Three-bit asynchronous binary counter using JK flip flops and its timing diagram for one cycle.
(3 marks)
Solution

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Question 4 (6 marks)
For the following D-Flip flops input equations:
𝑫𝑨 (𝑨, 𝑩, 𝑪, 𝑿) = ∑ 𝒎(𝟓, 𝟕, 𝟖, 𝟗, 𝟏𝟏)

𝑫𝑩 (𝑨, 𝑩, 𝑪, 𝑿) = ∑ 𝒎(𝟑, 𝟒)

𝑫𝑪 (𝑨, 𝑩, 𝑪, 𝑿) = ∑ 𝒎(𝟐, 𝟒, 𝟔, 𝟖, 𝟏𝟎)

a) Derive the state table. (1 mark)
b) Derive the state diagram of the circuit. (2 marks)
c) Find the simplified three input equations for the D-Flip flops. (3 marks)
Assume the unused states as don’t care conditions (unused states for the circuit are 0, 1, 12, 13, 14
and 15).

Solution

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Question 5 (7 marks)
Design an up-down binary counter which counts up or down from 0-3:
Use clocked RS flip-flops.
Hint:
 When the control line value is equal to 1: the counter counts up.
 When the control line value 0: the counter counts down.
Solution

GOOD LUCK
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