1098 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO.

4, APRIL 2015

Back-Gate Effect on R ON,sp and BV for Thin

Layer SOI Field p-Channel LDMOS
Xin Zhou, Student Member, IEEE, Ming Qiao, Member, IEEE, Yitao He, Zhuo Wang, Member, IEEE,
Zhaoji Li, and Bo Zhang, Member, IEEE

Abstract— The Backgate (BG) effect on specific ON-resistance

(RON,sp ) and breakdown voltage (BV) for the thin layer
Silicon On Insulator (SOI) field p-channel lateral diffusion
MOS (pLDMOS) are investigated in this paper. BG-induced
dual conduction mode for the thin layer SOI field pLDMOS
is revealed, which includes drift and accumulation conduction.
Hole accumulation layer induced by BG voltage (VBG ) provides
extra charges, resulting in a RON,sp reduction. An expression
of equivalent RON,sp is given to describe the dependence of
RON,sp on VBG . Simultaneously, VBG impacts strongly on BV,
inducing three breakdown mechanisms: surface breakdown,
bulk breakdown, and punchthrough breakdown. For surface
breakdown, a positive linear dependence of BVs on VBG
is given with consideration to multiple field plates (MFP).
BV of −366 V and RON,sp of 7.5  · mm2 for the thin layer SOI
field pLDMOS are achieved experimentally at VBG = −200 V.
Index Terms— Back-gate (BG) effect, breakdown mechanism,
dual conduction (DC) mode, specific ON-resistance (RON,sp ), thin
layer SOI field p-channel lateral diffusion MOS (pLDMOS).
I. I NTRODUCTION

S OI lateral diffusion MOS (LDMOS) transistor provides

fast switching time and ease of integration with CMOS
technology, used widely in motor driver, power supplies, and
automotive sector [1]–[5]. To simplify circuit design,
Silicon On Insulator (SOI) field p-channel LDMOS (pLD-
MOS) replaces the high side n-channel LDMOS and its
inherent complex driver circuit [6]–[9]. As operating at high
side, SOI field pLDMOS suffers from the potential differ-
ence between the source and back-gate (BG), which impacts
strongly upon performance of SOI field pLDMOS. Thin layer
SOI structure provides low parasitic effect and good process
compatibility [10]–[12]. However, thin layer SOI field pLD-
MOS is subjected to more severe BG effect due to the SOI
layer thinned further by thick field oxide. BG effect for thick
layer SOI LDMOS has been investigated in [13]–[16], but little
care is devoted to the thin layer SOI field pLDMOS, which
suffers from more severe and complex BG effect. In addition,
Manuscript received August 4, 2014; revised January 14, 2015; accepted
January 30, 2015. Date of publication February 17, 2015; date of current
version March 20, 2015. This work was supported in part by the Fundamental
Research Funds for the Central Universities under Project ZYGX2013J030
and in part by the National Natural Science Foundation of China under Project
61376080. The review of this paper was arranged by Editor H. S. Momose.
The authors are with the State Key Laboratory of Electronic Thin Films and
Integrated Devices, University of Electronic Science and Technology of China,
Chengdu 610051, China (e-mail: xinzhou7788@gmail.com; qiaoming@
uestc.edu.cn; yitaohe@126.com; zwang@uestc.edu.cn; zjli@uestc.edu.cn;
zhangbo@uestc.edu.cn).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2015.2399504
0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Fig. 1. (a) Schematic cross-sectional view of high side thin layer
SOI field pLDMOS with MFP technology. A–C represent three breakdown
mechanisms. (b) Schematic of DC mode at ON-state. Due to accumulation
layer induced by VBG , DC paths in parallel are formed in p-drift.
those studies force primarily on the effect of BG voltage (VBG )
on behavior of BV with little concern to specific ON-resistance
(RON,sp ), which is affected severely as well.
In this paper, BG effect on RON,sp and BV for thin layer
SOI field pLDMOS are investigated by modeling, simulating,
and verified experimentally. BG-induced dual conduction (DC)
mode is disclosed in Section II. BG effect on RON,sp is
analyzed in Section III. To describe the dependence of RON,sp
on VBG , an expression of equivalent RON,sp is given. BG
effect on breakdown mechanism is investigated in Section IV.
The surface breakdown is discussed in detail by giving a
dependence of surface breakdown voltage (BVs) on VBG
which considers multiple field plates (MFPs).
II. S TRUCTURE AND DC M ODE
The high side thin layer SOI field pLDMOS is proposed
in [9], as shown in Fig. 1(a). The thickness of SOI
and Buried OXide (BOX) layers are 1.5 and 3 μm,
respectively. Actually, the effective thickness of p-drift region
ZHOU et al.: BG EFFECT ON RON,sp AND BV FOR THIN LAYER SOI FIELD pLDMOS 1099

(ts ) is thinned to about 1.2 μm by thick field oxide.

Due to REduced SURface Field (RESURF) action inhib-
ited, a very low doping of p-drift region is required to
achieve full depletion [5]. In this paper, p-drift region
adopts 15–25- · cm p-type material without any additional
impurity doping. MFP constructed by polysilicon and metal
layers are adopted to modulate electric field distribution of
the depleted drift region. A–C represent the surface, bulk, and
punchthrough breakdowns, respectively.
Fig. 1(b) shows the schematic of DC mode at ON-state.
Due to VBG , a hole accumulation layer is formed at the
bottom of p-drift region, which provides a low ON-resistance
conduction path. Thus, DC mode including drift and accu-
mulation conduction in parallel is present, which benefits to
a RON,sp reduction. The ON-resistance of p-drift region is
equivalent to the accumulation layer resistance (Racc ) and
drift doping resistance (Rdd ) in parallel. However, the benefit
from accumulation conduction is weakened or even minimized
expectedly for thick SOI layer, because fewer holes from
channel can sink to the accumulation layer compared with
that in thin SOI layer.
To investigate the BG effect on behaviors of the thin layer
SOI field pLDMOS, BG is biased negative voltage relative
to the source shorted to the ground in analytic, measure,
and simulation RON,sp is calculated at Vd = −0.1 V and
Vg = −200 V with consideration to only resistance of p-drift
region in the simulation. Shockley–Read–Hall recombination
with concentration-dependent model, mobility model using the
parallel electric field component, mobility model using the
concentration component, mobility model using the surface
scattering component, and impact ionization model are spec-
ified in the simulation. In the measure, a big device with the Fig. 2. (a) Analytical and simulated hole concentration distribution along
channel width of 800 μm is chosen. cut line AA . Inset: Dacc as a function of VBG . (b) Simulated hole current
distribution along cut line AA . N D = 4e14 cm −3 . Vg = −200 V and
Vd = −0.1 V.
III. BG E FFECT ON RON,sp
Drift region resistance is the main contributor to the total
reaches 2 × 1018 cm−3 four orders of magnitude higher than
ON -resistance because of its low doping concentration and
that in the bulk. As a result, a low ON-resistance conduction
great length. For thin layer SOI field pLDMOS, VBG redistrib-
path is formed at the bottom of p-drift region. The inset shows
utes carriers in p-drift region, giving rise to hole accumulation
the analytical and simulated dose of accumulation layer (Dacc )
layer at the bottom. In Appendix A, the hole concentration
as a function of VBG . Dacc can be obtained with integral
Nacc (d) within the accumulation layer on VBG is obtained as
of Nacc from d = 0 to wacc . Expectedly, Dacc increases
follows:
√ with VBG increasing. When VBG = −169 V, Dacc increases
Nacc = N D sec2 {[arctan(VBG · ϕ)]−d/ 2L D }, 0 < d < wacc up to 1.3 × 1012 cm−2 which is RESURF condition [16].
(1) That implies a low RON,sp can be achieved for the thin
layer SOI field pLDMOS despite of low N D , because the
where d is √ the distance to the SOI/BOX interface. accumulation layer provides extra charges.
ϕ = −εox / 2q N D L D tox , in which tox is the thickness of Fig. 2(b) shows the simulated hole current density
BOX layer, and εox is the dielectric constant of silicon dioxide. distribution along cut line AA . The hole current density has
L D is the Debye length equal to (εs kT /q 2 N D )1/2 . k and a similar distribution with the hole concentration for differ-
T are the Boltzmann constant and absolute temperature, ent VBG . As VBG increases, the current density at the bottom
respectively. wacc is the accumulation layer width. increases. When VBG = −300 V, the maximum current density
Fig. 2(a) shows the analytical and simulated hole is 930 A/cm3 nearly 1000 times that while VBG = 0 V. Despite
concentration distribution along cut line AA . For VBG = 0 V, of the similar current density distribution beyond d = 0.6 μm,
holes distributes uniformly in p-drift region. As VBG increases, the higher current density at the bottom for VBG < 0 V is in
holes rapidly crowd near the SOI/BOX interface, inducing a favor of a low RON,sp compared with that for VBG = 0.
high density hole accumulation layer. The simulation results DC mode consisting of two parallel conduction paths is
show that the interface hole concentration for VBG = −300 V present, as shown in Fig. 2(b). The allocation of current
1100 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 4, APRIL 2015

Fig. 3. Analytical and simulated RON ,sp as a function of VBG for Fig. 4. Analytical and simulated RON ,sp as a function of VBG for different ts .
different N D . ts = 1.2 μm. Inset: hole current density for ts = 5 μm at VBG = −0 and −300 V. The
current density close to the interface is one-tenth of that for ts = 1.2 μm at
VBG = −300 V. N D = 4 × 1014 cm −3 .
density is determined by ON-resistance in each conduction
path. As shown in Fig. 1(b), ON-resistance of p-drift region
is equivalent to Rdd and Racc in parallel, which are given as
follows:
L d − L ov
Rdd = (2)
qμdd N D ts Z
(L d − L ov )tox
Racc = − (3)
μacc εox Z VBG
where L d and L ov represent the length of p-drift
region and polysilicon overlay p-drift region, respectively.
μdd and μacc are the hole mobility in drift doping region
and accumulation layer. Z is the channel width per square
centimeter. Here, wacc is too small to be minimized, thus, ts is
adopted instead of ts -wacc in (2).
In this paper, L d and L ov are 28 and 5 μm. μdd and μacc are
assigned as 480 and 330 cm2 /(V · s) [17]. Z is 1 cm/cm2 . Fig. 5. Measured RON ,sp and saturated drain current Idsat as a function
Hence, RON,sp for the thin layer SOI field pLDMOS is given of VBG .
by (4), in which only drift region resistance is calculated.
The accumulation layer resistance under the polysilicon
in p-drift region is minimized as well. In (4), the first and of Rdd . Therefore, when VBG is higher than −200 V,
second terms of denominator represent 1/Rdd and 1/Racc , RON,sp varies slightly with different N D . The saturation of
respectively. The presence of the second term introduced by RON,sp for high VBG can be ascribed to Q acc saturation.
accumulation conduction contributes to a lower RON,sp with Fig. 4 shows the analytical and simulation RON,sp as a
the same dose of p-drift region function of VBG for different ts . Similarly, RON,sp sharply falls,
and then becomes saturation with VBG increasing. However,
1
RON,sp = . (4) an anomalous behavior of RON,sp for different ts is observed
1.45 × 10−13 ts N D − 7.07 × 10−4 VBG in simulation that RON,sp increases with ts increasing for high
Fig. 3 shows the analytical and simulated RON,sp as a VBG . The inset shows the hole current density distribution cut
function of VBG for different N D . The analytical and sim- line AA at VBG = 0 and −300 V for ts = 5 μm. The hole
ulated results show that RON,sp reduces sharply with VBG current density near the interface at VBG = −300 V is about
increasing. For VBG = 0 V, the current density distributes 100 A/cm2 , which is one-tenth of that for ts = 1.2 μm with
uniformly in p-drift region, resulting in RON,sp depending the same VBG and N D . Small hole current density near the
strongly on N D . Thus, RON,sp for VBG = 0 V reduces interface can account for the behavior of RON,sp different ts
distinctly with N D increasing. For VBG < 0 V, current for high VBG . For large ts , fewer holes from channel can sink
crowds in the accumulation layer with high density. The to the accumulation layer compared with that for small ts .
DC mode provides DC paths in parallel, which leading to Thus, the benefit from the accumulation conduction for large
a RON,sp reduction. As the VBG increases, the second term ts is weakened, however, which is not considered in (4).
of denominator in (4) become larger than the first term, Fig. 5 shows the measured RON,sp and saturated drain
enabling Racc to dominate in RON,sp with the replacement current (Idsat ) as a function of VBG . RON,sp expectedly drops
ZHOU et al.: BG EFFECT ON RON,sp AND BV FOR THIN LAYER SOI FIELD pLDMOS
Fig. 6. Equipotential contours before breakdown for (a) VBG = 0 V and
(b) VBG = −200 V (10 V/contour). E i,d and E i,s are the electric fields in
dielectric layer at x = 10 and 45 μm, respectively. Both breakdown points
locate under the end of drain field plate.
and saturates with VBG increasing. For VBG = −200 V,
RON,sp of 7.5 · mm2 is achieved. If only considering L D ,
RON,sp is 6.6 · mm2 . Thus, RON,sp can decrease further with
optimized n-/p-well area, for example, reducing the length of
p+/n+ contact Idsat has a similar behavior with RON,sp on VBG .
In addition, the saturation of Idsat on VBG lags behind that
of Ron,sp, which attributes to the stronger lateral electric field.
Compared with RON,sp , Idsat is measured at lager Vd leading to
more holes directly pulled to the drain side before sink to the
accumulation layer. Thus, higher VBG is required to achieve
the domination of accumulation conduction in Idsat which is
the reason for the saturation on VBG.
IV. BG-I NDUCED B REAKDOWN M ECHANISMS
In addition to RON,sp , BV is also affected severely by VBG .
Fig. 6 shows the equipotential contours distribution before
breakdown for VBG = 0 and −200 V. Surface breakdown
occurs under the end of drain field plate for both VBG = 0 and
−200 V. For VBG = 0, the equipotential contours concentrate
at the end of drain field plate, giving rise to the premature
breakdown before the full depletion of p-drift region, as
shown in Fig. 6(a). For VBG = −200 V, more equipotential
contours are introduced to the source side because of the
potential difference between the source and BG, as shown in
Fig. 2(b). More uniform distribution of equipotential contours
in p-drift region contributes to the full depletion of p-drift
region and high BVs. In addition, as VBG increases,
E i,d decreases from 7.2 × 105 to 6.6 × 105 V/cm, and
E i,s increases from 2.3 × 103 to 6.6 × 105 V/cm. Expectedly,
due to high E i,s , the bulk breakdown occurs at p-drift/n-well
junction at the SOI/BOX interface with VBG increasing further.
1101
Fig. 7. Electric field distribution at the surface for different VBG before
surface breakdown.
Fig. 8. Measured, simulated, and analytical BV as a function of VBG for
breakdown mechanism A and B. BVb is defined as the VBG inducing bulk
breakdown, and VHV is the supply voltage of the switching IC.
Fig. 7 shows the surface electric field distribution for different
VBG . BG bias contributes to the full depletion of p-drift region
and uniform distribution of surface electric field, which leading
to high BVs.
To provide a deep insight into the relationship between the
BVs and VBG , an analytic BV model considering VBG and
MFP is present. Considering MFP, the whole drift region is
divided into five regions denoted by I–V as shown in Fig. 1(a),
of which boundaries are x = p0–p5. In Appendix B, solving
the Poisson equation of each region, the dependence of BVs
on VBG for the thin layer SOI field pLDMOS is given
BVs = 0.98 × VBG − 198.4. (5)
Fig. 8 shows the measured, simulated, and analytical
BV as a function of VBG for the surface breakdown and
bulk breakdown. For surface breakdown, BVs increases lin-
early with VBG increasing. The expression of BVs on VBG
provides a good fitting to the simulation and measured results.
When VBG exceeds about −300 V, BVs start to drop sharply,
which can be ascribed to bulk breakdown. The bulk breakdown
1102
Fig. 9. Measured drain current Id as a function of VBG for the different
Dnwell with Vd = −10 V.
occurs with a low Vd at p-drift/n-well junction at the SOI/BOX
interface because of high E i,s . Due to E i,s determined mainly
by VBG , BVb can be calculated based on Gauss’ law. For
the thin layer SOI field pLDMOS, BVb is about −300 V
for tox = 3 μm, coinciding with the measured and simulated
results. For the switching IC, supply voltage VHV is 200 V,
that is, both BVs at VBG = −200 V and BVb are required to
be higher than −200 V.
In addition, BG punchthrough should be concerned for
thin SOI layer. VBG induces depletion in the n-well while
accumulation layer in p-drift. As long as the vertical
depletion region starts attacking the built-in barrier of the
p-field/n-well junction, the punchthrough breakdown occurs.
Though high VBG can induces strong inversion layer leading
to the maximum depletion width, applying Vd extracts holes
in the inversion layer, which pushes n-well to nonequilibrium
again. In [9], a criterion for punchthrough breakdown is given,
which is utilized to calculate BVp. Based on the criterion, the
doping concentration of n-well and the depth of p-field/n-well
junction are optimized to achieve a high BVp.
Fig. 9 shows the measured drain current Id as a function
of VBG for different dose of n-well (Dnwell ) at Vd = −10 V.
The rapid increase of Id is ascribed to punchthrough
breakdown in the n-well. BVp is defined as the VBG
inducing punchthrough breakdown, and then BVp are
about −85, −140, and −225 V for Dnwell = 8 × 1012 ,
1 ×1013 , and 1.5 × 1013 cm−2 , respectively. BG punchthrough
breakdown is more prone to occur for low Dnwell . As well as
BVs at VBG = −200 V and BVb, BVp should be higher
than −200 V for safe operation. Therefore, Dnwell should
be higher than 1 × 1013 cm−2 to avoid BG punchthrough
at VBG = −200 V.
Based on the above discussion, we can obtain a design
require for the thin layer SOI field pLDMOS as described
in (6). Considering BG effect, the block capacity for the
thin layer SOI field pLDMOS depends on not only Vd ,
but also VBG . Appropriately increasing ts and tox can enhance
BVb, whereas the DC mode is inhibited. Based on the criterion
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 4, APRIL 2015
Fig. 10. Relationship between RON ,sp and BV for reported SOI pLDMOS and
this paper. Those SOI pLDMOS are manufactured on thick SOI layer except
for our work, while RESURF technology is used in [3], [4], [20], and [21].
given in [9], it is expected that BVp can be enhanced with
small depth of p-field/n-well junction and high Dnwell
VHV < min[|BVs|VBG =−VHV |, |BVb|, |BVp|]. (6)
Fig. 10 shows the relationship between RON,sp and BV
for reported SOI pLDMOS and this paper. In this paper,
BG effect on RON,sp and BV are considered seriously and
utilized to design device. Based on 1.5-μm SOI layer and
3-μm BOX layer RON,sp of 7.5 · mm2 and BV of 366 V
for the field pLDMOS are achieved experimentally, of which
p-drift region adopts 15–25  · cm p-type material without
additional impurity doping. For L d = 10, 14, 18, and 28 μm,
optimized simulation results are also given. These results are
all obtained at VBG = −200 V except L D = 10 μm. The
SOI pLDMOS with L D = 10 μm and tox = 2 μm is designed
at VBG = −100 V.
V. C ONCLUSION
BG effect on RON,sp and BV for thin layer SOI field
pLDMOS are investigated by modeling, simulation, and
verified experimentally. Hole accumulation layer induced by
VBG provides a low ON-resistance conduction path at the
bottom of p-drift region. DC mode including drift and accu-
mulation conduction is revealed, which contributes to a RON,sp
reduction. In addition, BG effect induces three breakdown
mechanisms of which BVs are required to be higher than the
supply voltage. For surface breakdown, a positive linear depen-
dence of BVs on VBG is given with consideration to MFP.
By utilizing BG effect, RON,sp of 7.5 · mm2 and BV of
366 V for the thin layer SOI field pLDMOS is achieved
experimentally.
A PPENDIX A
A. DC Mode
In the hole accumulation layer, potential distribution
(d) in the direction perpendicular to the SOI/BOX interface
ZHOU et al.: BG EFFECT ON RON,sp AND BV FOR THIN LAYER SOI FIELD pLDMOS 1103

is given in [22] Due to the drift region depleted fully, the potential function
      (x, y) in the silicon layer can be approximately expressed
kT qφ I d
(d) = − ln sec2 arccos exp −√ as [23]
q 2kT 2L D
(A1) Φ(x, y) = φ f (x) + φ1 (x)y + φ2 (x)y 2 (A7)
where k and T are the Boltzmann constant and temperature,
and the boundary conditions are given as follows:
respectively. φ I is the potential on SOI/BOX interface. Holes
within the accumulation layer follow the Boltzmann distri- d(x, y) k

bution, thus, the hole concentration Nacc can be obtained y=0 = φ1 (x) = φ f (x) − Vfp (A8a)
dy ti
in (1)
d(x, y) k
     y=ts = φ1 (x) + 2ts φ2 (x) = [VBG − φb (x)]
qφ I d dy tb
Nacc (d) = N D sec arccos exp
2
−√
2kT 2L D (A8b)
0 < d < wacc . (A2)
with
Subsequently, the accumulation layer charge Q acc can be
given by integrating Nacc (d) within the accumulation layer as φb (x) = (x, ts ) = φ f (x) + φ1 (x)ts + φ2 (x)ts2 (A9)
follows:
 wacc where k = εox /ε S , ε S is dielectric constant of silicon.
Q acc = q Nacc (d)dd t = ts /2 + tox /k, ts and tox are the effective thickness of SOI
0    and BOX layers, respectively. ti is the thickness of oxide layer
√ β
= − 2q N D L D tan(β) + tan √ below field plate in each region. Vfp is the bias voltage applied
2L D
√ at the each field plate. Equations (A8a) and (A8b) assume that
≈ − 2q N D L D tan(β) (A3) the flat-band voltage at the SOI/BOX interface is minimized.
√ Thus, solving (A7) with those boundary conditions, lateral
where wacc = 2L D β obtained by setting (d) = 0. surface electric field E x (x) is obtained as follows:
β = arccos[exp(qφ
√ I 2kT )]. To obtain a simple expression
of φ I , tan(β 2L D ) is neglected in (A3) because of its value is x− pi−1
(Vi − ϕi ) coshTi
p −x
+(ϕi − Vi−1 ) coshTii
much smaller than tan(β) at high VBG . Assuming that Q acc is E x (x) = p − pi−1
equal to the BG charge Q BG = VBG · εox /tox , thus, Ti sinh Tii
φ I and Nacc are given (A10)
2kT
φI = ln{cos[ara tan(VG · ϕ)]} (A4) with
q
      −2
d √ ts k
Nacc = N D sec2 [arctan(VG · ϕ)] − √ , 0 < d < wacc . Ti = tts 1 + t + (A11)
2L D 2 ti
      
(1) 1 ts k q ND
ϕi = VBG + t + Vfp − × Ti2 ,
According to (1) or VBG · εox /tox to calculate Q acc , Racc tts 2 ti εS
can be derived. Thus, Rdd and Racc are described as follows: i = 1, 2, 3, 4, 5 (A12)

L d − L ov where Vi is the voltage at x = pi , in which V0 = 0 V and

Rdd = (2)
qμdd N D ts Z V5 = Vd . E x must satisfy the continuity at boundaries, that is,
(L d − L ov )tox E x of each region keep equality at boundaries. The vertical
Racc =− . (3)
μacc εox Z VBG surface electric field E y is also obtained by solving (A8a).
Hence, the net electric field distribution E net in whole p-drift
As shown in Fig. 1, RON,sp is regarded equivalently as Rdd region can be obtained with given VBG , Vd , and N D , which
and Racc in parallel, thus, it can be described as (A5). Noting equals (E x2 + E 2y )1/2 .
that the equality sign in (A5) can be taken after simplifying In turn, the dependence of BVs on VBG can be obtained
RON,sp = Rdd Racc /(Rdd + Racc ), VBG ≤ 0V. (A5) by solving E net (p4) = E cri and the electric field continu-
ity equations, where E cri is the critical breakdown electric
field of silicon. For the thin layer SOI field pLDMOS,
A PPENDIX B p1 , p2 , p3 , p4 , and p5 are 5, 10, 13, 25.5, and 28 μm,
B. Relationship of BVs and V BG respectively. t1 , t2 , t3 , t4 , and t5 are 0.5, 1.1, 2.0, 1.1,
and 1.1 μm, respectively. N D = 4 × 1014cm−3 . Thus,
The potentials of each region in the silicon layer must satisfy
the dependence of BVs on VBG can be is given with
the Possion equation
E cri = 3.3 × 105 V/cm
d 2 (x, y) d 2 (x, y) q ND
+ = . (A6) BVs = 0.98 × VBG − 198.4. (4)
dx 2 dy 2 εS
1104 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 4, APRIL 2015

R EFERENCES Xin Zhou received the B.S. degree from the Hefei
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S. Maegawa, “Enhancement of current drivability in field PMOS by power integrated circuits.
optimized field plate,” in Proc. 22nd ISPSD, 2010, pp. 253–256.
[7] T. Miyoshi et al., “300 V field-MOS FETs for HV-switching IC,” in
Proc. IEEE 23rd ISPSD, May 2011, pp. 40–43.
[8] D. H. Lu, T. Mizushima, H. Sumida, M. Saito, and H. Nakazawa, “High Yitao He received the B.S. degree from the Uni-
voltage SOI P-channel field MOSFET structures,” in Proc. 21st ISPSD, versity of Electronic Science and Technology of
2009, pp. 17–20. China, Chengdu, China, in 2011, where he is cur-
[9] M. Qiao et al., “300-V high-side thin-layer-SOI field pLDMOS with rently pursuing the Ph.D. degree with the State Key
multiple field plates based on field implant technology,” IEEE Electron Laboratory of Electronic Thin Films and Integrated
Device Lett., vol. 33, no. 10, pp. 1438–1440, Oct. 2012. Devices.
[10] T. Letavic et al., “Lateral smart-discrete process and devices based on He is involved in semiconductor power devices.
thin-layer silicon-on-insulator,” in Proc. 13th ISPSD, 2001, pp. 407–410.
[11] M. Qiao, B. Zhang, Z. Xiao, J. Fang, and Z. Li, “High-voltage tech-
nology based on thin layer SOI for driving plasma display panels,” in
Proc. 20th ISPSD, 2008, pp. 52–55.
[12] I. Cortés, G. Toulon, F. Morancho, D. Flores, E. Hugonnard-Bruyère,
and B. Villard, “Analysis and optimisation of lateral thin-film silicon-on- Zhuo Wang received the M.Sc. degree from the
insulator (SOI) PMOS transistor with an NBL layer in the drift region,” University of Electronic Science and Technology of
Solid-State Electron., vol. 70, pp. 8–13, Apr. 2012. China (UESTC), Chengdu, China, in 2001, where
[13] S. Schwantes, T. Florian, T. Stephan, M. Graf, and V. Dudek, “Analysis he is currently pursuing the Ph.D. degree.
and optimization of the back-gate effect on lateral high-voltage SOI He is currently at UESTC. His current research
devices,” IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1649–1655, interests include power devices and power manage-
Jul. 2005. ment integrated circuits.
[14] S. Schwantes, T. Florian, M. Graf, F. Dietz, and V. Dudek, “Analysis
of the back gate effect on the breakdown behaviour of SOI LDMOS
transistors,” in Proc. 34th ESSDERC, 2004, pp. 253–256.
[15] M. Qiao, B. Zhang, Z. J. Li, and J. Fang, “Analysis of back-gate effect on
breakdown behaviour of over 600V SOI LDMOS transistors,” Electron.
Lett., vol. 43, no. 22, pp. 1231–1232, Oct. 2007. Zhaoji Li received the B.S. degree in 1963.
[16] K. Zhou, X. Luo, Q. Xu, Z. Li, and B. Zhang, “A RESURF-enhanced He was a Visiting Scholar with the Georgia Insti-
p-channel trench SOI LDMOS with ultralow specific on-resistance,” tute of Technology, Atlanta, GA, USA, from 1982
IEEE Trans. Electron Devices, vol. 61, no. 7, pp. 2466–2472, Jul. 2014. to 1984. He has authored over 80 papers on the
[17] S. M. Sze and K. K. Ng, “Physics and properties of semiconductors— IEEE T RANSACTIONS ON E LECTRON D EVICES and
A review,” in Physics of Semiconductor Devices, 3rd ed. Hoboken, NJ, the IEEE E LECTRON D EVICE L ETTERS . His cur-
USA: Wiley, Oct. 2006, pp. 7–75. rent research interests include semiconductor device
[18] K. Kobayashi, H. Yanagigawa, K. Mori, S. Yamanaka, and A. Fujiwara, physics, semiconductor power devices, and ICs.
“High voltage SOI CMOS IC technology for driving plasma display
panels,” in Proc. 10th ISPSD, 1998, pp. 141–144.
[19] M. R. Lee et al., “SOI high voltage integrated circuit technology for
plasma display panel drivers,” in Proc. 11th ISPSD, 1999, pp. 285–288.
[20] T. Nitta et al., “Wide voltage power device implementation in 0.25 μm
SOI BiC-DMOS,” in Proc. IEEE 10th ISPSD, Jun. 2006, pp. 1–4. Bo Zhang received the M.S. degree from the Univer-
[21] T. Miyoshi, T. Tominari, H. Fujiwara, T. Oshima, and sity of Electronic Science and Technology of China
J. Noguchi, “Design of a reliable p-channel LDMOS FET with (UESTC), Chengdu, China, in 1988.
RESURF technology,” IEEE Trans. Electron Devices, vol. 61, no. 5, He was a Visiting Professor with the Virginia Poly-
pp. 1451–1456, May 2014. technic Institute and State University, Blacksburg,
[22] J. P. Colinge and C. A. Colinge, “The MOS transistor,” in Physics VA, USA, from 1996 to 1999. He has been with
of Semiconductor Devices. New York, NY, USA: Springer-Verlag, UESTC, since 1999, where he has been involved in
Oct. 2005, pp. 165–250. power devices and smart power integrated circuits.
[23] S.-K. Chung and S.-Y. Han, “Analytical model for the surface field
distribution of SOI RESURF devices,” IEEE Trans. Electron Devices,
vol. 45, no. 6, pp. 1374–1376, Jun. 1998.