FMC-SDR400, Sundance RF Radio

FMC-SDR400 Module
User Guide
Copyright © Sundance DSP Inc.
All rights reserved. No part of this document may be reproduced, translated,

stored in a retrieval system, or transmitted, in any form or by any means,
electronic, mechanical, photocopying, recording or otherwise, without prior
written permission of the owner.
REVISION HISTORY
Revision Comments Originator Date

1.0 draft Stephen Malchi Dec 22nd 2017
Updated example application using
1.1 Stephen Malchi Jul 28th 2018
PXIe700
FMC-SDR400-UG Page 2 of 29 Rev. 1.1
Sundance Digital Signal Processing Inc.

4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1-775-827-3103, Fax: +1-775-827-3664, email: sales@sundancedsp.com
www.sundancedsp.com © Sundance Digital Signal Processing Inc 2017.
Table of Contents
1 Introduction ................................................................................................................................... 5
1.1 Hardware features ................................................................................................................. 5
2 Board Description ......................................................................................................................... 6
2.1 Block Diagram ....................................................................................................................... 6
2.2 Dimensions ............................................................................................................................ 8
2.3 Environmental ........................................................................................................................ 8
2.4 Images of FMC-SDR400 ........................................................................................................ 9
2.5 FMC HPC ............................................................................... Error! Bookmark not defined.
2.6 RF Transceiver .................................................................................................................... 11
2.7 ADC ..................................................................................................................................... 11
2.8 Clock.................................................................................................................................... 12
2.9 Tunable Band pass filter ...................................................................................................... 12
2.10 RF Input ............................................................................................................................... 12
2.11 RF Output ............................................................................................................................ 13
2.12 External Reference Clock Input............................................................................................ 13
3 Operation .................................................................................................................................... 14
3.1 VADJ ................................................................................................................................... 14
3.2 Operational Limitations ........................................................................................................ 14
4 Typical Programming Sequence ................................................................................................. 15
5 Board Support Package .............................................................................................................. 15
6 Reference list .............................................................................................................................. 15
7 Cooling ....................................................................................................................................... 15
8 SAFETY ...................................................................................................................................... 15
9 EMC............................................................................................................................................ 15
10 Ordering Information................................................................................................................ 16
11 Appendix ................................................................................................................................. 17
11.1 Recommended Antennas..................................................................................................... 17
11.1.1 Frequency range 1, 2 band antenna (2.4 GHz and 5.6 GHz) ........................................ 17
11.1.2 Frequency range 2, 400 MHz - 480 MHz (very popular frequency band) ...................... 17
11.1.3 Frequency range 3, below 70 MHz ............................................................................... 17
11.2 FMC HPC pinout for FMC-SDR400 Row wise ..................................................................... 17
11.3 Board Support package for FMC-SDR400 Attached to PXIe700 .......................................... 21
11.3.1 Linux drivers on Microblaze .......................................................................................... 22
11.3.2 Host Application ............................................................................................................ 22

Table of Figures
Figure 1: FMC-SDR400 Engineering Block Diagram ............................................................................ 6

Figure 2: FMC-SDR400 Block Diagram................................................................................................ 7
Figure 3: FMC-DAQ2p5 board placement Diagram .............................................................................. 7
Figure 4: Component side of FMC-SDR400 ......................................................................................... 9
Figure 5: Solder side of FMC-SDR400 ................................................................................................. 9
Figure 6: FMC-SDR400 3D View (3D view is available at this link) .................................................... 10
Figure 7: System Block Diagram ........................................................................................................ 21
Figure 8: RX1 input time domain plot (sinus 2,4 GHz) ........................................................................ 23
Figure 9: RX1 input frequency domain plot (sinus 2,4 GHz) ............................................................... 24
Figure 10: Castellation plot (RX1 sinus 2,4 GHz, RX2 not connected) ............................................... 25
Figure 11: Cross correlation (RX1 sinus 2,4 GHz, RX2 not connected) .............................................. 26

1 INTRODUCTION
FMC-SDR400 is an RF FMC module with two RF channels of Rx/Tx. The module is based on AD9361
RF Agile Transceiver, and AD9656 125MSPS ADC and is ideal for a broad range of RF applications
including point-to-point communications, Femtocell/picocell/microcell base stations, and Software
Defined Radio. FMC-SDR400 supports two simultaneous Rx/Tx channels covering 70Mhz to 6GHz on
FPGA carrier cards with LPC FMC connector. For operating below 70 MHz it offers two Rx channels
and requires an FPGA carrier card with at least one high speed serial transceiver @ 6.5Gb/s or more.
1.1 Hardware features

The hardware has the following features:
1. AD9361 – RF Agile Transceiver

2. AD9656 – 16bit 125MSPS JESD204B ADC
3. JESD204B via HPC connector, 4 lanes @ 6.4Gbps per lane.
4. 12 LVDS differential pair via FMC HPC.
5. Output power – up to 8 dBm for frequencies from 47 MHz to 0.8 GHz, up to 6.5 dBm for
frequencies from 0.8 GHz to 6 GHz.
6. Bandwidth – tunable from 200kHz to 56MHz.
7. AD9553 – High performance clock generator.
8. Five SSMC connectors for
1) Two single ended input of RF signal, up to 6GHz.
2) Two output RF signal from AD9361.
3) One reference clock input.
9. JESD204B Subclass 1 capable.
10. 40 MHz onboard OCXO, frequency stability over temperature and tolerance - ±100 ppb.
11. External reference clock input from 1 to 80 MHz.
12. VADJ voltage supported:1.8V ONLY.
13. Power consumptions: 12V – max 1A, 3.3V – max 1.5A, Vadj – max 0.4A

2 BOARD DESCRIPTION
2.1 Block Diagram
The following diagram shows the major blocks of FMC-SDR400 2 channel board:
FMC HPC RF RF RF IN
Connector
RX1A
switches switch
LNA
TBF Connector
Power
12V, 3.3V, Vadj
RF RF RF IN
FMC_LA[10:15] TX_D[0:5]
RX2A
switches switch
LNA
FMC_LA[01]_CC FB_CLK TBF Connector
FMC_LA[02:07] RX_D[0:5]
RF Front end
AD9361 RF OUT
FMC_LA[00]_CC DATA_CLK TX1A Balun Connector
FMC_LA[33], SPI
SPI RF OUT
FMC_HA[00]
TX2A Balun Connector
FMC_LA[19:20] CTRL_IN[0:3]
XT ALN
FMC_LA[21:24] CTRL_OUT[0:7]
FMC_LA[30] RFFE (2-wire)
INA
FMC_DP[0:3] SERDOUT[0:3]
IND
FMC_LA[17]_CC SYSREF ADC
FMC_LA[18]_CC SYNC AD9656
SPI
FMC_LA[16,31:32]
DEV_CLK
REF CLK IN
FMC_CLK0_M2C
RF
switch
Clock OCXO
OUT_1 buffer 40MHz
FMC_GBTCLK0 OUT_2
REFA
AD9553
SPI
FMC_LA[31:32]
EXT_CLK_SEL
FMC_LA[26]-
1 – Ext ernal clock
0 – Internal OCXO
FMC_LA[27] Negative VCC_VG G
CP for LNA
Figure 1: FMC-SDR400 Engineering Block Diagram

Figure 2: FMC-SDR400 Block Diagram
Figure 3: FMC-DAQ2p5 board placement Diagram

2.2 Dimensions
This FMC module adheres to the VITA57.1 single width FMC dimensions
2.3 Environmental
Operating temperature: 0˚C to +45˚C

Storage temperature: -25˚C to +60˚C
Humidity: 10% to 90% non-condensing

2.4 Images of FMC-SDR400
Figure 4: Component side of FMC-SDR400
Figure 5: Solder side of FMC-SDR400

Figure 6: FMC-SDR400 3D View (3D view is available at this link)
2.5 HPC FMC Carriers
A High Pin Count (HPC) FMC connector is used to interface the module to the FPGA carrier
card; although an LPC connector can also be used if frequencies below 70MHz are not
required.
Four high speed transceivers are connected to AD9656 ADC (JESD204B interface) for
transferring digitized data when the module is used in RX band below 70 MHz. Please note
that at least 1 serial link with a minimum speed of 6.5Gb/s is required for interfacing to the
AD9656 for supporting frequencies below 70MHz.
When operating at frequencies from 70 MHz to 6 GHz the ADC’s on AD9361 are used. This
interface is implemented over 6 LVDS differential pairs on the LA bus and hence LPC carriers
can be used.
The DAC’s on AD9361 are also interfaced via 6 LVDS differential pairs on the LA bus. SPI
RFFE and other controls to configure RF and ADC chips are also connected to LA bus.

2.6 RF Transceiver
FMC-SDR400 uses AD9361 RF Agile Transceiver from Analog Devices. AD9361 is a high-
performance RF transceiver suitable for 3G, 4G base station applications. The device
combines an RF front-end with a flexible mixed signal baseband section and integrated
frequency synthesizers. The AD9361 receiver operates from 70 MHz to 6 GHz and the
transmitter LO operates from 47 MHz to 6 GHz and supports a channel bandwidth from less
than 200 KHz to 56 MHz.
The key features of the transceiver are given below:
Receive:
• Supports up to 2 direct conversion RF receive channels

• Fully Integrated synthesizers (Including loop filters)
• Data paths consists of LNA, Demodulator, LPF, ADC and digital filters
• AGC, Quadrature calibration and DC offset calibration
• NF: 2.5dB @1GHz
• ADC: Continuous time sigma-delta, 640 MSPS
• Digitals filters: 128 complex taps, decimation between 2 and 48
• Gain: 1 dB step size, 80dB analog rang, 30dB digital range (post ADC scaling)
• On-chip sensor for temperature-corrected RSSI
Transmit:
• Supports up to 2 RF transmit channels

• Fully Integrated synthesizers (Including loop filters)
• Data path consists of digital filters, DAC and modulators
• Digital filters: 128 complex taps, interpolation between 2 and 48
• Gain: 0.25dB step size 86dB range
• DAC 320 MSPS
For more information please refer to the link below
http://www.analog.com/media/en/technical-documentation/data-sheets/AD9361.pdf
2.7 ADC
FMC-SDR400 uses Analog Devices AD9656 quad 16-bit 125 MSPS, Analog to Digital
Converter to handle signals below 70MHz. The device is optimized for outstanding dynamic
performance and low power. The ADC contains several features designed to maximize
flexibility such as programmable output clock, data alignment and digital test pattern
generation.

Features of ADC are given below
• SNR = 79.9 dBFS at 16 MHz (Vref = 1.4V)

• SNR = 78.1 dBFS at 64 MHz (Vref = 1.4V)
• SFDR = 86dBc to Nyquist (Vref = 1.4V)
• JESD204B Subclass 1 coded serial digital outputs
• Flexible analog input range 2.0 V p-p to 2.8 V p-p
• 1.8V supply operation
• Low power 197mW per channel at 125 MSPS (two lanes)
• DNL = ±0.6 LSB (Vref = 1.4V)
• INL = ±4.5 LSB (Vref = 1.4V)
• 650 MHz analog input bandwidth full power
• Serial port control
For More information on the AD9656 and configuration please refer to the link below
2.8 Clock
Clock on this module is provided by AD9553 from ADI. AD9553 is a phase locked loop, based clock
translator designed for base stations and passive optical networks (PON). The device has multiple
clock outputs with individual clock divider. Clock output ranges from 0 to 810 MHz and VCO output
ranges from 3350 to 4050 MHz
For more information on AD9553 and accessing the registers please refer to the link below
2.9 Tunable Band pass filter
There is a tunable band pass filter implemented between the RF Receiver input and AD9361. This
filter is implemented using HMC550-AE SPST failsafe switch and STPTIC-68G2 tunable capacitor.
The filter is configured to 2.4 GHz via RFFE interface from the FPGA.
2.10 RF Input
The RF input is fed to the board using SSMC connector via a Low Noise Amplifier from Analog
Devices HMC8410. The LNA operates from 0.01 GHz to 10 GHz with a typical gain of 19.5 dB and
noise figure of 1.1 dB. The signal is then passed through a MUX switch to be fed into different devices
based on the operation required.
1. AD9656 input for Low frequency sampling < 70 MHz

2. AD9631 input for sampling between 70 MHz – 6.0 GHz

3. AD9631 input via tunable Band Pass Filter (tuned to 2.4 GHz)
2.11 RF Output
The RF output is directly driven to SSMC connectors without any filtering.
2.12 External Reference Clock Input
The board contains internal 40 MHz OCXO for improved frequency stability over temperature and
aging. It also has an external reference clock input via SSMC connector for a more stable reference
clock selectable by a RF switch.

3 OPERATION
The FMC module is operational when populated on an FPGA carrier card. Initialization of the
Transceiver, ADC and clock are done via the SPI over the FMC connector. The following factors need
to be considered for proper operation of the module.
3.1 VADJ
FMC-SDR400 supports VADJ voltage of 1.8V. For this reason, the EEPROM is left empty.
Note: Customers should make sure the FPGA carrier card supports 1.8V VADJ voltage to work with
this module.
3.2 Operational Limitations
1. Maximum line rate for AD9656 ADC is 6.4 Gb/s, so the FPGA carrier transceivers must
support this rate or above for operating below 70 MHz.
2. External input reference clock is limited to 80 MHz, due to AD9631 limitation.

4 TYPICAL PROGRAMMING SEQUENCE
1. Program AD9553 clock chip via SPI to generate the required clocks
2. Program AD9361 transceiver and integrated ADC’s and DAC’s via SPI interface
3. Tune Band Pass Filter via RFFE interface to 2.4 GHz
4. Capture data from the receiver process it and transmit.
5 BOARD SUPPORT PACKAGE
The module can work in an FMCCOM3 compatible mode. The application provided by ADI on
their web site could be used for SDR400. An example of using FMC-SDR400 on the PXIe700
(Kintex-7 FPGA PXIe card) is available and the entire project with sources could be supplied.
Please contact Sundance DSP Inc for further information. Brief description of the solution is
included in Appendix section 11.3.
6 REFERENCE LIST
A set of links for your easy access to guides for devices used on this module:
AD9361 – RF agile Transceiver;

AD9656 – 125MSPS 16-bit JESD204B ADC;
RFFE standard
PG066-JESD204.pdf – JESD204B Logic core IP user guide.
7 COOLING
User must make sure that adequate air flow and/or conduction cooling is provided for when using this
module.
8 SAFETY
The module presents no hazard to the user.
9 EMC
The module is designed to operate within an enclosed host system that provides adequate EMC
shielding.
Operation within the EU EMC guidelines is only guaranteed when the module is installed within an
appropriate host system.
The module is protected from damage by fast voltage transients introduced along output cables from
outside the host system.
Short-circuiting any output to ground does not cause the host PC system to lock up or reboot.

10 ORDERING INFORMATION
FMC-SDR400 This is the default model

11 APPENDIX
11.1 Recommended Antennas
11.1.1 Frequency range 1, 2 band antennas (2.4 GHz and 5.6 GHz)
https://www.digikey.com/product-detail/en/taoglas-limited/GW.71.5153/931-1066-ND/2332693
or
http://productfinder.pulseeng.com/productSearch/w1028b
These two antennas have a RP-SMA male connector. You will need an additional RF adapter RPSMA-SMA
11.1.2 Frequency range 2, 400 MHz - 480 MHz (very popular frequency band)
https://www.digikey.com/product-detail/en/linx-technologies-inc/ANT-433-CW-QW-SMA/ANT-
433-CW-QW-SMA-ND/3045488
spec can be found here: https://linxtechnologies.com/wp/wp-content/uploads/ant-433-cw-qw.pdf
11.1.3 Frequency range 3, below 70 MHz
http://www.nagoya.com.tw/s/2/product-548648/WP-1105.html
or
http://www.mobileone.com.au/6c_70to88mhz.html
Antennas for this band are rather big and without SMA connector and some adaptors may be needed.
11.2 FMC HPC pinout for FMC-SDR400 Row wise
ROW A
Signal Name FMC Pin FMC Signal
DOUT_B+ A2 FMC_M2C_DP1+
DOUT_B- A3 FMC_M2C_DP1-
DOUT_C+ A6 FMC_M2C_DP2+
DOUT_C- A7 FMC_M2C_DP2-
DOUT_D+ A10 FMC_M2C_DP3+
DOUT_D- A11 FMC_M2C_DP3-
ROW C
DOUT_A+ C6 FMC_M2C_DP0+
DOUT_A- C7 FMC_M2C_DP0-

RX_D4+ C10 FMC_LA06+
RX_D4- C11 FMC_LA06-
TX_D0+ C14 FMC_LA10+
TX_D0- C15 FMC_LA10-
TX_D4+ C18 FMC_LA14+
TX_D4- C19 FMC_LA14-
ADC_SYNC+ C22 FMC_CC_LA18+
ADC_SYNC- C23 FMC_CC_LA18-
VGG_SET_2V C26 FMC_LA27+
LNA_PWR_ON C27 FMC_LA27-
SCL C30 FMC_SCL
SDA C31 FMC_SDA
GA0 C34 FMC_GA0
ROW D
PG_C2M D1 FMC_PG_C2M
FMC_GBTCLK0+ D4 FMC_GBTCLK0+
FMC_GBTCLK0- D5 FMC_GBTCLK0-
FB_CLK+ D8 FMC_CC_LA01+
FB_CLK- D9 FMC_CC_LA01-
RX_D3+ D11 FMC_LA05+
RX_D3- D12 FMC_LA05-
TX_FRAME+ D14 FMC_LA09+
TX_FRAME- D15 FMC_LA09-
TX_D3+ D17 FMC_LA13+
TX_D3- D18 FMC_LA13-
ADC_SYSREF+ D20 FMC_CC_LA17+
ADC_SYSREF- D21 FMC_CC_LA17-
CTRL_OUT4 D23 FMC_LA23+
CTRL_OUT5 D24 FMC_LA23-
TX/RX# D26 FMC_LA26+
EXT_CLK_SEL D27 FMC_LA26-
GA1 D35 FMC_GA1
ROW F
PG_M2C F1 FMC_PG_M2C
SPI_SDO F4 FMC_CC_HA00+

ROW G
DATA_CLK+ G6 FMC_CC_LA00+
DATA_CLK- G7 FMC_CC_LA00-
RX_D1+ G9 FMC_LA03+
RX_D1- G10 FMC_LA03-
RX_FRAME+ G12 FMC_LA08+
RX_FRAME- G13 FMC_LA08-
TX_D2+ G15 FMC_LA12+
TX_D2- G16 FMC_LA12-
SPI_CS# G18 FMC_LA16+
ADC_PWRDWN G19 FMC_LA16-
CTRL_IN2 G21 FMC_LA20+
CTRL_IN3 G22 FMC_LA20-
CTRL_OUT2 G24 FMC_LA22+
CTRL_OUT3 G25 FMC_LA22-
ENABLE G27 FMC_LA25+
EN_AGC G28 FMC_LA25-
TBF_HI G30 FMC_LA29+
TBF_BYPASS G31 FMC_LA29-
MULT_SDIO G33 FMC_LA31+
MULT_SCK G34 FMC_LA31-
SPI_SCK G36 FMC_LA33+
SPI_SDI G37 FMC_LA33-
ROW H
REF_CLK+ H4 FMC_M2C_CLK0+
REF_CLK- H5 FMC_M2C_CLK0-
RX_D0+ H7 FMC_LA02+
RX_D0- H8 FMC_LA02-
RX_D2+ H10 FMC_LA04+
RX_D2- H11 FMC_LA04-
RX_D5+ H13 FMC_LA07+
RX_D5- H14 FMC_LA07-
TX_D1+ H16 FMC_LA11+
TX_D1- H17 FMC_LA11-

TX_D5+ H19 FMC_LA15+
TX_D5- H20 FMC_LA15-
CTRL_IN0 H22 FMC_LA19+
CTRL_IN1 H23 FMC_LA19-
CTRL_OUT0 H25 FMC_LA21+
CTRL_OUT1 H27 FMC_LA21-
CTRL_OUT6 H28 FMC_LA24+
CTRL_OUT7 H29 FMC_LA24-
LF_SEL_CH1 H31 FMC_LA28+
LF_SEL_CH2 H32 FMC_LA28-
REFE_SCL H34 FMC_LA30+
REFE_SDA H35 FMC_LA30-
MULT_CS# H37 FMC_LA32+
ADC_CS# H38 FMC_LA32-

11.3 Board Support package for FMC-SDR400 Attached to PXIe700
Functionality of FMC-SDR400 was tested on a Kintex-7 based PXIe FPGA carrier card (PXIe700). In
this development we also used SMT580 PCIe-to-cPCIe adapter card and a CPIe-to-PCIe cable from
Samtec (PCIEC-098-0151-EC-EM-C) to connect the adapter card to a host PC. The block diagram
below shows the data flow between SDR400 and FPGA IP-core.
Figure 7: System Block Diagram

The main components of the system are:
- Linux drivers on Microblaze for configuring AD9361 and Band pass filter
- GUI Host application (via PCIe interface) on Windows 10 PC
11.3.1 Linux drivers on Microblaze

The Linux OS deployment on MicroBlaze processor allows the user to use libiio-related software to
control AD9361 and transfer data. On the host PC ADI IIO-Oscilloscope is executed to control
AD9361. FPGA hosts microblaze soft core with linux drivers to configure AD9361 and tunable band
pass filter via SPI interface.
11.3.2 Host Application

Data processing and display is done by IIO-Oscilloscope. The host application software
communicates with iio-server inside FPGA via PCIe interface
In GUI application mode transceiver data is not stored to DDR memory and immediately transferred to
PC application. In user mode the DATA CROSSBAR IP Core will allow data storage to DDR memory.
The described data path is implemented by a few DMAs, multiplexers and demultiplexes groped into a
single DATA CROSSBAR IP Core. The data path configuration is set up by Linux driver via
axi_ad9361 ip-core.
Analog Devices ADC and DAC DMA cores are also configured by Linux driver directly. IIO-server is
executed over this driver and process command issued by IIO-client via PCIe interface.

Figure 8: RX1 input time domain plot (sinus 2,4 GHz)

Figure 9: RX1 input frequency domain plot (sinus 2,4 GHz)

Figure 10: Castellation plot (RX1 sinus 2,4 GHz, RX2 not connected)

Figure 11: Cross correlation (RX1 sinus 2,4 GHz, RX2 not connected)
11.4 Windows software installation

Three things have to be available on WIN10 machine:
1. SCom AXI drivers
2. Installed IIO-Oscilloscope v0.5
3. eth2pcie adapter (Ethernet to PCIe) – a single statically linked .exe file.
11.5 User Guide for running the sample application

1. Attach PXIe700 to WIN10 PC (see fig. 1)
2. Connect JTAG programmer.
3. Connect auxiliary UART for Linux console (see section below).
4. Download FW and Linux (see section below).
5. Reboot FPGA board

6. Reboot WIN10 PC
7. Run SCom-Demo.exe and click Connect to check the PCIe interface
visibility
8. Run eth2pci.exe
9. Run IIO-Oscilloscope software
10. Select Settings->Connect
11. Remote Devices (network) -> Enter IP address: 127.0.0.1
12. Click Refresh -> Info on available peripheral modules should appear.
13. Click OK. Wait for some time.
14. File -> New Plot
15. Select a few plot channels and configure plot type.
16. Click “Play”
Fig.1. Hardware attachment showing ADI RF FMC (used for initial app development) +PXIe700+SMT580 and
Samtec PCIe-to-PCIe cable.
11.6 UART connection (optional)

UART settings: 115200, 8 bits, no parity, no flow control. Connector J5 pinout
TX Pin 2
RX Pin3
GND Pin 10
11.7 Firmware and Linux downloading

This section describes a FW downloading on PXIe700 board with FMCOMM3 DSP board. The firmware
downloaded permanently into external BPI FLASH.

1. Open Vivado (we used 2017.2, but 2016.4 or less will be ok).
2. In top menu choose Flow/Hardware manager.
3. Click button Auto Connect in Hardware window.
4. Right-click on xc7k410t_XX device in device-tree and choose Add configuration memory device.
5. Choose 28f00ap30t-bpi-16x.
6. Choose OK to program configuration memory device.
7. In Configuration File box choose full_image.mcs (it contains bitstream for FPGA and Linux image) and
click OK.
8. Wait for process ends.
9. Right-click on xc7k410t_XX and choose Boot from configuration memory device.
10. Disconnect JTAG from PXIE700.
11. Reboot PC with connected PXIE700. To see Linux console run Putty (or other terminal emulator).
Connect to COM port with settings above. Linux loading takes around 50 seconds. Login: root.
After Linux loading the system is ready to process IIO-Oscilloscope request via PCIe bus.
Bootloader started
Loading PXIe700 Linux image...
Starting Linux...
Ramdisk addr 0x0000000a,
Compiled-in FDT at 803b2d90
Linux version 4.9.0-g01a3695-dirty (roman@ws-278) (gcc version 6.2.0 (crosstool-NG 1.20.0) ) #31
Sun Oct 22 12:48:45 +03 2017
setup_cpuinfo: initialising
setup_cpuinfo: Using full CPU PVR support
wt_msr_noirq
setup_memory: max_mapnr: 0x30000
setup_memory: min_low_pfn: 0x80000
setup_memory: max_low_pfn: 0xb0000
setup_memory: max_pfn: 0xb0000
Zone ranges:
DMA [mem 0x0000000080000000-0x00000000afffffff]
Normal empty
Movable zone start for each node
Early memory node ranges
node 0: [mem 0x0000000080000000-0x00000000bfffffff]
Initmem setup node 0 [mem 0x0000000080000000-0x00000000bfffffff]
On node 0 totalpages: 196608
free_area_init_node: node 0, pgdat 804bd04c, node_mem_map 80800000
DMA zone: 1536 pages used for memmap
DMA zone: 0 pages reserved
DMA zone: 196608 pages, LIFO batch:31
pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
pcpu-alloc: [0] 0
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 195072
Kernel command line: console=ttyUL0,115200
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
Fig.2. Linux start log
11.8 Features
Our software intended to support IIO-Oscilloscope work with FMCOMMS2-3 board. For functionality
description and user manual see:
https://wiki.analog.com/resources/tools-software/linux-software/iio_oscilloscope.
Within current version a Capture Window is supported only. Software able to capture:

- Signals in time domain;
- Frequency domain;
- Calculate costellation graphs;
- Calculate cross correlations graphs.
See earlier screen shots.
11.9 Known bugs

- IIO-Oscilloscope Debug module doesn’t communicate with IIO daemon on FPGA side.
Possible reason: another TCP/IP port is in use.
- Additional delays appear when IIO-Oscilloscope communicates with FPGA via SCom-PCIe
driver. Possible reasons: Small data packet size at transport layer. Too much time spends on
transfer initialization.
- WIN10 can crash when PCie connection lost, adapter application closed. Possible reason:
SCom driver operates in blocked mode without any legal method to decline read operation.
- Specific version of IIO-Oscilloscope is currently supported. Possible reason: it is necessary to
match IIO-lib on FPGA and IIO-Oscilloscope on PC versions.


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FMC-SDR400 Module

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Revision Comments Originator Date

FMC-SDR400-UG Page 2 of 29 Rev. 1.1

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FMC-SDR400-UG Page 3 of 29 Rev. 1.1

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Figure 1: FMC-SDR400 Engineering Block Diagram ............................................................................ 6

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1.1 Hardware features

1. AD9361 – RF Agile Transceiver

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FMC_LA[30] RFFE (2-wire)

FMC_LA[27] Negative VCC_VG G

Figure 1: FMC-SDR400 Engineering Block Diagram

FMC-SDR400-UG Page 6 of 29 Rev. 1.1

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Figure 3: FMC-DAQ2p5 board placement Diagram

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Operating temperature: 0˚C to +45˚C

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Figure 4: Component side of FMC-SDR400

Figure 5: Solder side of FMC-SDR400

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2.5 HPC FMC Carriers

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• Supports up to 2 direct conversion RF receive channels

• Supports up to 2 RF transmit channels

For more information please refer to the link below

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• SNR = 79.9 dBFS at 16 MHz (Vref = 1.4V)

2.9 Tunable Band pass filter

1. AD9656 input for Low frequency sampling < 70 MHz

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The RF output is directly driven to SSMC connectors without any filtering.

2.12 External Reference Clock Input

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3.2 Operational Limitations

2. External input reference clock is limited to 80 MHz, due to AD9631 limitation.

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5 BOARD SUPPORT PACKAGE

AD9361 – RF agile Transceiver;

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spec can be found here: https://linxtechnologies.com/wp/wp-content/uploads/ant-433-cw-qw.pdf

11.1.3 Frequency range 3, below 70 MHz

11.2 FMC HPC pinout for FMC-SDR400 Row wise

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FMC-SDR400-UG Page 20 of 29 Rev. 1.1

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Figure 7: System Block Diagram