EE 200

Xilinx FPGA Architecture

„ IOB: Input/output blocks
„ CLB: Configurable logic blocks
„ Programmable interconnections

EE200
2
 XC4000 FPGA Architecture

I/O Blocks
Programmable (IOB)
Interconnect

Long
interconnections

Configurable
Logic Block
(CLB)

SRAMS cells throughout the FPGA determine

the functionality of the device
EE200
3
 XC4000E CLB
MUX C1 C2 C3 C4
2 Four-input function
generators (Look Up
H0/SR H1 DIN S/R EC
Tables) S/R
Control

1 Three-input function G4 DIN

F
0
SD
2 Registers: G3 G G G
1
2 D Q YQ
G2 Func. H 3
- Pos. or Neg. edge- Gen. H1
G1 SG S3S2 EC
trig. Synchronous and 0
G 1
RD

1
H H 0' Y
asynchr. Set/Reset Din 0 Func 1
S/R
.Gen.
1 Sy Control

Possible functions: F4 SF DIN

F3 F 0
- any fct of 5 var. F2
Func.
F
G
1
D
SD
Q XQ
Gen. F 2
H 3
- two fcts of 4 var. + F1
S1S0
one fct of 3 var. EC
RD
1
- some fct of 9 var. 0
1
X
K (clock) Sx

EE200 Figure courtesy of Xilinx, Inc. © Xilinx, Inc. 1996. All rights reserved
4
 Example
„ Implement the following functions on a single
CLB of the XC4000 FPGA:
X = A’B’ (C + D)
Y = AK + BK + C’D’K + AEJL

„ Use look up table F to implement X

„ Use look up table G for AEJL
„ Use F, G and H for Y:
Y = K(A+B + C’D’) + AEJL
= KX’ + AEJL= KF’+G

EE200
5
 Example
MUX C1 C2 C3 C4

H0/SR H1 DIN S/R EC

S/R
Control

DIN
L G4 H1 F
0
SD
J G3
G G G
1
2 D Q YQ
Func. H 3
E G2 Gen
. K
A G1 SG S3S2 EC
1 RD
0
G 0 1
1
H H 1' Y=AK+BK+C'D'K
Din 0 Func S/R +AEJL
.Gen.
1 Sy Control
=1
D F4
SF DIN
F 0
C F3 Func
. 1 F
G
1
SD
XQ
D Q
B F2 Gen. F 2
H 3
A F1
S1S0 EC
RD

0 1
1
X=A'B'(C+D)
EE200 K (clock) Sx=1
6
 XC4000E IOB
Simplified block diagram Program Controlled Options
Output: comb. CLK CLK OUT TS SEL SLEW PULL UP/
Vcc

or reg; direct or IN
INV
OUT
INV
INV INV OUT RATE Down

inverted 50-100KΩ

Input: comb. or Enable Output

reg; zero hold Output
time option Buffer

PAD
Internal FFs for Output Data
D Q
input & output
paths EC
Output Clock OK
R M
Fast/Slow Clock Enable 50-100KΩ
outputs Direct In Vgnd
5 ns vs. 30 ns Q D
TTL or CMOS
rise Registered In EC Input Buffer

R Delay
Pull-up/down Input Clock IK
used with
unused IOBs Global Reset

Ref. Xilinx Data Book (1997); R. Katz, “Contemporary Design”

EE200
7
 XC4000E Interconnections
Simplified diagram
Direct
Connections
3 types: DI CE A
B
DI CE A
B
X X
C CLB0 C CLB1
* Fast Direct Connections K Y K Y
E D R E D R
Horizontal
* General Purpose Long Line
Connections with
Switching Matrix Switching
Matrix
* Horizontal/Vertical Long Horizontal
Lines Long Line
DI CE A DI CE A
Types of lines: B X B X
C CLB2 C CLB3
K Y K Y
* Single length (8) E D R E D R
* Double length (4)
* Long lines (6)
* Global lines (4) Vertical Global
Long Lines Long Line
EE200 After R. Katz, “Contemporary Logic Design”
8
 Direct Interconnect

„ Between
neighboring blocks
„ From CLB to CLB
„ From CLB to IOB
„ Fastest, short
distance connections
„ X: Hor. connection
„ Y: Vert. connection
Figure courtesy of Xilinx, Inc. © Xilinx, Inc. 1996. All rights reserved
EE200
9
XC4000E Programmable Matrix

Figure courtesy of Xilinx, Inc. © Xilinx, Inc. 1996. All rights reserved
EE200
10
 What goes on in the chip?

„ EPIC Screen clip

„ Use of 2 CLBs (out of
100; only 2% used for
the smallest FPGA
4003)

EE200 Screen clip from Xilinx Foundation XACTstep(TM) software

11
 Detail view of inside wiring

CLB (blue)

Direct lines
(green)

Switch
Matrix

Long lines
(purple)

Screen clip from Xilinx

Foundation XACTstep(TM)
software

EE200
12