Chapter 8:

FET Amplifiers
 Introduction

FETs provide:

• Excellent voltage gain

• High input impedance
• Low-power consumption
• Good frequency range

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 FET Small-Signal Model

Transconductance

The relationship of a change in ID to the corresponding change in VGS is

called transconductance or mutual conductance

Transconductance is denoted gm and given by:

ΔI D
gm 
ΔV GS

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 Graphical Determination of gm

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 Mathematical Definitions of gm
I D
For JFET and D-MOS gm 
 VGS
2
 V  2I DSS  VGS 
I D  I DSS 1  GS  gm   1  
 VP  VP  V P 

2I DSS
Where VGS =0V g m0 
VP
 V 
g m  g m0 1  GS 
 VP 

VGS ID
Where 1 
VP I DSS

 V  ID
g m  g m0  1  GS   g m0
 VP  I DSS

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 Mathematical Definitions of gm
I D
For E-MOS gm 
 VGS

I D  K VGS  VT 
2

g m  2 K VGS  VT 

ID
Where ( VGS  VT ) 
K

ID
g m  2K  2 KI D
K

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 FET AC Equivalent Circuit

Input impedance: Zi   
1
Output Impedance: Z o  rd 
y os
VDS
where: rd  VGS  constant
I D
yos= admittance parameter listed on FET specification sheets.

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 Common-Source (CS) Fixed-Bias Circuit

Input impedance:

Zi  RG

Output impedance:

Z o  R D || rd

Zo  R D
rd  10R D

Voltage gain:

Vo
Av    g m (rd || R D )
Vi
Vo
Av   g m R D
Vi rd  10R D

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 Common-Source (CS) Self-Bias Circuit

Voltage gain: Input impedance: Zi  RG

Vo g m v gs R D g R Output impedance: Zo  R D
Av    m D
Vi v gs  g m v gs R S 1 gmRS

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 Common-Source (CS) Voltage-Divider Bias

Input impedance:

Z i  R 1 || R 2

Output impedance:

Z o  rd || R D

Zo  R D
rd  10R D

Voltage gain:
A v   g m (rd || R D )

A v  g m R D
rd 10R D

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 Source Follower (Common-Drain) Circuit

Input impedance: Zi  R G
v
Output impedance: Z0  o when v i  0
Io
v0
Io   g m v gs
R s || rd
v gs   v o
vo 1
Zo   rd || R S ||
Io gm
1
Zo  R S || r 10R
gm d S
Voltage gain:
V g (r || R S )
Av  o  m d
Vi 1  g m (rd || R S )
Vo g R
Av   m S rd 10
Vi 1  g m R S

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 Common-Gate (CG) Circuit

The input is on the source

and the output is on the
drain.

There is no phase shift

between input and output.

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 Calculations
Input impedance:
v
Zi  i
ii
v
i i  i  g m v gs
Rs
v gs   v i
 1 
Zi  R S ||  
gm  rd  10R D
Output impedance: Voltage gain:
Zo  R D Vo  g m v gs R D  g m v gs R D
Av     g m R D
Vi vi  v gs

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 D-Type MOSFET AC Equivalent

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 E-Type MOSFET AC Equivalent

gm and rd can be found in

the specification sheet for
the FET.

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 Common-Source Drain-Feedback

There is a 180 phase shift

between input and output.

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 Calculations
vi
Input impedance: Zi 
Ii
v i  I i R F  I R rd || R D
I R  I i  g m v gs
v i  I i R F  ( I i  g m v gs )rd || R D
v i (1  g m rd || R D )  I i ( R F  rd || R D )
R F  rd || R D
Zi 
1  g m (rd || R D )
Output impedance:
Z o  R F || rd ||R D

Z o  R D R F  rd || R D , rd  10R D
Voltage gain:

A v  g m (R F || rd || R D )

A v  g m R D R F  rd ||R D ,rd 10R D

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 Common-Source Voltage-Divider Bias

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 Calculations
Input impedance:
Z i  R 1 || R 2

Output impedance:
Z o  rd || R D
Z o  R D rd  10

Voltage gain:
A v   g m (rd || R D )
A v   g m R D rd  10R D

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 Summary Table

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 Summary Table

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