EXPERIMENT-6

AIM: TO DESIGN AND SIMULATE ASYNCHRONOUS UP AND DOWN COUNTER USING J-K FLIP
FLOP.
TOOL USED: XILINX 14.7

THEORY: If the flip-flops do not receive the same clock signal, then that counter is called
as Asynchronous counter. The output of system clock is applied as clock signal only to first
flip-flop. The remaining flip-flops receive the clock signal from output of its previous stage
flip-flop.An ‘N’ bit Asynchronous binary up counter consists of ‘N’ J-K flip-flops. It counts
from 0 to 2^N− 1.And an ‘N’ bit Asynchronous binary down counter consists of ‘N’ T flip-
flops. It counts from 2^N − 1 to 0.

ASYNCHRONOUS UP COUNTER:

CIRCUIT DIAGRAM:

VERILOG CODE:
module jkff(
input j,
input k,
input r,
input clk,
output reg q,
output qo
);
initial
begin
q<=0;
end
always@ (posedge clk or posedge r)
 if(r)
begin
q<=1'b0;
end
else
begin
case({j,k})
2'b00 : q<=q;
2'b01 : q<=1'b0;
2'b10 : q<=1'b1;
2'b11 : q<=~q;
endcase
end
assign qo =~q;
endmodule

module upcounter(input clk,r,

inout [3:0]q,
output [3:0]qo);
jkff f1(1,1,r,clk,q[0],qo[0]);
jkff f2(1,1,r,q[0],q[1],qo[1]);
jkff f3(1,1,r,q[1],q[2],qo[2]);
jkff f4(1,1,r,q[2],q[3],qo[3]);
endmodule

TEST BENCH:
module downtest;
/ Inputs
reg clk;
reg ;
/ Outputs
wire [3:0] qo;

/ Bidirs
wire [3:0] q;
upcounter uut (
.clk(clk),
.r(r),
.q(q),
.qo(qo)
);
initial begin
clk = 0;
r =0;
 end
always
begin
#10 clk=~clk;
end
endmodule

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORM:

ASYNCHRONOUS DOWN COUNTER:

CIRCUIT DIAGRAM:
VERILOG CODE:

module jkff(
input j,
input k,
input r,
input clk,
output reg q,
output qo
);
initial
begin
q<=0;
end
always@ (posedge clk or posedge r)
if(r)
begin
q<=1'b0;
end
else
begin
case({j,k})
2'b00 : q<=q;
2'b01 : q<=1'b0;
2'b10 : q<=1'b1;
2'b11 : q<=~q;
endcase
end
assign qo =~q;
endmodule
module downcounter
 (input clk,
input r,
inout [3:0]q,
inout [3:0]qo);

//and(r,q[0],q[1],qo[2],q[3]);
jkff f1(1,1,r,clk,q[0],qo[0]);
jkff f2(1,1,r,qo[0],q[1],qo[1]);
jkff f3(1,1,r,qo[1],q[2],qo[2]);
jkff f4(1,1,r,qo[2],q[3],qo[3]);
endmodule

TEST BENCH:

module downtest;
/ Inputs
reg clk;
reg r;
/ Outputs
wire [3:0] qo;
/ Bidirs
wire [3:0] q;
downcounter uut (
.clk(clk),
.r(r),
.q(q),
.qo(qo)
);
initial begin
clk = 0;
r =0;
end
always
begin
#10 clk=~clk;
end
endmodule

RTL SCHEMATIC DIAGRAM:

OUTPUT WAVEFORM:

RESULT:
The asynchronous up and down counter is successfully design and simulated using xilinx
14.7.