Sequential Logic Circuits

• Sequential circuits
– primitive sequential elements
– combinational logic
• Models for representing sequential circuits
– finite-state machines (Moore and Mealy)
– representation of memory (states)
– changes in state (transitions)
• Basic sequential circuits
– shift registers
– counters
• Design procedure
– state diagrams
– state transition table
– next state functions
Classification of Digital Circuits
• Combinational logic circuits.
– Output depends only on present input.
• Sequential circuits.
– Output depends on present input and present
state of the circuit.
 Combinational vs. Sequential Logic

In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit

State

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

Sequential Circuits
Sequential Circuits:
• Circuits require memory to store intermediate data,
• Sequential circuits use a periodic signal to
determine when to store values. clock signal can
determine storage times.Clock signals are periodic
• Single bit storage element is a flip flop
A basic type of flip flop is a latch
Latches are made from logic gates
NAND, NOR, AND, OR, Inverter
Sequential Circuits
Design steps
 Sequential Circuits
Inputs Combinational Outputs
circuit Flip
Next Flops
state Present
state

Timing signal
(clock)
Clock
a periodic external event (input)
Clock
•synchronizes when current state changes happen
•keeps system well-behaved
•makes it easier to design and build large systems
 Latches and Flip-Flops
• A latch is a temporary storage device that
has two stable states (bistable). It is a basic
form of memory
• The sequential devices differ in the way
their outputs are changed:
– The output of a latch changes independent of a
clocking signal.
– The output of a flip–flop changes at specific
times determined by a clocking signal.
 S-R Latch
• SR latch based on NOR gates.
• The S input sets the Q output to 1 while R reset it
to 0.
• When R=S=0 then the output keeps the previous
value.
• When R=S=1 then Q=Q’=0, and the latch may go
to an unpredictable next state.
 S-R Latch
• S’R’ latch based on NAND gates.
• The S’ input sets the Q output to 1 while R’ reset
it to 0.
• When R’=S’=1 then the output keeps the previous
value.
• When R’=S’=1 then Q=Q’=1, and the latch may
go to an unpredictable next state.
 S-R Latch
• The S-R (Set-Reset) latch is the most basic type.
• It can be constructed from NOR gates or NAND gates.
• With NOR gates, the latch responds to active-HIGH
inputs; with NAND gates, it responds to active-LOW
inputs.
 S-R Latch with control input (Clocked SR Latch)
Gated SR Latch

Occasionally, desirable to avoid latch changes

C = 0 disables all latch state changes
Control signal enables data change when C = 1
 Clock Pulse Definition
Positive Pulse Negative Pulse

Positive Negative Negative Positive

Edge Edge Edge Edge

Edges can also be referred to as leading and trailing.

 SR Latch Characteristics
0d SR d0
10
0 1
Excitation Present Next
01
inputs state state
S R Q Q* (b)

0 0 0 0 No change
SR S
0 0 1 1
0 1 0 0 Reset Q 00 01 11 10
0 1 1 0
1 0 0 1 Set 0 0 0 Ð 1
1 0 1 1
1 1 0 Not allowed
1 1 1 Q 1 1 0 Ð 1

(a)
R
(c)

Q* = S + R Q
 Gated D Latch (D flip-Flop)
Q0 indicates the previous state (the previously stored value)
X
D S
Q
C

Q’

Y R
X Y C Q Q’
D C Q Q’
0 0 1 Q0 Q0’ Store ( previous state)
0 1 0 1 0 1 1 0 1 Reset
1 1 1 0 1 0 1 1 0 Set
X 0 Q0 Q0’ 1 1 1 1 1 Not allowed
X X 0 Q0 Q0’ Store
 D flip-Flop
X
D S
Q
C

Q’

Y R
D C Q Q’
0 1 0 1
1 1 1 0
X 0 Q0 Q0’

Input value D is passed to output Q when Clock is high

Input value D is ignored when Clock is low

 D flip-Flop Latches on following
edge of clock

CLK

D Q D
CLK
Q

Q only changes when E is high

If CLK is high, Q will follow D

 D flip-Flop Latches on following
edge of clock

CLK
D Q D
CLK
Q

The D latch stores data indefinitely, regardless of input D

values, if CLK = 0
Forms basic storage element in computers
 Characteristic Equations
• algebraic descriptions of the next-state table
of a flip-flop
• constructing from the Karnaugh map for
Qt+1 in terms of the present state and input
 D Latch Characteristics
Enable Excitation Present Next
input input state state
C D Q Q*
0 0 0 Hold
0 ´ 1 1 0d, 10 CD 0d, 11
1 0 0 0 Store 0
1 0 1 0 11
1 1 0 1 Store 1 0 1
1 1 1 1
10
(a) (b)

Q* = DC + C Q

With clk is high Q* = D

 Symbols for Latches

SR latch is based on NOR gates

S’R’ latch based on NAND gates

D latch can be based on either.

D latch sometimes called delay latch

 D Flip-Flop
Stores a value on the positive edge of Clk
Input changes at other times have no effect on output

Positive edge triggered

D C Q Q’
D Q
0 0 1
C Q’ 1 1 0
X 0 Q0 Q0’

D gets latched to Q on the rising edge of the clock.

 Master-Slave D Flip Flop
Consider two latches combined together
Only one Clk value active at a time
Output changes on falling edge of the clock
 Clocked D Flip-Flop
Stores a value on the positive edge of C
Input changes at other times have no effect on output
 Edge Triggered J-K Flip-Flop

• The operation of inputs J and K in the J-K flip-flop is similar

to the operation of inputs S and R in the S-R flip-flop.
• The difference arises when J and K are asserted
simultaneously.
• In this situation the output of the J-K flip-flop inverts its
current state.
 Edge Triggered J-K Flip-Flop

• The J-K flip-flop is more versatile than the D flip flop.

• In addition to the clock input, it has two inputs, labeled J
and K.
• When both J and K = 1, the output changes states (toggles)
on the active clock edge (in this case, the rising edge).
 Timing diagram for JK Flip-flop
Negative Edge Triggered

cloc
k

toggle hold reset set

J=K=1 J=K=0 J= 0 J= 1
 Clocked J-K Flip Flop
Two data inputs, J and K
J -> set, K -> reset, if J=K=1 then toggle output

Characteristic Table
Characteristic equation of JKFF
Master-slave JK flip-flop
 Edge Triggered J-K Flip-Flop
• of the clock (for example the D or J-K
inputs).
• Most flipflops have other inputs that are
asynchronous, meaning they affect the
output independent of the clock.
• Two such inputs are normally labeled
preset (PRE) and clear (CLR).
• These inputs are usually active LOW.
• A J-K flip flop with active LOW preset
and CLR is shown.
 T Flip-Flop
• Also known as the toggle flip-flop.
• When input T = 0 the output Q retain its previous
value.
• When input T = 1 the output Q inverts on every
tick of the clock.
• When inputs J and K of a J-K flip-flop are
connected together, the J-K flip-flop will behave
like a T flip-flop.
 Positive Edge-Triggered T Flip-Flop

Created from D flop CL T Q Q’

T=0 -> keep current K
K resets 0 Q Q’
T=1 -> invert current 1 TOGGLE
 Asynchronous Inputs

• J, K are synchronous inputs Effects on the output are synchronized with

the CLK input.
• Asynchronous inputs operate independently of the synchronous inputs
and clock
Set the FF to 1/0 states at any time.
Flip-flop Characteristics
Summary
 Asynchronous sequential circuit
• This is a system whose outputs depend upon the order in
which its input variables change and can be affected at any
instant of time.
• Gate-type asynchronous systems are basically combinational
circuits with feedback paths.
• Because of the feedback among logic gates, the system may, at
times, become unstable.
• Consequently they are not often used.
 Synchronous sequential circuits
• Synchronous sequential circuits use logic gates and flip-flop
storage devices. Synchronization is achieved by a timing
device called a clock pulse generator.
• Sequential circuits have a clock signal as one of their inputs.
• All state transitions in such circuits occur only when the clock
value is either 0 or 1 or happen at the rising or falling edges of
the clock depending on the type of memory elements used in
the circuit.
• Clock pulses are distributed throughout the system in such a
way that the flip-flops are affected only with the arrival of the
synchronization pulse.
• Synchronous sequential circuits that use clock pulses in the
inputs are called clocked-sequential circuits.
• They are stable and their timing can easily be broken down
into independent discrete steps, each of which is considered
separately.