IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 7, NO.

2, JUNE 2019 1329

Transformerless Hybrid Converter With AC and DC

Outputs and Reduced Leakage Current
Somdut Dey, Vinod Kumar Bussa , Student Member, IEEE, and R. K. Singh , Senior Member, IEEE

Abstract— In photovoltaic (PV) generation systems, due to

the high efficiency, compactness, and low costs, transformerless
hybrid converters with ac and dc outputs have become pop-
ular in recent times. However, common-mode leakage current
occurs in these converters when the converter neutral point is
grounded or it is tied to the grid. The presence of leakage cur-
rent causes considerable safety and electromagnetic interference
problem along with the improper operation of safety devices.
This paper proposes a transformerless hybrid converter capable
to give simultaneous ac and dc outputs with reduced leakage
current for the PV system. In order to ensure the reduced leakage
Fig. 1. Micorgrid architecture based on hybrid power converter with
current for all operating states (power, shoot through, and LF transformer.
zero) of the proposed converter, a novel pulsewidth modulation
(PWM) switching scheme is also introduced in this paper. As the
proposed hybrid converter can provide both dc and ac outputs,
it can supply both dc and ac loads simultaneously. The detailed
steady state analysis and dynamic modeling of the proposed
hybrid converter is carried and discussion on the developed
PWM technique for reducing the leakage current is presented
in this paper. A comparative analysis between the proposed and
conventional converters is also carried out. The performance of
the proposed algorithm is validated through experimental results.
Index Terms— Leakage current, microgrid, shoot-through
operation, transformerless hybrid converter.
Fig. 2. Micorgrid architecture based on hybrid power converter without LF
transformer.
I. I NTRODUCTION

I N RECENT times, photovoltaic (PV) technology has

become one of the fastest growing and most prevalent
clean energy resources [1]–[4]. Modern architecture of a
into reduced current between the PV panel and ground [8].
However, the LF transformer is bulky and increases size,
weight, and cost of the overall system. Moreover, the presence
hybrid microgrid use hybrid boost converters capable to give
of the LF transformers also reduces the efficiency of the
simultaneous ac and dc outputs [5]–[7]. The two possible
system. The weight and the volume of the system can be
architectures for the hybrid microgrid are: 1) architecture
reduced by using a high-frequency (HF) transformer in the
with galvanic isolation using transformer between PV system
power conversion stage. However, due to the inclusion of
and ac output and 2) transformerless architecture, i.e., no
the HF transformer, the power conversion stage becomes
transformer is placed between PV system and ac output.
complex and there is no significant improvement in the overall
Fig. 1 shows microgrid architecture based on hybrid power
efficiency of the system.
converter with galvanic isolation. This architecture uses low-
Due to the challenges associated with the LF and HF
frequency (LF) transformer to interface PV system with the
transformers, the transformerless converters for PV system
local ac load or grid and it gives both dc and ac outputs
have gotten attention of late, because of its compactness and
in one single unit. The LF transformer provides galvanic
lower volumetric size [9]. However, in these converters, if the
isolation between the PV system and ac ground, which results
converter neutral point is grounded or it is tied to the grid,
Manuscript received January 14, 2018; revised April 15, 2018; accepted HF common-mode voltage appears across the PV-to-ground
November 15, 2018. Date of publication November 26, 2018; date of current capacitance that leads to a strong flow of leakage current
version May 1, 2019. Recommended for publication by Associate Editor (ground current). Fig. 2 shows modern microgrid architecture
Dragan Maksimovic. (Corresponding author: R. K. Singh.)
The authors are with the Department of Electrical Engineering, based on hybrid power converter without galvanic isolation.
IIT (BHU) Varanasi, Varanasi 221005, India (e-mail: somdutdey@gmail.com; It may be observed from Fig. 2 that a strong ground current
vinod.rs.eee14@iitbhu.ac.in; rksingh.eee@iitbhu.ac.in). flows which give an adverse effect to human safety [10],
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. due to the absence of a bulky LF transformer. Furthermore,
Digital Object Identifier 10.1109/JESTPE.2018.2883243 the flow of large leakage current may also trip the ground
2168-6777 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1330 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 7, NO. 2, JUNE 2019
current/fault monitoring system. Thus, for ensuring equipment
and personnel safety, the leakage current must be minimized
below certain level [11].
In order to minimize the leakage current flow, several
topologies have been reported in [12]–[18]. A family of neutral
point clamped full bridge topologies are reported in [19] to
reduce the leakage current in transformer less topologies.
Minimization of leakage current in the single phase ac–dc
full bridge inverter is discussed in [20]. It is observed that
the transformerless topologies with reduced leakage current
are single output inverters and these do not give regulated
dc and ac power simultaneously. Thus, the existing convert-
ers with reduced leakage current are not applicable to the
PV powered hybrid microgrid which gives more number of
ac and dc outputs.
The transformerless hybrid converter proposed in this paper
minimizes leakage current below the specified limit and gives
simultaneous dc and ac outputs. In order to reduce the leakage
current, a novel pulsewidth modulation (PWM) switching
scheme is introduced to ensure the total common-mode voltage
equal to zero for all the operating states (power, shoot through,
and zero) of the proposed hybrid converter. Detailed dynamic
modeling and closed loop analysis for both dc and ac outputs
are carried out to demonstrate the properties of the proposed
converter.
Section II of this paper deals with the mathematical model-
ing of the leakage current. Description of switching conditions
of the PWM scheme for minimization of leakage current in
hybrid converters is given in Section III. Section IV describes
the proposed hybrid converter with reduced leakage current.
Dynamic modeling and closed loop operation of the proposed
hybrid converter is discussed in Section V. Verification of
the proposed concept through experimental results is done in
Section VI. Finally, conclusions are drawn in Section VII.
Note that, in this paper, instantaneous values are represented
by lower case letters, dc and RMS values are represented by
upper case letters, ac components are represented by lower
case letter with tilde (∼), and lower case letter with sub-script
pk [(-)pk ] represents peak value.
II. R EVIEW OF M ATHEMATICAL M ODELING
OF L EAKAGE C URRENT
Due to the large conducting surface of the PV panel,
a capacitor is formed between the PV panel and grounded
metal frame which holds the panel. This capacitor is called
PV to ground parasitic capacitor (CPVg ). The value of this
capacitor depends on mounting technique used, PV cell man-
ufacturing process, weather condition such as rain, humidity,
dust, and so on, and its value could be 0.1 μF/kW system.
As the inverter neutral is grounded, due to HF switching,
high (dv/dt) is impressed across the CPVg resulting into flow
of leakage current. The flow of leakage current increases
overall system loss and electromagnetic interference (EMI),
brings distortion in output current, and causes safety problem
to the personnel working at PV panel area. According to the
DIN VDE 0126-1-1 standard, for personal safety, a residual
current-monitoring device (RCMD) is essential in transformer
less inverter [4]–[10]. RCMD should monitor ground current,
Fig. 3. Single-phase neutral grounded inverter with parasitic parameters.
Fig. 4. Simplified common-mode model for frequency <50 KHz. (a) Inter-
mediate step before obtaining the simplified common mode model. (b) Final
common mode model.
and if ground current is more than the 300 mA, the inverter
should be disconnected within 0.3 s of detection. In this
section, the generalized model of leakage current is presented
for the single-phase full bridge inverter shown in Fig. 3. It can
be observed that Fig. 3 represents a single phase inverter
with parasitic parameters and a common-mode EMI filter. The
filter inductor is split into two parts (L 1 and L 2 ) so that the
developed model can be applied to any other inverter topology
(symmetrical or asymmetrical filter-based topology).
If negative terminal of PV panel N is taken as a reference,
then the output of the inverter bridge is terminals 1 and 2 as
shown in Fig. 3. Then, the common-mode voltage (v cm ) and
the differential mode voltage (v dm ) of the inverter can be
defined as
v 1N + v 2N
v cm = (1)
2
v dm = v 1N − v 2N = v 12 . (2)
From (1) and (2), v 1N and v 2N can be written as
v dm
v 1N = v cm + (3)
2
v dm
v 2N = v cm − . (4)
2
To develop a simplified leakage current model, which is valid
for medium frequency range (<50 kHz), the circuit repre-
sented in Fig. 3 can be converted into Thevenin’s equivalent
circuit [3] across CPVg and is given in Fig. 4(a) and (b).
It is clear from Fig. 4(a) and (b) that v tcm = v cm + v s1 ,
where v S1 = v dm ((L 2 − L 1 )/(2(L 2 + L 1 ))) and v tcm acts as a
voltage source of leakage current. If there is no HF component,
then voltage across the CPVg is constant in the common-mode
HF (<50 kHz) model.
DEY et al.: TRANSFORMERLESS HYBRID CONVERTER WITH AC AND DC OUTPUTS AND REDUCED LEAKAGE CURRENT
TABLE I
D EVELOPING C ONDITIONS FOR R EDUCED L EAKAGE
C URRENT D URING P OWER S TATE
III. S WITCHING C ONDITIONS OF PWM S CHEME FOR
M INIMIZATION OF L EAKAGE C URRENT IN
THE H YBRID C ONVERTERS
In the hybrid converters [5], PWM techniques consist of
three operating states, 1) shoot-through state; 2) zero state;
and 3) power state. During the shoot-through state one of the
legs of the inverter bridge is shorted. In boost derived hybrid
converter [5]–[7], the shoot-through state defines duty cycle
for the dc operation of the output voltage. In the middle of
the nonshoot-through operation, a sinusoidally modulated
pulse is included for extracting ac power. While the ac power
is not being drawn, filter inductor current must freewheel
and this state is called zero state. During shoot-through
state, v 1N and v 2N are equal to zero which results into
v tcm = v cm + v dm ((L 2 − L 1 )/(2(L 2 + L 1 ))) = 0. The PWM
technique existing for hybrid converter in the literature
has oscillating v tcm . The aim of this section is to develop
switching operation for the proposed hybrid converter so that
v tcm is equal to zero for all the operating states, i.e., shoot
through, zero, and power states. During zero state, if filter
inductor current is freewheeled through lower two switches
of the inverter bridge of the proposed hybrid converter, then
v 1N and v 2N will become zero and v tcm will become zero.
During power state, v cm is always VPV /2 because for positive
half cycle v 1N = VPV and v 2N = 0, and for negative half
cycle v 1N = 0 and v 2N = VPV . Thus, to make v tcm = 0,
v S1 (= v dm ((L 2 − L 1 )/(2(L 2 + L 1 )))) must be equal
to −VPV /2. Voltage v S1 depends on filter configuration,
which could be one of the following types:
1) when L 1 = L 2 = L f (say);
2) when L 1 (= L f ) is present and L 2 = 0;
3) when L 1 = 0 is present and L 2 (= L f ).
Voltage v S1 for different configuration of filter inductor is
given by
⎧ S1 , S4 , and S5 are kept ON and S2 , S3 , and S6 are kept OFF.
⎨
⎨ 0, L1 = L2 = L f
⎨
⎨ v dm
v S1 = − 2 , L 1 = L f ; L 2 = 0 (5)
⎨
⎨ v dm
⎨
⎩+ , L 1 = 0; L 2 = L f .
2 and current i L2 is zero. Similarly, it may be observed from
Voltage v dm = v 1N − v 2N is either VPV or −VPV depend-
ing upon the positive or negative half cycles, respectively.
If L 1 = L f and L 2 = 0 during positive half cycle and
L 1 = 0 and L 2 = L f during negative half cycle, then v tcm
would become zero. It can be noticed from Table I that for
condition 2 (L 1 = L f and L 2 = 0) during positive half cycle
1331
Fig. 5. Proposed transformerless hybrid converter with ac and dc outputs
and reduced leakage current.
and condition 3 (L 1 = 0 and L 2 = L f ) during negative
half cycle, v tcm becomes equal to zero, thereby reducing the
leakage current. Thus, the leakage current can be reduced by
operating the proposed hybrid converter as follows.
1) AC filter inductor current must freewheel through the
lower two switches of the inverter bridge.
2) The value of L 2 = 0 for positive half cycle and L 1 = 0
for negative half cycle.
It is important to mention that the developed PWM tech-
nique is implemented on the hybrid converter proposed in this
paper (discussed in Section IV) in order to reduce the leakage
current and obtain simultaneous dc and ac outputs.
IV. P ROPOSED H YBRID C ONVERTER W ITH
R EDUCED L EAKAGE C URRENT
The proposed transformerless hybrid converter with reduced
leakage current is shown in Fig. 5. The topology shown
in Fig. 5 gives simultaneous ac and dc outputs and is designed
to adapt the proposed PWM discussed in Section III.
The proposed PWM ensures total common-mode voltage
equal to zero in the proposed hybrid converter and therefore,
the leakage current is reduced while operating with PV system.
The detailed operation of the proposed hybrid converter with
leakage current minimization is explained in the following
subsections.
A. Modes of Operation of the Proposed Hybrid Converter
1) Shoot-Through State: The operation of the proposed
transformerless hybrid converter during the shoot-through state
for v ac > 0 and v ac < 0 is shown in Fig. 6(a) and (b),
respectively. It is clear from Fig. 6(a) that for v ac > 0,
Meanwhile, the diode D is reverse biased. During this state,
inductor (L) current i L rises and capacitor Cdc discharges
through the dc load resistance Rdc . Current i L1 freewheels
through the switch S5 and antiparallel diode of the switch S4
Fig. 6(b) that for v ac < 0, S1 , S4 , and S5 are kept OFF
and S2 , S3 , and S6 are kept ON. Meanwhile, the diode D is
reverse biased. In this state also current i L keeps on rising and
capacitor Cdc discharges through the dc load resistance Rdc .
Current i L2 freewheels through the switch S6 and anti-parallel
diode of the switch S2 and current i L1 is zero.
1332 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 7, NO. 2, JUNE 2019
Fig. 6. Operating modes of the proposed hybrid converter in shoot-through
state: (a) for v ac > 0. (b) for v ac < 0.
Fig. 7. Operating modes of the proposed hybrid converter in zero state.
(a) for v ac > 0. (b) for v ac < 0.
2) Zero State: The operation of the proposed transformer-
less hybrid converter during zero state for v ac > 0 and v ac < 0
is shown in Fig. 7(a) and (b), respectively. It is clear from
Fig. 7(a) that for v ac > 0, S5 is kept ON and S1 , S2 , S3 , S4 ,
and S6 are kept OFF. During this state, current i L decreases
and capacitor Cdc charges by diode current i D . Current i L1
freewheels through the switch S5 and anti-parallel diode of the
switch S4 and current i L2 remains zero. Similarly, it is clear
from Fig. 7(b) that for v ac < 0, S6 is kept ON and S1 , S2 ,
S3 , S4 , and S5 are OFF. During this state, current i L decreases
Fig. 8. Operating modes of the proposed hybrid converter in power state.
(a) for v ac > 0. (b) for v ac < 0.
and capacitor Cdc charges by diode current i D . Current i L2
freewheels through the switch S6 and anti-parallel diode of
the switch S2 and current i L1 is zero.
3) Power State: The operation of the proposed transformer-
less hybrid converter during power state for v ac > 0 and
v ac < 0 is shown in Fig. 8(a) and (b), respectively. It may be
observed from Fig. 8(a) that for v ac > 0, S1 and S5 are kept
ON and S2 , S3 , S4 , and S6 are kept OFF . During this state,
i L decreases, Cdc charges by diode current i D , current i L1
supplies the ac load, and i L2 remains zero. Similarly, it may
be noticed from Fig. 8(b) that for v ac < 0, S3 and S6 are kept
ON and S1 , S2 , S4 , and S5 are kept OFF . During this state,
current i L decreases, capacitor Cdc charges by diode current
i D , i L2 supplies the ac load, and current i L1 is zero.
B. Minimization of Leakage Current
Fig. 9(a) and (b) show PWM signals for v ac > 0 and
v ac < 0, respectively, and Fig. 9(c) shows inductor cur-
rent (i L ), diode current (i D ), and switched node current (i SN ).
Based on the PWM signals shown in Fig. 9(a) and (b),
complete switching pattern along with the values of v cm and
v dm of the proposed hybrid converter for zero, power, and
shoot-through states is tabulated in Table II. Table III is derived
from the results of Table II and gives the values of the total
common-mode voltage v tcm in all the operating states of the
proposed hybrid converter. It can be observed from Table III
that the total common-mode voltage v tcm is constant and equal
to zero in the HF leakage current model. This ensures the
reduced leakage current in the proposed transformerless hybrid
converter.
C. DC and AC Voltage Gains and Their Load Powers
In the proposed transformerless hybrid converter, the output
dc voltage can be controlled by varying the shoot through duty
DEY et al.: TRANSFORMERLESS HYBRID CONVERTER WITH AC AND DC OUTPUTS AND REDUCED LEAKAGE CURRENT 1333

Fig. 9. Switching waveforms: (a) PWM signals for positive half cycle of ac output voltage, v ac > 0. (b) PWM signals for negative half cycle of ac output
voltage, v ac < 0. (c) Inductor current (i L ), diode current (i D ), and switch node current (iSN ) for v ac > 0.

TABLE II
C OMPLETE S WITCHING S TATES OF THE P ROPOSED C ONVERTER

TABLE III
T OTAL C OMMON -M ODE V OLTAGE T HROUGH OUT THE S WITCHING C YCLE

ratio (D). The output dc voltage expression is same as boost The peak output ac voltage is a function of both modulation
converter and is given by index (Ma ) and D. The expression for the peak output ac
voltage is given by
VPV
Vdc = (6) (V ac )pk = Ma Vdc (7)
1− D
Ma V P V
(V ac )pk = . (8)
where Vdc = average output voltage at the dc side. 1− D
1334 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 7, NO. 2, JUNE 2019

As the same set of switches control the dc and ac output as I L ,pk−pk of the average current and LF output voltage
voltages, the following constraint exists on Ma and D for the ripple equal as V dc,pk−pk of average dc output voltage (Vdc ).
proposed hybrid converter: Limiting LF oscillation was the main design criteria. From the
chosen specifications of the proposed topology, the L and Cdc
Ma + D ≤ 1. (9)
can be designed to satisfy (20) by assuming V dc,pk−pk and
The dc output power of the proposed hybrid converter is given I L ,pk−pk .
by The ac side passive (L f and C f ) components are design
based on the corner frequency of L f and C f , and switching
(VPV )2
Pdc = . (10) frequency of the controlled switches. To design the ac side
Rdc (1 − D)2 passive components, corner frequency is chosen to be kept
Instantaneous ac output power ( pac ) is given by at ( f sw /9), where f sw is switching frequency. It gives enough
attenuation at 10 KHz switching frequency
pac = (v ac ) × (i ac ) (11)
1 f sw
(Vac )2  = . (21)
Pac = (12) 2π L f C f 9
Rac
(Vac )2pk (sin ωt)2 Therefore, the ac side passive components can be chosen to
pac = (13) satisfy (21).
Rac
(Vac )2pk (1 − cos 2ωt)
pac = (14) E. Power Loss Analysis of the Proposed Converter
2Rac
(Vac )2pk (Vac )2pk Power losses in the proposed converter occur due to con-
pac = − cos 2ωt. (15) duction and switching states of the semiconductor devices, and
2Rac 2Rac
due to losses in the passive components [24], [25].
Instantaneous ac power pac contains steady state component 1) Conduction Losses in the Semiconductor Devices: The
as well as time varying ac component. The steady state power dissipation during conduction is computed by multiply-
component is the real power consumed by the load and ing the ON-state voltage and the ON-state current. In PWM
is denoted by Pac . The time varying ac component of the converters, the conduction loss for the controlled switches
instantaneous power is denoted by p̃ac and is given by (insulated-gate-bipolar transistors (IGBTs) are considered in
(v ac )2pk this paper) must be multiplied by the duty factor to obtain the
p̃ac = cos 2ωt (16) average power dissipation as given in the following equation:
2Rac
= Pac − p̃ac .
pac (17) 1 T
Pavg,cond = VCE,Sat (t) ∗ i CE (t)d x (22)
Furthermore, if I L is the average inductor (L) current, then T 0
Pdc + Pac where VCE,Sat is the ON state saturation voltage of an IGBT
IL = . (18) and i CE is the instantaneous current flowing through the IGBT.
VPV
Conduction loss for the diode D can be calculated as
Component p̃ac is balanced by i L and capacitor (Cdc ) volt- follows:
age v dc ; therefore, inductor current (i L ) and capacitor voltage
(v dc ) contain LF ripple (twice the ac output voltage frequency). PD,avg,cond = V D I D (23)
The power balance equation is given by
  where V D is diode forward voltage drop and I D is average
d 12 Cdc v dc
2 + 1 Li 2
L diode current. For the conduction losses of the semiconduc-
p̃ac = 2
(19)
dt tor devices, the conduction sates of the devices are shown
Pac in Fig. 10.
L I L I L ,pk−pk + C Vdc V dc,pk−pk = . (20)
ω 2) Switching Losses in the Semiconductor Devices: In
LF ripples in the output dc voltage as well as in inductor power electronics switching losses typically contribute a sig-
current increases with an increase in ac load current. By sim- nificant amount to the total system losses. Switching losses
plifying (19), (20) is obtained and it can be observed from (20) occurred because the transitions from ONstate to OFFstate and
that if Pac increases, LF ripples V dc,pk−pk and I L ,pk−pk vice versa, do not occur instantaneously. During the transition
increases. Values of L and Cdc can be designed using (20). intervals, both the current through and the voltage across the
device are substantially larger than zero, which leads to large
instantaneous power loss. The switching power losses in the
D. Design of Passive Elements
controlled switches are calculated based on the normalized
The dc side passive components (L and Cdc ) are designed values (provided in the manufactures datasheet) as follows:
based on (20). Due to the presence of single-phase inverter
system in the proposed topology, there is LF oscillation PSw
(2 ∗ 50 = 100 Hz) in the both the dc output voltage and (E ON + E OFF )Vdc × average current through IGBT × f sw
=
the input inductor current. For designing L and Cdc , consider Vnom Inom
the LF allowable ripple in the input inductor (L) current (24)
DEY et al.: TRANSFORMERLESS HYBRID CONVERTER WITH AC AND DC OUTPUTS AND REDUCED LEAKAGE CURRENT 1335

Fig. 11. Inductor current and voltage sensing of ac output of the proposed
hybrid converter.

Fig. 10. Conduction time period of various semiconductor devices

(ST = Shoot through state, Z = Zero state, P = Power state, and Tsw = HF
switching time period).

where Vnom = normalized voltage, Inom = normalized current,

E ON = turn ON switching energy loss, and E OFF = turn Fig. 12. Circuit of proposed hybrid converter referred to ac side.
OFF switching energy loss known from the manufacturer’s
datasheets of the devices.
Switching losses of the diode D are due to reverse recovery Fig. 11 shows filter inductor current and ac output voltage
energy, which can be calculated as follows: sensing of the proposed hybrid converter. It may be observed
E rec Vdc × I D−pk × f sw from Fig. 11 that, during the positive half cycle, i Lf flows
PSwD = (25) through inductor L 1 and, during negative half cycle, it flows
Vnom I  nom
through inductor L 2 . Fig. 12 represents the circuit diagram
where E rec = reverse recovery energy and I D− pk = diode of the converter referred to the ac side. L f represents L 1
peak current. during positive half cycle and L 2 during negative half cycle.
3) Power Losses in the Passive Components: The power Voltage v inv can take three values Vdc , 0 or −Vdc . Pulsewidth
losses of inductors include core losses and winding losses. of these voltage levels are modulated by reference signal given
Generally, the core losses are negligible for pulsewidth modu- to the PWM block.
lated converters [24], [25]. The winding losses depend on the By applying Kirchhoff’s voltage and current law in Fig. 12,
windings resistance (r L ) of inductors L and are calculated as the following can be obtained:
follows:
di Lf r vc f Vdc
2
Pwind_L = r L I L(rms) . (26) =− i Lf − + ma (28)
dt Lf Lf Lf
The power losses of the capacitors depend on the equivalent dv c f vc f
Cf = i Lf − . (29)
series resistances (rC ) and are calculated as follows: dt Rac

1 Ts For αβ − dq transformation, β components are generated by
PC = rC i C2 dt. (27)
Ts 0 delaying α components by 90◦ . αβ − dq transformations are
done using following transformation matrix:
V. DYNAMIC M ODELING AND C LOSED L OOP C ONTROL



Xd cos ωt sin ωt Xα
The proposed transformerless hybrid converter consists of = . (30)
Xq − sin ωt cos ωt Xβ
two controllers for regulating the dc and ac outputs. For
regulating ac output, dq control method is used and Type-3 After αβ − dq transformation of (28) and (29), the following
compensator is used to regulate the dc output of the proposed is obtained:
hybrid converter.




d iLf d 0 ω iLf d r iLf d
= −
dt i L f q −ω 0 iLf q L f iLf q
A. dq Modeling of the Proposed Converter


1 vc f d m d Vdc
− + (31)
In dq control of ac output voltage, two-time variant quanti- L f vc f q mq L f
ties, i.e., ac output voltage and filter inductor current are sensed




d vc f d 1 iL f d 0 ω vc f d
and αβ −dq transformation is applied to make control scheme = +
easier [21], [22]. Due to αβ − dq transformation, sensed ac dt v c f q C f iL f q −ω 0 vc f q


voltage and filter inductor current become dc time invariant in 1 vc f d
− . (32)
dq domain. C f Rac v c f q
1336 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 7, NO. 2, JUNE 2019

Fig. 13. Closed loop ac control structure (Vd = Vc f d , Vq = Vc f q , Id = I L f d , and Iq = I L f q ).

Fig. 14. Bode plots: (a) AC outer voltage controller. (b) AC inner current controller. (c) DC Voltage controller.

Taking Laplace transformation of (31) and (32), inner current
loop and outer voltage loop transfer function are given by
I L f d (s) I L f q (s) 1 =
= =
Uid (s) Uiq (s) r + sL f
Vc f d (s) Vc f q (s) Rac
= =
Uvd (s) Uvq (s) Rac C f + 1
where
Uid (s) = Md (s)V Dc + ωL f I L f q (s) − v c f d (s)
Uiq (s) = Mq (s)V Dc + ωL f I L f q (s) − v c f q (s)
Uvd (s) = I L f d (s) + ωC f Vc f q (s)
Uvq (s) = I L f q (s) − ωC f Vc f d (s).
Closed loop control structure for ac output of the proposed
hybrid converter is given in Fig. 13. To design a controller
for outer ac voltage loop, a Type-2 controller is used to have
adequate gain and phase margin. Fig. 14(a) shows a bode
plot for uncompensated and compensated ac voltage loop.
It can be observed from Fig. 14(a) that for voltage loop, phase
margin = 84.2◦ and bandwidth = 578 Hz are achieved.
Fig. 14(b) shows bode plot for uncompensated and compen-
sated inner current loop, and it is clear that phase margin = 90°
and bandwidth = 3 kHz are achieved.
B. DC Side Voltage Controller
The control-to-output transfer function of the proposed
hybrid converter is same as that of the conventional boost
converter [26] and is given by
ṽ dc Vdc D  − s L Vdc
D  Rdc
. (35)
s 2 LCdc + 2
Rdc + D
sL
(33) d̃
The type-3 controller is used to get gain margin = 20 dB
(34) and phase margin = 61.8°. Fig. 14(c) shows bode plot
of uncompensated and compensated system for dc output.
It may be observed from Fig. 14(c) that the phase margin for
uncompensated and compensated system is −19.5° and 61.8°,
respectively. It is also clear from Fig. 14(c) that the gain
margin for uncompensated and compensated system is
−45.8 dB and 20 dB, respectively.
VI. E XPERIMENTAL V ERIFICATION
The proposed transformerless hybrid converter with
reduced leakage current is validated through experimentation
on 300 W laboratory prototype. Fig. 15 shows the overall
implementation of the proposed algorithm. Fig. 16 shows the
photograph of the experimental set up. According to [23], the
PV-to-ground capacitance for the glass-face modules should
be 50–150 nF/kW and 1 μF/kW for thin-film modules in
damp environment. In this paper, for experimental analysis,
the value of CPVg (shown in Fig. 5) is taken equal to 110 nF.
A. Steady-State Performance of the Proposed Hybrid
Converter at Low Power Operating Condition
The steady state performance of the proposed trans-
formerless hybrid converter is validated for the following
DEY et al.: TRANSFORMERLESS HYBRID CONVERTER WITH AC AND DC OUTPUTS AND REDUCED LEAKAGE CURRENT
Fig. 15. Overall implementation of the proposed transformerless hybrid converter.
Fig. 16. Photograph of experimental set up.
Fig. 17. Experimental verification of PWM signals. (a) PWM signals for S1 ,
S2 , S3 , and S4 for positive half cycle of ac output voltage. (b) PWM signals
for S1 , S4 , S5 , and S6 .
specifications: input voltage to the converter VPV = 80 V,
duty ratio D = 0.36, modulation index Ma = 0.48, switching
frequency = 10 kHz, line frequency = 50Hz, L = 1120 μH,
Cdc = 1800 μF, L f (= L 1 = L 2 ) = 2 mH, and CPVg =
110 nF. Fig. 17(a) shows PWM signals given to the switches
S1 to S4 for the positive half cycle of ac output voltage and
Fig. 17(b) shows PWM signals given to the switches of one
leg, S5 and S6 . It can be seen from Fig. 17(b) that during
positive half cycle, S1 and S4 are operated and S5 is kept ON.
Fig. 18(a) shows the steady state results showing input volt-
age (VPV ), output dc voltage (Vdc ), output ac voltage (Vac ) and
leakage current (i Leakage ). It can be observed from Fig. 18(a)
that for VPV = 80 V and given reference voltages (60 V peak
for ac reference and 125 V for dc reference), the proposed
converter gives (Vac )pk = 60 V and Vdc = 125 V.
1337
Fig. 18. Closed loop steady state results. (a) VPV = 80 V, Vdc = 125 V,
(Vac )pk = 60 V, and iLeakage . (b) VPV , Vdc , Vac , and inductor current i L
containing 100 Hz component.
Fig. 19. Steady state results VPV , i L2 , iLf , and v ac . (a) For positive half
cycle (v ac > 0) filter current flows through L 1 . (b) For negative half cycle
(v ac < 0) inductor current flows through L 2 .
It can also be observed from Fig. 18(a) that the leak-
age current i Leakage is significantly small. Fig 18(b) shows
inductor (L) current (i L ), input voltage (VPV ), output dc
voltage (Vdc ), and output ac voltage (Vac ). It may be observed
from Fig. 18(b) that i L contains twice the ac line frequency
component (100 Hz) as described in Section III.
Fig. 19(a) shows that for positive half cycle of ac output
voltage (Vac ), inductor (L 2 ) current i L2 is zero because the net
filter inductor current i Lf (i Lf = i L1 in this case) is bypassed
by the switch S5 . During negative half cycle of the Vac , net
filter inductor current flows through L 2 and i L1 is equal to
zero, which is shown in Fig. 19(b).
1338 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 7, NO. 2, JUNE 2019
Fig. 20. (a) Switching waveforms of the proposed hybrid converter (PWM
signal S1 and S4 , input inductor current i L , and diode current i D ). (b) Results
confirming no HF component in voltage across CPVg and reduced leakage
current iLeakage .
Fig. 21. (a) Switching voltage stress of S1 and S4 along with i L and G S1 .
(b) Switching voltage stress of S5 and S6 along with iLf and Vac .
Fig. 20(a) shows inductor current (i L ) and diode (D)
current (i D ) profiles with PWM signals S1 and S4 for the
positive half cycle of ac output voltage (Vac > 0). It can be
seen from Fig. 20(a) that when S1 and S4 are ON (which is
shoot-through state and is equivalent to duty cycle of boost
converter), inductor current rises and diode current is zero.
When S4 and S1 are OFF, this represents zero state and
the whole inductor current flows through the D. After zero
state, S1 is turned ON and this represents power state. During
power state, it can be seen from Fig. 20(a) that there is a
sudden drop in diode current because, as the S1 is turned ON,
ac load draws current and the energy is supplied from Cdc
(also from the inductor L) to the ac load. Fig. 20(b) shows
that there is no HF (switching frequency) voltage across CPVg
which results in reduced leakage current. Fig. 21(a) shows
switching stresses of one leg (S1 and S4 ) for Vac > 0 along
with inductor current i L . It can be seen that maximum voltage
stress that appear is equal to the dc output voltage. Fig. 21(b)
shows switching stresses of switch S5 and S6 . It can be
observed that the maximum voltage stress is the peak value
of ac output voltage. Moreover, no abnormal voltage spike
has been observed in Fig. 21. Fig. 22(a) shows a zoomed-in
view of the switch node voltage VSN , output dc voltage Vdc ,
input voltage to the converter VPV , and leakage current of
the proposed converter. Further, Fig. 22(b) shows a zoomed-in
view of VPV , Vdc , VSN , and inductor current i L . It can be seen
from Fig. 22(b) that during shoot-through state, switch node
voltage is zero and inductor current rises. During nonshoot-
through state, switch node voltage equals to Vdc and inductor
current falls.
Fig. 22. (a) Switch node voltage along with leakage current profile.
(b) Inductor current i L along with the switch node voltage.
Fig. 23. Performance of the proposed hybrid converter with dynamic change.
(a) 2-A step-up change in dc load. (b) 2-A step-down change in dc load.
(c) 1-A step-up change in ac load. (d) 1-A step-down change in ac load.
B. Dynamic Performance
Fig. 23 shows the performance of the proposed transformer-
less hybrid converter for dynamic change in dc and ac loads.
Fig. 23(a) shows that for a 2-A step-up change in the dc load,
there is sink in dc output voltage which settles quickly in about
30 ms and ac output voltage remains unaffected. In the same
way, it may be seen from Fig. 23(b) that for a 2-A step-down
change in dc load, a swell is caused in the dc output voltage,
which settles in about 40 ms, and the ac voltage remains
unaffected during this operation.
Fig. 23(c) and (d) shows the dynamic response of the
proposed transformerless converter for a step change in the
ac load. It can be seen from Fig. 23(c) that for a 1-A (rms)
step-up change in the ac load current, ac load voltage (Vac )
decreases and settles quickly in about 40 ms. The dc output
remains unaffected with the step-up change in the ac load.
Similarly, it may be observed from Fig. 23(d) that for a
1-A (rms) step-down change in the ac load current, there is a
sudden rise in Vac which is restored quickly in about 30 ms.
DEY et al.: TRANSFORMERLESS HYBRID CONVERTER WITH AC AND DC OUTPUTS AND REDUCED LEAKAGE CURRENT 1339

TABLE IV
C OMPARATIVE A NALYSIS A MONG THE P ROPOSED C ONVERTER AND S OME C ONVENTIONAL T OPOLOGIES

Fig. 25. Efficiency variation with change in the load power. (a) Efficiency
versus output load with variation in ac output load. (b) Efficiency versus output
load with variation in dc output load.

C. Grid Integration of the Proposed Hybrid Converter

Fig. 24. Test results of the proposed converter for high voltage and high-
power application. (a) Grid voltage (Vac ) and current (Iac ) along with the
leakage current. (b) Grid voltage (Vac ) and output dc voltage (Vdc ), input
voltage VPV along with the leakage current Ileakage . (c) Grid voltage (Vac )
and output dc voltage (Vdc ), voltage across ground parasitic capacitor VCpvg
along with the leakage current Ileakage .
In this case, the dc output also remains unaffected. Results
in Fig. 23 confirm good cross regulation of the proposed hybrid
converter.
The test results of the proposed converter for the grid inte-
gration are shown in Fig. 24 for the following specifications:
VPV = 400 V, D = 0.5, M = 0.42, Pdc = 1200 W,
Pac = 300 W, line frequency = 50 Hz, and switching
frequency = 10 kHz. It can be noticed from Fig. 24 that there
is no HF voltage component across the capacitor CPVg , which
results in low leakage current profile in the proposed converter
at power applications.
D. Efficiency Analysis of the Proposed Converter
The efficiency of the proposed transformerless hybrid con-
verter is measured both for dc and ac load change and
is shown in Fig. 25. It may be observed from Fig. 25(a)
that the proposed converter gives maximum efficiency equal
1340 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 7, NO. 2, JUNE 2019
Fig. 26. Leakage current profile. (a) In the conventional single-phase inverter.
(b) In the conventional dual output hybrid converter.
to 94.2% for change in the ac load, while dc load remains
constant. Similarly, Fig. 25(b) shows that the converter gives
maximum efficiency equal to 94.9% for the change in the
dc load, while ac load remains constant. It is important to
mention that efficiency can be improved further by optimizing
printed circuit board, semiconductor devices, and passive
elements.
E. Verification of Leakage Current in the Conventional
Topologies and Comparative Analysis Among Some
Conventional Topologies and the Proposed Converter
Fig. 26 shows leakage current in the conventional single-
phase inverter and the conventional hybrid converter [5].
It can be observed from Fig. 26 that there is HF voltage
component across the capacitor CPVg , which results in flow
of strong leakage current. It may be observed that the leakage
current in the conventional single-phase inverter and the hybrid
converter is significantly high as compared with the leakage
current of the proposed transformerless hybrid converter as
shown in Fig. 18(a). Table IV gives comparison between
different transformerless converter topologies and the proposed
transformerless hybrid converter. It may be observed from
Table IV that the proposed hybrid converter gives ac and dc
outputs simultaneously with the reduced leakage current unlike
the conventional dual output hybrid converters.
VII. C ONCLUSION
A transformerless hybrid converter able to give simulta-
neous dc and ac outputs with reduced leakage current for
PV system is proposed in this paper. In order to ensure zero
total common-mode voltage in all the operating states (power,
shoot through, and zero) of the proposed hybrid converter and
thereby reduction in leakage current, a novel PWM technique
is also introduced in the paper. As the proposed hybrid
converter can provide power to dc and local ac loads or grid
simultaneously, it can be applied to the PV powered hybrid
microgrid. The detailed mathematical modeling, steady state
analysis, and dynamic modeling are carried and discussion
on the developed PWM scheme is presented in this paper.
The proposed hybrid converter is also compared with the
conventional inverter and hybrid converter topologies. Finally,
the algorithm is validated through experimental results in this
paper.
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Somdut Dey received the B.Tech. degree in elec-
trical engineering from the Netaji Subhash Engi-
neering College, Kolkata, India, in 2014, and the
M.Tech. degree in electrical engineering–power elec-
tronics from IIT (BHU) Varanasi, Varanasi, India,
in 2017.
He is currently involved in automotive domain.
His current research interests include the design
of power electronics converters for microgrid, elec-
tric vehicle/hybrid electric vehicle applications, and
motor drives.
1341
Vinod Kumar Bussa (S’16) received the
B.Tech. degree in electrical and electronics
from the Vignan’s Engineering College (Vignan
University), Guntur, India, in 2012, and the M.Tech.
degree in power electronics and drives from the
National Institute of Technology at Kurukshetra,
Kurukshetra, India, in 2014. He is currently
pursuing the Ph.D. degree with the Department
of Electrical Engineering, IIT (BHU) Varanasi,
Varanasi, India.
His current research interests include the design
of power electronics converters for microgrid and electric vehicle/hybrid
electric vehicle applications.
R. K. Singh (S’08–M’13–SM’16) received the
B.Tech. degree in electrical engineering from the
College of Technology at Pantnagar, Pantnagar,
India, in 2001, the M.Tech. degree in electrical
machines and drives from IIT (BHU) Varanasi,
Varanasi, India, in 2003, and the Ph.D. degree in
electrical engineering from IIT Kanpur, Kanpur,
India, in 2013.
He has been an Associate Professor with the
Department of Electrical Engineering, IIT (BHU)
Varanasi, since 2005. His current research interests
include renewable power conversion for hybrid microgrid, power conversion
for electric vehicles/hybrid electric vehicles, optimal charging/discharging of
energy storage system, and converter modeling and control.