14 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 20, NO.
1, FEBRUARY 2010
New Delay-Time Measurements on a 64-kb
Josephson–CMOS Hybrid Memory
With a 600-ps Access Time
Kan Fujiwara, Qingguo Liu, Member, IEEE, Theodore Van Duzer, Life Fellow, IEEE,
Xiaofan Meng, and Nobuyuki Yoshikawa, Member, IEEE
Abstract—A 64-kb subnanosecond Josephson–CMOS hybrid
random-access memory (RAM) has been developed with ultra-
fast hybrid interface circuits. The hybrid memory is designed
and fabricated using a commercial 0.18-μm CMOS process and
NEC-SRL’s 2.5-kA/cm2 Nb process for Josephson circuits. The
millivolt-level Josephson signals are amplified to volt-level CMOS
digital signals by a hybrid interface amplifier, which is the most
challenging part of the memory system. The performance of this
amplifier is optimized by minimizing its parasitic capacitance
loading. The 4-K operation of short-channel CMOS devices and
circuits is reviewed, and a complete 4-K CMOS BSIM3 model,
which has been verified by experiments, is discussed. The memory
bit-line output currents are detected by ultralow-power high-speed
Josephson devices. Here, we report the first high-frequency access-
time measurements on the full critical path showing 600 ps for a
single bit. We discuss future designs made to reduce the crosstalk
and improve margins, as well as plans to reduce power dissipation
and latency.
Index Terms—Access time, high-speed measurement, hybrid
memory, interface circuit.
I. I NTRODUCTION
J OSEPHSON-JUNCTION-BASED rapid single-flux-
quantum (RSFQ) logic is the only technology with
demonstrated capability of an order of magnitude increase in
speed over CMOS logic while having orders-of-magnitude-
lower power dissipation [1]. Random access memory is needed
to complement the RSFQ logic. However, the lack of large-
capacity and sufficiently fast memory has been a long-standing
Manuscript received May 15, 2009; revised September 21, 2009. First
published November 24, 2009; current version published January 29, 2010.
This paper was recommended by Associate Editor O. Mukhanov. The work
of Q. Liu, T. Van Duzer, and X. Meng was supported by the Office of Naval
Research under Grant N00014-03-1-0065. The work of N. Yoshikawa was
supported by the VLSI Design and Education Center (VDEC), The University
of Tokyo, Tokyo, Japan, in collaboration with Cadence Design Systems, Inc.,
and Synopsys, Inc.
K. Fujiwara is with SanDisk Limited, Yokkaichi 512-8550, Japan (e-mail:
Kan.Fujiwara@sandisk.com).
Q. Liu was with the Department of Electrical Engineering and Computer Sci-
ences and the Engineering Research Support Organization (ERSO), University
of California, Berkeley, CA 94720 USA. He is now with National Semiconduc-
tor Corporation, Santa Clara, CA 95051 USA (e-mail: qingguo.liu@nsc.com).
T. Van Duzer and X. Meng are with the Department of Electrical Engineering
and Computer Sciences, University of California, Berkeley, CA 94720 USA
(e-mail: vanduzer@eecs.berkeley.edu; meng@eecs.berkeley.edu).
N. Yoshikawa is with the Department of Electrical and Computer Engi-
neering, Yokohama National University, Yokohama 240-8501, Japan (e-mail:
yoshi@yoshilab.dnj.ynu.ac.jp).
Digital Object Identifier 10.1109/TASC.2009.2034471
1051-8223/$26.00 © 2009 IEEE
problem in superconducting digital technology, particularly
for high-end computing applications. Some superconducting
memory systems were demonstrated using purely Josephson
junction (JJ) technology, which, however, were both
insufficiently dense and too small in capacity for high-end
applications [2], [3].
Josephson–CMOS hybrid RAMs have the potential to re-
move the memory bottleneck faced by JJ digital technology.
The basic idea is to use high-density CMOS memory and inter-
face it to high-speed ultralow-power superconductive devices.
Fig. 1 shows the system block diagram. The memory core and
decoders have been fabricated in a commercial CMOS technol-
ogy; the current sensors are fabricated using standard Nb tech-
nology, and the interface circuits involve both technologies. The
memory cell is modified from the traditional three-transistor
dynamic RAM (DRAM) cell, which works as a static memory
cell at 4 K due to nearly zero subthreshold leakage current.
This approach was proposed in 1993 [4], and some preliminary
simulations and measurements that confirm its feasibility have
been reported [5], [6]. In this paper, high-frequency component
delay times and access-time measurements of the full critical
path of the hybrid memory are presented for the first time.
II. S HORT-C HANNEL MOSFETs AT
C RYOGENIC T EMPERATURE
We have reported [7] that, for several submicrometer
commercial CMOS processes (Rohm 0.35-μm CMOS, Na-
tional Semiconductor Corporation (NSC) 0.25-μm CMOS, and
Hitachi 0.18-μm CMOS), both individual devices and circuits
work better at 4 K than at room temperature. Details of
4-K CMOS operation can be found in [7]–[9]. Here, we sum-
marize the advantages of 4-K operation of commercial short-
channel CMOS devices. Six key changes of properties upon
lowering the temperature from 300 to 4 K are given here.
1) Saturation velocity increases by up to about 30%.
2) Threshold voltage Vt increases from about 0.35 V to
about 0.55 V.
3) Subthreshold leakage becomes effectively zero, with the
subthreshold swing changing from 70–100 mV/dec to
about 10 mV/dec.
4) Source and drain capacitances decrease by a factor of
about 8. (Gate capacitance does not change.)
FUJIWARA et al.: DELAY-TIME MEASUREMENT ON JOSEPHSON–CMOS HYBRID MEMORY WITH ACCESS TIME
Fig. 1. Hybrid memory system of 64 kb for measuring delays including overall access time for a single cell.
Fig. 2. 3-T memory cell. Upon accessing the cell, current will flow down the
BL Read line if charge representing a “1” is stored at node X.
5) Ring oscillator measurements indicate a logic speed in-
crease of about 50%.
6) Static power is essentially eliminated, so the total power
dissipation is appreciably reduced.
In order to simulate the 0.18-μm CMOS circuits used in this
4-K experiment, we modified the room-temperature BSIM-3
model file according to our experimental data and verified it
by measuring simple circuits, including ring oscillators. Several
important parameters (threshold voltage, average mobility, and
subthreshold swing) were extracted from the 4-K I–V curves.
By adjusting other parameters, the model was trimmed, so that
the simulated I–V curves closely fit the measured ones. Then,
the 4-K capacitances are measured and added to the model.
In this paper, the so-called 3-T DRAM cell (Fig. 2) is chosen
as the memory cell for its high density and because a nonde-
structive readout is desired. Upon readout in standard room-
temperature operation, the voltage on the bit line is sensed to
determine whether a “0” or a “1” is stored [10]. However, in
15
our hybrid memory, current flows from the cell to a very low
impedance and ultralow-power high-speed Josephson current
sensor at the end of the bit line, which translates a current into
a millivolt pulse that goes to the processor.
The decoder for the 64-kb memory is an eight-input AND
gate circuit. In order to have minimum power consumption and
more robustness, the “static” CMOS logic family is chosen
[10]. The “logical effort” approach [10] has been used to
minimize the delay in the critical path. In addition, for mini-
mum delay, the decoder is designed such that the low-to-high
transition is faster than the high-to-low transition. Simulations
show a 400-ps total delay for the driver, decoder, memory cell,
and current sensor.
III. I NPUT I NTERFACE A MPLIFIER
The most challenging part of this hybrid approach is the
input interface between the two logic families. In order to
convert millivolt-level superconductor digital signals to volt-
level CMOS digital signals with minimum delay and power
dissipation, the hybrid interface amplifier shown in Fig. 3 was
implemented [11].
Part 1 of the interface amplifier is the so-called Suzuki stack
[12], which has widely been studied for converting millivolt
pulses to multi-millivolt signals [13]. Based on simulations, the
delay time is about 20 ps for a Suzuki stack with a 40-mV
output.
The operation of Part 2 of this hybrid amplifier is as follows:
When the clock is high, M1 is biased so that the current
in M1 , M2 , and the N -junction array is a little less than
the critical current in the N junctions, which is typically
0.8Ic . When the 40-mV input arrives at the gate of M1 , this
n-channel MOS transistor acts like a voltage-controlled current
source, increasing the current by ΔiM 1 = vin gm , where gm
is the transconductance of M1 at the given bias point. Note
that ΔiM1 must be much greater than the process variation of
16 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 20, NO. 1, FEBRUARY 2010

Fig. 3. Input interface amplifier. Part 1 is the so-called Suzuki stack with
16 junctions in each leg. It converts the 200-μA input pulse into a 40-mV pulse
that drives Part 2 of the amplifier. The junctions in both the Suzuki stack and
the 400-junction load array have critical currents of 400 μA.

critical currents in order to achieve robust switching and should Fig. 4. 5 mm × 5 mm Josephson chip. (The circuits in the center are for other
provide enough overdrive to switch the output stack at a high experiments.)
speed. When the current in the junctions exceeds the critical
current, all of the junctions switch, and the output voltage is
lowered by NVg by discharging capacitor C0 , which represents
all the parasitic capacitances at that node. In the present design,
N is 400 and gives a 1.1-V voltage drop. The M3 p-channel
MOS transistor is provided to speed up the resetting. When
the clock is low, M2 is off, and M3 is on, the output voltage
is charged up to VDD via M3 , and all N junctions return to
the zero-voltage state. When the clock is high again, all the
junctions are biased at 0.8Ic and are waiting for the next input.
The delay time of the Part 2 amplifier depends on the
discharging process of the output node that occurs when the
400-junction array goes into the voltage state, so the output-
to-ground capacitance is very critical. Several approaches
have been reported to decrease that parasitic capacitance [9],
[14]. Simulations using the currently employed 2.5-kA/cm2
Josephson technology and 0.25-μm CMOS process indicate a
delay of 170 ps with VDD = 1.5 V.
The stage following the interface amplifier is a CMOS in-
verter. The delay of the interface circuit also strongly depends
on the voltage level needed to trigger that inverter and can be re-
duced by lowering the VDD of the interface circuit. To minimize
capacitive loading, a minimum-size inverter is used. Due to the
sharp threshold characteristics and the larger threshold voltage, Fig. 5. 2.4 mm × 2.4 mm 64-kb CMOS memory chip. The gray cross strips
the initial inverter gate voltage can be as low as VDD − Vt are a requirement for the processing. The square surrounding the cross strips is
the boundary of the memory. The target memory cell is beneath those strips.
without compromising the output level. (The PMOS is still off
with an extremely small leakage current.) Given a 1.5-V VDD IV. H IGH -F REQUENCY M EASUREMENTS
of the CMOS digital circuits and 0.55-V threshold voltage, the
A. Test Setup
VDD of the interface amplifier can be as low as 1.0 V. We need
only 0.5-V voltage drop rather than 1.0-V voltage drop from The chips for the hybrid memory were fabricated using a
the interface amplifier to drive the following inverter. We have standard 0.18-μm CMOS process and NEC-SRL’s 2.5-kA/cm2
seen from simulation that the delay of the interface amplifier Nb Josephson process. The physical sizes are 5 mm × 5 mm for
can be reduced to less than 100 ps. The simulation results for the JJ chip shown in Fig. 4 and 2.4 mm × 2.4 mm for the CMOS
the complete critical path show that the total memory access chip shown in Fig. 5. In our previously reported measurements
time can be about 500 ps. [6], wire bonding was used to connect the Josephson and
FUJIWARA et al.: DELAY-TIME MEASUREMENT ON JOSEPHSON–CMOS HYBRID MEMORY WITH ACCESS TIME 17

Fig. 6. Circuit used for making delay measurements on various parts of the memory system. The arrays of four JJs are used to provide sharp rise time signals for
the oscilloscope. For example, the Suzuki stack and Part 2 comprise the input interface amplifier; when a clock signal (CLK1 ) is applied, current flows into the
OUT1 array and switches it. It also switches both parts of the interface amplifier and current flows into the OUT2 array, causing it to switch. With the oscilloscope
connected to OUT1 and OUT2 , the signals appear as in the sketch, and the delay can be measured. Other delays in the circuit can be measured in the same way,
including the overall delay, or access time.

CMOS chips. For this paper, we were able to employ solder-

bump bonding, so the parasitic inductances between chips
were greatly reduced. The measurements were made using two
different wideband probes. One is a BCP-2 cryoprobe manu-
factured by American Cryoprobe, Inc. The ground block was
modified by introducing a hole to accommodate the CMOS chip
mounted on the Josephson chip. The other one is an SRL probe.
Both probes have a bandwidth that is higher than 10 GHz,
which makes high-frequency measurements possible.

B. Delay Measurement Circuit

We have reported [5] a delay measurement circuit that is spe-
cially designed for measuring small delays that are difficult to
traditionally measure. In this paper, several delay-measurement
circuits were included, so that it is possible to measure delays
for various parts of the memory and the total access time. The
diagram of this setup is shown in Fig. 6. In this configuration,
the five p-type MOSFETs M4 – M8 each deliver about 200 μA
of current when they are completely turned on. In addition,
all the 4JJ arrays have the same critical current of 150 μA.
The full critical path measurement is as follows: CLK1 and
DCLK1 trigger M4 and M5 , OUT1 is then switched to 10 mV
and a 200-μA current flows into the Suzuki stack; after some
small delay, the Part-2 amplifier and, subsequently, the decoder
switch. Then, the target memory cell is selected and delivers a
current of about 200 mA to switch OUT4 . The time difference
between OUT1 and OUT4 is the total access time. At the same
time, the delay of the interface amplifier can also be measured
by taking the difference between OUT1 and OUT2 . If we want
to measure the memory cell delay, we can trigger M7 and
M8 by CLK2 and DCLK2 and measure the signals at OUT3
and OUT4 .
The cables from OUTx to the oscilloscope must exactly be
the same in type and length. We used cables with part number
TCF35BAA1000FC made by TSSJ (a Japanese company). We
estimate the potential inaccuracies in propagation delays to be
about 20 ps.
Fig. 7. Dependence of the delay in Part 2 of the interface amplifier as a
function of the supply voltage “AMP VDD adjusted” on the Part 2 circuit, with
the VDD of the remaining CMOS circuits in the memory kept at 1.5 V.
C. Measurements
We previously reported the delay of the memory core and
Part 2 of the interface amplifier with wire bonding between
CMOS and Josephson chips [6]. In that work, the clock sig-
nals were generated by signal generator Rhode & Schwarz
Signal SMP22, and the output signals were monitored using a
Tektronix 11801 oscilloscope. In those wire-bonded samples,
we were able to measure the relationship between the two
VDD ’s and the delay time of the Part 2 amplifier of the interface
circuit, as shown in Fig. 7.
Now, using solder-bump-bonded chip sets, the whole inter-
face amplifier (Part 1 and Part 2) delay has been measured.
As discussed in Section III, the delay of the interface circuit
can be adjusted by changing the supply voltage of the interface
amplifier. Fig. 8 shows the waveforms of OUT1 and OUT2 at
a 1-GHz clock frequency; the time difference between the two
outputs of about 100 ps represents the delay of the interface
18 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 20, NO. 1, FEBRUARY 2010
Fig. 8. Measured delay of about 100 ps in the input amplifier with the
amplifier VDD set at 1.05 V and the VDD of the remaining CMOS system
at 1.5 V.
Fig. 9. Access-time measurement using OUT1 and OUT4 . There is consider-
able crosstalk into OUT4 from the 1.5-V system clock. By subtracting (b) the
OUT4 signal in the absence of a reading command from (a) that with the read
command, we obtained the graph in (c). From this, we determine the access
time to be about 600 ps. The different slopes of the rising curves in (c) result
from the different loading on OUT1 and OUT4 .
circuit with VDD = 1.05 V for the interface and VDD = 1.5 V
for the CMOS part.
Fig. 9 shows the result of the total access time measure-
ment. Fig. 9(a) shows the waveforms when the Suzuki VDD is
applied so a memory cell is being read, and Fig. 9(b) shows
the waveforms when the Suzuki VDD is turned off. There
is millivolt-level crosstalk in both situations, which makes it
difficult to read the delay. Therefore, we subtracted the data
in Fig. 9(b) from Fig. 9(a) to get the result in Fig. 9(c). The
usual way of measuring delay at the mid-levels of the output
and input signals is inappropriate here, because the slopes of
the switching at OUT1 and OUT4 are different due to the
different loading capacitances at two pads, which are mainly
caused by the bit-line capacitance. Therefore, the right way to
read the delay is to read from two starting points, which gives
a delay of about 600 ps. The different output levels are because
of the different currents supplied by M1 and the measured
memory cell. The measurement delay is a little higher than
the simulation result; the possible reason is unaccounted-for
parasitics. The waveform of OUT4 is noisier than that of OUT1
and has a sharp peak, even before OUT1 rises. The reason
is believed to be the crosstalk into OUT4 from the volt-level
CMOS signals CLK1 .
V. D ISCUSSION
The crosstalk problem, as shown in Fig. 9, is one of the most
important issues that must be corrected. Only measurements
that involve memory bit lines have the crosstalk problem. The
2-mm-long bit line can serve as an antenna to pick up undesired
signals from the volt-level CMOS digital clock. More careful
design and layout are necessary. Since the clock lines have,
in relation to the bit lines, comparable currents but voltage
that is two to three orders of magnitude higher, we expect that
the coupling between them is electrical rather than magnetic.
This problem is being addressed in the next design by physical
separation of the clock and bit lines, and by electric shielding of
the bit lines. We will also consider possible inductive coupling
into the bit lines.
The functionality and high-speed operation of the memory
have been confirmed. However, the margins and robustness
of the interface amplifier need improvement. Both the Suzuki
stack and Part-2 amplifier need improvement. For the Suzuki
stack, the margins at high frequencies are lower than the
margins at low frequencies, mainly because the punchthrough
effect is worse at higher frequencies [15]. Resistors added
as shunts on the junctions can significantly suppress the
punchthrough [9]. Simulations have shown that, with appropri-
ate shunting resistance, Suzuki stacks have larger margins with
lower bit error rate, without compromising the output level. We
are also considering modified versions of the Suzuki stack.
The performance of Part 2 of the input interface amplifier is
critically dependent on the bias on M1 since the input signal
from the Suzuki stack is only 40 mV. We are implementing a
precision CMOS calibration circuit to set the bias at 20 mV
using an eight-junction Josephson array held in the voltage state
as a reference.
With the continued development of both semiconductor and
superconductor technologies, more advanced processes are ex-
pected to be used in the hybrid memory in the future. A
20-kA/cm2 Nb process has been demonstrated in the laboratory
[16], and 90-nm CMOS processes are now industrial standard.
Based on the scaling rules of CMOS and assuming that the
low-temperature improvement of CMOS does not change much
FUJIWARA et al.: DELAY-TIME MEASUREMENT ON JOSEPHSON–CMOS HYBRID MEMORY WITH ACCESS TIME
with scaling, one can calculate that the hybrid memory ac-
cess time for 90-nm CMOS will be 240 ps, whereas power
dissipation decreases only a little, because the interface static
power dominates [17]. Furthermore, if a special low-voltage
4-K CMOS process becomes available, the power dissipation
can greatly be reduced.
VI. C ONCLUSION
The complete critical path of a 64-kb hybrid memory has
been measured for the first time; a 600-ps access time, as well
as the delay of components of the memory system, was shown.
The measured delays are somewhat larger than simulated ones,
and the possible reasons and potential improvements were
discussed. Future elimination of crosstalk and the correction
of the small-margin problem were also discussed. With a
20-kA/cm2 process and a 90-nm CMOS process, the total
access time for a 64-kb hybrid memory will be about 240 ps,
and power dissipation will be somewhat lower than that for the
present design. The power dissipation can further be improved
if a special CMOS technology targeted at 4-K operation could
be used.
ACKNOWLEDGMENT
The authors would like to thank the reviewers for their
careful reading and their insightful comments. Q. Liu would
like to thank J. Wieser and J. Zhang of NSC for their help
on the CMOS layout. K. Fujiwara would like to thank SRL re-
searchers Dr. M. Hidaka, Dr. Y. Hashimoto, Dr. Y. Kameda, and
Dr. T. Miyazaki, and all the people who worked in the Process
Group at SRL for the Nb JJ foundry service and the generous
help in making the bump-bonded samples.
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Kan Fujiwara received the B.E., M.E., and Ph.D. degrees in electrical and
computer engineering from Yokohama National University, Yokohama, Japan,
in 2000, 2002, and 2005, respectively.
From 2005 to 2007, he was a Postdoctoral Researcher in the Department
of Electrical Engineering and Computer Sciences, University of California,
Berkeley, where he worked on the Josephson–CMOS hybrid random access
memory project. From 2007 to 2008, he was a JSPS Research Fellow with
ISTEC-SRL. He is currently with SanDisk Limited, Yokkaichi, Japan, as a
Process Integration Engineer. His research interests include superconductive
devices and their applications, particularly memory circuits in digital systems.
Qingguo Liu (S’03–M’07) received the B.S. and M.S. degrees from Nanjing
University, Nanjing, China, in 1999 and 2002, respectively, and the Ph.D.
degree from the University of California, Berkeley, in 2007.
He is currently with NS Labs, National Semiconductor Corporation,
Santa Clara, CA. His research interests include superconductive electronics and
CMOS circuits in power management for energy storage and conversion.
Theodore Van Duzer (S’52–A’54–M’60–SM’75–F’77–LF’93) received the
B.S. degree in electrical engineering from Rutgers University, New Brunswick,
NJ, in 1954, the M.S. degree in engineering from the University of California,
Los Angeles, in 1957, and the Ph.D. degree in electrical engineering from the
University of California, Berkeley, in 1960.
Since 1961, he has been with the Department of Electrical Engineering and
Computer Sciences, University of California, Berkeley, where he is currently an
Emeritus Professor. Since 1968, he has led a research group in superconductive
electronics, including both devices and circuits. He is a coauthor (with S. Ramo
and J. R. Whinnery) of Fields and Waves in Communication Electronics and
a coauthor (with C. W. Turner) of Introduction to Superconductive Devices.
His current research interests include hybrid superconductor/semiconductor
4-K random access memory.
Prof. Van Duzer initiated and served as the founding Editor-in-Chief of the
IEEE T RANSACTIONS ON A PPLIED S UPERCONDUCTIVITY and as a Guest
Editor for several IEEE journal special issues. He is a member of the U.S.
National Academy of Engineering.
20 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 20, NO. 1, FEBRUARY 2010

Xiaofan Meng received the B.S. and Ph.D. degrees (equivalent) from Peking Nobuyuki Yoshikawa (M’06) received the B.E., M.E., and Ph.D. degrees
University, Shenzhen, China, in 1962 and 1976, respectively, both in physics. in electrical and computer engineering from Yokohama National University,
He is currently a Senior Development Engineer in the Department of Elec- Yokohama, Japan, in 1984, 1986, and 1989, respectively.
trical Engineering and Computer Sciences, University of California, Berkeley Since 1989, he has been with the Department of Electrical and Computer
(UC Berkeley). Beginning in 1984, he was an Assistant and Associate Professor Engineering, Yokohama National University, where he is currently a Professor.
and then the Director of the Superconducting Electronics Group, Department His research interests include superconductive devices and their applications in
of Physics, Peking University. During 1987–1991, he was a Visiting Asso- digital and analog circuits, and single-electron-tunneling devices and quantum
ciate Professor in the Department of Electrical Engineering and Department computing devices.
of Physics, University of Virginia, Charlottesville. In 1991, he became a Prof. Yoshikawa is a member of the Institute of Electronics, Information and
Senior Visiting Scientist in the Department of Electrical Engineering and Communication Engineers of Japan, Japan Society of Applied Physics, Institute
Computer Sciences, UC Berkeley. He is also a Consultant to many high- of Electrical Engineers of Japan, and Institute of Electrical and Electronics
technology companies. He has extensive research experience in superconductor Engineers.
and semiconductor electronics, MEMS and other devices, and IC fabrication,
including thin-film deposition, photolithography, wet and dry etching, mate-
rial characterization, low-temperature technology, high and ultrahigh vacuum
technology, nanotechnology, and clean room fabrication. He is a coauthor
(with Y. X. Pan) of the book Brief History of Science and Technology in Ancient
China (Beijing, China: People’s Publishing House of China) and a co-translator
(with G.J. Cui) of the Chinese edition of Physics and Application of Josephson
Effect (Beijing, China: Metrology Publishing House of China) (A. Barone and
G. Paterno). He has more than 80 publications on superconductive electronics
and other fields. His current research interest is superconductor device and
circuit fabrication, including Josephson junctions, ICs, and superconductor
bolometer arrays.
Dr. Meng was the recipient of awards from Peking University, Peking
Commission of Science and Technology, and Chinese National Commission
of Science and Technology for superconductor device and low temperature
research; the Wel Zeilinger Staff Excellence Award; and Distinguished Service
Awards from the Department of Electrical Engineering and Computer Sciences,
UC Berkeley.