EXPERIMENT NO.

1
GATE FAMILIARIZATION

OBJECTIVES

1. To identify the input and output terminals of a gate in an IC package.

2. To identify the supply terminals of SSI IC.
3. To determine the state of input and output terminals of SSI gates using LED.

BASIC INFORMATION

Some TTL circuits as shown in Figure 1-1. Each IC is enclosed withing a

14 ot 16 pin package. A notch placed on the left side of the package is used as
reference for the pin numbers. The pins are numbered along the two sides
starting from teh notch and continuing counterclockwise. The inputs and outputs
of the gates are connected to the package pins.

The TTL IC’s are distinguished by their numerical designation, e.g. the
5400 and 7400 series. The former has a wide temperature range is suitable for
military use, while the latter has a narrower temperature range and is suitable for
commercial use. The numerical designation of the 7400 series means that the IC
packages are numbered as 7400, 7401, 7402, etc.

The TTL logic family actually consists of several subfamilies or series.

Table 1-1 list the name of each series and the prefix designation that identifies
the IC as being part of that series. ICs that are part of the high-speed TTL series
have an identification number that starts with 74H; ICs in the Schottky TTL series
starts with 74S; and similarly for the other series.

The differences between the various TTL series are in their electrical
characteristics, e.g., power dissipation, propagation delay, and switching speed.
They do not differ in pin assignment nor on the logic operation performed by the
internal circuits. For example, all the Ics listed in Table 1-1 with an 86 number, no
matter what the prefix, contain four exclusive OR gates with the same pin
assignment in each package.

EXPERIMENT 1: GATES FAMILIARIZATION 1

 Table 1-1 Various series of the TTL Logic Family
TTL Series Prefix Example
Standard TTL 74 7486
High-Speed TTL 74H 74H86
Low-Power TTL 74L 74L86
Schottky TTL 74S 74S86
Low-Power Schottky TTL 74LS 74LS86
Advanced Schottky TTL 74AS 74AS86
Advanced Low-Power Schottky 74ALS 74ALS86
TTL

MATERIALS

1 LED
1 9V Battery with connector
2 Resistor 1k ohms
1 Resistor 500 ohms
3 resistor 100 ohms
1 Protoboard / Breadboard
1 Long Nose Pliers
1 Wire Stripper Pliers
Connecting Wires (RED, BLACK, WHITE, VIOLET)

Integrated Circuits (ICs)

1 74LS00
1 74LS02
1 74LS04
1 74LS08
1 74LS32
1 74LS86

PROCEDURES

1. Examine the ICs supplied to you. The number is printed on the surface of
each IC.
74LS00, 74LS02, 74LS04, 74LS08, 74LS32 and 74LS86.
2. Connect the 74LS00 as shown in Figure 1-2. Supply the IC with 5V and
Ground.
3. Using the logic probe, test the status condition or logic level at the input and
output terminals.
4. Of each gate in the IC. Record the logic values in the corresponding tables.
5. Remove the IC mounted on the protoboard and replace it with another IC.

EXPERIMENT 1: GATES FAMILIARIZATION 2

6. Repeat step 3 for each of the other ICs.

+5V
Ground Terminal
Terminal

Figure 1-2 Experimental Circuit Set-up

EXPERIMENT 1: GATES FAMILIARIZATION 3

CIRCUIT DIAGRAMS / SCHEMETICS
14 13 12 11 10 9 8 14 13 12 11 10 9 8
Vcc Vcc

GND GND
1 2 3 4 5 6 7 1 2 3 4 5 6 7
74LS08 - Quad 2-Input AND Gate 74LS00 - Quad 2-Input NAND Gate

14 13 12 11 10 9 8 14 13 12 11 10 9 8
Vcc Vcc

GND GND
1 2 3 4 5 6 7 1 2 3 4 5 6 7
74LS32 - Quad 2-Input OR Gate 74LS86 - Quad 2-Input XOR Gate

14 13 12 11 10 9 8 14 13 12 11 10 9 8
Vcc Vcc

GND GND
1 2 3 4 5 6 7 1 2 3 4 5 6 7
74LS02 - Quad 2-Input NOR Gate 74LS04 - Hex Inverter
Figure 1-1 Basic Gates Pin Configuration

EXPERIMENT 1: GATES FAMILIARIZATION 4

DATA AND RESULTS

Table 1-1 Test Results for 74LS00 IC

Input Output
Terminals Terminals
Pin Logic Pin Logic Table 1-2 Test Results for 74LS02 IC
No. Level No. Level Input Output
1 3 Terminals Terminals
2 6 Pin Logic Pin Logic
4 8 No. Level No. Level
5 11 2 1
9 3 4
10 5 10
12 6 13
13 8
9
Table 1-3 Test Results for 74LS08 IC 11
Input Output 12
Terminals Terminals
Pin Logic Pin Logic Table 1-4 Test Results for 74LS32 IC
No. Level No. Level Input Output
1 3 Terminals Terminals
2 6 Pin Logic Pin Logic
4 8 No. Level No. Level
5 11 1 3
9 2 6
10 4 8
12 5 11
13 9
10
Table 1-5 Test Results for 74LS86 IC 12
Input Output 13
Terminals Terminals
Pin Logic Pin Logic Table 1-6 Test Results for 74LS04 IC
No. Level No. Level Input Output
1 3 Terminals Terminals
2 6 Pin Logic Pin Logic
4 8 No. Level No. Level
5 11 1 2
9 3 4
10 5 6
12 9 8
13 11 10
13 12

EXPERIMENT 1: GATES FAMILIARIZATION 5

QUESTIONS
1. What is the logical equivalent of the “hang” input? __________
2. Identify the following ICs with the same pin configuration.

3. Describe the pin configurations of 74LS02 and 74LS04 ICs.

EXPERIMENT 1: GATES FAMILIARIZATION 6