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DESCRIPTION
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established strip-
based PowerMESH™ layout. In addition to pushing
on-resistance significantly down, special care is tak- INTERNAL SCHEMATIC DIAGRAM
en to ensure a very good dv/dt capability for the
most demanding applications. Such series comple-
ments ST full range of high voltage MOSFETs in-
cluding revolutionary MDmesh™ products.
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ IDEAL FOR OFF-LINE POWER SUPPLIES,
ORDERING INFORMATION
SALES TYPE MARKING PACKAGE PACKAGING
STP20NK50Z P20NK50Z TO-220 TUBE
STW20NK50Z W20NK50Z TO-247 TUBE
THERMAL DATA
TO-220 TO-247
Rthj-case Thermal Resistance Junction-case Max 0.66 0.66 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 50 °C/W
Tl Maximum Lead Temperature For Soldering Purpose 300 °C
AVALANCHE CHARACTERISTICS
Symbol Parameter Max Value Unit
IAR Avalanche Current, Repetitive or Not-Repetitive 20 A
(pulse width limited by Tj max)
EAS Single Pulse Avalanche Energy TBD mJ
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
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DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
gfs (1) Forward Transconductance VDS = 8 V, ID = 10 A TBD S
Ciss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 2600 pF
Coss Output Capacitance 400 pF
Crss Reverse Transfer 55 pF
Capacitance
Coss eq. (3) Equivalent Output VGS = 0V, VDS = 0V to 400V TBD pF
Capacitance
SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(on) Turn-on Delay Time VDD = 250 V, ID = 10 A TBD ns
tr Rise Time RG = 4.7Ω VGS = 10 V TBD ns
(Resistive Load see, Figure 3)
Qg Total Gate Charge VDD = 400V, ID = 20 A, 95 nC
Qgs Gate-Source Charge VGS = 10V TBD nC
Qgd Gate-Drain Charge TBD nC
SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(off) Turn-off Delay Time VDD = 250 V, ID = 10 A TBD ns
tf Fall Time RG = 4.7Ω VGS = 10 V TBD ns
(Resistive Load see, Figure 3)
tr(Voff) Off-voltage Rise Time VDD = 400V, ID = 20 A, TBD ns
tf Fall Time RG = 4.7Ω, VGS = 10V TBD ns
tc Cross-over Time (Inductive Load see, Figure 5) TBD ns
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Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuit For Fig. 4: Gate Charge test Circuit
Resistive Load
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mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151
E
A
D
C
D1
L2
F1
G1
H2
G
Dia.
F
F2
L5
L9
L7
L6 L4
P011C
5/7
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 4.85 5.15 0.19 0.20
D 2.20 2.60 0.08 0.10
E 0.40 0.80 0.015 0.03
F 1 1.40 0.04 0.05
F1 3 0.11
F2 2 0.07
F3 2 2.40 0.07 0.09
F4 3 3.40 0.11 0.13
G 10.90 0.43
H 15.45 15.75 0.60 0.62
L 19.85 20.15 0.78 0.79
L1 3.70 4.30 0.14 0.17
L2 18.50 0.72
L3 14.20 14.80 0.56 0.58
L4 34.60 1.36
L5 5.50 0.21
M 2 3 0.07 0.11
V 5º 5º
V2 60º 60º
Dia 3.55 3.65 0.14 0.143
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granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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