Silicon-Ceramic

Composite
Substrate
Michael Fischer, Sebastian Gropp,
Johannes Stegner, Astrid Frank,
Martin Hoffmann, and Jens Mueller

T
he starting point for integrating RF func- ceramic layer) must take place
tions in silicon (Si) and low-temperature before any micro or nano struc-
cofired multilayers with an Si-ceramic turing is performed. Thus, the
(SiCer) composite substrate was the need influence of these processes on
for cross-sectional construction and con- sensitive structures (especially
nection of both parts from the nanometer to millimeter on sensitive mechanical systems)

IMAGE LICENSED BY INGRAM PUBLISHING

range. The application of nano and micro effects and
structures in microelectromechanical systems (MEMS)
requires the fabrication of intelligent and robust con-
nections (electrical, mechanical, fluidic, and thermal)
to a manageable carrier system or a printed circuit
board. These functions are enabled using SiCer sub-
strates [1]. Crucial back-end processes such as assembly
and packaging (mechanical Si bonding or wiring in the
can be minimized.
For the manufacturing of RF compo-
nents, different substrate materials are used depend-
ing on the particular application. Because of their
outstanding dielectric properties, ceramic materials in
a 3D multilayer technology [low-temperature cofired
ceramic (LTCC)] are primarily used for passive com-
ponents (capacitors and inductors), functional groups

Michael Fischer (michael.fischer@tu-ilmenau.de) and Jens Mueller (jens.mueller@tu-ilmenau.de) are with the Electronics Technology Group,
IMN MacroNano, Technical University of Ilmenau, Germany. Sebastian Gropp (sebastian.gropp@tu-ilmenau.de) and Martin Hoffmann
(martin.hoffmann@tu-ilmenau.de) are with the Micromechanical Systems Group, IMN MacroNano, Technical University of Ilmenau, Germany.
Johannes Stegner (johannes.stegner@tu-ilmenau.de) is with the 3RF and Microwave Research Group, IMN MacroNano, Technical University of
Ilmenau, Germany. Astrid Frank (astrid.frank@imms.de) is with the Institute for Microelectronics and Mechatronics Systems, Ilmenau, Germany.

Digital Object Identifier 10.1109/MMM.2019.2928675

Date of publication: 10 September 2019

28 1527-3342/19©2019IEEE October 2019

(filters, phase shifters, and antennas), and circuit
boards. Mechanical (moving) RF components (switch-
es and acoustic resonators) as well as electronic RF
components (amplifiers, buffers, and bias circuits) are
realized with semiconductor substrates [Si and gal-
lium nitride (GaN)/Si carbide] using semiconductor
and thin-film technologies [2]–[4]. However, a limiting
element in classical ceramic technology is the achiev-
able geometrical resolution (minimally printable con-
ductor widths at 40  µm and minimally punchable
vias at 75 µm). Because of their surface and material
properties, semiconductor technologies (CMOS and
MEMS) enable the use of thin-film technology. During
processing, it is possible to achieve significantly high-
er lateral resolutions and thereby significantly shorter
signal paths than in ceramic technology. On the other
hand, such semiconductor materials have generally
poorer dielectric properties than ceramic materials.
Due to the conductivity of the semiconductor materi-
als, the dissipation factor is significantly higher com-
pared to ceramic.
Monolithic SiCer-composite substrates combine the
advantageous properties of both substrate classes (Si
and LTCC). Current bonding concepts for Si on ceram-
ics require auxiliary materials such as solders, adhe-
sives, or glass frit, which are usually avoided due to
differences in thermal coefficient of expansion (TCE).
Alternatively, Si components can be mounted to a TCE-
matched, prefired LTCC by anodic bonding. The latter
requires expensive surface polishing, which becomes
obsolete with new techniques [1].
SiCer-composite substrates can be manufactured
and processed by standard LTCC and Si technologies.
The stack basically consists of an LTCC layer, ensur-
ing passive electronic functionality, and usually a thin
Si layer that ensures thin-film processing for MEMS
components. The technology design is more complex
than a classic design for semiconductor MEMS devices,
because the assembly and packaging technology must
be taken into account from the beginning. However,
this added complexity in the design phase is worth the
effort, because with SiCer it is possible to combine very
short vertical signal paths with integrated functions in
the system housing.
Usually, the manufacturing process begins with the
preprocessing of both sublayers of the composite sub-
strate. In the LTCC multilayer, for example, wiring and
electrical vias are generated, and thin-film structures
such as holes and thin wetting layers are produced in the
Si layer. After preprocessing, both layers are connected by
pressure-assisted sintering. The resulting quasi-mono-
lithic composite substrate can be further processed like a
normal wafer to build the RF component in the Si layer.
RF transmission lines can be provided in the ceramic
layer due to ceramic’s better dielectric properties. MEM
October 2019
structures such
as moving ele-
ments and hinges
are realized in the
Si layer due to Si’s
superior mechanical
properties. After MEMS
processing, individual ele-
ments and areas in the Si layer
can be separated from each other by
deep reactive ion etching (DRIE). Simultaneously,
other LTCC areas can be exposed for mounting noninte-
grable devices (e.g., CMOS devices). Because its thermal
expansion coefficient is similar to that of Si, the LTCC
material can also be used to manufacture functionalized
housings. Figure 1 shows the fabrication concept of SiCer
composite substrates.
Si-Bonding Techniques
Back-end processes in wafer format require wafer-
bonding techniques. These techniques are divided
into wafer bonding without intermediate layers
(e.g., direct Si and anodic bonding) and bonding
with intermediate layers using solder, adhesive,
glass frits, or eutectic bonding. In either case, both
wafers need to be TCE-matched to avoid bending,
delamination, or cracking under thermal load. Typi-
cal bonding partners are Si, glass [5], [6], and glass
ceramics, including LTCC [7]. The use of LTCC can
be very beneficial because it can already contain
horizontal and vertical wiring (minimization of par-
asitic elements). However, the typical as-fired sur-
face roughness is insufficient for an anodic bonding
procedure; expensive grinding and polishing steps
are necessary.
Bonding of Wafer-Shaped LTCC and Si
Substrates Using Anodic Bonding
One suitable method for bonding LTCC and Si wafer-
shaped substrates is anodic bonding. For the fabrica-
tion of an anodically bondable LTCC wafer,
a sodium-containing ceramic material is
necessary. This LTCC material (devel-
oped by the Fraunhofer Institute for
Ceramic Technologies and Systems)
consists in the initial state of a powder
mixture of alumina, cordierite, and a
sodium-containing glass as well as
a polymer binder. The LTCC wafer is
manufactured separately using stan-
dard LTCC technologies. After sintering,
the LTCC wafer has a relatively high surface
roughness (Ra $ 200 nm). Because a surface rough-
ness of Ra 1 50 nm is necessary for anodic bonding, the
LTCC wafer must be lapped and polished. Subsequently,
29
 Si and LTCC wafers are aligned to each other and heated
to 400 °C, and a dc voltage exceeding 600 V is applied.
The electric field causes sodium depletion at the bond
interface, electrostatic attraction, and formation of oxy-
gen bridges between the Si surface and the glass portion
of the LTCC, resulting in hermetic bonding.
Mohri et al. [8] used this method to bond prestruc-
tured Si and LTCC wafers together and simultaneously
Via Holes Si
Via, Wiring, Resistors, LTCC
Inductors, Capacitors
(a)
(b)
MEMS Devices With TSVs
(c)
MEMS Switch MEMS Resonator
(d)
MEMS LTCC
MEMS
Switch Housing
Resonator
BAW
ASIC 1 ASIC 2
Oscillator
(e)
Figure 1. The concept for fabricating SiCer composite
substrates along with the subsequent assembly
technology. (a) The preprocessing of both substrate
layers: Si: hole etching, thermal oxidation, and bond
interface; LTCC (bondable ceramic tape): via punching,
filling, and screen printing. (b) The bonding: lamination
and pressure-assisted sintering (3 kPa, 900 °C). (c) The
MEMS processing: thin-film sputtering/evaporation,
lithography, etching, chemical vapor deposition
processes, and plasma etching. (d) The separation and
exposure of mounting areas: DRIE and etch-stop on
LTCC. (e) The packaging and mounting of external
devices: soldering, wire bonding (if necessary), and chip
bonding. TSV: through-Si via; BAW: bulk acoustic wave;
ASIC: application-specific integrated circuit.
30 October 2019
establish an electrical connection between the sub-
strates [Figure 2(a)]. To avoid the expense of polish-
ing. Ihle et al. [9] used a glassy carbon with a very low
surface roughness as a nonwetting separating plate
during the sintering of the preprocessed LTCC wafer
[Figure  2(e)]. In this way, the expenditure for polish-
ing can be minimized or completely avoided. Ihle et
al. have demonstrated the technological feasibility
and use of anodic bonding to provide preprocessed Si
wafers with sensor structures having robust electrical
contacts (vias and wiring).
One disadvantage with both methods is that the
substrates cannot be processed further after the bond-
ing because sodium-containing substrates are no
longer compatible with standard semiconductor pro-
cesses. Furthermore, process-induced LTCC shrink-
age tolerances, which can also occur locally, lead to
problems in alignment of both joining partners
because the positions of the electrical structures dif-
fer between the materials. This effect also increases as
wafer size increases.
SiCer Bonding Techniques
The bonding between the two layers of the SiCer
substrate always occurs during the sintering of the
ceramic multilayer. For this, a family of alkali-free,
Si-adapted LTCC tapes [material designation: bond-
able ceramic tape (BCT)] has been developed [10]. In
principle, BCTs consist of a powder mixture (Figure 3;
particle size in the 400-nm range) of nonmelting com-
ponents and a melting glass component (sodium-free)
as well as a polymer binder. Various ceramic tapes are
available for the construction of the SiCer substrates.
BCT6 is used most often, as it has the best properties
for bonding to Si. BCT6’s nonmelting filler compo-
nent is quartz. Another tape, BCT1, has significantly
improved properties for screen printing (resolution) of
metal pastes, for example, but it also has lower bond-
ing properties (adhesion to Si). The nonmelting filler
component of BCT1 is alumina.
If the glass component reaches the liquid phase
during the sintering process, the natural oxide layer
on the Si surface is wetted by the glass. Depending on
the technology employed, the wetting is maintained
under constraint (pressure sintering, p = 800 kPa) or
induced by means of thin, wetting intermediate layers
in an unconstrained manner (pressure-assisted sinter-
ing, p = 3 kPa).
Original SiCer Bonding Procedure
With Nanostructures
A nanotextured Si surface is generated by a modi-
fied reactive ion etching (RIE) process that leads to
homogeneously distributed Si needles, also known
as black Si or Si grass, across a full wafer. In this case
a parallel plate reactor (STS 320, Surface Technology
Systems, Newport, UK) with a cooled wafer elec-
trode and a sulfur hexafluoride (SF6) /oxygen plasma
is used. Depending on the process time, needles up
to 2.5  µm in length can be achieved, with a diameter
varying from top to bottom between 5 and 400 nm, as
can be seen in Figure 3(b). The needle-like structures
have a pitch between 100 and 200 nm. For an adequate
penetration into unfired ceramic tape, the needles are
too long and flexible. Therefore, an additional plasma
treatment with argon is performed for shrinking and
thinning out the needles, as indicated in Figure 3(c), to
adapt the needle geometry to the powder morphology
of the unfired BCT, as displayed in Figure 3(a).
The first step of the bonding procedure is a lami-
nation process of the nano-structured Si surface with
the green BCT (“green” refers to unsintered ceramic
tape) to bring the substrates into close contact. The
needles penetrate the polymer matrix of the green
tape, and the particles touch the needle surfaces.
Pressure, time, and temperature, as well as the force
rising rate, are important lamination parameters
and determine the bonding properties of the final
compound. For the lamination, an isostatic press is
used to eliminate the risk of plate parallelism failure
with a standard press. Due to the highly increased
su r face a rea ( h ig h ly con-
centrated Si tips), a form-fit
bonding and a material con-
there is the possibility of an inhomogeneous bond
interface between the LTCC and Si if the wedge error
compensation of the sintering furnace does not work
properly due to impurities on the sinter plate. A
closer inspection of the bond interface between the
LTCC and nanostructured Si surface after the sinter-
ing process reveals the problem: the softened glass of
the LTCC matrix does not wet the Si surface properly.
Only the areas where there is high ambient pressure
are wetted by the glass. At regions with less or no
pressure, the glass shows a typical nonwetted shape,
which is a well-known effect of nanostructures with
dewetting properties for liquids (Figure 4).
The effect of surface roughness on the wetting
behavior of liquids on structured solids was described
by ­Wenzel [12]. In response, Young’s law was extended
by a so-called roughness factor r which represents the
ratio of the structured surface area to the (projected)
geometrical surface r $ 1, shown in Figure 5. Wenzel’s
equation for the contact angle reads [13]
cos i w = r · cos i y,
with i w for the Wenzel contact angle and i y the
Young contact angle. A key result is that any kind of
mechanical surface modification, and thus change in

5–50 µm
nection between the glass LTCC Au LTCC
Au
phase of the BCT and Si are
generated by pressure sinter-
ing (lateral zero shrinking). SiO2 Porous Au Bump

1–20 µm
(a) Au/Pt/Cr
The firing profile works with
a pressure of 0.8 MPa and a Au
LTCC SOI Wafer
peak temperature of 900  °C.
A typical scanning electron
Diaphragm
microscope (SEM) view of the
(b) (c)
resulting interface is shown
in Figure 3(d).
Au
SiCer Bonding Procedure LTCC
Using Wetting Layers
The sintering approach with
high pressure at high temper-
atures also has drawbacks:
Si usually undergoes plastic
deformations at temperatures
(d) (e)
above 600 °C [11] if a mechan-
ical stress gradient is applied;
Figure 2. The generation of an Si LTCC wafer composite with gold (Au) vias bonded
during the sintering process by anodic bonding with a polished LTCC surface [8]. (a) The production of the LTCC
at 800 to 900  °C under high substrate. (b) Wet-etching the LTCC wafer to make a cavity. (c) The LTCC and Si
isostatic pressure, the Si base substrates are aligned. (d) Anodic bonding forms an electrical connection. (e) The surface
material could suffer struc- of a bondable LTCC wafer with gold vias fabricated using glassy carbon [9]. Pt: platinum;
tural damage. Furthermore, Cr: chrome; SOI: silicon on insulator.

October 2019 31
 LTCC Glass Phase
Nonmelting
Particle

1 µm 1 µm 1 µm Si Tip
100 nm
(a) (b) (c) (d)

Figure 3. A set of SEM images showing stages in the development of BCT. (a) A view of the powder morphology of BCT
without the polymer binder. (b) Si that has been nanotextured by RIE. (c) The textured Si after treatment with argon
plasma. (d) A view of the bond interface with nano structures after sintering.

the wetting promoter should, at least, not degrade the

Si
LTCC
500 nm 1 µm
(a) (b)
Figure 4. Two SEM photos from the LTCC tape fabrication
process. (a) A view of typical dewetting behavior between Si
needles and the LTCC. (b) The back side of the LTCC tape
after sintering, showing single Si needles with their tips
sticking out of the molten glass matrix of the LTCC.
σL
σS θy
σLS
Nanostructured Si Surface
Figure 5. A schematic view of molten LTCC on a
nanostructured surface.
the roughness, intensifies the wetting behavior of that
surface: wetting and dewetting are amplified. Based
on this fact, it becomes clear that the contact angle
between the glass melt of the LTCC and the solid Si
surface must be reduced by a wetting promoter to val-
ues below 90°. The nanostructures will then allow for
a perfect wetting of the surface. On the other hand,
adhesion of the glass to the Si surface.
It is well known that there are promising adhe-
sion-promoting layers in MEMS technology. Nor-
mally they are used to get a proper bond of metals
on Si: titanium (Ti) or chromium, physically vapor-
deposited in very thin layers (1 30 nm). In this case,
both materials undergo oxidation during sintering,
as this usually happens in air. For LTCC firing as
well, oxygen is mandatory to burn the binding poly-
mers. For this reason, an oxidation of Si and Ti can be
assumed. Figure 6(a) shows Si nanostructures, man-
ufactured for SiCer fabrication and the particle size
of the LTCC matrix. In this case, the needles were
coated with Ti after annealing in air. The surface
exhibits an additional substructure of Ti dioxide in
the nanometer range.
Ti is known to be a suitable addition in low-TCE
glasses [14] and glass ceramics [9] based on borosilicate
glasses. It can be assumed that it forms a strong glassy
network close to the surface that supports wetting by
the softened glass as well as an excellent bonding of
the glass on the silica surface. As the total amount of Ti
is in the lower parts per million range, it proves chal-
lenging to identify the detailed glass composition at
the interface.
As the investigation of a SiCer substrate after suc-
cessful sintering is quite difficult, in the present study,
the substrates were tested by performing sintering
experiments using the previously described modified
Si nanostructures and finely ground glass powder
from the LTCC matrix.
On Si grass wafers, a thin layer of Ti (25 nm) was
sputtered as sketched in Figure 6(b). As a reference,
a second wafer with uncoated Si grass was tested.
Small amounts of the finely ground glass powder were
applied on these wafers. The samples were annealed
at 900 °C for 25 min in air. During the sintering, the Ti

32 October 2019
reacts with the oxygen of the ambient air in the furnace
to form Ti dioxide (TiO2) [15], [16].
Table 1 summarizes the results of the annealed glass
powder samples, processed according to the standard
procedure for SiCer fabrication. The SEM pictures dis-
play a clear difference between the uncoated and Ti-
coated Si surfaces. The most obvious difference is the
strong corona around the molten glass powder on the
TiO 2 sample.
The corona consists of solidified glass that has
filled the pores between the needles during annealing.
Due to the fast solidification of small amounts of glass
after sintering, the triple-phase contact line of hemi-
wicking was identified (hemi-wicking can be described
as an intermediate state between spreading and imbi-
bition). This type of wetting was discussed in [17] for
common liquids. Here, the nanostructured surface is
considered a porous material that “soaks” softened
glass into the structures. However, this is only a par-
tial process, and so the tips of the needles around the
glass powder sample are kept free from glass wetting.
The principle is sketched in Figure 7. Deposition of Ti
changes the dewetting behavior of the surface into
wetting behavior. Figure 7(b) confirms this conclusion
via SEM.
Through the Ti coating of the nanostructured Si
surface, the SiCer composite substrate can now be
fabricated at a reduced pressure during the sintering
process. This allows for the fabrication of compound
substrates without pressure-induced crystal damage in
Si and presumably with much higher bond strength.
Furthermore, new fabrication methods are now possi-
ble for releasing movable and active MEMS structures,
TABLE 1. A comparison of molten glass powder on bare and Ti-coated Si needles.
Glass Powder From LTCC Matrix SEM × 50 Magnification
Bare Si grass surface
Si grass surface with 25-nm Ti
October 2019 33
such as beams and membranes, using nanocarbon
paste at the SiCer bond interface.
Advantages of the Composite Substrate
LTCC technology is a mature substrate technology
for RF and microwave modules in different fields
of application, such as satellite communications,
automobile manufacturing, and medicine. Typical
applications place strong requirements on LTCC sub-
strates in terms of reliability and durability under
even harsh environmental conditions [19]. LTCC
technology is also considered a high-density inter-
connect technology due to its multilayer capability
and the ability for direct integration of passive device
1) Nanostructured Si
2) Bare Ti
Glass Power
3) Bare Ti
500 nm
(a) (b)
Figure 6. (a) An SEM photo of Ti-coated Si needles (black
Si) after annealing in air. (b) A schematic view of the
wetting behavior of glass powder on bare and modified
nanostructures. In the first step, nanoscaled needles are
etched using RIE in the Si substrate. Subsequently, the
substrates are locally coated with a thin layer of Ti. On these
surfaces, the glass powder is applied.
Detail: SEM × 12 k Magnification
 functions [20]. The implementation of 3D structures
such as cavities or channels opens up options for flu-
idic system packaging [21].
Besides being used for fabricating integrated cir-
cuits or photovoltaic cells, Si is also used for mechani-
cal systems. MEMS can be widely found in sensor
applications or as RF components. Figure 8 shows an
example with piezoelectric MEM double-clamped
beam resonators from epitaxially grown aluminum
GaN (AlGaN)/GaN layers on Si [22]. Individual com-
ponents are manufactured in large arrays at wafer
level. In most cases, they need to be hermetically
sealed, which can be achieved either at wafer level or
by packaging after singulation and picking from the
wafer. The latter process provides higher design flex-
ibility but at higher cost.
The SiCer composite substrate combines the advan-
tages (best of two worlds) of multilayer, low-tem-
perature, cofired technology and Si microelectronic
and MEM technologies. Bonding of both materials is
Triple-Phase
Contact Line
Liquid
Air dx
Solid
500 nm
(a) (b)
Figure 7. (a) A sketch of the spreading and imbibition of
glass in a porous material. (b) An SEM image of a molten
glass sample on Ti-sputtered RIE nanostructures. The
powder forms clusters due to high surface tension. Where
it contacts the modified nanostructures, the contact angle
remains below 90° [18]. dx: direction of propagation.
20 µm
Figure 8. An SEM image of beam resonators from
epitaxially grown AlGaN/GaN layers. (Source: K. Tonisch;
used with permission.)
34 October 2019
accomplished at the wafer level without the additional
processing steps and interface materials required by
typical LTCC cofiring. Structuring the Si layer is typi-
cally accomplished after firing (postprocessing); conse-
quently, the effort needed to mount such manufactured
MEMS devices is low. In addition, the use of conven-
tional LTCC mounting technologies on the ceramic
layer of SiCer (soldering, flip-chip bonding, housing,
and so on) enables real wafer-level packaging.
SiCer is, on one hand, a substrate on which a
MEMS component (e.g., a resonator in the Si layer)
can be manufactured and, on the other hand, a cir-
cuit carrier in which an electronic control (e.g., an
oscillator circuit in the ceramic layer) is realized. Due
to the more compact design and short vertical signal
paths, parasitic conduction effects (e.g., capacitance)
are reduced [23].
New Technological Capabilities Using SiCer
Cavities, Gaps, and Windows
in the Ceramic Layer
The preparation of cavities and windows in the ceramic
layer of the composite substrate extends the techno-
logical opportunities of Si-MEMS technologies to the
design of switches and resonating elements. For exam-
ple, through the integration of cavities, resonators can
be decoupled from the substrate, or Si solid joints and
membranes can be etched thinner through a window
in the ceramic; a fabrication of backside contacts in the
Si layer is enabled by a ceramic opening.
Windows are made by punching or laser cutting
all the individual ceramic layers and by exact stack-
ing and lamination. However, the pressure at peak
temperature (900 °C) of the sintering profile must be
significantly reduced (from 800 kPa to 250 kPa for a
100-mm wafer) to avoid a deformation of the ceramic
structure. Figure  9(a) shows 4-mm-square windows
in the ceramic layer of a SiCer substrate. The prepara-
tion of cavities at the interface of Si and BCT6 was car-
ried out with the help of carbon tape (C12, Advanced
Technologies; thickness: 127 µm). For this purpose,
suitable pieces of carbon tape are inserted into a pre-
prepared BCT6 stack with exactly punched or lasered
cutouts in the top layer. The preprocessed stack is
then laminated with the carbon-filled side facing the
Si wafer (Si surface is nanostructured [4]) and is sub-
sequently sintered under pressure. Figure 9(b) illus-
trates 6-mm-square cavities in the ceramic layer of a
SiCer substrate.
It is important to reduce to a minimum the lat-
eral gap between carbon and the BCT window (by
selecting optimum laser parameters). The second
row in Figure  9(b) depicts the behavior of the sin-
tered ceramic when reducing the gap by 5  µm per
 BCT Window
Cracks

Decrease of Gap Distance

Between Carbon and BCT
Underlying
Si Layer

(a) (b) (c)

Figure 9. A SiCer substrate with (a) windows on the ceramic side, (b) cavities at the interface of Si and BCT, and (c)
vertical gaps (light gray colored; BCT is translucent) at the interface.

column (beginning with 25  µm on the left-hand 9260 with a thickness of 8 µm was applied. Because of
side). If the lateral gap is too large, the BCT is the translucence of the BCT6 layer, the progress of Si
already damaged during lamination, which leads removal can be easily followed. Figure 10 displays sev-
to cracks during burnout and sintering. The use of eral stages of etching.
local vertical gaps simplifies the manufacture of The etching rate at the wafer edge (3.1 µm/min)
movable switch elements and solid joints because is significantly higher than in the middle (2.0 µm/min)
it is not necessary to release them subsequently by of the wafer. Obviously, this is caused by the ther-
additional etching processes (e.g., sacrificial layer mal conductivity of BCT6, 1.4 W/(m∙K), which is
etching at Si on insulator substrates). The procedure approximately 100 times lower than that of Si. Thus,
is similar to that for cavities. Instead of inserting a the helium backside cooling of the peripheral area of
carbon tape, a nanocarbon paste is deposited using the wafer during etching is inefficient, and the etch-
screen printing where bonding between Si and BCT ing rate increases. The open Si etching area in the
is to be prevented. This results in a vertical gap of selected mask design amounts to 38%. In this case
approximately 4 μm [Figure 9(c)]. Subsequently, the an etch selectivity between Si and AZ 9260 of 57:1 is
desired structure can be etched through the Si layer determined. During the whole etching process, the
by means of DRIE. maximum substrate temperature of 55 °C was not
exceeded (confirmed with an integrated pyrometer).
DRIE of SiCer Substrates As shown in Figure  10(d), the etched side walls of
Another advantage of the SiCer substrate is that the the Si structures are perpendicular to the surface
ceramic layer takes on the carrier function, and Si is of the substrate, which established that the etching
used only where the specific properties (mechanical
properties, thin-film functions, and lithography) are
required. It is possible to eventually remove unneeded TABLE 2. Process parameters for the DRIE of SiCer.
Si through an etching process and decouple indi-
Passivation Etching
vidual RF components in the semiconductor layer, if
C4F8 gas flow (sccm) 85 –
necessary. DRIE was chosen to structure the Si layer
because it lends itself to good process control. As the SF6 gas flow (sccm) – 130
etching device, an STS Multiplex ICP (inductively O2 gas flow (sccm) – 13
coupled plasma) tool was used. The tool provides an Cycle time (s) 7 13
advanced Si etch (ASE) process that consists of alter- Coil power (W) 600 600
nating cycles of etching and polymer deposition to Platen power (W) – 18
protect the side walls from further etching. The basic Chamber pressure valve Constant at 82%
process parameters are listed in Table 2. The etching
Chamber temperature (°C) 40
behavior was tested on a 100-mm SiCer substrate. The
Plate temperature (°C) 20
wafer has a thickness of 634 µm (Si layer: 380 µm; BCT6
Helium backside cooling Yes
layer: 254  µm). For masking, positive photoresist AZ

October 2019 35
A good heat transfer in the
substrate ultimately determines the
integration density of the electronic
components and thus the size of the
RF modules to be assembled.
behavior of SiCer wafers using DRIE is consistent
with that of standard Si wafers. Only the homogene-
ity of the etching rate across the whole wafer appears
to be slightly lower.
For separating areas protected by photoresist
(rapid Si removal), the described etching process is
adequate. For the etching of finer structures (e.g.,
flexure hinges and springs; structure size: <20 µm),
an adaptation of the etching process is necessary
(e.g., adjusting the gas ratio in the plasma). Due to
the lower thermal conductivity of the ceramic layer,
an increased temperature in comparison with a stan-
dard Si wafer is observed on the substrate surface
during etching. This leads to a reduction of the poly-
mer deposition rate (passivation cycle) and therefore
to a premature etch attack. Here, two strategies are
conceivable: the platen temperature could be low-
ered (e.g., from 20 to 15 °C), or the passivation cycle
time could be increased (e.g., from 7 to 9 s). Further-
more, an inhomogeneous heat dissipation and thus a
reduced etch uniformity are to be expected when a
SiCer substrate with windows in the ceramic layer is
structured by DRIE. This will be the subject of fur-
ther investigations.
Metal Pastes for BCTs
At this time, there are no commercially available, spe-
cially developed metal paste systems for SiCer technol-
ogy. Thus, to integrate electronic components, such as
surface-mount devices (SMDs) or bare dies, on SiCer
(a) (b)
Figure 10. Photos documenting several stages of Si etching on SiCer after (a) 131 min, (b) 163 min, and (c) 185 min. (d) A
detail view of separated test chips.
36 October 2019
substrates, compatible metal pastes for soldering
and wire bonding needed to be found. This section
describes the process and results of the investigations
aimed at finding the best available paste systems from
third-party sellers.
The workability (printing and sinter behavior) of
cofired metal pastes on BCT has been visually assessed
in [24]. However, for the integration of external devices
(SMD or bare chip) on SiCer composite substrates,
quantitative investigations of wire bondability and
solderability of BCT to metal pads are also essential.
To assess this, test patterns of candidate metal pastes
(Table 3) were created for the different BCTs using
screen printing and pressure-assisted sintering.
After substrate dicing, 50 wire bonds (ball-wedge,
Au, 25 -µm wire th ick ness) per metal pad were
applied, using an automatic wire bonder (Delvotec
5610). For the evaluation of solderability, solder paste
was applied (Alpha, OM 338, lead-free) by stencil
printing on the pads, and SMD resistors (type 0402)
were mounted on the patterned BCT carrier with
an automatic chip placer (Vico, Häcker GmbH) and
reflowed in a box furnace (RP 6, SEF Systec GmbH).
Figure  11 illustrates a typical result. Subsequently,
all connections were destructively tested with the
Condor 70 pull and shear tester (XYZTEC). Pull and
shear strengths of the wire bonds as well as shear
strengths of the soldered devices were determined
and compared.
The experiments show that the gold pastes exhibit
the highest wire bonding strengths on BCT1 and BCT6;
however, silver-palladium pads also exhibit acceptable
strengths in combination with BCT1 (Figures  12 and
13). On BCT6, the silver-containing pastes show a highly
glazed surface; thus, no wire bonds can be realized.
For soldering, the silver pastes have the highest
shear strengths, especially on BCT1 (Figure 14). Above
all, silver-platinum pads (TC 7601) have the highest
shear strength in combination with BCT1.
Freestanding
Si Chip
BCT 6
5 mm
(c) (d)
Thermal Behavior of SiCer
It is important to know the thermal behavior (thermal
resistance) of a novel RF circuit carrier material. In
particular, it is essential to ensure good heat dissipa-
tion for lossy components (power amplifiers). A good
heat transfer in the substrate ultimately determines the
integration density of the electronic components and
thus the size of the RF modules to be assembled.
The BCT layer in a SiCer substrate has a signifi-
cantly lower thermal conductivity [<0.9 W/(m∙K)]
than the Si [150 W/(m∙K)]. This leads to a consider-
ably increased thermal resistance of the composite
substrate compared to a standard Si wafer of similar
dimensions. However, fully metallic thermal vias can
be generated in the LTCC layers to reduce the thermal
resistance of the BCT layer [24], making it is possible
to build up a substrate with locally adjustable ther-
mal resistance. The following section describes the
procedure for determining the thermal resistance as
well as the technological implementation of various
SiCer configurations.
Measuring Assembly
The thermal resistance of a SiCer junction is determined
by a self-adjusting temperature difference between the
Si and the ceramic of the SiCer wafer at a defined heat
flow through the substrate. A SiCer carrier structure
was fabricated containing a thermal test chip (PST1-02,
Delphi Corporation). The square-cut chip has an edge
length of 3 mm and was glued with a silver-filled adhe-
sive (m = 60 W/(m $ K )) to the SiCer carrier. The chip
includes a planar resistor for generating a thermal load
(P ) and diodes that are used as a temperature sensor
to measure the chip temperature (TJ) . To ensure stable
measuring conditions, the SiCer carrier was placed on a
temperature-stabilized heat sink. The heat sink consists
of a Peltier element, a water cooler on the back side, and
a copper heat spreader on top of the Peltier element. Fig-
ure 15 depicts the setup.
40
36 36
35 33 34
Shear Strength (cN) 30
30
27 25
25 23

Not Bondable

Not Bondable

Not Bondable

Not Bondable
20
TABLE 3. The evaluated metal pastes for BCTs.
15
Name Manufacturer Material Recommended Use 10
TC 7601 Heraeus AgPt Fine line, solderable 5
0 0 0 0 0
TC 7305 Heraeus Ag Fine line, solderable
01

05

02

01

02
QG 150 DuPont Au Fine line, etchable
15
76

73

71

74

74
G
Q
TC

TC

TC

TC

TC
TC 7102 Heraeus Au Fine line, AI/Au wire
bondable
BCT1 BCT6
TC 7401 Heraeus AgPd, Fine line,
27:1 development state
Figure 12. A comparison of the shear strength of ball bonds
TC 7402 Heraeus AgPd, 6:1 Fine line, solderable
(Au, 25-µm diameter) on the investigated metal pads on
AgPt: silver platinum; AgPd: silver palladium.
BCT. The metal pastes used are detailed in Table 3.

10
9
9 8 8
8 8 8
Pull Strength (cN)

7 7
6 6
Not Bondable

Not Bondable

Not Bondable

Not Bondable

5
(a) 4
3 3
2
1
0 0 0 0
0
01

05

02

01

02
15
76

73

71

74

74
G
Q
TC

TC

TC

TC

TC

(b)
(c)
Figure 11. (a) A sheet of BCT substrate with mounted
SMD resistors. (b) A closeup of a soldered resistor. (c) A
sheared wire bond on a pad with QG 150 metal paste.
BCT1 BCT6
Figure 13. A comparison of the pull strength of wire bonds
(Au, 25-µm diameter) on the investigated metal pads on
BCT. The metal pastes used are detailed in Table 3.

October 2019 37
 The copper heat spreader includes a temperature-
1,200 dependent resistor (PT1000; accuracy: 100 mK at 22 °C)
1,060
for measuring the temperature of the heat sink (TGND).

Pad Sinks Into BCT6

Shear Strength (cN) 1,000
811 The input power of the Peltier element was adjusted by
800

Pad Dissolves
624 a proportional-integral-derivative controller (TED4015,
600 510 Thorlabs Inc.; ! 1 mK stability) using the heat-sink tem-
400 perature as the current value [25]. An ohmic heating
265 285
200 157 generated a thermal load that led to an increase in the
105 110 121
0 0 chip temperature. After reaching thermal equilibrium,
0
the thermal resistance (R th) of the demonstrator was cal-
01

05

02

01

02
15 culated using the following formula:
76

73

71

74

74
G
Q
TC

TC

TC

TC

TC
TJ - TGND
BCT1 BCT6 R th = .
P

Figure 14. A comparison of the shear strength of soldered

Technological Realization of the SiCer Carrier
SMD resistors on the investigated metal pads on BCT. The
metal pastes used are detailed in Table 3. To determine the thermal resistance of a SiCer junc-
tion, various configurations on the substrates were
realized. For a constant via diameter of 200 µm, the
number (from 0 to 9) and the arrangement (distance
Adhesive Thermal Test Chip (P, TJ)
between the outer vias and the chip center) of ther-
BCT Thermal Vias mal vias were varied. The structure of the SiCer wafer
Si was carried out as described previously. The LTCC
TGND SiCer Carrier multilayer consists of five BCT6 layers and one outer
PT1000 Resistor BCT1 layer. The LTCC layers were prestructured by
Copper Heat Spreader punching the via holes and filling with via pastes (TC
701, DuPont, gold/silver mixed-metal paste; and 6141,
Peltier Element DuPont, silver paste), as shown in Figure 16(a). With
Water Cooler the punching operation, the wafer contour of LTCC
(100-mm diameter) was generated simultaneously.
The conducting path for the electrical connection of
the thermal test chip (QG 150, DuPont, gold paste)
Figure 15. The measurement setup, consisting of the SiCer and a metal pad for a better wetting of the adhesive
carrier with a thermal test chip and a temperature-stabilized (6146, DuPont, silver/palladium paste) were applied
heat sink. by screen printing at the BCT1 layer. Subsequently,
all BCT layers were aligned and stacked together by
a lamination step with a 300-µm-thick, double-side
polished Si wafer. A subsequent pressure-assisted
Thermal Vias sintering step generated the monolithic SiCer wafer.
After a substrate cleaning step, the thermal test chips
were assembled on the SiCer wafer with an automatic
chip placer (Vico) using silver adhesive (DM6030,
(b) (c) Diemat). The thermal test chips were connected to
the conducting paths by wire bonding [Figure 16(b)]
before the various SiCer carriers were separated by
sawing [Figure 16(c)].

(a) Behavior Depending on the Number of Vias

(d) Basically, the thermal resistance in the corresponding
substrate area decreases with increasing via number
(or via area). But there must also be enough ceramic
Figure 16. (a) A SiCer wafer (ceramic side) with mounted material to hold the metal vias. In addition, the sinter-
test chips. (b) A test layout with two thermal vias. (c) A ing behavior of the materials used must be taken into
wire-bonded thermal test chip. (d) Several separated SiCer account because, for example, air inclusions (voids) in
carrier modules. the thermal via cause the functionality to fail.

38 October 2019
 200-µm Vias Adhesive Layer 200-µm Vias

Voids
Paste: 6141
Paste: TC 701 Air Inclusion

(a) (b) (c)

Figure 17. Several X-ray images of SiCer test modules. (a) Voids that developed in thermal vias. (b) Uniformly distributed air
in the adhesive layer. (c) Homogeneously formed thermal vias.

Increasing the number and therefore total area of
the thermal vias in the SiCer resulted in a significant
reduction of thermal resistance. However, initial simu-
lations with ANSYS of the thermal resistance showed
poor correlation with the measurements. It was found
that the paste (TC 701) used for via filling was not suit-
able for thermal vias in SiCer because voids develop in
the via holes during sintering [Figure  17(a)]. Further-
more, uniformly distributed air inclusions formed in
the adhesive layer [Figure 17(b)] during the assembly of
the semiconductor die.
Using a different paste [6141, Figure 17(c)] and consid-
ering all previous findings, a good agreement between
the measurements and the simulation (thermally static
analysis using ANSYS Workbench) was achieved. The
theory curve shown in Figure 18 is based on the ther-
mal resistor network of the individual material layers.
The insert in Figure 18 shows a simulated temperature
distribution of the chip model.
Example of a SiCer Platform: MEMS Switch
SiCer substrate. In the following section, the design,
simulation, and implementation on a SiCer substrate
are described in detail.
MEMS Switching Topologies
Over the last few decades, many MEMS switch topolo-
gies have been presented in the literature. From a cir-
cuit function point of view, MEMS switches can be
divided into two main types: series and shunt switch
configuration, as shown in Figure  19. The MEMS-
based switching element is part of an RF transmis-
sion line. If the switch is deactivated, the signal path
is open. By activating the switch, a membrane or beam
is deflected, and the transmission line is closed and
establishes a low-ohmic contact between input and
output [28]. One design example that is often used for
45
40
Thermal Resistance (K/W)

One of the most obvious applications of SiCer technol- 35

ogy is the use of a SiCer composite substrate for RF
30
MEMS components. Si is known to be a suitable mechan-
ical material for MEMS, including RF MEMS devices 25
[26], but it also has drawbacks such as a high attenu- 20
ation constant at radio frequencies. RF MEMS devices 15
also suffer during system integration, as they need a 1-mm
10
first-level package that enables assembly on printed cir- Test Vias
cuit boards. In many cases, the parasitic effects of the 5
package and the additional effort for assembly wipe out
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
the benefits of Si. On the other hand, LTCC is a very Via Area (mm2)
good carrier for RF components, although is not suit-
able for implementing micromechanical devices. To Measurement Simulation Theory
combine these advantages, a MEMS RF switch design
was set up. The advantages and disadvantages of dif- Figure 18. The trend of thermal resistance as a function of
ferent topologies were taken into account to find the the effective area (number) of thermal vias. The inset shows
most suitable MEMS switch for implementation on the the simulated temperature distribution in the test setup.

October 2019 39
The required switch for the
LTE receiver, the SiCer system
demonstrator, is realized using three
single-pole, single-throw switches
connected at one port.
the realization of series MEMS switches is the Rock-
well Science Center [28] design shown in Figure 19(a),
which has been optimized by other scientists and
institutions for frequencies up to more than 40 GHz
[29]. The switch consists of an RF transmission line
with a gap that can be closed by a metallic cantilever.
To move the cantilever onto the transmission line, a dc
voltage in the range of 20−80 V must be applied [28].
This type of MEMS switch actuation is called electro-
static [28]. To improve the electrical isolation of MEMS
switches, a push–pull configuration is used to lift up
the cantilever in the off state and so reduce the elec-
trical capacitance between the open transmission line
and the cantilever [31].
Another RF switch topology is the capacitive shunt
switch, which can also be employed as a varactor. In
this type, also called the Raytheon capacitive MEMS
shunt switch [31], a movable membrane forms part
of a transmission line, as sketched in Figure  19(b).
Located below the membrane is a pull-down elec-
trode. The membrane is actuated by an electro-
static force induced by a bias voltage in the range of
10–60 V. It is pulled down toward the electrode and
increases its capacitance to ground, resulting in a
capacitive short circuit to ground. The design of the
capacitive shunt MEMS switch depends on the fre-
quency range of the target application because the
switch capacitance depends on frequency, whereas
the operating-frequency range of a series switch is
inherently broadband.

MEMS Switch on SiCer

Switch Contact
To demonstrate a MEMS switch within SiCer, a single-
pole, triple-throw band-select switch had to be imple-
mented on the SiCer substrate. Because this article
Pull-Down Electrode RF Line With Cavity
focuses on presenting the benefits of the technology
(a)
platform (combination of LTCC and Si, buried cavi-
Membrane
RF Out
ties, and Si etching), the required switch for the LTE
RF In
receiver, the SiCer system demonstrator, is realized
using three single-pole, single-throw switches con-
Pull-Down Electrode nected at one port. Hence, a capacitive shunt-switch
(b) implementation is not possible, as switching off at one
band would induce a short circuit at the antenna port.
Figure 19. (a) A Rockwell Science Center MEMS series Instead, a series switch topology using electrostatic
switch [28]. An electrostatic force is generated by applying actuation was selected. The complete specifications are
a dc voltage at the pull-down electrode. The beam is then
summarized in Table 4.
pulled down, and the metallization (switch contact) closes
Based on these specifications a MEMS series switch
the RF line. (b) A Raytheon capacitive MEMS shunt switch
[31]. A membrane is part of an RF transmission line. The was designed, using Si MEMS technology, that inter-
membrane can be pulled down by applying a dc voltage rupts a transmission line realized on LTCC at the bond
at the pull-down electrode and, consequently, forms a interface of the SiCer substrate. As the demonstrator
capacitive shunt to ground. is specified for use in handheld devices, it requires
low power consumption, low-voltage actuation for
switching, and bistable operation, or at least very low
TABLE 4. The LTE MEMS switch parameter. power for the switched state. Furthermore, a switch
design with an in-plane movement was selected, as it
Parameter Value
is best suited for the SiCer technology and highlights
Actuation Electrical, in-plane movement the performance of the new platform, including DRIE
Movement In-plane, parallel plate and buried cavities. Various designs for electrostatic
Voltage < 20 V actuators are available that enable large movements
Transmission line Grounded coplanar waveguide of more than 10  µm with low voltages. The result-
Bandwidth 0–10 GHz ing switch design, shown as a finite element method
Insertion loss < 2 dB (FEM) model in Figure 20 [32], consists of three main
parts. The moving element of the switch is the piston,
Isolation > 25 dB @ 3 GHz
which is attached to a frame and mechanically con-
Switching time < 50 ns
nected to the LTCC carrier substrate by a meander

40 October 2019
spring. The spring also produces the mechanical force
that pulls the piston into the in-plane transmission
line. The electrostatic force causing the switch to move
is applied by a dc voltage between two electrode pairs.
The two parallel-plate actuators consist of Si cantile-
vers that are narrow (20-µm gap) compared with the
fixed parts and thus flexible enough to move in plane.
These actuators are suspended above the LTCC mono-
lithically and connected to the stiff piston. When an
actuation voltage of about 20  V is applied, the elec-
trostatic force between the electrodes bends the free
ends of the electrode plates toward one another. The
concept was adopted from an optical fiber switch that
needed large displacement at a high force [33]. This
leads to a reduction of the initial gap between the par-
allel plates, and the attracting force increases due to a
self-amplifying effect [Figure 20(b)]. Consequently, the
piston and spring move, and the signal is switched off.
An insulating layer prevents direct contact and thus
electrical breakdown between the electrodes [34]. In
different levels of abstraction. The blue line indicates the
RF simulation in Cadence; the red dashed curve is based
on the FEM field simulation results. Figure  21(c) illus-
trates the RF simulation model. The metallic parts—
piston and transmission line—are modeled by the
resistances R 1, R 2, and R 3 . The capacitances between
the piston and the transmission-line elements, as well
as the capacitances between the two transmission-line
elements, are modeled using variable capacitances C 1,
C 2, and C 3 because deflection of the piston changes the
capacitive behavior of the structure. Two static capaci-
tances, C 01 and C 02, represent the capacitive effect of the
transmission lines to ground. The agreement between
Isolation
–30
–40

|S21|2 (dB)
the open state, the isolation of the transmission line is
–50
very important, whereas, in the closed state, insertion
loss is the important parameter. –60
RF Simulation
Figure  21 shows the forward transmission param-
–70 RF Model
eter S 21 in the open and closed states over frequency for
0 5 10
Frequency (GHz)
(a)
Insertion Loss
Electrode Pair 1 Electrode Pair 2 0
|S21|2 (dB)

–1
Ground
Signal
Piston RF Simulation
Fixed
Return Spring RF Model
–2
0 5 10
Frequency (GHz)
(b)
(a)
Materials: Si Au R2
R1 C1 C2 R3
+
–
C01 C3 C02
(c)

Figure 21. The forward-transmission parameter S 21 (a)

(b)
Figure 20. An FEM representation of the switch design
(a) in the closed state and (b) in the open state. For the open
state, a dc voltage must be applied.
in the open state of the switch and (b) in the closed state of
the switch. The isolation of the switch reaches 29 dB at a
deflection of 1 μm; the insertion loss remains below 1.4 dB.
(c) The extracted simulation model is shown, consisting
of resistive elements R 1, R 2, and R 3 for the conductors
and capacitive elements C 1, C 2, C 3, C 01, and C 02 for the
interaction of the transmission-line elements with ground,
the piston, and each other.

October 2019 41
 the RF field simulation and the schematic, model-based
simulation proves the consistency of the RF model. The
deviations of the insertion loss between the two mod-
els are negligible. For the isolation, a deviation of up to
3 dB can be observed at 10 GHz, but the model fits the
FEM-simulated results quite well at lower frequencies.
Therefore, the schematic model is sufficient for use in
system simulations below 5 GHz and is an efficient tool
to reduce simulation effort and simulation time. A mini-
mum isolation of 29  dB can be determined for deflec-
tions of the piston of 1 μm, and the maximum insertion
loss was simulated to be 1.4 dB. The specifications given
in Table 4 can hence be met by this type of RF MEMS
switch. For the generation of the schematic model of the
switch, elementary electrical equations are used (i.e.,
TABLE 5. The LTE MEMS switch parameter overview.
Parameter Value
R 1, R 3 0.24 X
R2 1.8 X
C 1, C 2 9.4 fF
C3 0.51 fF
C 01, C 02 180 fF
Gap between transmission line and piston 10 nm
Gap between transmission lines 31 nm
Width of transmission line 20 nm
the plate-capacitor formula and the equation for ohmic
losses in materials). As discussed previously, these equa-
tions are suitable for computing the equivalent-circuit
model of the switch. The element values for the resis-
tance and capacitances are given in Table 5. An example
of a fabricated RF MEMS switch is shown in Figure 22.
Conclusions
This article presented the concept of SiCer substrates as
well as an example of a SiCer platform suitable for the
integration of RF components. The platform enables the
combination of thin-film and LTCC technology, allow-
ing significantly higher lateral resolutions and signifi-
cantly shorter signal paths than in common ceramic
technology combined with chip assembly. Different
components can be realized in their respective opti-
mum layer (wiring inductances and capacitances in
the ceramic layer; mechanical switches and resonators
in the Si layer). Components (e.g., CMOS devices) that
cannot be realized with the SiCer technology shown
in this article can be integrated with classic packaging
technologies (e.g., flip chip). The material properties of
the substrate and the combination with different paste
systems were studied. The substrate behavior using
DRIE, which is necessary to separate various compo-
nents on the platform, was investigated. The fabrication
of free-moving MEMS elements (e.g., switches) in SiCer
was greatly simplified by the use of carbon paste (local
vertical gaps). The thermal behavior of SiCer was also
investigated. For MEMS requiring a high temperature

Piston
Spring
Cavity

LTCC
Mount

S4800 10.0 kV 10.1 mm ×2.00 k SE(M) 20.0 µm

Piston
(b)
Electrode Pair 1

Electrode Pair 2

LTCC

S4800 10.0 kV 8 mm × 30 SE(M) 1.00 mm S4800 2.0 kV 10.3mm × 300 SE(M) 100 µm

(a) (c)

Figure 22. (a) An SEM image of the produced RF MEMS switch on SiCer. A detail view of (b) the piston hovering over the
LTCC surface and (c) the two electrode pairs.

42 October 2019
gradient within the substrate, SiCer in combination
with thermal vias offers great potential (e.g., for dew
point sensors or thermally stabilized RF MEMS). Due
to its outstanding substrate characteristics, combining
extreme material properties in one wafer, SiCer allows
novel MEMS applications, such as 3D tunable varactors
or Si MEMS switches that switch RF functions directly
and without any RF parasites in the ceramics.
Acknowledgment
We are grateful for the financial support of the Ger-
man Research Foundation (DFG) in the framework of
the MUSIK (Multiphysical Synthesis and Integration of
Complex RF Circuits) research unit (FOR1522).
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