National Institute of Technology Goa

Department of Electronics and Communication Engineering

Master of Technology VLSI

Lab Report
on
MOS Characteristics

Submitted by:
Danthamala Nikhil
VLSI 1st year
19ECE2005
Contents

1 Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) 3

1.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 N channel-MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1 NMOS circuit: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.2 IDS -VGS characteristics of a n-channel MOSFET . . . . . . . . . . . . 6
1.3.3 Parametric analysis of IDS -VGS characteristics of a n-channel MOSFET 7
1.3.4 IDS -VDS characteristics of a n-channel MOSFET . . . . . . . . . . . . 8
1.3.5 Parametric analysis of IDS -VDS characteristics of a n-channel MOSFET 9
1.3.6 IDS -Width(w) characteristics of a n-channel MOSFET . . . . . . . . . 10
1.4 P channel-MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4.1 PMOS circuit: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.2 IS D -VS G characteristics of a p-channel MOSFET . . . . . . . . . . . . 14
1.4.3 Parametric analysis of IS D -VS G characteristics of a p-channel MOSFET 15
1.4.4 IS D -VS D characteristics of a p-channel MOSFET . . . . . . . . . . . . 16
1.4.5 Parametric analysis of IS D -VS D characteristics of a p-channel MOSFET 17
1.4.6 IS D -Width(w) characteristics of a p-channel MOSFET . . . . . . . . . 18
1.5 Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1
List of Figures

1.1 The NMOS Circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2 IDS -VGS variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 IDS -VGS characteristics by varying VDS . . . . . . . . . . . . . . . . . . . . . 7
1.4 IDS -VDS variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 IDS -VDS characteristics by varying VGS . . . . . . . . . . . . . . . . . . . . . 9
1.6 IDS -W graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 The PMOS Circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.8 IS D -VS G variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.9 IS D -VS G characteristics by varying VSD . . . . . . . . . . . . . . . . . . . . . 15
1.10 IS D -VS D variation graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.11 IS D -VS D characteristics by varying VSG . . . . . . . . . . . . . . . . . . . . . 17
1.12 IS D -W graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2
Chapter 1

Metal-Oxide Semiconductor Field-Effect

Transistor (MOSFET)

1.1 Objective
To simulate the Nmos and Pmos circuits and to observe the variations in drain current ID by
varying different values of gate voltage and drain-source voltage.

1.2 Introduction
The metal-oxide semiconductor field-effect transistor (MOSFET) is actually a four-terminal
device. In addition to the drain, gate and source, there is a substrate, or body, contact. Generally,
for practical applications, the substrate is connected to the source terminal. If this is the case
(and it usually is), the MOSFET may be considered a standard three-terminal device, with the
drain, gate and source the terminals of interest.

Like all FET structures, the MOSFET uses the field effect to operate – the attraction or repul-
sion of charge carriers through an applied voltage – but this device has a twist that has allowed
it to become the predominant technology for silicon based FETs. The MOSFET structure has
dominated primarily due to the availability of a high quality oxide (SiO2, or silicon dioxide)
for the silicon system. As we will see, this oxide acts as an insulator and provides electrical
isolation between the gate and an active (conduction) channel between the source and drain,
thus providing the required input/output isolation.

The MOSFET (Metal Oxide Semiconductor Field Effect Transistor) transistor is a semi-
conductor device which is widely used for switching and amplifying electronic signals in the
electronic devices. The MOSFET is a core of integrated circuit and it can be designed and
fabricated in a single chip because of these very small sizes. The MOSFET is a four terminal
device with source(S), gate (G), drain (D) and body (B) terminals. The MOSFET is very far
the most common transistor and can be used in both analog and digital circuits.

The MOSFET is of two types Enhancement type and Depletion type. In Depletion type the
channel is already formed and in Enhancement type channel is formed after giving the gate
voltage. Enhancement type MOSFET is used mostly because it gives more control over the
device.

3
 Again the EMOSFET is divided into two types :

• The n-channel MOSFET, called the NMOS, where the majority carrier type is electrons.

• The p-channel MOSFET, or PMOS, where the majority carrier type is holes.

1.3 N channel-MOSFET
The N-Channel MOSFET has a N- channel region between source and drain.In this type of
MOSFET the drain and source are heavily doped n+ region and the substrate or body is P- type.
The current flows due to the negatively charged electrons.

When we apply the positive gate voltage the holes present under the oxide layer pushed
downward into the substrate with a repulsive force. The depletion region is populated by the
negative charges which are associated with the acceptor atoms. The electrons reach channel is
formed. The positive voltage also attracts electrons from the n+ source and drain regions into
the channel.

Now, if a voltage is applied between the drain and source the current flows freely between the
source and drain and the gate voltage controls the electrons in the channel. Instead of positive
voltage if we apply negative voltage a hole channel will be formed under the oxide layer.

Conditions for a NMOS to operate in different regions are :

Cutoff region :

Vgs < Vthn Id = 0

Linear region :

W 1
Vgs > Vthn , Id = µn Cox [(Vgs − Vthn )Vds − Vds2 ]
L 2
Vds < Vgs − Vthn

Saturation region :

1 W
Vgs > Vthn , Id = µn Cox [(Vgs − Vthn )2 ]
2 L
Vds ≥ Vgs − Vthn

4
Parameters:

• Vgs -The gate-source voltage.

• Vds -The drain-source voltage.

• Vthn -The threshold voltage.

• Id -The drain current.

• W-The width of the transistor.

• L-The gate length of the transistor.

• µn -The electron mobility of the transistor substrate.

• Cox -The specific capacitance of the gate oxide.

1.3.1 NMOS circuit:

G D

S
+ Vds
−
Vgs +
−

Figure 1.1: The NMOS Circuit diagram

5
1.3.2 IDS -VGS characteristics of a n-channel MOSFET

output

250.0µ

200.0µ

150.0µ
ID(A)

100.0µ

Subthreshold
50.0µ

0.0

Vth
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VGS(v)

Figure 1.2: IDS -VGS variation

The drain current variation by varying gate voltage can be seen from above graph, where the
Vth =477.155 mv=0.477 v.Theoretically before Vth the drain current should be zero but,practically
the current IDS is not zero before Vth , that region is called subthreshold.

Practically in subthreshold region the drain current ID is not zero, but very little current
exists in that region.

6
1.3.3 Parametric analysis of IDS -VGS characteristics of a n-channel MOS-
FET
VDS=0.6 v

VDS=1.2 v

VDS=0.2 v

VDS=0.4 v

250.0µ

200.0µ

150.0µ
ID(A)

100.0µ

VDS

50.0µ

0.0

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VGS(v)

Figure 1.3: IDS -VGS characteristics by varying VDS

We can observe the variation in graphs of IDS -VGS by varying the values of VDS from 0 to
1.8 V.As VDS is decreasing the current is also decreasing,as VDS becomes zero the current also
becomes zero.

7
1.3.4 IDS -VDS characteristics of a n-channel MOSFET

output

70µ

60µ

50µ

40µ
ID(A)

30µ

20µ

10µ

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VDS(v)

Figure 1.4: IDS -VDS variation

The current IDS variation by varying VDS voltage can be seen from above graph.As the
voltage VDS is increasing to 1.8 v the current IDS is becoming constant.

8
1.3.5 Parametric analysis of IDS -VDS characteristics of a n-channel MOS-
FET

VGS=1.8 v

VGS=0.9 v

VGS=1.1 v

VGS=1.3 v

VGS=1.5 v
250.0µ VGS
VGS=0.6 v

200.0µ

150.0µ
IDS(A)

100.0µ

50.0µ

0.0

-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

VDS(v)

Figure 1.5: IDS -VDS characteristics by varying VGS

We can observe the variation in graphs of IDS -VDS by varying the values of VGS from 0 to
1.8 V.As VGS is decreasing the current is also decreasing,as VGS becomes zero the current also
becomes zero.

9
1.3.6 IDS -Width(w) characteristics of a n-channel MOSFET

output

18.0m

16.0m

14.0m

12.0m

10.0m
ID(A)

8.0m

6.0m

4.0m

2.0m

0.0

0 20 40 60 80 100

w(um)

Figure 1.6: IDS -W graph

From the formula of IDS we can say that, ”w” and IDS are directly proportional to each
other so, as in the above graph we can say that as ”w” increases, the current IDS also increases
linearly.

10
1.4 P channel-MOSFET
The P- Channel MOSFET has a P- Channel region between source and drain. The drain and
source are heavily doped p+ region and the body or substrate is n-type. The flow of current is
positively charged holes.

When we apply the negative gate voltage, the electrons present under the oxide layer with
are pushed downward into the substrate with a repulsive force. The depletion region populated
by the bound positive charges which are associated with the donor atoms. The negative gate
voltage also attracts holes from p+ source and drain region into the channel region.

A PMOS transistor is made up of p-type source and drain and a n-type substrate. When a
positive voltage is applied between the source and the gate (negative voltage between gate and
source), a p-type channel is formed between the source and the drain with opposite polarities.

A current is carried by holes from source to the drain through an induced p-type channel. A
high voltage on the gate will cause a PMOS not to conduct, while a low voltage on the gate will
cause it to conduct. Logic gates and other digital devices implemented using PMOS are said
have PMOS logic. PMOS technology is low cost and has a good noise immunity.

PMOS circuits are slow to transition from high to low. When transitioning from low to high,
the transistors provide low resistance, and the capacitive charge at the output accumulates very
quickly.But the resistance between the output and the negative supply rail is much greater, so
the high-to-low transition takes longer.

Conditions for a PMOS to operate in different regions are :

Cutoff region :

Vsg < |Vthp | Id = 0

Linear region :

W 1
Vsg > |Vthp |, Id = µn Cox [(Vsg − |Vthp |)Vsd − Vsd2 ]
L 2
Vsd < Vsg − |Vthp |

Saturation region :

1 W
Vsg > |Vthp |, Id = µn Cox [(Vsg − |Vthp |)2 ]
2 L
Vsd ≥ Vsg − |Vthp |

11
Parameters:

• Vsg -The source-gate voltage.

• Vds -The source-drain voltage.

• |Vthp |-The threshold voltage.

• Id -The drain current.

• W-The width of the transistor.

• L-The gate length of the transistor.

• µn -The electron mobility of the transistor substrate.

• Cox -The specific capacitance of the gate oxide.

12
1.4.1 PMOS circuit:

S
G

+ Vsd
Vsg + −
−

Figure 1.7: The PMOS Circuit diagram

13
1.4.2 IS D -VS G characteristics of a p-channel MOSFET

output

80.0µ

60.0µ
ID(A)

40.0µ

20.0µ

0.0

-2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2
|Vth|
VSG(v)

Figure 1.8: IS D -VS G variation

The drain current variation by varying source-gate voltage can be seen from above graph,
where the |Vth |=570.2 mv=0.57 v.Theoretically before |Vth | the drain current should be zero
but,practically the current IS D is not zero before |Vth |, that region is called subthreshold.

Practically in subthreshold region the drain current ID is not zero, but very little current
exists in that region.

14
1.4.3 Parametric analysis of IS D -VS G characteristics of a p-channel MOS-
FET

VSD=-0.6 V

VSD=-0.4 V

VSD=-1 V

VSD=-1.6 V
100.0µ
VSD=-1.8 V

80.0µ

60.0µ
ID(A)

40.0µ
VSD

20.0µ

0.0

-2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0

VSG(v)

Figure 1.9: IS D -VS G characteristics by varying VSD

We can observe the variation in graphs of IS D -VS G by varying the values of VSD from 0 to
-1.8 V.As VSD is increasing the current is decreasing,as VSD becomes zero the current becomes
zero.

15
1.4.4 IS D -VS D characteristics of a p-channel MOSFET

output

100.0µ

80.0µ

60.0µ
ID(A)

40.0µ

20.0µ

0.0

-2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2

VSD(v)

Figure 1.10: IS D -VS D variation graph

The current IS D variation by varying VS D voltage can be seen from above graph.As the
voltage VS D is decreasing to -1.8 v the current IS D is becoming constant.

16
1.4.5 Parametric analysis of IS D -VS D characteristics of a p-channel MOS-
FET

VSG=-0.6 v

VSG=-0.8 v

VSG=-1.2 v
100.0µ
VSG=-1.4 v

VSG VSG=-1.8 v

80.0µ

60.0µ
ID(A)

40.0µ

20.0µ

0.0

-2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2

VSD(v)

Figure 1.11: IS D -VS D characteristics by varying VSG

We can observe the variation in graphs of IS D -VS D by varying the values of VSG from 0 to
-1.8 V.As VSG is increasing the current is decreasing,as VSG becomes zero the current becomes
zero.

17
1.4.6 IS D -Width(w) characteristics of a p-channel MOSFET

output

6.0m

5.0m

4.0m
ID(A)

3.0m

2.0m

1.0m

0.0

0 20 40 60 80 100

w(um)

Figure 1.12: IS D -W graph

From the formula of IS D we can say that, ”w” and IS D are directly proportional to each
other so, as in the above graph we can say that as ”w” increases, the current IS D also increases
linearly.

18
1.5 Result
Theoretically, the variation in the graph of IDS -VGS or IS D -VS G in NMOS and PMOS re-
spectively should start from the threshold voltage Vth , but practically as we have observed in
the lab during simulation, there exists little current ID before the threshold voltage, which is
called subthreshold region.

1.6 Conclusion
After performing this simulation in the lab, we have observed, how the drain current is
changing by varying different parameters like gate-source voltage, drain-source voltage and
width of the Mosfet in both NMOS and PMOS.

19