Abhijit Thesis Good PDF

Design of Grid Connected Solar Inverter
with Reduced THD using Adaptive

Harmonic Elimination Technique
A Project Report
Submitted in Partial Fulfilment of
Requirement for the Degree of
Master of Engineering
in
Electrical Engineering
By
Abhijit K
Department of Electrical Engineering

Indian Institute of Science
Bangalore - 560 012
India
June 2011
Acknowledgements
I feel fortunate to have Dr. Vinod John as my project guide. I thank him for letting me
work on an exciting as well as challenging problem. His invaluable, timely suggestions have
been extremely helpful throughout the course of the project. I am grateful for his interest
in my work and his constant encouraging words. He has been the impetus for my project.
It was a great learning experience in the courses taught by him. His course on ‘Top-
ics in Power Electronics and Distributed Generation’ gave me a new perspective on power
electronics design.
With an extreme sense of gratitude, I thank Prof. V Ramanarayanan for the enlightening
courses he taught. He remains a great source of motivation for me to continue working in
the field of Power Electronics. His simplified way of explaining the concepts of engineering
in general have been greatly inspiring.
It was a pleasure attending the course on ‘Electric Drives’ by (Late)Prof. VT Ran-
ganathan. His outstanding teaching and the simulation exercises given by him were instru-
mental in making me learn the concept of vector control and contro design in general. His
passing away was an extremely painful event and a huge loss for our department.
I sincerely thank Prof. G Narayanan for his excellent teaching. The lab courses offered
by him and the corresponding mini-projects were very helpful.
I thank Prof. Udayakumar and Prof. Kuruvila Verghese of CEDT for their excellent
courses on Electromagnetism and Digital design with FPGAs respectively.
I thank all the professors at IISc who have taught me.
I would like to thank Anirudh, Nimesh, AKP, Pavan for the useful academic discussions
I have had with them. I also thank Anirban, Shivaprasad, Soumitro, Amit Jain for their
help. I am grateful to M.E seniors Venkat, Modi, Shan, Anand for being extremely helpful
and for their academic suggestions.
i
ii Acknowledgements
My stay at IISc has been a pleasurable experience due to my control system lab group
namely Arjun, Francis, Chinmay, Deba, Pradeep. I thank my friends Rahul, Sujata, Anil,
Srikanth, Umesh for the fruitful academic discussions with them and for being supportive
always. I specially thank Sethupathy for introducing me to the wonderful world of Linux
and making me an active Linux user. I should mention the table tennis I used to play with
Deba, Francis, Rahul, Sujata which used to be a lot of fun. I thank Anindita, my friend
from B.tech days for her interest in my project and the helpful suggestions. I thank Arun
K, friend from B.Tech and IISc for the discussions on linguistics we used to have. I thank
all M.E friends of mine for helping me in one way or the other.
I would like to thank GE for providing me scholarship and making me a part of GE
scholar leader program.
I thank Shankar for making the layouts for my circuit boards.
I thank Silvi madam for her kind help. I thank Mr. D.M Channegowda, Mr. H.N
Purushottam, Mr.Kini for providing excellent administrative help. I thank the members of
workshop for helping me for my project.
I dedicate all my success to my loving parents. Their faith in me, their encouragement
and guidance are the the reason for whatever I have achieved in my life. I thank them for
being with me always and supporting me at all times.
Finally, I thank God Almighty for giving me strength at all times.
Abstract
Presently a lot of work is being carried out in the field of distributed generation. Many
distributed generation systems are being designed and connected to the electric grid. At the
time when the conventional sources of energy such as coal, oil etc are fast disappearing, a
study of distributed generation systems and building of such systems using renewable energy
sources becomes very important.
When a DG source is being connected to the grid, there are many constraints to be
met one of which is the harmonic content of the current being injected into the grid. The
current being injected should have harmonic content conforming to standards such as IEEE
512-1992[19].
This project deals mainly with building the hardware for a grid interactive inverter. This
means that a proper scheme should be present in the system to limit the harmonic current
injection into grid. The hardware is customized to be used for a PV panels based distributed
generation system.
In this work, filters are designed to eliminate only the higher order harmonics. This
is due to the reason that filters would be less bulky and cheap when they are designed to
attenuate only the higher order harmonics. In order to mitigate the lower order harmonics,
an adaptive selective harmonic elimination technique(AHE) is used. The validity of AHE
technique is verified in hardware.
Overall, the project work involves the building of the inverter hardware, the filters, trans-
former and design and implementation of closed loop control along with AHE scheme.
iii
Contents
Acknowledgements i
Abstract iii
List of Tables vii
List of Figures viii
Nomenclature xii
1 Introduction 1
1.1 Project Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Organization of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Theoretical Background 6
2.1 Lower order harmonic injection . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Limitations of the dead-time effect analysis . . . . . . . . . . . . . . . . . . . 10
2.3 LMS Adaptive Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 LMS algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Adaptive Harmonic Elimination . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Hardware Design 15
3.1 System Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Design of the boost stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1 Construction of boost inductor . . . . . . . . . . . . . . . . . . . . . 17
3.3 Design of dc bus capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
iv
Contents v
3.3.1 Calculation of 100Hz ripple . . . . . . . . . . . . . . . . . . . . . . . 20

3.3.2 Calculation of switching frequency ripple . . . . . . . . . . . . . . . 20
3.4 Transformer Design[7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Output filter inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6 Development of the main circuit board . . . . . . . . . . . . . . . . . . . . . 23
3.7 Design of Non-isolated voltage and current sensor board . . . . . . . . . . . 24
3.7.1 Limitations of the designed sensor board . . . . . . . . . . . . . . . . 27
3.8 Loss Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 Control Design 29
4.1 Design of single phase PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.2 Design of the current control . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3 Voltage controller design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.4 Digital implementation of control blocks . . . . . . . . . . . . . . . . . . . . 37
4.4.1 PI controller implementation . . . . . . . . . . . . . . . . . . . . . . . 37
4.4.2 Implementation of resonant controller . . . . . . . . . . . . . . . . . . 38
4.4.3 Per-unit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5 Simulation Results 41
5.1 Parameters used for simulation . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2 Low load without AHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.3 Low load with AHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.4 Higher load without AHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.5 Higher load with AHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6 Experimental Results 45
6.1 Stand-alone operation without transformer . . . . . . . . . . . . . . . . . . . 45
6.2 Stand-alone mode with transformer . . . . . . . . . . . . . . . . . . . . . . . 47
6.3 Grid connected case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3.1 Operation in upf without compensation . . . . . . . . . . . . . . . . . 50
6.3.2 Operation in STATCOM mode without compensation . . . . . . . . . 51
6.4 Compensation issues in grid connected case . . . . . . . . . . . . . . . . . . . 51
6.5 System Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
vi Contents
7 Conclusions 56
A Main circuit board schematics 58

A.1 Connectors of main circuit board . . . . . . . . . . . . . . . . . . . . . . . . 58
A.2 Adjustable Dead-time Generation Circuits . . . . . . . . . . . . . . . . . . . 59
A.3 Level Shifting Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
A.4 Main Protection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
A.5 Comparator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
A.6 Annunciation Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
A.7 On-board power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
A.8 Power circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
B Pictures of Hardware Setup 66

B.1 Main circuit board - Version 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 66
B.2 Sensor board - Version 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
B.3 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
References 69
List of Tables
3.1 Ratings of solar panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.2 Control power requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Estimated losses in power circuit . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1 Current controller parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.2 Voltage controller parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.3 pu values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
vii
List of Figures
1.1 Schematic diagram of a DGS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Power circuit topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Terminal characteristics of a solar panel (Present on department roof) . . . . 3
2.1 Switching logic pulses for a leg . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Error voltage due to dead-time . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Dead-time influence on average pole voltage . . . . . . . . . . . . . . . . . . 8
2.4 Schematic of a grid connected 1-φ inverter . . . . . . . . . . . . . . . . . . . 9
2.5 Net error voltage across filter . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Generalized adaptive filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7 Block diagram of adaptive estimation of a particular harmonic . . . . . . . . 13
2.8 Generation of voltage reference from estimated ik . . . . . . . . . . . . . . . 14
3.1 Power circuit topology with L filter at ac side . . . . . . . . . . . . . . . . . 15

3.2 Boost stage of the power circuit . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Current through boost inductor under CCM . . . . . . . . . . . . . . . . . . 17
3.4 Fringing effect model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 N Vs lg curve for boost inductor . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 One channel of the non-isolated voltage sensor circuit . . . . . . . . . . . . . 25
3.7 One channel of the current sensor circuit . . . . . . . . . . . . . . . . . . . . 25
3.8 Voltage sensor transfer characteristics for dc input voltage . . . . . . . . . . 26
3.9 Current sensor transfer characteristics for ac input current . . . . . . . . . . 26
4.1 Structure of second order generalized integrator[2] . . . . . . . . . . . . . . . 30

4.2 Aligning grid voltage along q-axis . . . . . . . . . . . . . . . . . . . . . . . . 30
viii
List of Figures ix
4.3 Single phase PLL control structure . . . . . . . . . . . . . . . . . . . . . . . 31

4.4 Step response of transfer functions in SOGI (experimental result) . . . . . . 31
4.5 Step response of transfer functions in SOGI (simulation result) . . . . . . . . 32
4.6 Input and corresponding unit vectors(experimental result) . . . . . . . . . . 32
4.7 PLL outputs when input is rich with harmonics (experimental result) . . . . 33
4.8 Complete current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.9 Current loop for equivalent 3-φ system . . . . . . . . . . . . . . . . . . . . . 35
4.10 Voltage control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.11 Magnitude bode plot for voltage control . . . . . . . . . . . . . . . . . . . . 36
4.12 Digital circuit of PI controller . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.13 Digital circuit of resonant controller . . . . . . . . . . . . . . . . . . . . . . . 39
5.1 Output current and its spectrum without adaptive compensation(low load) . 42
5.2 Output current and its spectrum with adaptive compensation(low load) . . . 42
5.3 Output current and its spectrum without adaptive compensation(high load) 43
5.4 Output current and its spectrum with adaptive compensation(high load) . . 44
6.1 Power circuit for stand-alone mode without transformer . . . . . . . . . . . . 45

6.2 Load current[CH2: Red; Scale: 3.2A/1V] and its third harmonic content[CH1:
Blue; Scale: 3.2A/1V] stand-alone without transformer and without compen-
sation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Blue; Scale: 3.2A/1V] stand-alone without transformer and with compensation 46
6.4 Effect of enabling current control. [CH1:Blue:Current controller error; Scale:
1A/1V] and [CH2:Red:Load current; Scale: 3.2A/1V] . . . . . . . . . . . . . 47
Blue; Scale: 3.2A/1V] stand-alone without transformer and without compen-
sation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Blue; Scale: 3.2A/1V] stand-alone without transformer and with compensation 48
6.7 Power circuit for stand-alone mode with transformer . . . . . . . . . . . . . 48
x List of Figures
6.8 Primary current[CH2: Red; Scale: 3.2A/1V] , its third harmonic content[CH1:
Blue; Scale: 3.2A/1V] and secondary current[CH3: Green; Scale: 1A/1V]
stand-alone with transformer and without compensation . . . . . . . . . . . 49
6.9 Primary current[CH2: Red; Scale: 3.2A/1V] , its third harmonic content[CH1:
Blue; Scale: 3.2A/1V] and secondary current[CH3: Green; Scale: 1A/1V]
stand-alone with transformer and with primary side compensation . . . . . . 50
6.10 Secondary current[CH2: Red; Scale: 1A/1V] , its third harmonic content[CH1:
Blue; Scale: 1A/1V] and primary current[CH3: Green; Scale: 3.2A/1V] stand-
alone with transformer and without compensation . . . . . . . . . . . . . . . 51
6.11 Secondary current[CH2: Red; Scale: 1A/1V] , its third harmonic content[CH1:
Blue; Scale: 1A/1V] and primary current[CH3: Green; Scale: 3.2A/1V] stand-
alone with transformer and with secondary side compensation . . . . . . . . 52
6.12 Load voltage[CH4: Pink; Scale: 1V/1V] , voltage reference[CH1: Blue; Scale:
1V/1V] and secondary current[CH3: Green; Scale: 1A/1V] stand-alone with
transformer and with secondary side compensation . . . . . . . . . . . . . . 53
6.13 Phasor diagram for upf operation . . . . . . . . . . . . . . . . . . . . . . . . 53
6.14 Sensed grid voltage[CH3: Green; Scale:1V/1V] , in phase unit vector[CH1:
Blue; Scale:1V/1V] , secondary current[CH4: Pink; Scale: 1A/1V], primary
current[CH2: Red; Scale: 3.2A/1V] when inverter is OFF . . . . . . . . . . . 53
6.15 Sensed grid voltage[CH3: Green; Scale:1V/1V] , in phase unit vector[CH1:
Blue; Scale:1V/1V] , primary current[CH4: Pink; Scale: 1A/1V] for upf opration 54
6.16 Fundamental component of secondary current[MATH: Cyan; Scale:1A/1V]
, Net harmonic current[CH1: Blue; Scale:1A/1V , secondary current[CH4:
Pink; Scale: 1A/1V] for upf opration . . . . . . . . . . . . . . . . . . . . . . 54
6.17 Grid voltage[CH3: Green; Scale:1V/1V], primary current[CH4: Pink; Scale:
1A/1V] for 0pf lead opration . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.18 Grid voltage[CH3: Green; Scale:1V/1V], primary current[CH4: Pink; Scale:
1A/1V] for 0pf lag opration . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.19 Grid current[CH2: Red; Scale: 1A/1V], Second harmonic component of grid
current[CH1: Blue; Scale: 1A/1V] for upf opration . . . . . . . . . . . . . . . 55
6.20 Grid current[CH2: Red; Scale: 1A/1V], Second harmonic component of grid
current[CH1: Blue; Scale: 1A/1V] for upf opration with adaptive compensation 55
List of Figures xi
A.1 Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
A.2 Dest-time generation circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
A.3 Level shifting circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
A.4 Main protection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
A.5 Comparator circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
A.6 Annunciation circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
A.7 On-board power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
A.8 Power Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
B.1 Picture of main circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . 66

B.2 Picture of non-isolated voltage and current sensor board . . . . . . . . . . . 67
B.3 Picture of Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Nomenclature
Symbols : Definitions
td : Dead-time
Vdc : Voltage of the dc bus
Ts : Switching period
∆V pole : Average error voltage due to dead-time
ζ : Performance function for general adaptive filter
w : Weight vector of an adaptive filter
x(n) : Input vector of an adaptive filter
e(n) : Error signal of an adaptive filter
Wcos , Wsin : Weights for adaptive estimator block
Lboost : Inductor of boost stage
Lf ilt : AC side filter inductor
Ap : Area-product
kw : Winding factor
J : Operating current density for copper
Bm : Peak flux density of inductor core
i100Hz : Ripple on dc bus voltage due to 100Hz component
isw,rms : Ripple on dc bus voltage due to switching frequency component
icap,ripple : Net dc bus capacitor ripple current
∆V : Voltage ripple on dc bus
Va , Vb : Outputs of SOGI
Vg : Grid Voltage
Kp,P R , Kr : Gains of PR controller
Kv , Tv : Gains of PI controller
xii
Nomenclature xiii
ωo : Grid frequency in rad/s

Chapter 1
Introduction
Renewable sources of energy such as solar, wind, geo-thermal have gained popularity due
to the depletion of conventional energy sources such as coal, gas etc. These renewable
energy sources are becoming very important in electric power generation. Presently many
distributed generation systems making use of the renewable energy sources are being designed
and connected to grid.
Fig.1.1 shows a schematic diagram of a distributed generation system (DGS) with solar
energy as the source. As in Fig.1.1, power converters, filters, transformers are required as
the interface between the energy source and the grid. The proper functioning of the DG
systems depends very much on the design of the interface.
Solar Panels - ~ / Grid
Interface
(Power Converter, Filter, Transformer)
Figure 1.1: Schematic diagram of a DGS
The design of the interface, usually consisting of the power converter, filter and trans-
former is expected to meet the following criteria:
• High efficiency of the complete system
• Conforming to the standards IEEE 519-1992[19] which specifies the amount of har-
monic current injection into the grid and IEEE 1547-2003[20] which is a standard for
1
2 Chapter 1. Introduction
interconnection of DGS with the electric power system.
• Reliability and Cost Reduction
1.1 Project Work

This project deals with the complete design and control of a power converter suitable for a
DGS using solar panels as the source. Fig.1.2 shows the power circuit topology.
Lboost Dboost S1 S3
Lfilt
PV Cdc
Vdc
Array Vg
Sboost S2 S4
~
Cfilt
Grid
1:10
Figure 1.2: Power circuit topology
As the design is done considering solar panels as the source, a boost stage is required
to operate the solar panels at the maximum power point (MPPT)[9]. Fig.1.3 shows the V-I
and P-V characteristics of a solar panel (From measurements).
Only at a particular operating point, the panels give maximum power. The boost stage
is used to adjust the resistance seen by the panels by controlling its duty ratio, hence keeping
the panels at MPPT. This arrangement is essential to have a better efficiency of the entire
system.
The boost stage is followed by the single phase H-bridge inverter. The switches of the
inverter are modulated using sine-triangle PWM to convert the dc input into pulsating ac
voltage output. The inverter switches are MOSFETs as the solar panels voltage levels are
quite small. Vmpp shown in Fig.1.3 is around 10-12V.
Output of the inverter is connected to the filter (either L or LC). Ideally, PWM of
1.1. Project Work 3
Figure 1.3: Terminal characteristics of a solar panel (Present on department roof)

4 Chapter 1. Introduction
switches shifts all the harmonics to switching frequency and its multiples. Thus the filter is
to be designed to attenuate these higher order harmonics.
However, in real systems, lower order harmonics are also present. The following factors
are responsible for the presence of lower order harmonics:
• The dead-time introduced between the switchings of devices of the same leg[5]
• The on-state voltage drops on the switches
• The magnetizing current drawn by the transformer is usually rich in lower order har-
monics
In order to limit the amount of lower order harmonic current into the grid, a simple
solution would be to increase the filter size. But this makes the filter bulky and increases
the cost. Thus in this project, an adaptive harmonic elimination technique (AHE)[1] is used
to limit the injection of these harmonics into the grid.
The details of lower order harmonic injection due to dead-time, device drops and the
details of the AHE technique are discussed in chapter2.
Apart from the hardware development, the project work involves the closed loop control
of the power converter. The power converter is controlled as a current source. As the inverter
is single phase, a PR controller is used in the current loop to have zero steady state error.
The AHE technique is incorporated in the control to reduce the lower order harmonics.
Chapter4 discusses the control design in detail.
1.2 Organization of the thesis

In chapter 2, the effect of dead-time and device drops in producing lower order harmonics is
discussed. It also includes a discussion on adaptive filters based on Least Mean Square(LMS)
algorithm, and making use of such a filter for adaptive harmonic elimination of lower order
harmonics.
Chapter 3 discusses the hardware design in detail. The selection of switches, dc bus
capacitors; design of filters, transformers and the development of main circuit board, sensor
board is discussed. This chapter also presents the loss calculations and the overall system
efficiency.
1.2. Organization of the thesis 5
Chapter 4 includes the details of the control system design and implementation of the
same in digital domain.
In chapter 5, simulation results of the grid connected inverter operation with AHE are
included. The simulations are carried out in MATLAB Simulink.
In chapter 6, all the experimental results with the pertinent waveforms are discussed.
Conclusion and Future work are discussed in chapter 7.
The schematics of main circuit board and the pictures of the hardware are provided in
Appendix.
Chapter 2
Theoretical Background
In this chapter, the effect of dead-time on producing the lower order harmonics[5] is discussed.
A simplified mathematical treatment of the same is presented. The limitations of the model
for a PWM inverter are also highlighted. Theory of adaptive filters and their application in
selective harmonic elimination is discussed in section 2.3 of this chapter.
2.1 Lower order harmonic injection

In any inverter, the devices on the same leg are switched in a complementary fashion. In real
devices, however, there is a finite switching time. Thus if complementary gate pulses were
to be given to these switches directly, then there would exist a finite time when both the
switches would not have turned off completely. This would result in shorting of the dc bus
which is undesired. Hence a dead-time is introduced between the switchings of the devices
of the same leg. Dead-time is the time during which the device which was ON would turn
off. So, after the dead-time the device which was OFF could be turned ON.
For an inverter leg with switches S1 and S2 , the pulses to be given ideally and the pulses
with dead-time are shown in Fig.2.1. The dead-time td has to be at least equal to the turn-off
time of the devices.
Now, to analyze the effect due to dead-time, consider Fig.2.3. In case-1, the top device is
ON. The current at the pole is assumed to be in the direction shown. When the top device
gets the turn-off command, the bottom would still be kept OFF to ensure the dc bus does
not get shorted.
During the dead-time when both the devices are OFF, the current would flow through
the body diode of the bottom device. This means that during the dead-time, when the
6
2.1. Lower order harmonic injection 7
S2 S2
Figure 2.1: Switching logic pulses for a leg
current is positive, the pole voltage would be same as the case when bottom device is ON.
Clearly from the Fig.2.3, it can be observed that the average pole voltage falls by a fixed
amount during positive half cycle of the current.
Similarly, when the current is negative, it can be proved that the average pole voltage
increases by the same amount.
Thus, the dead-time effect on average pole voltage can be summarized in the following
set of equations.
Vdc td
∆V pole = − f or i>0 (2.1)
Ts
Vdc td
∆V pole = f or i<0 (2.2)
Ts
Fig.2.2 shows the inductor current and the average pole voltage due to dead-time. This
is for one leg of an inverter.
i
0
time
-ipeak
Figure 2.2: Error voltage due to dead-time

8 Chapter 2. Theoretical Background
S1 S1
Lfilt Lfilt
Vdc Vpole Vdc Vpole
Iload Iload
S2 S2
Case-1 Case-2
Vpole
Vdc
Ts
Vpole
(Ideal)
Vdc
Ts
Figure 2.3: Dead-time influence on average pole voltage

2.1. Lower order harmonic injection 9
The same analysis can be extended to the other leg of a H-bridge inverter. Fig.2.4 shows
the schematic of a grid connected H-bridge inverter.
Cdc
S1 S3
G1 G3
Lfilt
Vdc
i
Cdc Vg
S2 S4 ~
G2 G4
Figure 2.4: Schematic of a grid connected 1-φ inverter
For the leg containing switches S3 and S4 , the error voltage due to dead-time would be
same as in Fig.2.2 except that there would be a phase lag of 180o . Thus the net voltage error
that gets applied to the filter would be as shown in Fig.2.5.
i,
0
time
-ipeak
Figure 2.5: Net error voltage across filter
From the square wave nature of the voltage that is being applied, it can be clearly
predicted that lower order harmonics would get injected into the grid. Hence the harmonic
voltage peak due to the dead-time error voltage is given by:
2Vdc td
Vn = F or odd n. (2.3)
nTs
The phase of each odd harmonic would be 180o out of phase with respect to the inductor
current. This Vn is responsible for injecting the lower order harmonic currents into the grid.
As mentioned in chapter 1, it could be reduced by using a bulky filter. In this project, an
adaptive technique is used instead.
2.2 Limitations of the dead-time effect analysis

The analysis explaining the effect of dead-time on lower order harmonics assumes that the
current is smooth. In real situation, however, the current is not smooth. It would contain
ripple over the fundamental sine. Thus there could be multiple zero crossings. There could
also be finite time for which the current stays very close to zero. This scenario is not modeled
in the analysis. The analysis assumes that there is only one zero crossing and the average
error voltage jumps sharply at this point.
In a somewhat more detailed model, the multiple zero crossings could be accounted and
that results in an error voltage with notches around the zero crossings. The detailed modeling
is not treated in this thesis. The focus is more on estimating these lower order harmonics
adaptively and compensating them.
2.3 LMS Adaptive Filter

Filters whose parameters (coefficients) are altered according to some algorithm are termed
as adaptive filters[10]. One of the important applications of adaptive filters is compensation
of sinusoidal interference signal[17]. Adaptive filters can adjust to time varying system char-
acteristics which is very attractive[10]. In this project, an adaptive filter whose coefficients
are changed as per Least Mean Square (LMS) algorithm is used.
Fig.2.6 shows a general adaptive filter with N coefficients (weights). The weights are
adapted by making use of LMS algorithm. This section gives the principle of the generalized
filter shown in Fig.2.6.
z-1 z-1 z-1

x(n) x(n-1)
w0 w1 wN-1
X X X
-
d(n) + e(n)
Figure 2.6: Generalized adaptive filter

2.3. LMS Adaptive Filter 11
2.3.1 LMS algorithm

For Fig.2.6 coefficient vector is defined as:
w = [wo w1 ... wN −1 ]T (2.4)
Input vector and filter output are given in Equations.2.5 and 2.6.
x(n) = [x(n) x(n − 1) ... x(n − N + 1)]T (2.5)
y(n) = wT x(n) (2.6)
The error signal is,

e(n) = d(n) − y(n) (2.7)
A performance function is defined as
ζ = E[e2 (n)] (2.8)
In any adaptive filter, the weight vector w is updated such that the performance function
moves towards its global minimum. Thus the updation of weights would be done as,
w(k + 1) = w(k) − µ∇k ζ (2.9)
In Equation.2.9 µ is the step size. The convergence of the adaptive filter depends on the
step size µ. A smaller value would make the adaption process very slow whereas a large
value would make the system oscillatory.
When the global minimum of ζ is reached, ∇ζ would be zero and there would not be
anymore adaption in weights.
The generalized algorithm mentioned above applies to all adaptive filters. LMS adaptive
filters incorporate a slight modification in the algorithm as in the performance function which
is the expectation of error squared is approximated to be the error squared itself.
Thus, for an LMS adaptive filter, the performance function would be,
ζ = e2 (n) (2.10)
From Equation.2.10, the update equation for LMS algorithm can be deduced. Eqn.2.9
would change as
w(n + 1) = w(n) − µ∇e2 (n) (2.11)
∇ is defined as the gradient with respect to the weights of the filter.

Thus,
∂ ∂ ∂
∇=[ ... ] (2.12)
∂wo ∂w1 ∂wN −1
It can be written that,
∂e2 (n) ∂e(n)

= 2e(n) (2.13)
∂wi ∂wi
From Equation.2.7 and by the assumption that input d(n) is independent of weights,
Equation.2.13 would change as
∂e2 (n)
= −2e(n)x(n − i) (2.14)
∂wi
Or,
∇e2 (n) = −2e(n)x(n) (2.15)
Combining Equation.2.15 and Equation.2.11, the final update equation for weights of an
LMS adaptive filter is obtained, which is
w(n + 1) = w(n) + 2µe(n)x(n) (2.16)
2.4 Adaptive Harmonic Elimination

LMS adaptive filter discussed previously can be used for selective harmonic elimination[?]
of any signal, say current injected into the grid. In this section, the theoretical treatment of
the same is considered.
To reduce a particular harmonic (say ik ) of grid current:
• ik is estimated from the samples of grid current and PLL outputs at that frequency
• A voltage reference is generated from the estimated value of ik
• The calculated voltage reference is subtracted from the main controller voltage refer-
ence. This would have an effect of canceling the voltage that was injecting ik hence
reducing its magnitude
2.4. Adaptive Harmonic Elimination 13
sin (kwot) i(grid current)

X
+
- Error
+
cos (kwot) ik
X
Wcos Wsin
LMS Algorithm
Figure 2.7: Block diagram of adaptive estimation of a particular harmonic
Fig.2.7 shows the block diagram of the adaptive filter that estimates ik .
Suppose k th harmonic of grid current i is to be estimated. The adaptive block takes in
two inputs sin(kωo t) and cos(kωo t) from PLL. These samples are multiplied by the weights
Wcos and Wsin . The output is subtracted from the sensed grid current sample which is taken
as the error to LMS algorithm. The weights are then updated as per LMS algorithm and
the output of this filter would be an estimate of the k th harmonic of grid current.
The weights update would be done by using the equations given below (where Ts is the
sampling time, en is the error of nth sample and µ is the step size):
Wcos (n + 1) = Wcos (n) + 2µen cos(kωo nTs ) (2.17)

Wsin (n + 1) = Wsin (n) + 2µen sin(kωo nTs ) (2.18)
Now a voltage reference has to be generated from this estimated current. The simplest
way is to use a proportional gain. Another method reported is to modify Fig.2.7 to obtain
the direct estimate of the voltage responsible for any particular harmonic[1]. In this project,
the proportional gain method is used as it is very simple and gives practically acceptable
results.
Fig.2.8 shows scheme of the voltage reference generation from estimated harmonic cur-
rent.
The scheme shown in Fig.2.8 can be used to eliminate the lower order harmonics, say
third, fifth etc. The voltage references generated for these estimated currents would be
subtracted from the main reference voltage (produced by the closed loop current controller).
The validity of the algorithm is verified both in simulation and in hardware. These results
are discussed in the coming chapters.
i(grid current) ik vk,ref

sin (kwot) AHE K
cos (kwot)
Figure 2.8: Generation of voltage reference from estimated ik

Chapter 3
Hardware Design
The hardware design of the power circuit is explained in this chapter. It includes the selec-
tion of switches, dc bus capacitors, design and construction of filter inductors and output
transformer.The efficiency and loss calculations are presented. The development of the com-
plete circuit board and the non-isolated voltage and current sensor board are also discussed.
Fig.3.1 shows the power circuit topology.
Lboost Dboost S1 S3
Lfilt
PV Cdc
Vdc
Array Vg
Sboost S2 S4
~
Grid
Figure 3.1: Power circuit topology with L filter at ac side
3.1 System Ratings

The power circuit topology shown in Fig.3.1 is meant to be used as a grid connected inverter
for PV panels. There are six functional panels on the roof of Dept. of Electrical Engineering.
The rating of the power circuit is fixed based on the ratings of the available panels.
15
16 Chapter 3. Hardware Design
Table 3.1: Ratings of solar panels

Component Rated value Measured value
Voc 21V 18.5V
Isc 2.5A 2.15A
Pmax 35W 25W
Vo at Pmax 18V 12V
Measurements were carried out on the solar panels and table 3.1 lists the values.
Thus the total power rating would be 150W. The boost stage is used for MPPT and for
raising the dc bus voltage to around 40V. The inverter output would be stepped up by the
output stage transformer whose rating has to be 150VA at least. In the following sections,
the design of individual stages is presented.
3.2 Design of the boost stage

Only the boost stage of the power circuit is shown in Fig.3.2. Here the design consists of
switch selection, filter inductance calculation and construction.
Lboost Dboost
PV C
S
Array
Rload
Figure 3.2: Boost stage of the power circuit
The voltage input for the boost converter would be 12V. As the dc bust voltage is set at
40V, the steady state duty ratio of the converter would be D = 0.7
Under full rated condition, the current through boost inductor would be
Pmax
Idc = = 12.5A (3.1)
Vin
3.2. Design of the boost stage 17
IL,boost
Idc
0 Ton Ts t
Figure 3.3: Current through boost inductor under CCM
Fig.3.3 shows the current that would flow through the boost inductor under continuous
conduction mode (CCM).
The boost inductance can be evaluated as[18],
Vin DTs,boost
Lboost = (3.2)
∆I
For ∆I = 1App , Ts,boost = 10µs, the inductance turns out to be,
Lboost = 84µH (3.3)
3.2.1 Construction of boost inductor

After obtaining the value of the inductor, the next step would be to construct the inductor.
For that the following parameters are required:
• Core type and size
• Number of turns of wire and wire diameter
• Air-gap length
The core selected for this inductor is ferrite. To obtain the size of the core, area-
product(Ap ) for the inductor is evaluated. As explained in [18],
Lboost Ip Irms
Ap = (3.4)
kw Bm J
For the rated conditions and for Bm = 0.3T, kw = 0.4, J = 2.5A/mm2 , the value turns out
to be
Ap = 43750mm4
The core that suits for this case is EE 42/21/15. For this core, the number of turns(N ) and
the air gap length(lg ) are to be evaluated now. Considering fringing model as specified in
[3], graphical iterative method[4] is used to arrive at the values of N and lg . Fig.3.4 shows
the fringing model used. Fringing is the effective increase in the core area due to spreading
of the flux lines around air gap.
Figure 3.4: Fringing effect model
The steps involved in graphical iterative method are outlined below:
1. Using the fringing model as in Fig.3.4, the expression for inductance is given by:
N2
L= 1 2lg (3.5)
AL
+ µo (Ac+πlg 2 +2lg (f +d)
2. For a given value of L, N is plotted against lg from the equation above.
3. The peak magnetic flux density is given by
N Ip
Bm = 2lg (3.6)
Ac ∗ [ A1L + µo (Ac+πlg 2 +2lg (f +d)
]
4. Again, N vs lg is plotted for a max. allowable Bm which avoids the saturation of the
core.
5. The two curves obtained are superimposed over each other and set of N, lg satisfying
both would be the solution.
3.2. Design of the boost stage 19
Figure 3.5: N Vs lg curve for boost inductor
N Vs lg curve for boost inductor is drawn in Fig.3.5. From the intersection of the two curves
(dashed: at given Lboost ; solid: at given Bm ) the number of turns required and air-gap length
are computed. Thus the summary of design parameters for boost inductor are:
• N = 23
• lg = 0.8mm
• Conductor size = SW G 13
• EE42/21/15 F errite core
The active switch selected is IRF Z44 which satisfies the current and blocking voltage
requirements. Diode used is MUR420. The boost stage active switch is driven by the
MOSFET gate driver IR2110.
3.3 Design of dc bus capacitance

The function of dc bus capacitance is to take the ripple current consisting of 100Hz compo-
nent and switching frequency component while maintaining ripple voltage to be very small.
The design of dc bus capacitance depends on the rms current calculation and its correlation
with the voltage ripple. These calculations would also be required when loss in dc bus and
temperature rise are to be estimated.
3.3.1 Calculation of 100Hz ripple

The grid connected power circuit is rated for 150W. This means the grid current would be
150W/230V = 0.65Arms . The transformer turns ratio is evaluated as 1:10 (which is discussed
in the following section). This means primary current is 6.5Arms . 100Hz component is
evaluated by considering power balance. That is,
Vdc iinv = Vpri,pk ipri,pk (3.7)

Vm im sin2 (ωt)
⇒ iinv = (3.8)
Vdc
Vm im cos(2ωt)
⇒ i100Hz = − (3.9)
Vdc
From eqn. 3.9 and putting in the values, the rms 100Hz current is obtained as,
i100Hz,rms = 2.65A (3.10)
3.3.2 Calculation of switching frequency ripple

In Fig.2.4, let the leg containing switches S1 and S2 be named as leg-a. The other leg is
named leg-b. The duty ratio command for these legs would be:
da = 0.5 + 0.40625sin(ωt) (3.11)

db = 0.5 − 0.40625sin(ωt) (3.12)
√
The current through transformer primary is i = 6.5 2sin(ωt)A. The inverter switching
frequency is 40kHz, thus there would be Ns = 800 samples per fundamental cycle.
The following equation gives the ripple current due to inverter switching[5].
s −1
1 NX 1
isw,rms = |i(nTs )|[{|da (nTs ) − db (nTs )|} − {da (nTs ) − db (nTs )}2 ] 2 (3.13)
Ns n=0
3.4. Transformer Design[7] 21
Eqn.3.13 is evaluated for rated conditions and the ripple current is estimated as
isw,rms = 2.59A (3.14)
There is one more switching frequency component which comes from the boost side. Its
calculation is straightforward and is evaluated to be isw,boost = 5.73A
Thus net ripple current would equal,
q
icap,ripple = i2100Hz,rms + i2sw,rms + i2sw,boost (3.15)
This is calculated to be icap,ripple = 6.82A

A 1000µF, 63V capacitor can carry 1.18Arms (from standard capacitor datasheets). Thus
6 numbers of these capacitors are required in parallel for a ripple of 6.82A.
The voltage ripple would be mainly due to the 100Hz component. It should be ensured
if 6 of these capacitors in parallel give acceptable voltage ripple or not. The expression for
voltage ripple is,
i100Hz,peak
∆V = (3.16)
Cω
Eqn.3.16 for the rated condition would be 1Vpp which is quite acceptable. Thus the dc
bus capacitance is calculated to be 6000µF, 63V .
3.4 Transformer Design[7]

The step up transformer is required for interfacing the low voltage inverter output to the
grid. The transformer, however, adds to distortions in grid current due to the magnetizing
current drawn by it. The design of the transformer involves essentially fixing the number of
primary and secondary turns, the core type and size and construction.
Transformer designed in this project is a three winding transformer. The third winding
is used as the input for on-board control power supply. The control power supply is for the
control portions of main circuit board, sensor board and the FPGA control board. Measure-
ments were carried out to determine the power requirements for control power supply. Table
3.2 shows the power supply requirement for +15V, -15V and +5V. Accounting for losses
in the on-board power supply and transformer itself, the transformer is rated for a total of
170VA.
Transformer secondary is connected to grid and is at nominal voltage 230Vrms . The
√
primary rms would be mVdc / 2. For Vdc = 40V and assuming that the inverter operates at
Table 3.2: Control power requirement

Voltage Level Current Drawn Power
+15V 0.25A 3.75W
-15V 0.25A 3.75W
+5V 0.3A 1.5W
modulation index higher than 0.8, the main turns ratio is evaluated as 1:10. Thus, N1 : N2 =
1 : 10. The tertiary winding output is rectified and given to SMPS using 34166 buck,buck-
boost IC from ON semiconductor. The maximum output voltage in auxiliary power supply
is 15V. If the turns ratio between tertiary and secondary is taken as N3 : N2 = 1 : 10 then
the tertiary winding would have a nominal voltage of 32.5Vpk which is suitable for control
power supply. So the transformer turns ratio are: 1 : 10 : 1 The core selected for transformer
construction is amorphous type. The reason for that is the losses in amorphous cores are
small compared to core with steel stampings. The method used for fixing the transformer
construction data is the standard area-product method[6]. The expression for area-product
is
VA
Ap,trf = (3.17)
2.22Jkw Bm f
For the rated condition eqn.3.17 is evaluated as 100cm4 . Amorphous core AMCC 160 satisfies
the purpose as its Ap,trf is 135.20cm4 . Again the number of turns are evaluated as N1 =
53, N2 = 530, N3 = 53.
The summary of transformer construction parameters is given below:
• Core: Amorphous AMCC 160
• Primary turns: 53 (SWG 15)
• Secondary turns: 530 (SWG 22)
• Tertiary turns: 53 (SWG 22)
3.5 Output filter inductor design

The inverter output is a pulsating ac voltage with dominant harmonics at switching frequency
and its multiples. The L filter and the leakage inductance of the transformer form the
3.6. Development of the main circuit board 23
impedance between inverter output and the grid voltage. As one of the aim of the project is
to have an inductor which attenuates only higher order harmonics, the inductor is designed
assuming that lower order harmonics are absent. The adaptive control takes care of the
attenuation of lower order harmonics.
For a H-bridge inverter, it can be proved that the relation between maximum peak-to-
peak current ripple and filter inductance is given by eqn.3.18.
Vdc Ts
Lf ilt = (3.18)
2∆imax
Rated rms current through the inductor would be 6.5A. For 40kHz switching frequency
and 5% ripple at rated current, the inductance is evaluated as 667µH. For this inductor,
as explained in subsection 3.2.1 the core EE65/32/27 is found to satisfy the requirements.
Again the graphical iterative procedure was followed and the construction parameters were
evaluated as:
• Number of turns: 49
• Air-gap length: 1.5mm
• Conductor size: SWG 15
• EE65/32/27 Ferrite core
3.6 Development of the main circuit board

The main circuit board houses the power circuit shown in Fig.3.1, the gate-drive circuit,
the protection-delay circuit, indicator circuit and the control power supply. The magnetic
components ie., the inductors and the transformer are not mounted on-board. Connectors
are provided for these components on the board.
The functions of protection-delay circuit are mentioned below:
1. It takes in signals from sensor board and compares them with properly set references.
If any of the signal, say inductor current exceeds the reference, a shutdown signal would
be generated and the pulses would be stopped for the MOSFETs. There is protection
for over-current, over-voltage and under-voltage
2. The sensed signals are rerouted to the controller board via the PD circuit. connectors
are provided for the same
3. The PWM signals from controller are level shifted to 15V and input to the gate-driver
circuit after giving an adjustable dead-time
4. The fault-status signals are given to indicator circuit for proper indication of system
health
5. There is an option to disable the protection by simple jumper settings
The function of the indicator circuit is to indicate if there is any fault in the system by
glowing appropriate LEDs. It essentially consists of set of gates and latches.
The gate-drive circuit is very simplified which makes use of IR2110 gate-driver IC. Each
IC drives a leg of the inverter. It provides the proper level shifting required to drive both
high and low side switches as required. The IC has a shutdown(SD) pin which will be made
high under any fault. The gate driver IC withdraws pulses from both the devices once SD
pin is high thus providing protection.
First version of the board was made for si2-7000 MOSFETs (Manufactured in Bangalore).
These MOSFETs, however, were found to fail for a Vdc of more than 20V due to possible
manufacturing defect. Thus in the second version of the board the power circuit foot print
was changed as IRF MOSFETs of TO220 package were finalized for power circuit. The first
version of the board lacked the on-board power supply. Measurements for control power
supply were made on the first version of the circuit board and in the next version the power
supply is also included.
3.7 Design of Non-isolated voltage and current sensor

board
For control and protection of inverters, the information about the voltages and currents
in the circuit is required. The ‘Voltage and Current Sensor Card’ essentially provides this
information. The system voltages are scaled down and currents are converted into a corre-
sponding small signal voltage quantity. The outputs of the sensor card are fed to the PD
cards in the conventional inverters.
3.7. Design of Non-isolated voltage and current sensor board 25
Figure 3.6: One channel of the non-isolated voltage sensor circuit
Figure 3.7: One channel of the current sensor circuit
Usually the voltage sensor cards employ isolation between the input and the output. For
that purpose a separate power supply is designed on board. As isolation is not required
when the input is given as a differential signal. Thus in this work a general purpose sensor
card is designed with no isolation for the voltage sensor. Fig.3.6 shows one channel of the
voltage sensor portion and Fig.3.7 shows the current sensor portion. HE055T is used as the
Hall-effect sensor for current sensor card. A ‘zener clamp circuit’ is used to limit the output
to 10V as required for the controller board.
The sensor board designed has five voltage sensing channels and four current sensing
channels. The maximum voltage that can be sensed is 1000V while the maximum current
that can be sensed is 50A.
Fig.3.8 shows the experimental characteristics of the voltage sensor for dc input voltage
Figure 3.8: Voltage sensor transfer characteristics for dc input voltage
Figure 3.9: Current sensor transfer characteristics for ac input current

3.8. Loss Calculations 27
and Fig.3.9 shows the characteristics of the current sensor for ac current input. The linearity
of the curves can be observed. The same results were obtained for dc input quantity also for
current sensor and for ac input voltage for the voltage sensor.
3.7.1 Limitations of the designed sensor board

The designed sensor board layout needs certain modifications. For the purpose of this work,
the board is satisfactory. The proposed modifications are listed below:
1. The solder side of the board was filled with ground plane. This might result in failure
of the board for very high voltages, as the spacing between high voltage and ground
plane would not be adequate. Thus in the next version, the ground plane has to be
filled only at the region after the potential divider where the voltage levels would be
small.
2. The current sensor portion is designed to accommodate only the through hole mount
type hall effect sensors. In the next version, connectors can be given on-board for screw
type sensors which sense higher currents in the range of hundreds of amperes.
Also the board size could be reduced by improving and optimizing the overall routing of the
board.
3.8 Loss Calculations

Losses were computed for every component in the power circuit to have an estimate of the
efficiency of the system. The losses are mainly:
• Conduction and switching losses in MOSFETs
• Copper loss and core loss in inductors and transformer
• Losses in dc bus capacitor bank
Table 3.3 lists the losses of each of the components mentioned above for full load case.
Thus the total losses would be 19.21W. The full load efficiency would be 87.1%
Table 3.3: Estimated losses in power circuit

Component Net Loss
Capacitor bank 2.19W
Inverter switches(4) 3.44W
Boost switches(MOSFET and diode) 1.58W
Inductors(2) 4.5W
Transformer 7.5W
Chapter 4
Control Design
This chapter discusses the design of control blocks namely the phase locked loop(PLL),
the current control and dc voltage control. The digital controller specifications and the
implementation of the the control loops in digital domain is also explained.
4.1 Design of single phase PLL

In grid connected systems, it is required to track the frequency and phase of the grid voltage.
This necessitates the use of a Phase Locked Loop(PLL)[15]. In this project, since the inverter
is operated in single phase, a single phase PLL is required.
The design of single phase PLL is slightly different compared to three phase PLL. The
difference is only in the method of generating the orthogonal voltages Va and Vb . They are
easily obtained in a three phase PLL by making use of stationary three phase to two phase
transformation. This is not possible in single phase case.
Hence a block called ‘Second Order Generalized Integratorr’ (SOGI)[4] is used two obtain
Va and Vb . The following expressions are implemented by SOGI for Va and Vb .
Va (s) ωo s
= 2 (4.1)
Vg (s) s + ωo s + ωo2
Vb (s) ωo2
= 2 (4.2)
Vg (s) s + ωo s + ωo2
The SOGI essentially implements a band pass filter and a low pass filter to obtain the in-
phase and quadrature lagging components of the grid voltage. In Fig.4.1, the block diagram
of SOGI is shown.
29
30 Chapter 4. Control Design
Figure 4.1: Structure of second order generalized integrator[2]
In three phase synchronous PLL, the three grid voltages are converted into stationary
reference frame voltages Vα and Vβ . The grid voltage vector is aligned along q-axis. Fig.4.2
shows the phasor diagram.
Vq
Vg
Vd
Figure 4.2: Aligning grid voltage along q-axis
The following equations give the transformation required.

3
Vd = Vm cos(ωt − φ) (4.3)
2
3
Vq = Vm sin(ωt − φ) (4.4)
2
To align the grid voltage along q-axis, the reference for d-axis voltage is set to zero. The
actual Vd is computed and subtracted from Vd,ref to obtain the error which goes to a PI
controller. The PI controller ensures that the Vd stays at zero and gives an output ∆ω. This
is added to the nominal grid frequency and integrated to obtain the grid voltage phase angle
φ (or θpll in Fig.4.3). This is used to generate the unit vectors cosφ and sinφ.
4.1. Design of single phase PLL 31
The same scheme is used in case of single phase PLL wherein the d-q components of the
voltage are computed using Va and Vb of the SOGI output. The overall control scheme for
the single phase PLL is shown in Fig.4.3.
Figure 4.3: Single phase PLL control structure
The whole system is implemented in FPGA using VHDL. Fig.4.4 shows the experimental
step response of the two transfer functions realized by SOGI. The simulation result of the
same is shown in Fig.4.5.
Figure 4.4: Step response of transfer functions in SOGI (experimental result)
The locking feature of the PLL is shown in Fig.4.6. The figure is the experimental result.
Figure 4.5: Step response of transfer functions in SOGI (simulation result)
Figure 4.6: Input and corresponding unit vectors(experimental result)

4.2. Design of the current control 33
As SOGI implements filters, even if the grid voltage has significant harmonic content, the
unit vectors produced are of very good quality. Fig.4.7 shows the case when a triangle wave
is given as the input to PLL. As it can be observed, the unit vectors are produced properly.
Figure 4.7: PLL outputs when input is rich with harmonics (experimental result)
4.2 Design of the current control

The inverter is controlled as a current source which can inject current of any specified phase
into the grid. The phase of the current is fixed by making use of the PLL output unit vectors.
As the system is single phase, the conventional dq transformation along with the d-axis and
q-axis PI controllers cannot be used. Thus, for satisfactory dynamics and zero steady state
error, proportional + resonant (PR) controller is used for current control.
To attenuate the lower order harmonics, the AHE technique described in chapter 2 is
used. The overall current control is shown in Fig.4.8.
The current reference i∗ is ac reference at 50Hz. It is generated by the dc voltage controller
which comes as an outer loop. The design of the voltage control is considered in the following
section. The PR controller transfer function is shown in eqn.4.5.
Kr s
GP R (s) = Kp + (4.5)
s2
+ ωo2
The design of the PR controller of the current loop is done as per the steps listed below[12]:
• The PI controller parameters (say kp,P I and ki,P I of an equivalent three phase system
are determined
Vff+Vgff
Vdc
i* + + Vref
+ PWM
i
+
PR Controller & i
- Inverter
-
ifb Vadapt
Sensor
i i3
sin (3wot) AHE K3 Σ
cos(3wot)
i i5
sin (5wot) AHE K5
cos (5wot)
i i7
sin (7wot) AHE K7
cos(7wot)
i i9
sin (9wot) AHE K9
cos (9wot)
Figure 4.8: Complete current control
• The corresponding PR controller gains are determined using,
kp,P R = kp,P I (4.6)

kr = 2ki,P I (4.7)
The current loop for equivalent 3-φ system is shown in Fig.4.9. The PI parameters are to
be determined which depend on the filter resistance and inductance (which would include the
transformer leakage inductance also) and the bandwidth of the controller. The bandwidth
(ωbw ) should be high enough to have faster response but it should be lower than the switching
frequency of the system. In this work, the bandwidth is set to 600rad/s.
The PI is designed such that the pole due to the filter is canceled by the PI controller
4.3. Voltage controller design 35
i* + i
Vref
i
-
ifb
Figure 4.9: Current loop for equivalent 3-φ system
zero. This means,

Ltot
Tc = (4.8)
R
The frquency at which the resulting plant would cut 0dB line is,
kp
ωbw = (4.9)
Tc R
Using eqn.4.8 in eqn.4.9, kp can be evaluated as,
kp = Ltot ωbw (4.10)
Similarly,the integral gain is evaluated as,

kp
ki = (4.11)
Tc
⇒ ki = kp ωbw (4.12)
From eqns. 4.10 and 4.12, the corresponding gains for PR controller can be determined
as,
kp,P R = Ltot ωbw (4.13)

kr = 2kp ωbw (4.14)
The designed current controller parameters are listed in table 4.1.
4.3 Voltage controller design

The function of voltage controller is to maintain the dc bus voltage at desired value irrespec-
tive of load variations. In case of a PV system, the voltage controller output serves another
purpose. Its output is a measure of the power being drawn from the panels[6]. The duty
Table 4.1: Current controller parameters

Parameter Value
ωbw 600 rad/s
kp,P R 1.5
kr 1800
V*dc
i
+ idc Vdc
-
Vdc,fb
Figure 4.10: Voltage control loop
ratio of the boost stage can be adjusted by looking at the variation of the output of voltage
controller.
The voltage control loop is shown in Fig.4.10.
The bode magnitude plot of the open loop transfer function is shown in Fig.4.11.
Magnitude
(dB) -40dB/dec
-20dB/dec
0 dB w(rad/s)
Figure 4.11: Magnitude bode plot for voltage control
The bandwidth of voltage controller must be much smaller than the current control loop
bandwidth. The value chosen here is ωv,bw = 15rad/s. The pole at 1/Tv is set one decade
below ωv,bw . Thus Tv = 0.67sec. At ω = ωv,bw , the magnitude equals 0dB. It can be deduced
that,
kv = ωv,bw Tv C (4.15)
4.4. Digital implementation of control blocks 37
Substituting C = 6000µF and the other parameters, kv is evaluated as kv = 0.06 The

designed voltage controller parameters are listed in table 4.2.
Table 4.2: Voltage controller parameters

Parameter Value
ωv,bw 15 rad/s
kv 0.06
Tv 0.67s
4.4 Digital implementation of control blocks

The digital controller used in this project is Altera EP1C12Q240C8. It is an FPGA chip
programmed using any hardware description language. In this project VHDL is used for the
programming. The controller board is provided with ADCs, DACs and clocks (at 20MHz).
The controller board obtains the voltage and current signals from the main circuit board
and outputs PWM pulses to the main circuit board.
In this section the implementation certain control blocks PI, Resonant are explained
along with the digital circuit that the FPGA would synthesize.
4.4.1 PI controller implementation

The equation for PI controller in continuous time domain is
Z t
y(t) = kp u(t) + ki u(t)dt (4.16)
0
Eqn.4.16 is to be discretized. Let the proportional part be yp (k). So,
yp (k) = kp u(k) (4.17)
Similarly let the integral portion be yi (k). It can be shown that

u(k) + u(k − 1)
yi (k) = yi (k − 1) + ki Ts (4.18)
2
The final digital output would be
y(k) = yp (k) + yi (k) (4.19)
The digital circuit that implements eqns. 4.17 and 4.18 is shown in Fig.4.12.
yp(k) y(k)
kp
+
u(k) u(k-1)
D Q +
0.5kiTs
yi(k) yi(k-1)
D Q
clk
Figure 4.12: Digital circuit of PI controller
4.4.2 Implementation of resonant controller

The transfer function of PR controller is given in eqn.4.20
Y (s) Kr s
= 2 (4.20)
U (s) s + ωo2
Eqn.4.20 can be simplified to eqn.4.21
sY (s) ωo Y (s) kr U (s)
+ = (4.21)
ωo s ωo
The continuous-time domain equation for eqn.4.21 is
Z t
1 dy kr
+ ωo y(t)dt = u(t) (4.22)
ωo dt 0 ωo
Let Z t
ωo y(t)dt = x(t) (4.23)
0
⇒
1 dy kr
= u(t) − x(t) (4.24)
ωo dt ωo
Discrete time equivalent of eqn.4.23 is shown in eqn.4.25
x(k) − x(k − 1)
= ωo y(k − 1) (4.25)
Ts
4.4. Digital implementation of control blocks 39
Eqn.4.25 would be simplified to
x(k) = x(k − 1) + ωo Ts y(k − 1) (4.26)
Eqn.4.24 can be converted to equivalent digital form and simplified as
1 y(k) − y(k − 1) kr
= u(k) − x(k) (4.27)
ωo Ts ωo
y(k) = y(k − 1) + kr Ts u(k) − ωo Ts x(k) (4.28)
Eqns.4.26 and 4.24 can be implemented easily in FPGA. The circuit that would be
synthesized is shown in Fig.4.13.
u(k) kr Ts
y(k)
+
+
-
y(k) y(k-1)
D Q
x(k) x(k-1)
D Q wo Ts
clk
+ wo Ts
Figure 4.13: Digital circuit of resonant controller
4.4.3 Per-unit Values

All the control blocks are implemented in 16-bit digital arithmetic. The per-unit values and
the equivalent hex code are listed in table 4.3.
Table 4.3: pu values

pu value Hexadecimal representation
2pu 7FFFh
1pu 3FFFh
0 0000h
-1pu C000h
-2pu 8000h
Chapter 5
Simulation Results
In this chapter, simulation results of the current control are presented. The results prove the
validity of adaptive harmonic elimination (AHE) technique in the attenuation of lower order
harmonics. The distortions due to the transformer magnetizing current are not considered
in the simulations. The technique is found to be effective in reducing the distortion due to
transformer magnetizing current also, which is shown in the experimental results.
5.1 Parameters used for simulation

The simulation results shown in this chapter are the following four cases:
• Current control at low load without AHE
• Current control at low load with AHE
• Current control at higher load without AHE
• Current control at higher load with AHE
The AHE blocks are used for 3rd , 5th , 7th and 9th harmonics. Current controller parameters
used are the same as shown in table 4.1. For the adaptive control the proportional gain
constant used is 10. Dead-time used is 1.5µS
5.2 Low load without AHE

The current reference given is 1.6A. The output current and its low frequency spectrum are
shown in Fig.5.1.
41
42 Chapter 5. Simulation Results
Figure 5.1: Output current and its spectrum without adaptive compensation(low load)
5.3 Low load with AHE
For the same current reference as in section 5.2, adaptive compensation is included. The
result is shown in Fig.5.2.
Figure 5.2: Output current and its spectrum with adaptive compensation(low load)
5.4. Higher load without AHE 43
5.4 Higher load without AHE

The simulation is carried out for a current reference of 6.4A which is close to the full load
case. Fig.5.3 shows the result without compensation.
Figure 5.3: Output current and its spectrum without adaptive compensation(high load)
5.5 Higher load with AHE

For the same current reference as in section 5.4, adaptive compensation is included. The
result is shown in Fig.5.4.
The simulation results clearly indicate that the adaptive compensation is quite effective.
44 Chapter 5. Simulation Results
Figure 5.4: Output current and its spectrum with adaptive compensation(high load)
Chapter 6
Experimental Results
This chapter presents the experimental results of the hardware. The results are obtained for
the cases with and without adaptive compensation as in simulation. The results indicate the
effectiveness of the compensation technique. The issues that needed to be addressed while
having grid connected operation are also mentioned. The tests were done with a dc source
and not with the PV panels. The hardware would give similar results with the panels as the
source also as the panels are essentially dc sources. Only constraint with the usage of panels
as the source is the necessity of implementation of MPPT for improved efficiency[9][8].
6.1 Stand-alone operation without transformer

The power circuit for this case is shown in Fig.6.1.
Cdc S1 S3
G1 G3
Lfilt
Vdc
i
Cdc
S2 S4 Rload
G2 G4
Figure 6.1: Power circuit for stand-alone mode without transformer
In this configuration, the lower order harmonics would be mainly due to the dead-time
and device drops. In Fig.6.2 the load current and its third harmonic component are shown.
45
46 Chapter 6. Experimental Results
The third harmonic component is estimated adaptively. The noise seen in the third harmonic
estimate is actually due to the noise picked up by the DAC of controller board.
Figure 6.2: Load current[CH2: Red; Scale: 3.2A/1V] and its third harmonic content[CH1:
Blue; Scale: 3.2A/1V] stand-alone without transformer and without compensation
Fig.6.3 shows the same system but with a compensation for third harmonic. The attenu-
Blue; Scale: 3.2A/1V] stand-alone without transformer and with compensation
ation of the third harmonic and improvement in current wave-shape can be clearly observed
in Fig.6.3.
The operation of current control can be observed in Fig.6.4.
It can be clearly seen that the error falls to zero while the load current builds up to the
reference value. Waveforms similar to figures 6.2 and 6.3 are shown in figures 6.5 and 6.6
but with a higher load current.
6.2. Stand-alone mode with transformer 47
Figure 6.4: Effect of enabling current control. [CH1:Blue:Current controller error; Scale:
1A/1V] and [CH2:Red:Load current; Scale: 3.2A/1V]
Blue; Scale: 3.2A/1V] stand-alone without transformer and without compensation
6.2 Stand-alone mode with transformer
The power circuit for this case would be as in Fig.6.7 In this case there would be additional
distortion in the load current due to the magnetizing current of the transformer. Initially
the system was run without compensation and the results are shown in Fig.6.8. The figure
shows the primary current, secondary current and third harmonic of primary current. Fig.6.9
shows the compensated case wherein the compensation is applied to primary current.
Clearly, from figures 6.8 and 6.9, it can be seen that the secondary current remains with
high levels of third harmonic distortion. The primary current wave-shape is improved but
the secondary has no change. The reason for this is the fact that the magnetizing current is
not getting compensated which is getting reflected as the distortion in secondary.
Blue; Scale: 3.2A/1V] stand-alone without transformer and with compensation
Cdc
S1 S3
G1 G3
Lfilt
ipri isec
Vdc
Cdc
S2 S4
G2 G4
Rload
Figure 6.7: Power circuit for stand-alone mode with transformer
Keeping in mind the grid connected case, it is important that the secondary current is
of better quality. Thus the compensation has to be applied to the secondary current rather
than the primary.
Fig.6.10 shows the uncompensated case again but with the estimated third harmonic of
the secondary.
The improvement in secondary current can be observed in Fig.6.11 as the compensa-

tion is provided for the secondary current. Again, it can be seen that the primary current
now contains the necessary third harmonic hence improving the quality of secondary current.
6.3. Grid connected case 49
Figure 6.8: Primary current[CH2: Red; Scale: 3.2A/1V] , its third harmonic content[CH1:
Blue; Scale: 3.2A/1V] and secondary current[CH3: Green; Scale: 1A/1V] stand-alone with
transformer and without compensation
The secondary current, voltage reference and the load voltage under compensated case
are shown in Fig.6.12.
6.3 Grid connected case

In the grid connected case some difficulties were observed initially to run the system. The
following points explain the associated problems and how they were solved:
1. The system is configured such that initially the inverter is given grid voltage feed-
forward as the reference. So there would be some current injection into the grid initially.
The closed loop control is then initiated by pressing a push-button on the FPGA control
board. The push-button on-board was found to lack a hardware debounce logic. Thus,
the debounce of the push-button would not let the controller settle and the system
would trip. The problem was solved by making a FSM which takes in the input from
push-button and gives a clean control enable signal
2. The gate driver IC IR2110 can drive the high side switch of a leg only after the bootstrap
capacitor gets charged. To charge the bootstrap capacitor, the bottom switch has to
turn on. So when the control is enabled, the top switch of one leg and the bottom of
the other have to be kept ON to start injecting current. This will not happen unless
the bootstrap capacitor holds sufficient charge. As that would not happen, the grid
Figure 6.9: Primary current[CH2: Red; Scale: 3.2A/1V] , its third harmonic content[CH1:
Blue; Scale: 3.2A/1V] and secondary current[CH3: Green; Scale: 1A/1V] stand-alone with
transformer and with primary side compensation
would get short-circuited and the system would trip again. This was solved by limiting
the modulation index to be less than or equal to 0.9. This would ensure the proper
functioning of the driver IR2110.
3. The designed control parameters were tuned slightly to suit for the stand-alone opera-
tion. This change in values affected the grid connected performance. Once the original
designed values were used, the system started to function properly.
In grid interactive mode, the system was initially run in both STATCOM mode and in
upf injecting real power into grid.
6.3.1 Operation in upf without compensation
For upf operation, the ac current reference should be of same phase as the grid voltage.
Following Fig.6.13 shows the phasor diagram for this case. (VL is the net drop across filter
and transformer)
The Fig.6.14 shows the experimental result for the grid connected hardware when the
inverter is OFF. The transformer would take the magnetizing current which is shown in the
Fig.6.14.
The waveforms for upf operation without compensation are shown in Fig.6.15 and Fig.6.16.
6.4. Compensation issues in grid connected case 51
Figure 6.10: Secondary current[CH2: Red; Scale: 1A/1V] , its third harmonic content[CH1:
Blue; Scale: 1A/1V] and primary current[CH3: Green; Scale: 3.2A/1V] stand-alone with
transformer and without compensation
6.3.2 Operation in STATCOM mode without compensation

The figures 6.17 and 6.18 show the results for STATCOM operation in leading and lagging
0pf cases respectively.
6.4 Compensation issues in grid connected case

For both upf and STATCOM mode, third harmonic compensation was applied as done in
the stand-alone case. The results however showed that the compensation was not effective.
It can be seen from Fig.6.16 that the secondary current lacks half wave symmetry. This
observation lead to the use of adaptive block to estimate the amount of second harmonic
present in the grid current. Fig.6.19 shows the grid current and its second harmonic content.
The appearance of second harmonic is due to the 100Hz ripple in dc bus voltage. This
issue can be addressed in the following ways:
• Use the AHE technique to add an equivalent second harmonic voltage reference.
• Pre-multiply current controller output with Vdc,ref and divide it by sensed Vdc . The
output after the division would be the final voltage reference. This might be better
than the previous solution as the error is due to multiplication which would be better
compensated by division
• Use a PR controller for dc bus voltage controller (in addition to PI) at 100Hz[14]
Figure 6.11: Secondary current[CH2: Red; Scale: 1A/1V] , its third harmonic content[CH1:
Blue; Scale: 1A/1V] and primary current[CH3: Green; Scale: 3.2A/1V] stand-alone with
transformer and with secondary side compensation
The adaptive technique was tried and the result is shown in Fig.6.20. The second har-
monic content is very much attenuated but the half wave symmetry is still not achieved fully.
However, the adaptive technique to attenuate the distortion due to dc bus ripple might not
be a suitable option. The distortion due to dc bus ripple is because of the multiplication of
the dc bus voltage to the generated voltage reference. In such case, if a second harmonic
reference is added to the main voltage reference, there could be injection of dc component
in the output transformer. This is highly undesirable.
6.5 System Efficiency

The efficiency of the overall system was checked for operation in both stand-alone and grid
connected case. The measured overall efficiency was in the range of 82-84% in all the cases.
This is lesser than the predicted efficiency of around 87%. There was no significant variation
in efficiency for the cases with and without compensation.
6.5. System Efficiency 53
Figure 6.12: Load voltage[CH4: Pink; Scale: 1V/1V] , voltage reference[CH1: Blue; Scale:
1V/1V] and secondary current[CH3: Green; Scale: 1A/1V] stand-alone with transformer
and with secondary side compensation
VL Vinv
Vg
ig
Figure 6.13: Phasor diagram for upf operation
Figure 6.14: Sensed grid voltage[CH3: Green; Scale:1V/1V] , in phase unit vector[CH1:
Blue; Scale:1V/1V] , secondary current[CH4: Pink; Scale: 1A/1V], primary current[CH2:
Red; Scale: 3.2A/1V] when inverter is OFF
Figure 6.15: Sensed grid voltage[CH3: Green; Scale:1V/1V] , in phase unit vector[CH1:
Blue; Scale:1V/1V] , primary current[CH4: Pink; Scale: 1A/1V] for upf opration
Figure 6.16: Fundamental component of secondary current[MATH: Cyan; Scale:1A/1V] , Net

harmonic current[CH1: Blue; Scale:1A/1V , secondary current[CH4: Pink; Scale: 1A/1V]
for upf opration
Figure 6.17: Grid voltage[CH3: Green; Scale:1V/1V], primary current[CH4: Pink; Scale:
1A/1V] for 0pf lead opration
6.5. System Efficiency 55
Figure 6.18: Grid voltage[CH3: Green; Scale:1V/1V], primary current[CH4: Pink; Scale:
1A/1V] for 0pf lag opration
Figure 6.19: Grid current[CH2: Red; Scale: 1A/1V], Second harmonic component of grid
current[CH1: Blue; Scale: 1A/1V] for upf opration
Figure 6.20: Grid current[CH2: Red; Scale: 1A/1V], Second harmonic component of grid
current[CH1: Blue; Scale: 1A/1V] for upf opration with adaptive compensation
Chapter 7
Conclusions
The project was aimed at developing the hardware and control scheme for a low power grid
connected inverter. The motivation for this was to have a compact, efficient and economical
hardware for the PV panels present in the department. The issue of presence of lower
order harmonics in real systems was intended to be addressed using an adaptive harmonic
elimination technique (AHE).
Literature survey revealed that the effectiveness of AHE scheme was not tested in hard-
ware. Hence the aim of the project was also to validate the effectiveness of this technique in
hardware.
The hardware built for the project consists of:
• A main circuit board consisting of power circuit, and control circuits such as protection-
delay circuit, indicator circuit, gate-drive circuit and on-board control power supply
• A general purpose non-isolated voltage and current sensor board consisting of five
voltage channels and four current channels
• The magnetic components - inductors and transformer
The control developed for the hardware consists of the closed loop current control with
AHE. As the system is meant to be operated in grid interactive mode, a single-phase PLL
was designed. All the control was implemented successfully in FPGA controller coded using
VHDL.
Certain issues like frequent tripping of the system were observed in grid interactive mode
initially. The issues were solved by solving the debounce problem, gate-driver problem of
the hardware which were the major reasons for the trips.
56
57
The adaptive harmonic technique was found to be quite effective in hardware for com-
pensating the dead-time effect and distortion due to transformer magnetizing current. It was
also seen in grid connected operation, that the ripple on dc bus voltage introduces significant
even harmonics in the system. The adaptive technique was attempted to compensate for this
effect also. The technique did improve the waveshape, however, its effectiveness remains to
be verified against some other techniques available to compensate for dc voltage ripple.This
is because adaptive technique might not be suitable for attenuating distortions due to dc
bus ripple.This is due to the fact that in large systems there could be injection of dc current
if the distortions due to dc bus voltage ripple are attenuated using adaptive technique.
The hardware was tested with dc source as PV emulator. The system performance is
to be verified with the actual PV panels as the source. The system is expected to function
properly with the PV panels as the source also, as the panels are essentially dc sources.
The MPPT, however, is required to be implemented while using PV panels, to improve the
efficiency and to utilize the available solar power better.
Overall, the aim of building the hardware with closed loop control was successful. System
efficiency was acceptable but could be improved further by more judicious design of trans-
former and selection of switches with less on-state drops. The compensation method studied
and implemented was AHE. Other methods of harmonic elimination such as multi-resonant
controllers[14], hardware dead-time compensation technique[5] etc can also be investigated.
In this work, the transformer is in the grid side. The other configuration that can be con-
sidered is with a high frequency link transformer. Also, the EMI issues with the hardware
are to be studied and compliance to EMI standards is to be ensured.
Appendix A
Main circuit board schematics
A.1 Connectors of main circuit board
V+
Interface to Sensor Board 2 CN7
2 CN2 I1 2
VDC 1 2 VDC 2 1
1 1
3 4 1
5 6
TP7
0V
C1 V2 7 8
0V
9 10
1 0.1uF Tantalum V3 11 12 CN8
1 I2 2
2 13 14 2 CN3 2
2 V2 2 1
3 V4 15 16 1 1
3 17 18 1
CN1
C2 V5 19 20
Power Supply 0V 0V
21 22 0V
I1 23 24
0.1uF Tantalum
25 26 CN9
I2 2
27 28 V3
CN4 I3 2
2 1
29 30 2 1
TP8
I3 1
31 32 1
33 34
V- I4 35 36 0V
0V
37 38
39 40
CN5 I4 2 CN10
CON1 V4 2 2
0V 2 1
1 1
0V 1
0V 0V
TP9 TP10 TP11 TP12 TP13
2 CN6
V5 2
1
FPGA Interface 1
PWM1 1 2
0V
PWM2
3 4
PWM3
5 6
PWM4
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
PWM_E1 29 30
PWM_E2 31 32
PWM_E3 33 34
ENABLE_E 35 36
37 38
39 40
CON2
Title: Connectors
Author: Abhijit K
Figure A.1: Connectors
58
A.2. Adjustable Dead-time Generation Circuits 59
A.2 Adjustable Dead-time Generation Circuits
.1uF
V+
C24
V+
.1uF
C23
1N4148 R32
PWM1_SH
D7 TP28 0V
1 JP7
14
0V 470E
VDD
14
U3A
VDD
2 1 U4A
U3P 3 1
3
2 U4P 3 PWM2_INV
VSS
PWME1_SH 2
4011N
VSS
7
C8 4081N
2
7
3 1 12 U3D PWM7_INV
470pF 11
1N4148 R34 10k 13
TP29
R31
D6 4011N
470E TP33
0V
5 U4B
4 PWM1_INV U5D
12
6 PWM4_SH
11 PWM8_INV
4081N 13
2
3 1 C7
4081N
470pF
10k
.1uF
C25
R33
V+
0V
PWM3_SH
1 JP10 1N4148 R44 TP34 0V

1N4148 R36 2 D13
PWM2_SH TP30 470E
14
D9
VDD
3
1 JP8 470E 8 U3C
U5A
U3B 1
2 5 U4C PWME3_SH 10 U5P 3
8 PWM6_INV
3 4 9
10 PWM4_INV N$125 2
VSS
6 4011N
9 4081N
C14
7
PWME2_SH 4011N
C10 4081N
2
N$126
3 1 470pF
2
3 1 470pF 1N4148 R46

R38 TP35 10k
1N4148 TP31 D12 470E R43
D8 10k 0V
470E U5B
R35 0V 5
12 U4D 4 PWM5_INV
11 PWM3_INV 6
13 4081N
2
3 1
2
4081N C13
3 1
C9
10k 470pF
R37 470pF 10k
R45
0V
0V
Title: Dead-time generation circuit

Author: Abhijit K
Figure A.2: Dest-time generation circuits

60 Appendix A. Main circuit board schematics
A.3 Level Shifting Circuits

V+
.1uF
C28
V+
V+
0V
R73
R83
470k
470k TP22
R74
39k
3.3k
R75
R84
39k
TP20
3.3k
R85
R71
3
PWM1 5 U14A R81 U14C
1N4148
PWM3 9
1N4148
2
4.7k 14
4 4.7k
D21
D23
LM339N
LM339N
12
5.6k
R72
5.6k
R82
PWM1_SH
PWM3_SH
0V
0V
0V
V+
V+
R78
R88
470k TP21 470k
R79
39k
3.3k
R80
R89
39k
3.3k
R90
R76 TP23
7 U14B R86
PWM2 U14D
1N4148
PWM4 11
1N4148
1
4.7k 13
6 4.7k
D22
10
D24
LM339N
LM339N
5.6k
R77
PWM2_SH
5.6k
R87
PWM4_SH
0V
0V
.1uF
C29
V+ V+
R93 R98
0V
ENABLE 470k 470k
R94
R100
39k
R99
1 JP11
3.3k
39k
R95
3.3k
TP24 TP25
2 R91
3
5 U15A PWM_E1 R96 9 U15C

1N4148
1N4148
2 14
4.7k 4.7k
4
D29
D30
ENABLE_E LM339N LM339N
12
5.6k
R92
5.6k
R97
ENABLE_SH PWME1_SH
0V
0V 0V
V+
V+
R103
R108
470k
R104
470k
R105
R109
39k
3.3k
R110
TP26
39k
3.3k
PWM_E2 R101 TP27
7 U15B PWM_E3 R106
1N4148
1 11 U15D
1N4148
4.7k 13
6 4.7k
D31
10
D32
LM339N
LM339N
R102
5.6k
R107
5.6k
PWME2_SH
PWME3_SH
0V
0V
Title: Level shifter Circuits

Author: Abhijit K
Figure A.3: Level shifting circuits

A.4. Main Protection Circuit 61
A.4 Main Protection Circuit

Main Protection Circuit
TP32
V+
.1uF
C26
V+
.1uF
V+
C27
RESET_SIGNAL
14
R47
VDD
C15
1nF
1 U6A 0V
14
U6B
VDD
5.6k U6P 3 5
8 U6C 0V 1 U7A
2 4
5.6k
R50
10 2 U7P 9
Fault Indicator
VSS
4011N 6
9 8
7
4011N
VSS
PB1 4011N 4023N
1.8k
R48
R49
10k
LED1
P$1
P$3
0V T1
12 U6D 2N2222
P$1
P$3
11
0V 10k
TP37 13
LED On-- Fault Present
4011N R51
TP36
P$2
P$4
ENABLE_SH 0V
P$2
P$4
Combined Fault Signal Enable signal from FPGA

SD_FAULT
0V
V+ SD_FAULT goes to IR2110 MOSFET driver IC
V+ 3
5.6k 2
1
R52 TOGGLE
0V S2
1N4148
1 JP1
OV 2
D14
3
Jumper1
1N4148
UV 1 JP2
2
D15
3
Jumper2
1N4148
OC1 1 JP3
2
D16
3
Jumper3
1N4148
1 JP4
OC2 2
D17
3
Jumper4
1N4148
1 JP5
OC3 2
D18
3
Jumper5
1N4148
OC4 1 JP6
2
D19
3
Jumper6 1nF
C16
Connect jumpers between 2 and 3 to disable protection 0V
Title: Main-Protection Circuit

Author: Abhijit K
Figure A.4: Main protection circuit

A.5 Comparator Circuits
.1uF
V+ V+
C3
VDC 0V R14
V+ V+ TP4
R3 TP17
3.3k
3.3k
R15
R5
TP1 100k
100k
OC2
3
R1 R11
1N4148
1N4148
3
5 U1A UV 2 9 U1C
R4 R13
R23
10k
2 14
1k 2.2k
3
R2 R12
D1
D3
2 4 8
1
4.7k 4.7k
R21
10k
1k LM339N I2 2.2k LM339N
12
1
0V
TP14 V+
C4
.1uF
V-
0V
V+ V+ 0V
TP15 TP5
V+ R18
TP18
3.3k
R20
R8
TP2 100k
3
OC3
3.3k
R10
2
100k
R22
10k
3
R16
1N4148
2 11 U1D
1
R6 R19
1N4148
R24
U1B
10k
7 OV 13
R9 2.2k
R17
D4
1 10
1
1k
R7 4.7k
D2
VDC 6 I3 LM339N
4.7k 2.2k
1k LM339N
0V
V+
V+ 0V V+ V+
.1uF
C5
TP19
V+ 0V R55 TP6
TP16 R27
3.3k
R29
TP3
3.3k
R57
2
3M
R58
100k
10k
1
R53
1N4148
U2B
3
R25
1N4148
7 OC4
3
2 5 U2A OC1 R56

R28 1
R30
D20
1k
10k
2.2k 2 R54
R26 I4 6
D5
4 4.7k
1
4.7k LM339N
I1 LM339N 1k
2.2k
12
.1uF
C6
0V
0V
0V
V-
V+
.1uF
C51
V+
U21
VDC VCC NC 2 CN12

V+ 0V VCC NC 2
1
R122
R120 1
3.3k
P$3
OUT
TP45
100k 2 CN11
P$2 NO 2
UV2 Q9 COM NO 1
1
R118 2N2222
3
5 U20A
2
R121
1k
3
2
R119 4
R123
4.7k
10k
1k LM339N
R124
12
1
6.8k
0V
TP46 0V
.1uF
C52
V-
0V
Title: Comparators
Author: Abhijit K
Figure A.5: Comparator circuits

A.6. Annunciation Circuits 63
A.6 Annunciation Circuits
V+
V+
V+
C17
V+
5.6k
5.6k
R60
R66
TOGGLE
C20
0V
LED2
LED5
14
14
VDD
U11A 0V
VDD
1 U8A Q1 1 Q4
RESET_SIGNAL U8B U11B
U8P 3 5 2N2222 U11P3 5 2N2222
2 4 12 U8D OC2 2 4 12 U11D
R59 R65
VSS
VSS
4011N 6 11 4011N 6 11
7
7
4011N 13 4011N 13
10k 10k
4011N 4011N
0V 0V
8 U8C 0V 8 U11C 0V
10 10
9 9
OV 4011N 4011N
V+
V+
V+
5.6k
R62
C18
V+
5.6k
R68
C21
LED3
14
VDD
U9A
LED6
1 0V Q2
U9B
U9P 3 5 2N2222
14
0V
VDD
UV 2 4 12 U9D 1 U12A Q5
R61 U12B
VSS
4011N 6 11 U12P3 5 2N2222

U12D
7
4011N 13 OC3 2 4 12
10k R67
VSS
4011N 4011N 6 11
7
4011N 13
10k
0V 4011N
8 U9C 0V
0V
10
9 8 U12C 0V
4011N 10
9
4011N
V+
V+
V+ V+
5.6k
5.6k
R64
R70
C19
C22
LED4
LED7
14
14
0V
VDD
VDD
1 U10A 0V Q3 1 U13A Q6
U10B U13B
U10P3 5 2N2222 U13P3 5 2N2222
OC1 2 4 12 U10D OC4 2 4 12 U13D
R63 R69
VSS
VSS
4011N 6 11 4011N 6 11
7
7
4011N 13 4011N 13
10k 10k
4011N 4011N
0V 0V
8 U10C 0V 8 U13C 0V
10 10
9 9
4011N 4011N
Title: Annunciation Circuit

Author: Abhijit K
Figure A.6: Annunciation circuits

A.7 On-board power supply
MUR440RL MUR440RL
MUR440RL MUR440RL
J19
J20
TP49
D33
D11
IC1 V++
R125
4
6.8k
2
2
4
C49 C50 C53 C58
+
MUR1100
+
+
1
1
D34
D35
D36
5
3
0V
R126
1
J25
J26
6.8k
1
34166
0V 2
2
3
3
3
From the tertiary winding of transformer C54 CN13
6.8k Power Supply
0V
R127 0V
1
1
IC2 2
2
4
TP48 3
3
2 CN14
2
4
Power Supply for FPGA Board

V5
MUR1100
1
1
J21
J22
5
5 D37 1
3
1
2
34166 R128 C59 2
CN15
+
3
6.8k 5V supply for FPGA Board

C55
6.8k 0V
R130 0V
0V 0V
IC3
R129
4
6.8k
2 C57
2
4
MUR1100
1
J23
J24
1
D38
5
5
3
R131
6.8k
34166 0V
3
C56
6.8k C60
+
V--
R132 0V
TP47
0V
Title: On-board Power Supply

Author: Abhijit K
Figure A.7: On-board power supply

A.8. Power circuit 65
A.8 Power circuit
TP38
V+ V+
L_boost
U16
R39 MUR820
8 7 D10
HO J1 J2
1N4148
10E M1 M3 M5
9 6 IRF Z44 IRF Z44 IRF Z44 J5
VDD VB C31 C32
D25
J3
J4
Q13
10 5
PWM1_INV HIN VS C11 C12 C42 C43 C44 C45 IRF Z44
+
SD_FAULT
+
J6
R114
R117
R116
11 4
SD
2M
2M
2M
M2 M4 M6
12 3 TP39 IRF Z44 IRF Z44 IRF Z44
PWM2_INV LIN VCC
C30 13
VSS COM
2
.1uF 14 1
R40
LO
10E
R115
V+ TP40
2M
IR2110 0V
0V
V+ U17
8 7
R41
HO J13
1N4148
10E
9 6
VDD VB C34 C35
D26
C46 J14
10 5
PWM3_INV HIN VS
J7
J8
11 4
SD
12 3 TP41
PWM4_INV LIN VCC
J15
13 2
C33 VSS COM
14 1
R42
.1uF LO J16
10E C47
J10
J9
IR2110
V+ TP42
0V
V+ U18
J17
8 7
R111
HO
10E
1N4148
9 6 J18
VDD VB C37 C38
D27
J11
J12
C48
10 5
PWM5_INV HIN VS
11 4
SD
12 3 TP43
PWM6_INV LIN VCC
13 2
VSS COM
C36
14 1
R112
LO
.1uF 10E
IR2110
0V V+
U19
V+
8 7
HO
1N4148
9 6
VDD VB C40 C41
D28
10 5
PWM7_INV HIN VS
11 4
SD
12 3 TP44
PWM8_INV LIN VCC
13 2
VSS COM
14 1
R113
C39 LO
10E
.1uF
IR2110
0V
Title: Power Circuit

Author: Abhijit K
Figure A.8: Power Circuit

Appendix B
Pictures of Hardware Setup
B.1 Main circuit board - Version 2
Figure B.1: Picture of main circuit board
66
B.2. Sensor board - Version 1 67
B.2 Sensor board - Version 1
Figure B.2: Picture of non-isolated voltage and current sensor board

68 Appendix B. Pictures of Hardware Setup
B.3 Experimental Setup
Figure B.3: Picture of Experimental Setup

References
[1] Blasko. V, “A novel method for selective harmonic elimination in power electronic equip-
ment”,IEEE Transactions on Power Electronics, vol. 22, pp. 223-228, 2007.
[2] Venkatramanan. D, “Integrated magnetic filter transformer design for grid connected
single phase PWM-VSI”, M.E Thesis, Department of Electrical Engineering, Indian In-
stitute of Science, June 2010.
[3] Parikshith. BC, “Integrated approach to filter design for grid connected power convert-
ers”, M.Sc Thesis, Department of Electrical Engineering, Indian Institute of Science,
July 2009.
[4] Ciobotaru. M, Teodorescu. R, Blaabjerg. F “A new single phase PLL structure base on
second order generalized integrator”,IEEE PESC 2006, Jeju Korea,pp. 1511-1516.
[5] Seung-Gi Jeung, Min-Ho Park, “The analysis and compensation of dead-time effects in
PWM inverters”, IEEE Transactions on Industrial Electronics, vol. 38, No.2, April 1991
[6] Kitano. T, Matsui. M, De-hong. Xu “Power sensorless MPPT control scheme utilizing
power balance at DC link-System design to ensure stability and response”,27th Annual
Conference of IEEE Industrial Electronics Society, 2001.
[7] Ramanamurthy. GS, “Design of transformers and inductors at power frequency- a mod-
ified area product method”, M.Sc Thesis, Department of Electrical Engineering, Indian
Institute of Science, March 1999.
[8] Hamrouni. N, Chérif. A, “Modeling and Control of a Grid Connected Photovoltaic Sys-
tem”,Revue des energies renouvables,vol. 10,pp. 335-344,September 2007
69
70 References
[9] Umanand. L,“Lecture notes on Solar Photovoltaic systems”,CEDT, Indian Institute of

Science,Bangalore
[10] Feldbauer. C, Pernkopf. F, Rank. E, “Adaptive Filters”,A tutorial for the course -
Computational Intelligence, http://www.igi.tugraz.at/lehre/CI
[11] Srinath. R, “Digital Control of Solar Photovoltaic Converters”, M.Sc Thesis, Depart-
ment of Electrical Engineering, Indian Institute of Science, December 2009.
[12] Daniel Nahum Zmood, Donald Grahame Holmes, “Stationary Frame Current Regula-
tion of PWM Inverters with Zero Steady-State Error”, IEEE Transactions on Power
Electronics, vol. 18 (3), 2003.
[13] Muñoz. A R, Lipo. T A, “On-Line Dead-Time Compensation Technique for Open-

Loop PWM-VSI Drives”,IEEE Transactions on Power Electronics, VOL. 14, NO. 4,
JULY 1999
[14] Dipankar De, “High Frequency Link Inverters and Multiresonant Controllers ”, PhD
Thesis, Department of Electrical Engineering, Indian Institute of Science, October-2010
[15] Blaabjerg. F, Teodorescu. R, and Liserre , “Overview of control and grid synchronization
for distributed power generation systems” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp.
13981409, Oct. 2006.
[16] Ramanarayanan. V,“Course Material on Switched Mode Power Conversion”,Dept. of

Electrical Engineering, Indian Institute of Science,Bangalore
[17] John R Glover. JR, “Adaptive Noise Canceling Applied to Sinusoidal Interferences”,
IEEE transactions on acoustics, speech, and signal processing,Vol. Assp-25, No.6, De-
cember 1977
[18] Ranganathan. VT,“Course Material on Control of Electric Drives”,Dept. of Electrical

Engineering, Indian Institute of Science,Bangalore
[19] IEEE Standard 519-1992, IEEE Recommended Practices and Requirements for Har-
monic Control in Electrical Power Systems
[20] IEEE Standard 1547-2003, IEEE Standard for Interconnecting Distributed Resources
With the Electric Power System

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Design of Grid Connected Solar Inverter

with Reduced THD using Adaptive

Department of Electrical Engineering

List of Tables vii

List of Figures viii

3.3.1 Calculation of 100Hz ripple . . . . . . . . . . . . . . . . . . . . . . . 20

A Main circuit board schematics 58

B Pictures of Hardware Setup 66

3.1 Ratings of solar panels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 Current controller parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 36

1.1 Schematic diagram of a DGS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 Switching logic pulses for a leg . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Power circuit topology with L filter at ac side . . . . . . . . . . . . . . . . . 15

4.1 Structure of second order generalized integrator[2] . . . . . . . . . . . . . . . 30

4.3 Single phase PLL control structure . . . . . . . . . . . . . . . . . . . . . . . 31

6.1 Power circuit for stand-alone mode without transformer . . . . . . . . . . . . 45

B.1 Picture of main circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . 66

ωo : Grid frequency in rad/s

Solar Panels - ~ / Grid

Figure 1.1: Schematic diagram of a DGS

• High efficiency of the complete system

interconnection of DGS with the electric power system.

• Reliability and Cost Reduction

1.1 Project Work

Figure 1.2: Power circuit topology

Figure 1.3: Terminal characteristics of a solar panel (Present on department roof)

• The on-state voltage drops on the switches

1.2 Organization of the thesis

2.1 Lower order harmonic injection

Figure 2.1: Switching logic pulses for a leg

Figure 2.2: Error voltage due to dead-time

Figure 2.3: Dead-time influence on average pole voltage

Figure 2.4: Schematic of a grid connected 1-φ inverter

Figure 2.5: Net error voltage across filter

2.2 Limitations of the dead-time effect analysis

2.3 LMS Adaptive Filter

z-1 z-1 z-1

Figure 2.6: Generalized adaptive filter

2.3.1 LMS algorithm

w = [wo w1 ... wN −1 ]T (2.4)

x(n) = [x(n) x(n − 1) ... x(n − N + 1)]T (2.5)

y(n) = wT x(n) (2.6)

The error signal is,

A performance function is defined as

ζ = E[e2 (n)] (2.8)

w(k + 1) = w(k) − µ∇k ζ (2.9)

∇ is defined as the gradient with respect to the weights of the filter.

∂e2 (n) ∂e(n)

w(n + 1) = w(n) + 2µe(n)x(n) (2.16)

2.4 Adaptive Harmonic Elimination

• A voltage reference is generated from the estimated value of ik

sin (kwot) i(grid current)

Figure 2.7: Block diagram of adaptive estimation of a particular harmonic

Wcos (n + 1) = Wcos (n) + 2µen cos(kωo nTs ) (2.17)

i(grid current) ik vk,ref

Figure 2.8: Generation of voltage reference from estimated ik

Figure 3.1: Power circuit topology with L filter at ac side

3.1 System Ratings

Table 3.1: Ratings of solar panels

3.2 Design of the boost stage

Figure 3.2: Boost stage of the power circuit

Figure 3.3: Current through boost inductor under CCM

Lboost = 84µH (3.3)