Electronics Devices & Circuits Lab Manual Dept.

of Electronics & Telecommunication

Experiment No:1

TITLE: Design a single stage FET in CS configuration and verify DC operating point

OBJECTIVES: a) To find IDSS and Vp for the given JFET and plot the transfer
characterisics
b) Design a self bias circuit for a single stage JFET Amplifier
in CS Configuration and verify DC operating point.

PRE-LAB REQUISITES:

Analysis & Design of Self bias method of transistor in CS configuration

Concept of DC load line and Q-point.

APPARATUS:

Sr. No. Description Specifications

1. DC Power Supply 0-32V,2A

2. DMM (as current meter) 0-10mA dc

3. Breadboard/PCB ----------
4. DMM (as voltmeter) 0-20V dc
5. Connecting wires ---------

THEORY:

The Junction Field effect Transistor (JFET) is a voltage controlled terminal device. It
has got 3 terminals denoted as Source, Drain & Gate. For an n-channel JFET, drain and
source are n-type and gate is p- type. When a positive voltage is applied between the
drain and source, and gate is shorted to source, the pn junctions are reverse biased &
depletion regions are formed. The channel is more lightly doped than the p type gate, so
the depletion regions penetrate deeply in to the channel. As channel resistance initially
is almost constant and small, drain current I D flows. As VDD is increased, it increases.
This continues till the channel resistance becomes a high value and the current
saturates, and the channel width becomes minimum. This is known as pinch-off. The
corresponding value of VDS is called pinch off voltage Vp and the current is called as
the Drain-Source saturation current (IDSS). When the gate is biased negative with respect
to the source, and a positive voltage is applied between the drain and source, the
channel is narrowed, its resistance is increased, & I D is reduced. When the negative bias
voltage is further increased, the depletion regions meet at the center & I D is cutoff
completely. The value of VGS when ID becomes zero is the VGS(off) or –Vp.

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PROCEDURE:

Transfer Characteristics:
1. Connect the circuit as shown in the figure1.
2. Set voltage VDD to 20V.
3. Set VGS=0 and measure IDSS .
4. Varying VGG gradually, note down both drain current ID and gate-source
voltage(VGS)
5. Take readings of ID vs VGS till ID becomes zero .Note down Vp.

Fig. 1 a. : Set up to find transfer characteristics of FET

Fig. 1 .b : Transfer characteristics of JFET

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OBSERVATION TABLE

VDD= ---------- V

Sr.No VGS ID

b) Self-bias method for FET

Fig.2. CS Amplifier circuit with Self bias

Consider the common source amplifier shown in Fig 2. In self bias the gate – source is
provided by the voltage drop across a resistor in series with the device source terminal.
The voltage drop across RS is VS. The FET gate terminal is grounded with resister R G
hence VG = 0V, as IG= 0 and voltage at source terminal is more than gate so gate is
negative w. r. t. source. So for self-bias circuit

VGS= -IDRs (1)

The fact that ID determines VGS and that VGS sets the ID level means that there is a
feedback effect tending to control ID. Thus if ID increases when the device is changed,
the increased voltage across RS results in an increased gate – source voltage that tends
to lower ID back toward its original level. Similarly, a fall in I D produces a reduced VGS
which tends to raise ID toward its original level
For the output side ,
VDS= VDD-ID(RD+RS) (2)

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CIRCUIT DIAGRAM:

Fig.3 JFET self bias circuit

DESIGN:

1. Assume suitable value of IDQ .

2. Choose VDSQ = [(VDD-Vp)/2 ] +Vp
3. Assume RG= 1 MΩ
4. Find VGS corresponding to ID from Shockley’s equation:
ID = IDSS(1- VGS/Vp)2.
5. For the self-bias circuit,
VGS= -IDRs
Calculate Rs= -VGS/ID
6. Apply KVL to the output side of circuit shown in Fig2 to obtain the value of
RD
VDS= VDD-ID(RD+RS)
7. Build the self-bias circuit on breadboard and verify the designed values.

PROCEDURE:

1. Design the self-bias circuit for CS configuration. Connect circuit for dc analysis
as shown in Fig.3
2. Apply DC Supply voltage (VDD).
3. Measure the values of VDSQ, VGSQ & IDQ .
4. Compare with theoretical values.

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OBSERVATION TABLE

D.C.operating parameter IDQ (in mA) VDSQ (in Volt) VGSQ (in Volt)

Measured Practical
Values
Calculated
Values

DESIGN PROBLEM:

1. Design & Simulate a single Stage JFET amplifier with self bias for given Specifications
(DC Analysis) using BF245. The parameters of device are IDSS = 10mA, VP = 4V

VDD = 15V, IDQ= 4mA, VDSQ = 10V

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REFERENCES:

1. Boylstaed, Nashlesky, “Electronic Devices and Circuits Theory”, 9th Edition, PHI, 2006
2. David A. Bell, “ Electronics Devices and Circuits”, 5 th Edition Oxford press

QUESTIONS:

1. What are the different biasing circuits used for JFET?

2. Explain voltage divider bias method of JFET.
3. Define IDSS and Vp of JFET and show these parameters on the static characteristics

CONCLUSION:

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