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V, Inc
320A Kalmus Drive Costa Mesa, CA 92626
TEL : +714-668-0588 FAX :+714-668-9099
Top Confidential
Table of Contents
CONTENTS PAGE
Sections
1. Features 1-1
2. Specifications 2-1
8. Waveforms 8-1
Appendix
1. Main Board Circuit Diagram
Block Diagram
IBM and IBM products are registered trademarks of International Business Machines
Corporation.
Macintosh and Power Macintosh are registered trademarks of Apple Computer, Inc.
VESA, EDID, DPMS and DDC are registered trademarks of Video Electronics Standards
Association (VESA).
No part of this document may be copied, reproduced or transmitted by any means for any
purpose without prior written permission from VINC.
FCC INFORMATION
This equipment has been tested and found to comply with the limits of a Class B digital device,
pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates,
uses and can radiate radio frequency energy, and if not installed and used in accordance with
the instructions, may cause harmful interference to radio communications. However, there is
no guarantee that the interference will not occur in a particular installation. If this equipment
does cause unacceptable interference to radio or television reception, which can be
determined by turning the equipment off and on, the user is encouraged to try to correct the
interference by one or more of the following measures -- reorient or relocate the receiving
antenna; increase the separation between equipment and receiver; or connect the into an
outlet on a circuit different from that to which the receiver is connected.
FCC WARNING
To assure continued FCC compliance, the user must use a grounded power supply cord and
the provided shielded video interface cable with bonded ferrite cores. Also, any unauthorized
changes or modifications to Amtrak products will void the user’s authority to operate this
device. Thus VINC Will not be held responsible for the product and its safety.
CE CERTIFICATION
This device complies with the requirements of the EEC directive 89/336/EEC with regard to
“Electromagnetic compatibility.”
SAFETY CAUTION
Use a power cable that is properly grounded. Always use the AC cords as follows – USA (UL);
Canada (CSA); Germany (VDE); Switzerland (SEV); Britain (BASEC/BS); Japan (Electric
Appliance Control Act); or an AC cord that meets the local safety standards.
2. OPTICAL CHARACTERISTICS
Viewing Angle by Contrast Ratio °Ÿ 10
Left: 85°typ.
Right: 85°typ.
Top: 85°typ.
Bottom: 85°typ.
5. POWER SUPPLY
Power Consumption: 180W MAXPower OFF: to less than 3W MAX
6.Speaker
Output 8Ω/10W (max) X2
Precaution
Please pay attention to the followings when you use this TFT LCD module.
TV Source
A. PICTURE ADJUST:
a. PICTURE MODE (USER/ VIVID1 /VIVID2 / VIVID3)
b. Adjust the BACKLIGHT (0~100)
c. Adjust the BRIGHTNESS (0~100)
d. Adjust the CONTRAST (0~100)
e. Adjust the COLOR (saturation)(0~100)
f. Adjust the TINT (hue) (0~100)
g. Adjust the SHARPNESS (0~100)
h. CLOSED CAPTION (OFF/CC1/CC2/CC3/CC4/TT1/TT2/TT3/TT4)
B. AUDIO ADJUST:
a. VOLUME (0~100)
b. BASS (0~100)
c. TREBLE (0~100)
d. BALANCE (0~100)
e. SURROUND (ON/OFF)
f. REVERB (OFF, CONCERT, LIVINGROOM, HALL, ARENA)
g. MUTE (ON/OFF)
h. SPEAKERS (ON/OFF)
D. PARENTAL CONTROL:
a. PARENT LOCK ENABLE (ON/OFF)
b. TV RATING
c. MOVIE RATING
d. ACCESS CODE EDIT
E. PIP SETUP:
a. STYLE (OFF/PIP/POP)
b. Source (AV1、AV2、AV3、ANALOGHD1、ANALOG HD2、DIGITAL HD RGB)
c. SIZE (SMALL (20%)/MEDIUM (30%)/LARGE (40%))
d. POSITION (TOP LEFT/TOP CENTER/TOP RIGHT/MIDDLE LEFT/MIDDLE
RIGHT/BOTTOM LEFT/BOTTOM CENTER/BOTTOM RIGHT)
F. SPECIAL FEATURES:
a. LANGUAGE (ENGLISH/FRANCE/SPANISH)
b. SLEEP TIMER (OFF/30/60/90/120)
c. WIDE FORMAT (NORMAL/WIDE/ZOOM、PANORAMIC)
d. RESET ALL SETTING
PC Analog Mode
A. PICTURE ADJUST:
a. AUTO PICTURE (Run)
b. Adjust the BACKLIGHT (0~100)
c. Adjust the BRIGHTNESS (0~100)
d. Adjust the CONTRAST (0~100)
e. Adjust the V-POSITION (0~100)
f. Adjust the H-SIZE (0~100)
g. Adjust the H-POSITION (0~100)
h. Adjust the FINETUNE (0~100)
CONFIDENTIAL – DO NOT COPY Page 3-2
File No. SG-0168
B. COLOR TEMP:
a. COLOR TEMP. (User, 5000K, 6500K,
9300K)
b. RED (0~255)
c. GREEN (0~255)
d. BLUE (0~255)
C. AUDIO ADJUST:
a. VOLUME (0~100)
b. BASS (0~100)
c. TREBLE (0~100)
d. BALANCE (0~100)
e. SURROUND (ON/OFF)
f. REVERB (OFF, CONCERT, LIVING ROOM, HALL, ARENA)
g. MUTE (ON/OFF)
h. SPEAKERS (ON/OFF)
D. PIP SETUP:
a. STYLE (OFF/PIP/POP)
b. SOURCE (AV1、AV2、AV3、TV)
c. SIZE (SMALL (20%)/MEDIUM (30%)/LARGE (40%))
d. POSITION (TOP LEFT/TOP CENTER/TOP RIGHT/MIDDLE LEFT/MIDDLE
RIGHT/BOTTOM LEFT/BOTTOM CENTER/BOTTOM RIGHT)
E. SPECIAL FEATURES:
a. LANGUAGE (ENGLISH/FRANCE/SPANISH)
b. SLEEP TIMER (OFF/30/60/90/120)
c. WIDE FORMAT (WIDE)
d. RESET ALL SETTING
B. AUDIO ADJUST:
a. VOLUME (0~100)
b. BASS (0~100)
c. TREBLE (0~100)
d. BALANCE (0~100)
e. SURROUND (ON/OFF)
f. REVERB (OFF, CONCERT, LIVING ROOM, HALL, ARENA)
g. MUTE (ON/OFF)
h. SPEAKERS (ON/OFF)
C. PARENTAL CONTROL:
a. PARENT LOCK ENABLE (ON/OFF)
b. TV RATING
c. MOVIE RATING
d. ACCESS CODE EDIT
D. PIP SETUP:
a. STYLE (OFF/PIP/POP)
b. SOURCE (AV1、AV2、AV3、TV)
c. SIZE (SMALL (20%)/MEDIUM (30%)/LARGE (40%))
d. POSITION (TOP LEFT/TOPCENTER/TOP RIGHT/MIDDLELEFT/MIDDLE
RIGHT/BOTTOMLEFT/BOTTOM CENTER/BOTTOMRIGHT)
Video Sources:
AV1、AV2、AV3、ANALOG HD1、ANALOG HD2
A. PICTURE:
a. PICTURE MODE (USER/ VIVID1 /VIVID2 / VIVID3)
b. Adjust the BACKLIGHT (0~100)
c. Adjust the BRIGHTNESS (0~100)
d. Adjust the CONTRAST (0~100)
e. Adjust the COLOR (saturation)(0~100)
f. Adjust the TINT (hue) (0~100)
g. Adjust the SHARPNESS (0~100)
h. CLOSED CAPTION (OFF/CC1/CC2/CC3/CC4/TT1/TT2/TT3/TT4)
B. AUDIO ADJUST:
a. VOLUME (0~100)
b. BASS (0~100)
c. TREBLE (0~100)
d. BALANCE (0~100)
e. SURROUND (ON/OFF)
f. REVERB (OFF, CONCERT, LIVING
ROOM, HALL, ARENA)
g. MUTE (ON/OFF)
h. SPEAKERS (ON/OFF)
C. PARENTAL CONTROL:
a. PARENT LOCK ENABLE (ON/OFF)
b. TV RATING
c. MOVIE RATING
d. ACCESS CODE EDIT
E. SPECIAL FEATURES:
a. LANGUAGE (ENGLISH/FRANCE/SPANISH)
b. SLEEP TIMER (OFF/30/60/90/120)
c. WIDE FORMAT (NORMAL/WIDE/ZOOM、PANORAMIC)
d. RESET ALL SETTING
Pin Description
1 Red
2 Green
3 Blue
4 Ground
5 Ground
6 R-Ground
7 G-Ground
8 B-Ground
10 Ground
11 No Connection
12 (SDA)
13 H-Sync (Composite
Sync)
14 V-Sync
15 (SCL)
1 5
6 10
11 15
F-Type TV RF connector
a. Signal Level 60dBµV typical
b. System NTSC
c. Frequency 55~801MHz (NTSC)
Analog HD2
a. Frequency H: 15.734KHz V: 60Hz (NTSC-480i)
H: 31KHz V: 60Hz (NTSC-480p)
H: 45KHz V: 60Hz (NTSC-720p)
H: 33KHz V: 60Hz (NTSC-1080i)
b. Signal level Y: 1Vp-p Pb: ±0.350Vp-p Pr: ±0.350Vp-p
c. Impedance 75Ω
Pin Description
1 “Auto”
2 “Left”
3 “Right”
4 “Down”
5 “Gnd”
6 “Up”
7 “Menu”
8 “Source”
9 “Power”
10 “LED”
11 “IR”
12 “+5V”
J1 CONNECTION (TOP→BOTTOM)
Pin Description
1 “POWRSW”
2 “+12V”
3 “+12V”
4 “+12V”
5 “+12V”
6 “GND”
7 “GND”
8 “GND”
9 “+5V”
10 “+5V”
11 “+5V”
12 “PWM”
13 “BL ON/OFF”
BOLOCK DIAGRAM
2. TV Decoder
For pip/pop:
Dual identical TVD on chip
3D-comb for both path
Dual VBI decoders for the application of V-chip
3. Support Formats:
Support NTSC, NTSC-4.43
Automatic Luma / Chroma gain control
Automatic TV standard detection
NTSC Motion Adaptive 3D comb filter
Motion adaptive 3D Noise Reduction
VBI decoder for closed-caption/XDS/Teletext/WSS/VPS
Macro vision detection
4. 2D-Graphic/OSD processor
Two OSD planes.
Support alpha blending among these two planes and video
Support text/bitmap decoder
Support line/rectangle/gradient fill
Support bitblt
Support color key function
Support clip mask
65535/256/16/4/2-color bitmap format OSD
Automatic vertical scrolling of OSD image
Support OSD mirror and upside down
6. Video processor
a. Color management
b. De-interlacing
d. Display
7. DRAM Usage
8205,2pcs of 8X16 DDR166 is necessary
Here is a comparison chart between (2XDDR)and(1XDDR)
Pin description
The mode register stores the data for controlling the various operating modes of DDR
SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset
and various vendor specific options to make DDR SDRAM useful for variety of different
applications. The default value of the register is not defined, therefore the mode register
must be written after EMRS setting for proper DDR SDRAM operation. The mode register is
written by asserting low on CS , RAS , CAS , WE and BA0 (The DDR SDRAM should be in
all bank recharge with CKE already high prior to writing into the mode register).
The state of address pins A0~A11 in the same cycle as CS , RAS , CAS , WE and BA0
going low is written in the mode register. Two clock cycles are requested to complete the
write operation in the mode register. The mode register contents can be changed using the
same command and clock cycle requirements during operation as long as all banks are in
the idle state. The mode register is divided into various fields depending on functionality.
The burst length uses A0~A2, addressing mode uses A3, CAS latency (read latency from
column address) uses A4~A6. A7 is used for test mode. A8 is used for DLL reset. A7 must
be set to low for normal MRS operation. Refer to the table for specific codes for various
burst length, addressing modes and CAS latencies.
The precharge command is used to precharge or close a bank that has activated. The
precharge command is issued when CS, RAS and WE are low and CAS is high at the rising
edge of the clock. The precharge command can be used to precharge each bank
respectively or all banks simultaneously. The bank select addresses (BA0, BA1) are used
to define which bank is precharged when the command is initiated. For write cycle,
tWR(min.) must be satisfied until the precharge command can be issued. After tRP from the
precharge, an active command to the same bank can be initiated.
Burst Selection for Precharge by Bank address bits
4. Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS
low at the rising edge of the clock (CLK).
The DDR SDRAM has four independent banks; so two Bank Select addresses (BA0, BA1)
are required.
5. Read Bank
This command is used after the row activates command to initiate the burst read of data.
The read command is initiated by activating CS, CAS , and deasserting WE at the same
clock sampling (rising) edge as described in the command truth table. The length of the
burst and the CAS latency time will be determined by the values programmed during the
MRS command.
6. Write Bank
This command is used after the row activates command to initiate the burst write of data.
The write command is initiated by activating CS, CAS, and WE at the same clock sampling
(rising) edge as describe in the command truth table. The length of the burst will be
determined by the values programmed during the MRS command.
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such
that the Burst read command is issued by asserting CS and CAS low while holding RAS
and WE high at the rising edge of the clock (CLK) after tRCD from the bank activation.
The first output data is available after the CAS Latency from the READ command, and the
consecutive data are presented on the falling and rising edge of Data Strobe (DQS)
adopted by DDR SDRAM until the burst length is completed.
The Burst Write command is issued by having CS , CAS and WE low while holding RAS
high at the rising edge of the clock (CLK). The address inputs determine the starting column
address. There is no write latency relative to DQS required for burst write cycle.
The first data of a burst write cycle must be applied on the DQ pins tDS (Data-in setup time)
prior to data strobe edge enabled after tDQSS from the rising edge of the clock (CLK) that
the write command is issued.
The remaining data inputs must be supplied on each subsequent falling and rising edge of
Data Strobe until the burst length is completed. When the burst has been finished, any
additional data supplied to the DQ pins will be ignored.
BLOCK DIAGRAM
After the system writes the auto select command sequence, the device enters the auto
select mode. The system can then read auto select codes from the internal register (which
is separate from the memory array) on Q7-Q0. Standard read cycle timings apply in this
mode. Refer to the Auto select Mode and Auto select Command Sequence section for more
information. ICC2 in the DC Characteristics table represents the active current specification
for the write mode. The "AC Characteristics" section contains timing specification table and
timing diagrams for write operations.
Figure 1
3. READ/RESET COMMAND
The read or reset operation is initiated by writing the read/reset command sequence into
the command register. Microprocessor read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered. If program-fail or
erase-fail happen, the write of F0H will reset the device to abort the operation. A valid
command must then be written to place the device in the desired state.
5. RESET COMMAND
Writing the reset command to the device resets the device to reading array data. Addresses
bits are don't care for this command. The reset command may be written between the
sequence cycles in an erase command sequence before erasing begins. This resets the
device to reading array data. Once erasure begins, however, the device ignores reset
commands until the operation is complete. The reset command may be written between the
sequence cycles in a program command sequence before programming begins. This resets
the device to reading array data (also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores reset commands until the
operation is complete. The reset command may be written between the sequence cycles in
an SILICON ID READ command sequence. Once in the SILICON ID READ mode, the reset
command must be written to return to reading array data (also applies to SILICON ID READ
during Erase Suspend). If Q5 goes high during a program or erase operation, writing the
reset command returns the device to reading array data (also applies during Erase
Suspend).
The WM8776 supports fully independent sample rates for the ADC and DAC. The audio data
interface supports I2S, left justified, right justified and DSP formats.
BLOCK DIAGRAM
In slave mode the WM8776 has a master detection circuit that automatically determines the
relationship between the master clock frequency and the sampling rate (to within +/- 32
system clocks) If there is a greater than 32 clocks error the interface is disabled and
ADCLRC/DACLRC for optical performance, although the WM8776 is tolerant of phase
variations or jitter on this clock.
Table shows the typical master clock frequency inputs for the WM8776
DIN and DACLRC are sampled by the WM8776 on the rising edge of DACBCLK; ADCLRC is
sampled on the rising edge of ADCBCLK. ADC data is output on DOUT and changes on the
falling edge of ADCBCLK. By setting control bit BCLKINV the polarity of ADCBCLK and
DACBCLK may be reversed so that DIN and DACLRC are sample on the falling edge of
DACBCLK, ADCLRC is sampled on the falling edge of ADCBCLK and DOUT changes on the
rising of ADCBCLK Slave mode as shown in the following figure.
The wm8776 has two possible device addresses, which can be selected using the CE pin
In the L32 LCD TV CE pin is LOW (device address is 34h)
Sil9011 Application
The sil9011 provides a complete solution for receiving HDMI compliant digital audio and
video. Specialized audio and video processing is available within the sil9011 to easily and
cost effectively adds HDMI capability to consumer electronics devices such as digital TVs,
plasma displays, LCD TVs and projectors.
BLOCK DIAGRAM
MM1942 Application
The MM1942 IC is a 5-input 2-output AV switch controlled by the I2C BUS developed for use in
television.
1. I2c Bus
I2C BUS is interring bus system controlled by 2 lines (SDA, SCL). Data are transmitted and
received in the units of byte and Acknowledge. It is transmitted by MSB first from the Start
conditions.
The data format is set as shown in the following figure.
In the L32 TV MM1492 slave address, ADR terminal is L, and 90H is selected.
CONFIDENTIAL – DO NOT COPY Page 7-25
File No. SG-0168
The following figure indicates the control contents of control registers and switches.
b. Audio output 1
c. Audio gain
Block diagram
1. Input configuration
The TDA8946AJ inputs can be driven symmetrical (floating) as well as asymmetrical. In the
asymmetrical mode one input pin is connected via a capacitor to the signal source and the
other input is connected to the signal ground. The signal ground should be as close as
possible to the SVR (electrolytic) capacitor ground. Note that the DC level of the input pins
is half of the supply voltage VCC, so coupling capacitors for both pins are necessary
3. Mode selection
In the L32 LCD TV TDA8946AJ has two functional modes, which can be selected by applying the
proper DC voltage to pin MODE.
a. Mute — In this mode the amplifier is DC-biased but not operational (no audio output).
This allows the input coupling capacitors to be charged to avoid pop-noise. The device is in mute
mode when 3.5 V < VMODE < (VCC − 1.5 V).
b. Operating — In this mode the amplifier is operating normally. The operating mode is activated at
VMODE<1.0V.
GREEN (R194)
CH1 HDMI0 (U16 PIN 124) ;CH2 HDMI15 (U16 PIN 102)
CH1 DV120B (U6 PIN1); CH2 AV_V90 (U6 PIN3) POWER OFF
CH1 DV120B (U6 PIN1); CH2 AV_V90 (U6 PIN3) AC POWER OFF
CH1 DV33A (U5 PIN 1); CH2 DV18A (U5 PIN2) AC POWER OFF
CH1 DV25 (U13 PIN7); CH2 D1V25 (U13 PIN3) POWER OFF
CH1 DV25 (U13 PIN7); CH2 D1V25 (U13 PIN3) AC POWER OFF
Start
N0
1. Is Power board output
+5V?
LED is lighted
2. Is J1 connector good?
3. Is DC-DC OK?
4. Is U4 (3.3V) working ok?
Yes
It is in power saving
N0 1. Check video cable
LED is lighting? 2. Is the timing supported?
3. Check sync input
4. Check VGASOG rout if analog
(SOG)
Yes
N0
Yes
Yes
N0 It means data to LVDS
1.Is J6 connecting well?
U9 no data out? 2.Check J1 +5V&+12V
3.Is panel ok?
Yes
N0
1.Is U9 working good?
U9 no data in? 2.Is U11&U12 working good?
3.IS U10 working good?
END
Start
N0
1.Check video
Input signal good? 2.Check DVD player
Yes
N0
1.Check P2 signal
2.Check signal between P2 and
U20 (IF AV1/AV2 mode)
U20 input correct? 3.Check Tuner &U20 (IF TV mode)
4.Check J4&J6 (IF AV3&S-Video)
5.Check U20 POWER +9V
6.Check U22 data input/output
Yes
N0
1.Check signal between U20 and
U9
U20 output correct?
Yes
N0
1.Check signal between U20 and
U9
LVDS output correct? 2.Check U9 clock (27MHz)
3.Check U9 power
Yes
END
Start
N0
1.Check video
Input signal good? 2.Check host’s setting
Yes
N0
Yes
N0
1.Check signal between U21&U9
U9 input correct? 2.Check U9 Clock (27MHZ)
Yes
N0
1.Check U9
LVDS output correct ? 2.Check U9 power 3.3V 1.8V
Yes
END
Start
N0
1.Check video
Input signal good? 2.Check host’s setting
Yes
N0
1.Check p1 connect
U16 input correct? 2.Check signal between P1 and
U16
Yes
N0
1.Check U16 power
U16 no data out ? 2.Check between signal U16 and
U9
3.Check clock 28.224MHZ
Yes
Yes
END
Start
N0
The voltage is about + 5V
J1 PIN 9,10,11 1.Check power board
2.Check power cable connection
J1
Yes
N0
The voltage is about + 12V while
power switch on
J1 PIN 2,3,4,5 1.J1 connection good
2.Check U9 GPIO Pin
3.Check power board
Yes
N0
The voltage is about +5V while
power switch on
U7 pin 5 6 7 8 1.J1 connection good
2. Check U9 GPIO Pin
Yes
N0
The voltage is about +3.3V
1.J1 to connection good?
U4 pin2 2.Check U4
Yes
N0
The voltage is about +9V
1.Check U9 GPIO Pin
U6 pin 3 2.Check U6
Yes N0
The voltage is about +2.5V while
power switch on
U14 pin2 1.Check U9 GPIO Pin
2.Check U14
Yes
N0
The voltage is about +1.8V
1.Check J1 Connect
U5 pin2 2.Check U5&L5
END
Start
N0
Support DDC1/2B
1.Analog cable ok?
Analog DDC OK? 2.Check signal (U18 to P3)
3.Check U18 Voltage
4.Is compliant protocol?
Yes
N0
Support DDC1/2B
1.Analog cable ok?
HDMIDDC OK? 2.Check signal (U17 to P1)
3.Check U17 Voltage
4.Is compliant protocol?
Yes
END
Digital
Video bus Power Board AC IN
Speakers
J7 j6 J1 J5
Main Board
The TV system block diagram is powered by power board that transforms AC source
of 100V~240V AC +/- 10% @ 50/60 HZ into DC 5V & 12V& 24Vsource. The main
board receives different types of video signal into the MTK8205 Ic. Afterward, the
MTK8205 Ic process the signals control the various functions of the monitor and
outputs control signal, video signal and power to the 30” WXGA panel to be
displayed.
The power send to the panel is first processed by the inverter. The function of the
inverter is to step up the voltagesupplied by the main board to the power that is
needed to light up the lamps in the panel. Simultaneously, the digital video signals are
processed in the panel and the outcome determines the brightness, pixel on/off and
the color displayed on the panel.The analog video signals of S-video, YpbPr, TV, PC
and A/V all video signals are translated from analog signals into MTK8205 generates
the vertical and horizontal timing signals for display device.
The purpose is process the input audio signal to control volume, bass, treble,
surround, and balance. The HDMI video and audio is must transmitting to sil9011
processed then TMDS signal to the MTK8205 generates the vertical and horizontal
timing signals for display device. All functions are controllable by the main board.
Plus, all functions in the IC boards are programmable using I2C Bus.
3
2 STBY R4 10K/NC EXT_STBY HWSDA
HWSDA 4
3 3
2N3904/NC OBO7
OBO7 4,12
1
2N3904-SOT23 R5
10K/NC
GND PWM_DIM
PWM_DIM 12
BL_ON/OFF
BL_ON/OFF 12
J1
5VSB DTXD
DTXD 8
13 BL_ON/OFF DRXD
DRXD 8
12 PWM_DIM R32 0/0805
11 DTVRST
DTVRST 8
DTVRDY
SYSTEM EEPROM 10
9
8 GND
+ CE1
220uF/16V
+ CE2
100uF/16V CB1 CB2
DTVRDY 8
D1 1N4148/NC
2 2
R10 4.7k/NC U3
TP22 1 44
TP23 PD0 VCC
2 PA0/PWM2 PC0* 43
CB5 TP24 3 42 TP36
1uF/0805/NC TP25 PA1/PWM3 PC1* EXT_STBY
4 PA2/PWM4 PC2 41
TP26 5 40 TP35
PA3/PWM5 PC3/PWM0 TP34
6 PA4*/PWM6* PC4/PWM1 39
7 38 DTVCTL
DTVRST PA5*/PWM7* PC5
8 PA6*/PWM8* PC6 37
DTVRDY
I2C Level Shifter DRXD
9
10
11
PA7*/PWM9*
RSTB
PC7
PD1
36
35
34
TP33
TP32
5VSB DV33A DV33A DTXD P30/RXD PD2
12 PD6 NC 33
13 P31/TXD NC 32
14 31 TP31
R11 4.7k/NC TP27 PB2/ADC2/INTE0 PD3
15 PB3/ADC3/INTE1 PD4 30
IR 16 29
R6 R7 R8 R9 R12 4.7k/NC TP28 P34/T0 PD5 R303 33/NC SDA
17 P35/T1 PB7*/SDA1* 28
10K 10K 10K 10K TP29 18 27 R302 33/NC SCL
CB6 22p/NC TP30 PE0 PB6*/SCL1* R301 33/NC VGASDA
19 PE1 PB5*/SDA0* 26
QF1 20 25 R300 33/NC VGASCL
SCL_5V SCL OSCO PB4*/SCL0* OBO7
3 1 21 OSCI PB1/ADC1 24
Y3 22 23 R13 33/NC HWSDA
2N7002 GND PB0/ADC0
2N7002 12MHz/NC NT68F633L/NC
2
CB7 22p/NC
QF2
SDA_5V 3 1 SDA CB18
0.1uF/0603/NC
2N7002
2N7002
2
4 4
DV33A DV18A
U5 L5 0/0805
3 2 DV18A
IN OUT
1 0805L
DV50A DV33A ADJ/GND R15
U4 AZ1086D-1.8 + CE8
DV50A 1 2 L4 70uH F3 2A/125V CB9 1085 NC 220uF/16V CB10
VIN OUT
TabGND
.1u .1u
4 R14 0 0402C 0402C
GNG
FB
ON
CB8 NC
+ CE9 LM2596S-3.3 R16 D2 + CE10 R17
3
Adj:1.23x(1+R2/R1)
1.23x(1+1.69K/1K)=3.3V
3 3
DV120B AV_V90
U6
DV120B 1 3 AV_V90
IN OUT
2 ADJ/GND
+ CE11 UTC78D09A + CE12
220uF/16V CB13 1085 220uF/16V CB14
.1u .1u
0402C 0402C
5VSB DV50A
DV50A
DV50A
5VSB R18 0 DV50A
+ CE13
220uF/16V CB15 CB16 CB17
.1u .1u .1u
0402C 0402C 0402C
5VSB DV50A
U19
1 S1 D1 8
2 G1 D1 7
3 S2 D2 6
4 G2 D2 5
P-CH
R127 IRF7316/N.C
10K/N.C
DV33A DV33A
Q10
DV50B FOR Tuner TU_V50 GPIO R129 10K/N.C 2 2N3904/N.C CB23
.1u
CB24
.1u
CB25
.1u
CB26
.1u
L7 80ohm TU_V50 0402C 0402C 0402C 0402C
1
R152 + CE16
0805L 10K/N.C 1uF/50V/N.C
+ CE18
CB27 220uF/16V CB28
.1u .1u
0402C 0402C
DV18A 0402 PUT ON NEARLY BGA DV18A 0402 PUT ON NEARLY BGA
5VSB DV50B
DV18A DV18A
U7
1 8 CB29 CB30 CB31 CB32 C3 C4
S1 D1 0.1uF 0.1uF 0.1uF 0.1uF .1u .1u
2 G1 D1 7
3 6 0402C 0402C 0402C 0402C 0402C 0402C
S2 D2
4 G2 D2 5
P-CH
IRF7316
Dual P-Ch
R19
10K
NOTE : NC MEANS "NOT CONNECTED ON PCB BOARD"
ALL RESISTORS 0402 WATT,5% UNLESS NOTED.
High = > STANDBY POWER ON ALL RESISTORS VALUES IN OHMS UNLESS NOTED.
Low = > STANDBY POWER OFF R20 1K ALL CAPACITORS 50 VOLT & 105"C UNLESS NOTED.
1 ALL CAPACITOR VALUES IN uF UNLESS NOTED. 1
3
R22 + CE19
10K 1uF/50V
DACFS
DACVREF 4
DACFS 4
ADCPLLVDD1
ADCPLLVDD1 4
FOR DACVDD
ADCPLLVDD
ADCPLLVDD 4
DV33A
4 4
DV33A FB1 80ohm DACVDD APLLVDD
APLLVDD 4
C7 CB33
+ CE20 CB34 + CE21 1uF 0.1uF
10uF/16V 0.1uF 10uF/16V 0402
0402 DACVSS
ANALOGVDD
ANALOGVDD 4
DACVDD
C8 CB35
1uF 0.1uF VPLLVDD
VPLLVDD 4
0402
DACVREF DACFS DACVSS LVDDA
LVDDA 4
C9 R23
0.1uF/NC 560
0402
ADCVDD
ADCVDD 4
DACVSS DACVSS
DACVDD
DACVDD 4
AVCM
AVCM 4
R24 100K
FOR ADCVDD DV33A VOCM
VOCM 4
VICM
VICM 4
L9 80ohm Y1
CB59
0.1uF
0402
PWM2VREF
C26 CB67
+ CE32 CB62 CB63 CB64 CB65 1uF 0.1uF
C25 47uF/16V 0.1uF 0.1uF 0.1uF 0.1uF 0603C
0.1uF 0402C 0402C 0402C 0402C VPLLVSS
0402C
LVSSA
VREFP4
TP3
TP4
TP5
TP6
VGASOG SCL
VGASOG 10 SCL 1,6,11
SDA
SDA 1,6,11
RED+
ADCPLLVDD1
ANALOGVDD
ANALOGVDD
ANALOGVDD
RED+ 10
SYSPLLGND
ADCPLLVDD
SYSPLLGND
SYSPLLGND
SYSPLLGND
SYSPLLGND
SYSPLLGND
RED- IR
RED- 10 IR 1,12
ADCVDD0
ADCVDD0
ADCVDD0
ADCVDD0
ADCVDD0
ADCVSS4
APLLVDD
ADCGND
ADCGND
ADCGND
ADCGND
ADCGND
VGAHSYNC#
VGAVSYNC#
CB19 GREEN+ TxD
DV18A
DV18A
APLL_CAP
GREEN+ 10 TxD 12
DVIODCK
GND
GND
GND
MPX1 GREEN- RxD
VGASOG
0.1u
GREEN+
GREEN-
CVBS2+
CVBS1+
CVBS0+
GREEN- 10 RxD 12
CVBS2-
CVBS1-
CVBS0-
XTALO
BLUE+
VOCM
BLUE-
AVCM
MON0
MON1
XTALI
RED+
VICM
RED-
SOY
VI10
VI11
VI12
VI13
VI14
VI15
VI16
VI17
VI18
VI19
VI20
VI21
VI22
VI23
BLUE+
CR+
SC+
CB+
SY+
CR-
SC-
CB-
SY-
VI0
VI1
VI2
VI3
VI4
VI5
VI6
VI7
VI8
VI9
BLUE+ 10
Y+
Y-
BLUE-
BLUE- 10
XTALI
XTALI 3
VGAHSYNC# XTALO
VGAHSYNC# 10 XTALO 3
M13
M14
M15
M16
N13
D10
D11
C11
D13
C10
D12
C12
C13
C14
N14
D14
D15
C15
D16
C16
D18
D17
C17
C18
C19
D19
C20
D20
C21
D21
C22
D22
C23
D23
B10
A10
B11
A11
B12
A12
B13
A13
B14
A14
B15
A15
A16
B16
A17
B17
A18
B18
E23
A19
B19
A20
B20
A21
B21
A22
B22
A23
B23
L12
L13
L14
L15
L16
VGAVSYNC#
D5
C4
C5
D6
C6
D7
C7
C8
D9
C9
D8
B1
A1
B2
A2
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
B8
A8
B9
A9
VGAVSYNC# 10
4 U9 ANALOGVDD
ADCPLLVDD
ANALOGVDD 3 4
CVBS2P
CVBS1P
CVBS0P
SCP
SYP
CRP
CBP
YP
SOY
RP
GP
BP
DVSS
ADCPLLVSS
SYSPLLVSS
TESTP
XTALI
XTALVSS
APLL_CAP
APLLVSS
DMPLLVSS
VCLK_DVI
AVCM
VOCM
VICM
VFEVSS1
ADCVDD0
ADCVSS0
REFP0
REFN0
ADCVDD1
ADCVSS1
REFP1
REFN1
VFEVDD0
VFEVSS0
ADCVDD2
ADCVSS2
REFP2
REFN2
MON0
MON1
ADCVDD3
SOG
ADCVSS3
REFP3
REFN3
ADCPLLVSS1
ADCPLLVDD1
XTALO
VI0
VI1
VI2
VI3
VI4
VI5
VI6
DVDD18
VI7
VI8
VI9
VI10
VI11
DVSS3
VI12
VI13
VI14
VI15
DVSS18
VI16
VI17
VI18
VI19
VI20
VI21
VI22
VI23
CVBS2N
CVBS1N
CVBS0N
SCN
SYN
CRN
CBN
YN
RN
GN
BN
VSYNC
HSYNC
DVDD
ADCPLLVDD
SYSPLLVDD
TESTN
XTALVDD
APLLVDD
DMPLLVDD
ADCPLLVDD 3
CVBS1+ ADCPLLVDD1
CVBS1+ 10 ADCPLLVDD1 3
CVBS1- APLLVDD
CVBS1- 10 APLLVDD 3
SYSPLLGND
SYSPLLGND 3
ADCVDD4 C3 C24 DVIDE CVBS2+
VFEVDD1 DE_DVI CVBS2+ 10
ADCVDD4 D3 D24 DVIVSYNC CVBS2- VPLLVDD
ADCVDD4 VSYNC_DVI CVBS2- 10 VPLLVDD 3
C1 A24 DVIHSYNC VPLLVSS
SIF HSYNC_DVI VPLLVSS 3
MPX2 C2 Y24 DV18A SY+
AF DVDD18 SY+ 10
ADCVSS4 L11 A25 AOSDATA0 TP7 SY- ADCVDD0
ADCVSS4 AOSDATA0 SY- 10 ADCVDD0 3
VREFP4 D1 A26 AOSDATA1 ADCGND
REFP4 AOSDATA1 ADCGND 3
VREFN4 D2 B26 AOSDATA2 TP8 SC+ ADCVDD
REFN4 AOSDATA2 SC+ 10 ADCVDD 3
ADCGND F2 F23 DV33A SC-
ADCVSS DVDD3I SC- 10
ADC_IN4 D4 B25 AOSDATA3 TP10 DACVDD
TP9 ADIN4 AOSDATA3 DACVDD 3
ADC_IN3 E1 B24 DOUT SOY DACVSS
TP11 ADIN3 LIN SOY 10 DACVSS 3
ADC_IN2 E2 C26 DACBCLK
TP12 ADIN2 AOBCK
ADC_IN1 E3 C25 DACLRC Y+ LVDDA
TP13 ADIN1 AOLRCK Y+ 10 LVDDA 3
ADC_IN0 E4 E24 DACMCLK Y- LVSSA
TP14 ADIN0 AOMCLK Y- 10 LVSSA 3
ADCVDD F1 N15 GND
PWM2VREF ADCVDD DVSS3 A_DQ24 CB+ AUXTOP
F4 PWM2VREF DQ24 G26 CB+ 10 AUXTOP 3
AUXTOP F3 G25 A_DQ25 CB- AUXBOTTOM
AUXVTOP DQ25 CB- 10 AUXBOTTOM 3
AUXBOTTOM G3 F26 A_DQ26
VPLLVSS AUXVBOTTOM DQ26 DV25 CR+ REXTA
J3 VPLLVSS DVDD2 F24 CR+ 10 REXTA 3
VPLLVDD G4 F25 A_DQ27 CR- APLL_CAP
VPLLVDD DQ27 CR- 10 APLL_CAP 3
VPLLVDD H3 E26 A_DQ28 PWM2VREF
DLLVDD DQ28 PWM2VREF 3
VPLLVSS K3 N16 GND
VPLLVSS DLLVSS DVSS2 A_DQ29 AVCM
K4 BGVSS DQ29 E25 AVCM 3
REXTA J4 G24 DV25 DACBCLK VOCM
REXTA DVDD2 DACBCLK 11 VOCM 3
VPLLVDD H4 D26 A_DQ30 DACMCLK VICM
BGVDD DQ30 DACMCLK 11 VICM 3
LVDDA L3 D25 A_DQ31 DACLRC
LVDDA DQ31 DACLRC 11
AP7 G2 H25 A_DQS3 ADCVDD4
A7P DQS3 ADCVDD4 3
AN7 G1 H26 A_DQM1 DOUT ADCVSS4
A7N DQM1 DOUT 11 ADCVSS4 3
CLK2+ H2 P14 GND
CLK2- CLK2P DVSS18 A_DQS2 AOSDATA1
H1 CLK2N DQS2 J25 AOSDATA1 11
LVSSA M12 J26 A_DQ23
AP6 LVSSA DQ23 A_DQ22
J2 A6P DQ22 K25
AN6 J1 P16 GND
AP5 A6N DVSS2 A_DQ21 AP[0..7]
K2 A5P DQ21 K26 AP[0..7] 12
3 AN5 K1 L25 A_DQ20 AN[0..7] 3
A5N DQ20 AN[0..7] 12
LVDDA L4 AA24 DV18A
AP4 LVDDB DVDD18 A_DQ19 CLK1+
L2 A4P DQ19 L26 CLK1+ 12
AN4 L1 H24 DV25 CLK1-
A4N DVDD2 CLK1- 12
AP3 M2 M25 A_DQ18 VREFP4
A3P DQ18 VREFP4 3
AN3 M1 M26 A_DQ17 CLK2+ VREFN4
A3N DQ17 CLK2+ 12 VREFN4 3
LVSSA M11 N25 A_DQ16 CLK2-
LVSSB DQ16 CLK2- 12
CLK1+ N2 J23 A_RA4 DACFS
CLK1P RA4 DACFS 3
CLK1- N1 R16 GND DACVREF
CLK1N DVSS2 DACVREF 3
AP2 P2 J24 A_RA5
AN2 A2P RA5 A_RA6
MT8205
P1 A2N RA6 K23
LVDDA M3 K24 A_RA7 UP1_2
LVDDC RA7 UP1_2 9 A_DQS[0..3]
AP1 R2 L23 A_RA8
A1P RA8 A_RA[0..11] A_DQS[0..3] 5
AN1 R1 R14 GND UP1_3
A1N DVSS18 UP1_3 6 A_BA[0..1] A_RA[0..11] 5
AP0 T2 L24 A_RA9
A0P RA9 A_DQM[0..1] A_BA[0..1] 5
AN0 T1 M23 A_RA11 UP1_4
A0N RA11 UP1_4 7 A_DQ[0..31] A_DQM[0..1] 5
LVSSA N12 N26 A_CKE
LVSSC CKE A_DQ[0..31] 5
DACVDD N3 H23 DV25 UP1_5
DACVDDC DVDD2 UP1_5 11
DACVREF M4 P26 A_CLK A_CLK
VREF RCLK A_CLK 5
DACFS N4 P25 A_CLK# UP3_0 A_CLK#
FS RCLKB UP3_0 12 A_CLK# 5
DACVSS N11 P15 GND A_CKE
DACVSSC DVSS2 A_CKE 5
T4 M24 A_RA3 UP3_1 A_CS#
SVM RA3 UP3_1 6 A_CS# 5
DACVDD P3 N23 A_RA2 A_RAS#
DACVDDB RA2 A_RAS# 5
DACVSS R3 N24 A_RA1 PWM0 A_CAS#
DACVSSB RA1 PWM0 12 A_CAS# 5
DACVDD P4 R26 A_RA0 A_WE#
DACVDDA RA0 A_WE# 5
U4 P24 A_RA10 PWM1
G RA10 PWM1 11
DACVSS R4 P23 A_BA1 DV25
DACVSSA BA1 DV25 5
U3 U23 DV25 GPIO VREF
B DVDD2I GPIO 2 VREF 5
V4 AA23 DV18A
R DVDD18 A_BA0 HWSCL F_A[0..21]
T3 DE BA0 R24 HWSCL F_A[0..21] 5
U1 R23 A_CS#
VSYNCO RCS# A_RAS# HWSDA PCE#
U2 HSYNCO RAS# T24 HWSDA 1 PCE# 5
V1 R15 GND F_OE#
VCLK DVSS2 F_OE# 5
V2 T23 A_CAS# ORO0 PWR#
EBO7 CAS# ORO0 7 PWR# 5
V3 U24 A_WE#
EBO6 RWE# A_DQ8 ORO1 F_D[0..7]
W1 EBO5 DQ8 W26 ORO1 7 F_D[0..7] 5
W2 V25 A_DQ9
DV33A EBO4 DQ9 A_DQ10 ORO2
2
AC9 DVDD3I DQ10 V26 ORO2 7 2
W3 V23 DV25
EBO3 DVDD2 A_DQ11 ORO3 VI[0..23]
W4 EBO2 DQ11 U25 ORO3 6 VI[0..23] 6
Y1 T13 GND
EBO1 DVSS18 A_DQ12 ORO4 DVIODCK
Y2 EBO0 DQ12 U26 ORO4 7 DVIODCK 6
Y3 T25 A_DQ13 DVIDE
EGO7 DQ13 DVIDE 6
GND P11 T15 GND ORO5
DVSS18 DVSS2 ORO5 12
Y4 T26 A_DQ14 DVIHSYNC
EGO6 DQ14 DVIHSYNC 6
AA1 R25 A_DQ15 ORO6 DVIVSYNC
EGO5 DQ15 ORO6 12 DVIVSYNC 6
AA2 W25 A_DQS1
EGO4 DQS1 GND
AA3 EGO3 AVSS18 W23
AA4 Y23 DV18A HDDCSCL
EGO2 AVDD18 DVISCL 6
AB1 G23 VREF OGO0 HDDCSDA
EGO1 RVREF OGO0 6,8 DVISDA 6
AB2 T16 GND
EGO0 DVSS18 A_DQM0 OGO1 MPX1
AB3 ERO7 DQM0 Y26 OGO1 6,8 MPX1 8
AB4 Y25 A_DQS0
ERO6 DQS0 A_DQ7 OGO2 MPX2
AC1 ERO5 DQ7 AA26 OGO2 6,8 MPX2 10
DV18A AC18 V24 DV25
DVDD18 DVDD2 A_DQ6 OGO3
AC2 ERO4 DQ6 AA25 OGO3 6,8
AC3 AB26 A_DQ5 VGASCL
ERO3 DQ5 VGASCL 1,7
AC4 T14 GND OGO4 VGASDA
ERO2 DVSS2 OGO4 7 VGASDA 1,7
GND R11 AB25 A_DQ4
DVSS3 DQ4 A_DQ3 OGO5
AD1 ERO1 DQ3 AC26 OGO5 12
AD2 W24 DV25
OBO7 ERO0 DVDD2 A_DQ2 FCLK
AD3 OBO7 DQ2 AC25 FCLK 7
OBO6 AD4 AD26 A_DQ1 FCMD
OBO6 DQ1 FCMD 7
OBO5 AE1 AD25 A_DQ0 OGO7 FDAT
OBO5 DQ0 OGO7 6 FDAT 7
DVDD18
DVDD18
DVDD18
FCICMD
DVSS18
DVSS18
DVSS18
DVSS18
HIGHA7
HIGHA6
HIGHA5
HIGHA4
HIGHA3
HIGHA2
HIGHA1
HIGHA0
DVDD3I
FCIDAT
FCICLK
DVDD3
DVDD3
IOWR#
DVSS3
DVSS3
PRST#
IOOE#
GPIO0
IOCS#
PWM0
PWM1
IOALE
OGO7
OGO6
OGO5
OGO4
OGO3
OGO2
OGO1
OGO0
OBO[0..7]
ORO7
ORO6
ORO5
ORO4
ORO3
ORO2
ORO1
ORO0
IOA18
IOA19
IOA20
IOA21
OBO4
OBO3
OBO2
OBO1
OBO0
INT0#
SDA0
SDA1
UP12
UP13
UP14
UP15
UP16
UP17
UP30
UP31
UP34
UP35
SCL0
SCL1
IOA0
IOA1
IOA2
IOA3
IOA4
IOA5
IOA6
IOA7
WR#
OBO[0..7] 12
RXD
SDA
RD#
TXD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
SCL
A16
A17
ICE
IR
BGA388
MT8205
AE2
AF1
AF2
AE3
AF3
AE4
AF4
AC5
T11
AD5
AE5
AF5
AC6
AD9
AD6
AE6
AF6
AC7
AD7
AD18
AE7
AF7
AC8
AD8
AF8
P12
AE9
AF9
AE10
AF10
AC11
AD11
AF12
AE15
AD15
AC19
AC15
AF16
AE16
R12
AD16
AC16
AF17
AD17
AD14
AE14
AF14
AF13
AE13
AD13
AC13
AE8
AC10
AC17
AE12
AD12
AE11
T12
AF11
AE17
AF15
AC12
AC14
AF18
AE18
AD10
AF19
AE19
AF20
AE20
AD19
AD20
AC20
AF21
AE21
AD21
P13
AC21
AD22
AC22
AF22
AE22
AF23
AE23
AD23
AC23
AF24
AE24
AD24
R13
AC24
AF25
AE25
AF26
VGASDA AE26
HDDCSCL AB23
HDDCSDA AB24
INT0#
INT0# 6
DV33A
VGASCL
HWSDA
HWSCL
URST#
UP1_2
UP1_3
UP1_4
UP1_5
UP3_0
UP3_1
UP3_4
UP3_5
PWM0
PWM1
F_A15
F_A14
F_A13
F_A12
F_A11
F_A10
F_A16
F_A17
F_A18
F_A19
F_A20
F_A21
FCMD
OGO7
OGO6
OGO5
OGO4
OGO3
OGO2
OGO1
OGO0
PWR#
ORO7
ORO6
ORO5
ORO4
ORO3
ORO2
ORO1
ORO0
OBO4
OBO3
OBO2
OBO1
OBO0
INT0#
PCE#
FDAT
FCLK
GPIO
F_D0
F_D1
F_D2
F_D3
F_D4
F_D5
F_D6
F_D7
F_A9
F_A8
F_A0
F_A1
F_A2
F_A3
F_A4
F_A5
F_A6
F_A7
DV18A
DV18A
DV33A
DV33A
DV18A
RxD
TxD
1 1
ICE
GND
GND
GND
GND
GND
GND
IR
SW1
R34 R35 2 4 + CE34
AmTRAN MODEL VIZIO L32 (3200-0120-0150)
2=4
DV25 DV25
U10
RN1 22x4 U11 D1V25 F_A1 F_D0
25 A0 D0 29
A_RA3 7 8 D_RA3 1 66 F_A2 24 31 F_D1
A_RA2 D_RA2 D_DQ0 VDD VSS D_DQ15 RN2 75x4 F_A3 A1 D1 F_D2 A_DQS[0..3]
5 6 2 DQ0 DQ15 65 23 A2 D2 33 A_DQS[0..3] 4
A_RA1 3 4 D_RA1 3 64 D_RA0 7 8 F_A4 22 35 F_D3 A_RA[0..11]
VDDQ VSSQ A3 D3 A_BA[0..1] A_RA[0..11] 4
A_RA0 1 2 D_RA0 D_DQ1 4 63 D_DQ14 D_RA1 5 6 F_A5 21 38 F_D4
DQ1 DQ14 A4 D4 A_DQM[0..1] A_BA[0..1] 4
D_DQ2 5 62 D_DQ13 D_RA2 3 4 F_A6 20 40 F_D5
DQ2 DQ13 A5 D5 A_DQ[0..31] A_DQM[0..1] 4
RN3 22x4 6 61 D_RA3 1 2 F_A7 19 42 F_D6
VSSQ VDDQ A6 D6 A_DQ[0..31] 4
A_RA4 7 8 D_RA4 D_DQ3 7 60 D_DQ12 F_A8 18 44 F_D7
A_RA5 D_RA5 D_DQ4 DQ3 DQ12 D_DQ11 F_A9 A7 D7 A_CLK
5 6 8 DQ4 DQ11 59 8 A8 D8 30 A_CLK 4
A_RA6 3 4 D_RA6 9 58 RN4 75x4 F_A10 7 32 A_CLK#
VDDQ VSSQ A9 D9 A_CLK# 4
A_RA7 1 2 D_RA7 D_DQ5 10 57 D_DQ10 D_RA4 8 7 F_A11 6 34 DV33A A_CKE
DQ5 DQ10 A10 D10 A_CKE 4
D_DQ6 11 56 D_DQ9 D_RA5 6 5 F_A12 5 36 A_CS#
DQ6 DQ9 A11 D11 A_CS# 4
RN5 22x4 12 55 D_RA6 4 3 F_A13 4 39 A_RAS#
VSSQ VDDQ A12 D12 A_RAS# 4
A_RA8 7 8 D_RA8 D_DQ7 13 54 D_DQ8 D_RA7 2 1 F_A14 3 41 DV33A DV50A A_CAS#
DQ7 DQ8 A13 D13 A_CAS# 4
A_RA9 5 6 D_RA9 14 53 F_A15 2 43 R38 A_WE#
4 NC NC A14 D14 A_WE# 4 4
A_RA11 3 4 D_RA11 15 52 DV33A F_A16 1 45 F_A0 10K
D_DQS0 VDDQ VSSQ D_DQS1 RN6 75x4 F_A17 A15 D15 F_A19 DV25
1 2 16 LDQS UDQS 51 48 A16 A18 16 DV25 4
17 50 2 1 F_A18 17 13 R39 R40 VREF
A13 DNU A17 NC VREF 4
18 49 VREF D_RA11 4 3 15 14 0 0/NC
A_RA10 R41 22 D_RA10 VDD VREF D_RA9 R42 F_A20 RY/BY WP/ACC F_D[0..7]
19 DNU VSS 48 6 5 9 A19 BYTE 47 F_D[0..7] 4
D_DQM0 20 47 D_DQM0 D_RA8 8 7 10K F_A21 10
D_WE# LDM UDM D_CLK# CB70 PCE# A20 PCE#
21 WE CK 46 26 CE VCC 37 PCE# 4
RN7 47x4 D_CAS# 22 45 D_CLK 0.1uF F_OE# 28 F_OE#
CAS CK OE F_OE# 4
A_DQ0 7 8 D_DQ0 D_RAS# 23 44 D_CKE 0402C PWR# 11 27 CB71 PWR#
RAS CKE WE GND1 PWR# 4
A_DQ1 5 6 D_DQ1 D_CS# 24 43 D_RA10 R43 75 46 0.1uF
A_DQ2 D_DQ2 CS NC GND2 0402C
3 4 25 NC A12 42 DV33A 12 RESET
A_DQ3 1 2 D_DQ3 D_BA0 26 41 D_RA11 F_A[0..21]
BA0 A11 F_A[0..21] 4
D_BA1 27 40 D_RA9 RN8 75x4 MX29LV160 16Mb
RN9 47x4 D_RA10 BA1 A9 D_RA8 D_DQ0 28F400
28 A10/AP A8 39 7 8
A_DQ4 7 8 D_DQ4 D_RA0 29 38 D_RA7 D_DQ1 5 6
A_DQ5 D_DQ5 D_RA1 A0 A7 D_RA6 D_DQ2
5 6 30 A1 DDR A6 37 3 4
A_DQ6 3 4 D_DQ6 D_RA2 31 36 D_RA5 D_DQ3 1 2
A_DQ7 D_DQ7 D_RA3 A2 A5 D_RA4
1 2 32 A3 ?M x 16 A4 35
33 VDD VSS 34
RN10 47x4 RN11 75x4 D1V25 D1V25
A_DQ8 7 8 D_DQ8 M13L128168 8Mx16-6 D_DQ4 7 8
A_DQ9 5 6 D_DQ9 D_DQ5 5 6 D1V25 D1V25
A_DQ10 3 4 D_DQ10 D_DQ6 3 4
A_DQ11 1 2 D_DQ11 D_DQ7 1 2
CB72 CB73 CB74 CB75 CB76 CB77 CB78 C27 C28 C29 C30
RN12 47x4 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
A_DQ12 7 8 D_DQ12 RN13 75x4 0402C 0402C 0402C 0402C 0402C 0402C 0402C 0402C 0402C 0402C 0402C
A_DQ13 5 6 D_DQ13 D_DQ8 7 8
A_DQ14 3 4 D_DQ14 D_DQ9 5 6
A_DQ15 1 2 D_DQ15 D_DQ10 3 4
D_DQ11 1 2
D1V25 DV33A
DV25 DV25
RN14 75x4 D1V25 DV33A
RN15 47x4 U12 D_DQ12 7 8
A_DQ16 7 8 D_DQ16 1 66 D_DQ13 5 6
A_DQ17 D_DQ17 D_DQ16 VDD VSS D_DQ31 D_DQ14 CB79 CB80 CB81 CB82 CB83 CB84 CB85 C1 C2
5 6 2 DQ0 DQ15 65 3 4
3 A_DQ18 3 4 D_DQ18 3 64 D_DQ15 1 2 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 3
A_DQ19 D_DQ19 D_DQ17 VDDQ VSSQ D_DQ30 0402C 0402C 0402C 0402C 0402C 0402C 0402C 0402C 0402C
1 2 4 DQ1 DQ14 63
D_DQ18 5 62 D_DQ29
RN16 47x4 DQ2 DQ13 RN17 75x4
6 VSSQ VDDQ 61
A_DQ20 7 8 D_DQ20 D_DQ19 7 60 D_DQ28 D_DQ16 2 1
A_DQ21 5 D_DQ21 D_DQ20 DQ3 DQ12 D_DQ27 D_DQ17 D1V25
6 8 DQ4 DQ11 59 4 3
A_DQ22 3 4 D_DQ22 9 58 D_DQ18 6 5
A_DQ23 1 D_DQ23 D_DQ21 VDDQ VSSQ D_DQ26 D_DQ19 D1V25
2 10 DQ5 DQ10 57 8 7
D_DQ22 11 56 D_DQ25
RN18 47x4 DQ6 DQ9
12 VSSQ VDDQ 55
A_DQ24 7 8 D_DQ24 D_DQ23 13 54 D_DQ24 RN19 + CE35 + CE36 CB86 CB87 CB88 CB89 CB90 CB91
A_DQ25 D_DQ25 DQ7 DQ8 D_DQ20 75x41 220uF/16V 220uF/16V 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
5 6 14 NC NC 53 2
A_DQ26 3 4 D_DQ26 15 52 D_DQ21 4 3 0402C 0402C 0402C 0402C 0402C 0402C
A_DQ27 D_DQ27 D_DQS2 VDDQ VSSQ D_DQS3 D_DQ22
1 2 16 LDQS UDQS 51 6 5
17 50 D_DQ23 8 7
RN20 47x4 A13 DNU VREF
18 VDD VREF 49
A_DQ28 7 8 D_DQ28 19 48 DV25
A_DQ29 D_DQ29 D_DQM1 DNU VSS D_DQM1 RN21 75x4
5 6 20 LDM UDM 47
A_DQ30 3 4 D_DQ30 D_WE# 21 46 D_CLK# D_DQ27 1 2 DV25
A_DQ31 D_DQ31 D_CAS# WE CK D_CLK CB99 D_DQ26
1 2 22 CAS CK 45 3 4
D_RAS# 23 44 D_CKE 0.1uF D_DQ25 5 6
D_CS# RAS CKE 0402C D_DQ24 CB100 CB101 CB102 CB103 CB104 CB105 CB106 CB107
24 CS NC 43 7 8
25 42 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
D_BA0 NC A12 D_RA11 0402C 0402C 0402C 0402C 0402C 0402C 0402C 0402C
26 BA0 A11 41
A_DQS0 R44 47 D_DQS0 D_BA1 27 40 D_RA9 RN22 75x4
D_RA10 BA1 A9 D_RA8 D_DQ31
28 A10/AP A8 39 1 2
A_DQS1 R45 47 D_DQS1 D_RA0 29 38 D_RA7 D_DQ30 3 4
D_RA1 A0 A7 D_RA6 D_DQ29 DV25
30 A1 DDR A6 37 5 6
A_DQS2 R46 47 D_DQS2 D_RA2 31 36 D_RA5 D_DQ28 7 8
D_RA3 A2 A5 D_RA4 DV25
A_DQS3 R47 47 D_DQS3
32 A3 ?M x 16 A4 35
33 VDD VSS 34
M13L128168 8Mx16-6/ FOR ENTRY RN23 75x4 CB108 CB109 CB110 CB111 CB112 CB113 CB114 CB115
D_RAS# 7 8 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
D_CS# 5 6 0402C 0402C 0402C 0402C 0402C 0402C 0402C 0402C
RN24 22x4 D_BA0 3 4
A_CS# 7 8 D_CS# D_BA1 1 2
A_RAS# 5 6 D_RAS#
2 2
A_CAS# 3 4 D_CAS#
A_WE# 1 2 D_WE#
DV25
D_DQS2 R48 75
A_BA1 R49 22 D_BA1 R52 4.7K DV25
D_DQS3 R50 75
A_BA0 R51 22 D_BA0 D1V25 U13 DV25
1 8 D_CAS# R53 75 CB123 CB124 CB125 CB126 CB127 CB128 CB129
A_DQM0 R54 22 D_DQM0 GND VTT 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
2 SD PVIN 7
D1V25 3 6 D_WE# R55 75 0402C 0402C 0402C 0402C 0402C 0402C 0402C
A_DQM1 R56 22 D_DQM1 VREF VSENSE AVIN
TP15 4 VREF VDDQ 5
D_DQM1 R57 75
A_CKE R58 22 D_CKE LP2996 DDR Termination SOP8
D_DQS1 R59 75
A_CLK R60 22 D_CLK
CB116 CB117 + CE38 D_DQS0 R61 75
A_CLK# R62 22 D_CLK# 0.1uF 0.1uF 220uF/16V
0402C 0402C D_DQM0 R63 75
DV25
DV25
CB131 CB132
0.1uF 0.1uF R65
AmTRAN MODEL VIZIO L32 (3200-0120-0150)
0402C 0402C 0
TECHNOLOGY CIRCUITY DDR MEMORY&FLASH
PCB P/ N: 0171-2242-1791 Sheet 5 of 12
CHECKED BY:
ECN NO: APCN05010016 REV: 01
SCH FILE : VINC32-M1.DSN PCB REV: 01
APPROVED BY:
PCB FILE : VINC32-M1.PCB DATE: Wednesday, March 02, 2005
A B C D E
A B C D E
DV33A
VI[0..23]
VI[0..23] 4
FB20 80ohm AVCC DV33A VCC18
U15 DVIODCK
DVIODCK 4
DV33A 3 2 L12 80ohm VCC18 DVIDE
IN OUT DVIDE 4
+ CE44 CB136 C43
10uF/16V 0.1uF 0.1uF 1 0805L DVIHSYNC
ADJ/GND DVIHSYNC 4
0402C 0402C R66 DVIVSYNC
DVIVSYNC 4
+ CE45 CB137 AZ1117D-1.8/adj/NC + CE46 CB138 L21 80ohm VCC18_1
100uF/16V 0.1uF 1085 NC 220uF/16V 0.1uF DATA2+ 1 P1 HDDCSCL R84 100
DVISCL 4
0805L 2 HDDCSDA R85 100
HDMI TYPE-A DVISDA 4
DV33A CB36 CB37 DATA2- 3
0.1uF 0.1uF DATA1+ HDMI-19P SCL
4 SCL 1,4,11
FB21 80ohm IOVCC 5 SDA
SDA 1,4,11
R67 DATA1- 6
0 DATA0+
4
+ CE47 CB139 Adj:1.25x(1+300/680) DV50A
7
8
4
10uF/16V 0.1uF DATA0-
0402C 1.25x(1+300/680)=1.8V CLOCK+
9
10 UP3_1
UP3_1 4
D4 11
1N4148 CLOCK- 12 OGO7
OGO7 4
DV33A R68 0/NC 13
14 UP1_3
TP16 UP1_3 4
FB22 80ohm PVCC HDDCSCL_IN 15
HDDCSDA_IN 16 OGO0
OGO0 4,8
HDMIVSYNC
17 OGO1
OGO1 4,8
CE48 CB140 C44 HDMI_PLUGPWR D5 1N4148 PLUGPWR OGO2
HDCP_SDA
+
HDCP_CLK
18 OGO2 4,8
10uF/16V 0.1uF 0.1uF
VCC18
VCC18
R69 10K HDMICAB OGO3
IOVCC
IOVCC
IOVCC
19 OGO3 4,8
KWP
0402C 0402C
INT0#
INT0# 4
DV33A U16
SiI 9011
FB23 80ohm REGVCC IOVCC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
W/EDID
W/EDID 7,12
QO3
QO4
QO5
QO6
QO7
QO8
QO9
QO10
QO11
QO12
QO13
QO14
Q015
IOVCC
IOGND
CGND
CVCC18
IOVCC
IOGND
CGND
CVCC18
QO16
QO17
QO18
QO19
QO20
QO21
QO22
QO23
IOVCC
IOGND
VSYNC
CB141
0.1uF CB20
0402C 0.1uF ORO3
U23 ORO3 4
0402C
33 128 HDMIHSYNC 1 8
QO2 HSYNC HDMIDE NC VCC KWP
34 QO1 DE 127 2 NC WP 7
DV33A 35 126 3 6 HDCP_CLK
VCC18 QO0 CGND VCC18 NC SCL HDCP_SDA
36 CVCC18 CVCC18 125 4 GND SDA 5
FB24 80ohm XTLVCC 37 124 HDMI0
HDMII2CA CGND QE0 HDMI1 EEPROM 24C04
38 CI2CA QE1 123
HDMISDA 39 122 HDMI2
+ CE49 CB142 C46 HDMISCL CSDA QE2 HDMI3
40 CSCL QE3 121
10uF/16V 0.1uF 0.01uF HDDCSDA 41 120 IOVCC
0402C 0402C HDDCSCL DSDA IOVCC ODCK
42 DSCL ODCK 119
43 NC IOGND 118
PLUGPWR 44 117 HDMI4
VCC18_1 PWR5V QE4 HDMI5
3 45 CVCC18 QE5 116 3
DV33A HDMI_V33 46 115 HDMI6
PVCC PGND QE6 HDMI7
47 PVCC QE7 114
FB25 80ohm HDMI_V33 48 113
AVCC RSVD CGND VCC18
49 AVCC CVCC18 112
CLOCK- 50 111 HDMI8
+ CE50 CB143 C47 CLOCK+ RXC- QE8 HDMI9
51 RXC+ QE9 110
10uF/16V 0.1uF 0.01uF 52 109 HDMI10
0402C 0402C AVCC AGND QE10 HDMI11
53 AVCC QE11 108
DATA0- 54 107 IOVCC R71 1M
DATA0+ RX0- IOVCC
55 RX0+ IOGND 106
56 105 HDMI12 HDMI_V33
AVCC AGND QE12 HDMI13 Y2
57 AVCC QE13 104
DATA1- 58 103 HDMI14 XTLI XTLO
DATA1+ RX1- QE14 HDMI15
59 RX1+ QE15 102
60 101 HDMI16 R70 28.322MHz
AVCC AGND QE16 HDMI17 4.7K
61 AVCC QE17 100
DATA2- 62 99 HDMI18 C48 C49
DATA2+ RX2- QE18 IOVCC 18pF 18pF
63 RX2+ IOVCC 98
64 97 HDMII2CA
AGND IOGND
AUDPVCC18
AUDPGND
XTALOUT
XTALVCC
REGVCC
DVCC18
CVCC18
RESET#
R72
XTALIN
RSVDL
IOGND
IOGND
IOVCC
IOVCC
DGND
CGND
SPDIF
MUTE
MCLK
SDA R73 100 HDMISDA 4.7K/NC HDMI_V33
SCDT
QE23
QE22
QE21
QE20
QE19
SCK
SD3
SD2
SD1
SD0
INT
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
R75
HDMI_PLUGPWR 4.7K
HDMISCDT
HDMILRCK
HDMIBCLK
HDMIRST#
HDMISDO
VCC18_1
HDMI23
HDMI22
HDMI21
HDMI20
HDMI19
VCC18
VCC18
C50 R314
IOVCC
IOVCC
INT0#
XTLO
XTLI
0.1uF 4.7K
0402C U17 RN26 33x4
1 8 HDMI_V33 HDMI0 2 1 VI0
2 NC VCC R316 NC ORO3 HDMI1 VI1 2
2 NC WP 7 4 3
3 6 HDDCSCL_5V HDMI2 6 5 VI2
NC SCL HDDCSDA_5V HDMI3 VI3
4 GND SDA 5 8 7
R315 R77
TP17
TP18
TP19
TP20
TP21
1 0.1uF 0.1uF 0.1uF 0.1uF ALL RESISTORS 0402 WATT,5% UNLESS NOTED. 1
0402C 0402C 0402C 0402C ALL RESISTORS VALUES IN OHMS UNLESS NOTED.
ALL CAPACITORS 50 VOLT & 105"C UNLESS NOTED.
ALL CAPACITOR VALUES IN uF UNLESS NOTED.
HDDCSCL_IN R86 100 HDDCSCL_5V HDDCSDA_IN R87 100 HDDCSDA_5V ALL RESISTORS 25 VOLT IN .1uF UNLESS NOTED.
IOVCC M= METAL 1%
3
AV1
AV1 9
AV1L
AV1 / AV2 Input AV1_IN L13 2.2uH R88 18 AV1 AV1R
AV1L 9
VGA IN AV1R 9
3
FB26 80ohm
P2 C71 C72 R89
7 AV_GND D8 330pF 330pF 56 AV2
DV50A AV2 9
1 AV2_IN BAV99 D-SUB15 FEMALE
16
AV1_IN P3 DHSL-15A S2Y
YELLOW/V 4 S2Y 9
2
AV_GND FB27 0 S2C
S2C 9
8 GNDV 6 RED_GND
2 AV2L 11 1 RED D9 AV2L
AV2L 9
AV1L DV50A GRN_GND 1N4148 AV2R
WHITE/L 5
VGASDA_IN 12
7
2 GREEN
AV2R 9
4 4
9 GNDV AV2_IN L14 2.2uH R90 18 AV2 8 BLU_GND OGO4
OGO4 4
HSYNC# 13 3 BLUE SVDET#
SVDET# 9
3
AV1R D10 1N4148 VGA_PLUGPWR
RED/R 3
6 AV2R C73 C74 R91 VSYNC# 14
9
4 R92 N.C
D11 330pF 330pF 56 10 AV3
AV3 9
RCA2X3 BAV99 VGASCL_IN 15 5
RCA-JK2X3 AV3L
AV3L 9
2
AV_GND FB28 0 AV3R
AV3R 9
17
DV50A
VGASCL
VGASCL 1,4
P4 S2Y_IN L15 2.2uH R93 0 S2Y FB29 80ohm VGASDA
VGASDA 1,4
FB30 80ohm
3
S2C_IN 4 C Y 3 S2Y_IN
C75 C76 R94 VGAL
VGAL 11
S2C_GND 2 G G 1 S2Y_GND D12 330pF 330pF 75 VGA_PLUGPWR VGAR
VGAR 11
5 6 SVDET# BAV99
VGA_PLUGPWR
2
S-VIDEO DETECT S2Y_GND FB31 0 HSYNC#
HSYNC# 10
7
S-VIDEO R263
CB164 4.7K VSYNC#
U18 VSYNC# 10
DV50A 0.1uF
1 NC VCC 8
S2C_IN L16 2.2uH R95 0 S2C 2 7 RED
NC WP RED 10
3 6 VGASCL RED_GND
3 NC SCL RED_GND 10
4 5 VGASDA
DV50B C77 C78 R96 GND SDA R264 GREEN
GREEN 10
D13 330pF 330pF 75 EEPROM 24C02 100 GRN_GND
GRN_GND 10
R97 47K BAV99
BLUE
BLUE 10
1
3 DV50A 3
Y1
Y1 9
VGA_PLUGPWR VGA_PLUGPWR Y1_GND
Y1_GND 9
CB1
CB1 9
CB1_GND
CB1_GND 9
Y1_IN R105 0 Y1 R99 R100
10K 10K CR1
YPBPR Input. CR1 9
3
CR1_GND
CR1_GND 9
R106
P8 D17 75 VGASCL_IN R102 100 VGASCL VGASDA_IN R103 100 VGASDA YPBPR1L
YPBPR1L 9
7 Y1_GND BAV99 YPBPR1R
YPBPR1R 9
3
1 R259 0 DTVY
1
2
5 CB1_IN
CB1_IN R109 0 CB1 ORO0
ORO0 4
9 CR1_GND ORO1
ORO1 4
3
ORO2
ORO2 4
3 R262 0 DTVPR R110
6 CR1_IN D18 75
BAV99 ORO4
ORO4 4
RCA2X3 HPOUTR
HPOUTR 11
1
K1
K2
K3
K4
K5
3
RCA-JK4 BAV99
UP1_4
UP1_4 4
1
CR1_GND FB36 0
DTVY
DTVY 9
DTVPB
DTVPB 9
DV50A DTVPR
DTVPR 9
J3A DV33A
P7 P6
S1Y_IN R298 0 DTVSY AV3_IN L17 2.2uH R101 18 AV3 1 YPBPR1L 1 Y1_IN
1A 2 Y1_GND
3
2A ORO2 2 YPBPR1R
3A ORO1 R299 C79 C80 R104 3 CB1_IN
4A ORO0 75 D14 330pF 330pF 56 RCA2/NC 4 CB1_GND
5
3
4
5A FDAT FB59 BAV99 RCA-JK2
6A FCMD S1Y_GND 0 5 CR1_IN
1
27A S1Y_GND
AmTRAN MODEL VIZIO L32 (3200-0120-0150)
28A S1C_IN
S1C_GND
29A
30A SVDET2#
220uF/16V R246
TECHNOLOGY CIRCUITY VIDEO / AUDIO INPUT
47K
PCB P/ N: 0171-2242-1791 Sheet 7 of 12
CHECKED BY:
ECN NO: APCN05010016 REV: 01
CONN ASY PLUG 30 SCH FILE : VINC32-M1.DSN PCB REV: 01
APPROVED BY:
PCB FILE : VINC32-M1.PCB DATE: Wednesday, March 02, 2005
A B C D E
A B C D E
HA1
ADDRESS TU_CVBS
TU_CVBS 9
TUNER IF GNDS 1 AF
AF 10
DTVY_IN 2
GNDS 3 TUL
TUL 7,9
FQ1236 : NTSC C2 86 DTVPB_IN 4 TUR
TUR 7,9
GNDS 5
DTVPR_IN 6 SCL_5V
SCL_5V 1,9
GNDS 7 SDA_5V
SDA_5V 1,9
4 TU1 DTVHSYNC# 8 4
DTVVSYNC# 9
FQ1236-MK3 GNDS 10
DTVPCLK# 11 MPX1
MPX1 4
SCL_5V R115 33 TU_SCL RN38 0x4/NC GNDS 12
VI16 1 8 DTVYD0 13
AF /MPX
VI20 3 6 DTVYD4 15
VI22 DTVYD6
VS_IF
GND1
GND2
GND3
GND4
CVBS
4 5 16
AF-R
AF-L
SDA
SCL
RN39 0x4/NC GNDS 17
NC
NC
NC
NC
AS
VI8 1 8 DTVPBPRD0 18
VI9 2 7 DTVPBPRD1 19
TH1
TH2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TH3
TH4
VI10 3 6 DTVPBPRD2 20
VI11 4 5 DTVPBPRD3 21 DTVSY
DTVSY 7,9
GNDS 22 DTVSC
DTVSC 7,9
DTVRST# 23
BOTTOM
TU_V50 DTVRDY# 24
GNDS 25 OGO0
OGO0 4,6
TU_V50 L18 2.2uH R120 30 GNDS 26 OGO1
OGO1 4,6
TU_CVBS DTVCVBS_IN 27 OGO2
OGO2 4,6
GNDS 28 OGO3
OGO3 4,6
TU_SCL DTVSY_IN 29
TU_SDA C83 C84 R122 GNDS 30
330pF/NC 330pF 47 DTVSC_IN 31
SIF_IN GNDS 32
DTV_MCLK 33 DTXD
DTXD 1
AF CE51 47uF/16V DTV_BCLK 34 DRXD
DRXD 1
DTV_WS 35
+
DTV_DATA 36 DTVRST
DTVRST 1
RN40 0x4/NC GNDS 37 DTVRDY
DTVRDY 1
VI17 1 8 DTVYD1 38
VI19 2 7 DTVYD3 39
VI21 3 6 DTVYD5 40
L11 2.2uH VI23 4 5 DTVYD7 41
RN41 0x4/NC GNDS 42
VI12 1 8 DTVPBPRD4 43 DTVCTL
3 DTVCTL 1 3
VI13 2 7 DTVPBPRD5 44
+ CE23 VI14 3 6 DTVPBPRD6 45
VI15 4 5 DTVPBPRD7 46
47uF/16V GNDS 47
DTVTXD 48
DTVRXD 49
GNDS 50
DV120B
L8 80ohm
HEADER 50 SMD0.5 BOTTOM/NC
TUNER SIF BPF L/IND/P10.0
W05S-50A
R293
R291
R289
R287
1
2N3904
L/IND/DIP/P10.0 SOT23/SMD
U25 54HCT245/NC
3
4.7K/NC
4.7K/NC
4.7K/NC
4.7K/NC
B2
15 B3 A3 5
DTV_DATA 14 OGO0
DTV_WS B4 A4 6 1 8
OGO2
13 B5 A5 7 2 7
DTVTXD R286 33/NC DTXD DTV_BCLK 12 OGO1
DTVRXD R288 33/NC DRXD DTV_MCLK B6 A6 8 3 6
OGO3
2 11 B7 A7 9 4 5 2
R322 C36 + CE22 DTVRST# R290 33/NC DTVRST DV33A RN33 0x4/NC DV33A
75 NC 10uF/25V DTVRDY# R292 33/NC DTVRDY 20 1 DTVCTL
VCC DIR R323 0/NC
10 GND G 19
DV33A
C10
0.1u/NC
TU_V50
TU_V50
DV120B DV50B
J4
AV_V90
DV50B 1
DV50B 2 AV_V90
GND 3
GND 4
GND 5
GND 6
DV120B 7 GNDV
DV120B 8
8x1 W/HOUSING/NC
W200-8A
GNDS
1 1
AV SWITCH AV_V90
SCL_5V
SCL_5V 1,8
SDA_5V
SDA_5V 1,8
SCL_5V R130 33 SCL90H
C91
0.1uf SDA_5V R131 33 SDA90H AV1
0402 AV1 7
NEARLY U3 AVSW AV1L
40
AV1L 7
U20 AV1R
AV1R 7
AV_V90
VCC
AV1 CB165 0.1uF 0402C 1 37 CVBS1_SWO
V1-V VOUT1 AV2
AV2 7
3
AV2 CB166 0.1uF 0402C 7 39 CE52 10uF/16V Q4
+
D V2-V YOUT1 CVBS1_SWO R132 47 2N3904 S2Y D
2 S2Y 7
AV3 CB167 0.1uF 0402C 13 41 CE53 10uF/16V S2C
+
V3-V COUT1 S2C 7
1
CB168 0.1uF 0402C 16 23 CVBS2_SWO AUO1L_SWO AUO1_L R133 220 CVBS1 AV2L
TP43 STV-V VOUT2 AV2L 7
AV2R
AV2R 7
TU_CVBS CB169 0.1uF 0402C 43 27 SY_SWO
MTV-V YOUT2 R134 R135 R136
YIN1 34 TP44
10K 1K/NC 220 AV3
AV3 7
DTVSY CB170 0.1uF 0402C 3 25 SC_SWO
V1-Y COUT2 AV3L
C1N1 32 TP45 AV3L 7
DTVSC C85 0.01uF 0402C 5 CVBS1_GND AV3R
V1-C AV3R 7
19 CB171 0.1uF 0402C
S2Y CB172 0.1uF 0402C YIN2 C86 0.01uF
9 V2-Y CIN2 21
AV_V90 TU_CVBS
TU_CVBS 8
S2C C87 0.01uF 0402C 11 36 AUO1L_SWO
V2-C LOUT1 R137 R138 TUL
TUL 7
3
35 AUO1R_SWO 10K 10K Q5 TUR
ROUT1 TUR 7
AV1L CE54 2.2uF/25V 2 CVBS2_SWO R139 47 2 2N3904
V1-L AUO2L_SWO
26
+
1
24 AUO2R_SWO AUO1R_SWO AUO1_R R140 220 CVBS2 DTVSY
+
ROUT2 DTVSY 7
AV3L CE56 2.2uF/25V 14 DTVSC
V3-L DTVSC 7
6 S1
+
SCL YPBPR1R 7
CVBS2_GND
AV1R CE59 2.2uF/25V 4 29 SDA90H
V1-R SDA
+
CVBS1 10
AV3R CE61 2.2uF/25V 15 + CE62 CVBS1_GND
V3-R CVBS1_GND 10
3
22uF/16V Q6
+
CVBS2_GND 10
TUR CE64 2.2uF/25V 42 20
GND
GND
GND
MTV-R ADR
1
C AUO2L_SWO AUO2_L R145 220 SY SY C
+
SY 10
SY_GND
SY_GND 10
IC MM1492AF_F
22
33
28
SY_GND AUO1_L
AUO1_L 11
AUO1_R
AUO1_R 11
AV_V90 AUO2_L
AUO2_L 11
AV1L AV2L AV3L TUL YPBPR1L AUO2_R
AUO2_R 11
3
Q7
C88 R149 C89 R150 C90 R151 C127 R195 C92 R153 SC_SWO R154 47 2 2N3904
0.01uF 470K 0.01uF 470K 0.01uF 470K 0.01uF 470K 0.01uF 470K UP1_2
UP1_2 4
0402C 0402C 0402C 0402C 0402C
1
AUO2R_SWO AUO2_R R155 220 SC Y1
Y1 7
Y1_GND
Y1_GND 7
CB1
CB1 7
R156 R157 R158 CB1_GND
CB1_GND 7
10K 1K/NC 75/N.C CR1
CR1 7
AV1R AV2R AV3R TUR YPBPR1R CR1_GND
CR1_GND 7
SC_GND
C93 R159 C94 R160 C95 R161 C96 R162 C97 R163 DTVY
DTVY 7
0.01uF 470K 0.01uF 470K 0.01uF 470K 0.01uF 470K 0.01uF 470K DTVPB
DTVPB 7
0402C 0402C 0402C 0402C 0402C DTVPR
DTVPR 7
Y
Y 10
Y_GND
Y_GND 10
CB
CB 10
CB_GND
CB_GND 10
CR
CR 10
CR_GND
CR_GND 10
B B
SVDET#
SVDET# 7
DV50B
DV33A
U21 S2C R171 75 S2 AV_V90
YCBCRSEL 1 16 DV50B
22uF/16V R168 22uF/16V R169 22uF/16V R170 CB1SW S VCC GNDS
2 I0A E# 15
5.6K 5.6K 5.6K DTVPBSW 3 14 CB92 R172 C98
CB I1A I0D 0.1u 100K 1uF/50V
4 YA I1D 13
Y1SW 5 12 GNDV
DTVYSW I0B YD CR1SW
6 I1B I0C 11
Y 7 10 DTVPRSW
GNDS YB I1C CR
8 GND YC 9
IDTQS3VH257
SOIC16
DV50B DV50B DV50B
GNDS
A R178 0 A
CB1 R179 0/NC CB ALL RESISTORS VALUES IN OHMS UNLESS NOTED.
CB1_GND R180 0 CB_GND ALL CAPACITORS 50 VOLT & 105"C UNLESS NOTED.
22uF/16V R181 22uF/16V R182 22uF/16V R183 CR1 R184 0/NC CR ALL CAPACITOR VALUES IN uF UNLESS NOTED.
5.6K 5.6K 5.6K CR1_GND R185 0 CR_GND ALL RESISTORS 25 VOLT IN .1uF UNLESS NOTED.
M= METAL 1%
OUTPUT
R186 39K R187 39K CE71 47uF/16V FB37 2.2uH
AF MPX2 RED R188 0 R189 100 C99 47nF 0402C RED+ CVBS1+
+
CVBS1+ 4
CVBS1-
CVBS1- 4
C100 C101
15pF 15pF C102 R190
0402C 0402C 5pF 75
0402C CVBS2+
CVBS2+ 4
CVBS2-
CVBS2- 4
RED_GND R191 100 C103 47nF 0402C RED-
4 4
FB38 SY+
SY+ 4
80ohm SY-
SY- 4
SC+
SC+ 4
SC-
SC- 4
R192 0 C104 47nF 0402C VGASOG
VGASOG
VGASOG 4
RED+
RED+ 4
RED-
RED- 4
CVBS2 R199 22 C111 47nF 0402C CVBS2+ FB42 2.2uH
BLUE R200 0 R201 100 C112 47nF 0402C BLUE+ GREEN+
GREEN+ 4
GREEN-
GREEN- 4
C113
330pF C114 R202 BLUE+
5pF BLUE+ 4
0402C 75 BLUE-
BLUE- 4
0402C
CVBS2_GND R232 0 C115 47nF 0402C CVBS2- VGAVSYNC#
VGAVSYNC# 4
3
BLU_GND R204 100 C116 47nF 0402C BLUE- 3
VGAHSYNC#
VGAHSYNC# 4
FB43
80ohm FB44
80ohm MPX2
MPX2 4
FB49
80ohm/NC SY
2 SY 9 2
SY_GND
SY_GND 9
SC
SC 9
SC_GND
SC_GND 9
CB R212 0 R213 100 C123 47nF 0402C CB+ SY R214 0 R215 22 C124 47nF 0402C SY+
Y
Y 9
Y_GND
Y_GND 9
C125 R217 C126
33PF 220 330pF CB
CB 9
0402C 0402C CB_GND
CB_GND 9
CB_GND R218 100 C129 47nF 0402C CB- SY_GND R219 0 C128 47nF 0402C SY- CR
CR 9
CR_GND
CR_GND 9
FB50 FB51
80ohm/NC 80ohm
RED
RED 7
RED_GND
RED_GND 7
GREEN
GREEN 7
GRN_GND
GRN_GND 7
CR R220 0 R221 100 C133 47nF 0402C CR+ SC R222 0 R223 22 C130 47nF 0402C SC+ BLUE
BLUE 7
BLU_GND
BLU_GND 7
C131 R225 C132 VSYNC#
VSYNC# 7
33PF 220 330pF HSYNC#
HSYNC# 7
0402C 0402C NOTE : NC MEANS "NOT CONNECTED ON PCB BOARD"
ALL RESISTORS 0402 WATT,5% UNLESS NOTED.
CR_GND R226 100 C140 47nF 0402C CR- SC_GND R227 0 C134 47nF 0402C SC- ALL RESISTORS VALUES IN OHMS UNLESS NOTED. AF
AF 8
ALL CAPACITORS 50 VOLT & 105"C UNLESS NOTED.
ALL CAPACITOR VALUES IN uF UNLESS NOTED.
1 FB52 FB53 ALL RESISTORS 25 VOLT IN .1uF UNLESS NOTED. 1
80ohm/NC 80ohm M= METAL 1%
TP46
TP47
DV50B HPVDD DV33A DVDD SCL
SCL 1,4,6
SDA
SDA 1,4,6
TP48 SCL R231 100 SCL34H FB54 80ohm HPVDD FB55 80ohm DVDD
4.7K
4.7K
4 10uF/16V 10uF/16V 4
VGAR CE80 10uF/16V R234 10K 0402C 0402C
VGAR
+
VGAR 7
VGAL CE81 10uF/16V R237 10K VGAL
+ VGAL 7
AUO1_R
AUO1_R 9
AUO1_L
R235
R261
HPVDD AUO1_L 9
AUO2_R CE82 10uF/16V R238 10K
AUO2_R
AUO2_R 9
+
48
47
46
45
44
43
42
41
40
39
38
37
CB175 CB176 CB177
0.1uF 0.1uF 0.1uF
AIN2R
AINOPR
AINVGR
AIN3L
AIN3R
AIN4L
AIN4R
AIN5L
AIN5R
AINOPL
AINVGL
AGND
0402C 0402C 0402C DACBCLK
DACBCLK 4
DACMCLK
DACMCLK 4
DACLRC
DACLRC 4
AUO1_R CE85 10uF/16V R240 10K 1 36 HPVDD
AIN2L AVDD ADCREFP DOUT
2 35 DOUT 4
+
HPOUTR
ADCLRC
HPOUTL
HPGND
HPVDD
MODE
DGND
DVDD
NC
CE
CL
DI
13
14
15
16
17
18
19
20
21
22
23
24
3 U22 3
WM8776
QFP-48
DACLRC
HPOUTR
DACLRC
HPOUTL
SDA34H
SCL34H
HPVDD
DVDD
R242
1K T+12V
16
UA1
3
0.47uF/0805
4.7K RA9
VCC1
VCC2
47K 8 IN1+ R+
OUT1+ 1
AV_V90 AV_V90 CA5
6 IN2+ 0.1uf
T+12V 47K 3
4
3
Q8 12 14 L- CA9
AUSPL CE94 10uF/16V 2N3904 10uF/16V IN4+ OUT3- 0.1uf
2
R252 W250-4R
+
1
2 47K 17 L+ 2
100K CA4 OUT4+
1
2
22K 470 1K RA1 RA4 33 2 1 11 SVR
1
NC
CA7
3
47uF/16V
2
2 QA1 7
2N3904 SGND
1
3
UP1_5 10 MODE1
3
Q15 2 QA2
2 2N3904 P9 2N3904
1
AVOL PWM1 RA5 10K CA6 T+12V RA7 0
WHITE/L
GND1
GND2
1 5 MODE2
1
C70
1
2
0.1uF R255 CA8 RA6 RA8 TDA8947J
15
1K RCA2
10K N.C
4
3
5
Q9
AUSPR CE95 10uF/16V 2 2N3904 10uF/16V
+
R258
47K
R256 R257
22K 470 NOTE : NC MEANS "NOT CONNECTED ON PCB BOARD"
ALL RESISTORS 0402 WATT,5% UNLESS NOTED.
ALL RESISTORS VALUES IN OHMS UNLESS NOTED.
1 ALL CAPACITORS 50 VOLT & 105"C UNLESS NOTED. 1
ALL CAPACITOR VALUES IN uF UNLESS NOTED.
ALL RESISTORS 25 VOLT IN .1uF UNLESS NOTED.
M= METAL 1%
AMP_V120
AMP_V120 GNDV
AmTRAN MODEL VIZIO L32 (3200-0120-0150)
3 3
R269 R270
NC 10K/NC
AU R272 1K R271 NC
LG R272 NC R271 1K
R272
R271
RS-232 1K 1K/NC
5VSB
R273 10K PWM_DIM
U24
3
C135 .1u/NC 1 2 C136 .1u/NC
C1+ V+ PWM0 R274 4.7K Q12
2
3 6 C137 .1u/NC 2N3904 + CE4
C138 .1u/NC C1- V- 2N3904-SOT23 10uF/16V
4 C2+
1
5 C2-
TXD R275 33/NC 11 14 R276 33/NC PCTXD
T1IN T1OUT
10 T2IN T2OUT 7
RXD R277 33/NC 12 13 R278 33/NC PCRXD DV33A
R1OUT R1IN
9
16
R2OUT R2IN 8
15
KEYPAD - MAX 7-KEYS
2 VCC GND 2
R279
MAX3232/NC 10K
C139 SOIC16 DV33A
.1u/NC
0402C BL_ON/OFF
7
5
3
1
3
RN36 UP3_0 R280 4.7K 2 Q13
4.7Kx4 2N3904
TXD R281 0 PCTXD 2N3904-SOT23
1
RXD R282 0 PCRXD
8
6
4
2
P11 J7
8 AUTO OBO6 R304 0 1
6 R236 470 IR LEFT OBO5 R305 0 2
5 PCRXD RIGHT OBO4 R306 0 3
4 GND DOWN OBO3 R307 0 4
3 W/EDID 5VSB 5
2 PCTXD UP OBO2 R308 0 6
1 R285 0/N.C 5VSB MENU OBO1 R309 0 7
7 SOURCE OBO0 R310 0 8
PWR KEY OBO7 R311 0 9
RJ11 LED OGO5 R312 0 10
IR R313 0 11
5VSB 12
UI1
FM-6038TM2
IR BOARD
5VSB
ASSY' PN:3320-0012-0189
VOUT
GND
VCC
D D
3
47
RI1
QI1
DI1 2N3904 5VSB
LED
JI1
1 RI3 470
2 IR 1
3 RI4 470 2
3
LED 4
QI2
2N3906
CON4
5VSB
AJD1
1
IR 2
LED 3
PWR KEY 4
SOURCE 5
MENU 6
B UP 7 B
8
DOWN 9
RIGHT 10
LEFT 11
AUTO 12
CON12
CON4
A A
J1 HEADER 30 DV33
J6 J3
1 HPR 4
2 ORO2 R1 33 SD_D0 S1C_IN 4 C Y 3 S1Y_IN 3
3 ORO1 R2 33 SD_CMD HPDET 5
4 ORO0 R3 33 SD_CLK S1C_GND 2 G G 1 S1Y_GND HPL 2
5 FDAT R4 33 MS_SDIO P2 S SVDET2 AGND 1
D D
6 FCMD R5 33 MS_BS
7 S-VIDEO DETECT PHONEJACK 5P
P1
8 YC-CONN-006
FCLK R6 33 MS_CLK J4
9
10 GND AV3_GND 1
11 AV3_IN 2
12
13 AGND GNDV 3
14 HPR AV3L 4
15 HPL
16 HPDET GNDV 5
17 AV3R 6
18 R7 R8
19 22 22 DV33
20 AV3_IN RCA3
21 AV3_GND RCA-JK3B
22 AV3L
C 23 GNDV C1 C2 R9 R10 R11 R12 R13 R14 C
24 AV3R 0.1u 0.1u 1
25 GNDV 10K 10K 10K 10k 10k 10K 2
26 S1Y_IN 3
27 S1Y_GND SD_D0 4
28 S1C_IN 5
29 S1C_GND 6
30 SVDET2 7
MS_BS 8
SD_CLK 9
10
MS_SDIO 11
12
13
14
15
16
SD_CMD 17
B B
MS_CLK 18
19
20
C3 C4 21
10pf 10pf 22
P1
P2
R15
J7CARDER
47K