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Device architectures for the 5nm technology

node and beyond

Nadine Collaert
Distinguished member of technical staff, imec
Outline

• Introduction

• Beyond FinFET: lateral nanowires and vertical transistors

• High mobility materials

• New switching mechanisms

• Summary
Introduction
The future heterogeneous system
MAXIMIZING FUNCTIONALITY AND REDUCING POWER DENSITY

Heterogeneous
Memory stack Chip cooling
Devices on the same
die
Many-core
Logic chip
Optical I/O
I/O chip
3D-TSV
BGA Smart Silicon interposer
Standard CMOS, beyond Si & Beyond CMOS

High bandgap MX2 materials Low bandgap high


Spin logic... mobility materials
Vertical devices

FinFET, GAA,...

Standard CMOS and new devices to enable future heterogeneous systems


Ability to innovate & co-integrate devices to optimize performance & functionality is key
Increase compute power
Log (Functional CPU Scaling)

3nm 3D Logic

SYSTEM Advanced power Interposer 3D SoC


management 3D SiC 5nm

7nm

10nm
DESIGN 9T…7.5T 6T MX2 SPIN
14nm TFET
MTJ
DEVICE VFET
20nm
FinFET GAA CFET

28nm Co
v Ru
MATERIALS Ch-SiGe v
Ch-IIIV
HKMG

LITHOGRAPHY 193i (Multi)-Patterning EUV

2008 2010 2012 2014 2016 2018 2020 2022 2024 2026 2028 2030

Year of 1st Production


Beyond FinFET
Power-performance scaling: FinFET scaling to 7nm

160

14nm 9T FinFET
140
0.8V 10nm 9T FinFET
0.75V
120
Dynamic power [W]

28nm > 20%


100 10nm 7.5T FinFET
0.9V

> 40%
0.75V

80
7nm 7.5T FinFET
< 0.7V
60

30%
15%

<
40
0.55V 0.50V

RO INVD1 0.50V
20 FO3 0.65V
50 CGP BEOL load 0.45V
pSiGe(50%), nSi

0
0 20 40 60 80 100 120 140
Performance [GHz]
Scaling down the fin width to improve electrostatics
FW
Fin width

FH
5 nm 7 nm 10 nm 15 nm

TSMC16 HP (uLVT)

TSMC16 SVT

For a target gate length of 14nm, fin width has to be reduced to 5nm
to meet device electrostatics.
From FinFET to lateral nanowires (NW)
FW
Fin width

FH
5 nm 7 nm 10 nm 15 nm

NH

D= 10nm, Vdd=0.7V TSMC16 HP (uLVT)

D= 7nm, Vdd=0.5V
TSMC16 SVT

Nanowire FETs provide better electrostatics at relaxed nanowire diameter.


From FinFET to lateral NW

Fin 1 wire 2 wires 3 wires


SiO2
Fin

5nm
0.5nm
Decrease Sswing & DIBL

10nm
HfO2
1.5nm NW Roundin
25nm

5nm
30nm
spacin g radius
30nm

30nm

30nm
g 5nm 2.5nm

10nm
Fin

5nm
Increase Raccess
Spacin
g 5nm

STI STI STI STI

Higher stack is needed for nanowire FETs to compensate smaller


cross section than FinFET.
Increased parasitics require the enabling of new features e.g. internal spacers
Power-performance scaling: from FinFET to lateral NW

160
14nm 9T FinFET
140 10nm 9T FinFET
0.8V
Dynamic power [W]

0.75V
120
28nm
100 10nm 7.5T FinFET
0.9V
0.75V

80
7nm 7.5T
NanoWire
0.7V
60
5nm 7.5T NanoWire
40 +30% 0.65V

>50%
5nm 6T NanoWire
0.55V 0.50V 0.65V
20 RO INVD1 0.50V
FO3 0.65V 0.45V
50 CGP BEOL load
0.45V
0 pSiGe(50%), nSi
0.45V

0 20 40 60 80 100 120 140


Performance [GHz]

NW device allows further voltage scaling and performance gains


Lateral NW: an evolutionary path from FinFET

H. Mertens et al., VLSI Symp. 2016.

(a) Si/SiGe Multi-stack (b) Fin patterning & STI (c) Dummy gate

(d) Spacer, S/D, ILD0 & Gate removal (e) SiGe or Si removal (f) Final gate stack
Demonstration of a 2-stacked lateral nanowire device

H. Mertens et al., VLSI Symp. 2016.


No stressors

WF metal Si NW
45nm

RMG-HK

8 nm

• Demonstrated 2-stacked Si NWFET


• Improved performance and electrostatics as compared to FinFETs
Going vertical

Integration Device Circuit System

InGaAs

W top contact

Si
Gate
High mobility materials
Why high mobility materials?
After R. Pillarisetty, Nature, 2011.
Graphene 400x

InSb
Carrier Mobility (cm2/Vs)

InAs

10-40x GaAs
Ge InP
2-6x Si

Vdd limited <


0.5V?

Energy Band Gap (eV)

New Materials with Major Transport Enhancement over Si


Challenges for high mobility materials
Fin Replacement/Wide field/SRB Junction engineering
Epi & Integration & contacting

InGaAs Gate stack & Surface


Passivation

Defect & Phys. Metrology

Device performance and scalability


Challenges for epitaxial growth
Global Local Local
Wafer-level Wide-Area Device-level
Stress-Relaxed Buffer Virtual Substrate Virtual Substrate
(Wide-Trench ART) (Narrow Trench ART)

InP
Defect layer 500 nm
Defect layer

Si

300mm 0.5m-500nm < 50nm


Ge FinFET using fin replacement technique
FIN PITCH DOWN TO 45NM

L. Witters et al., VLSI Symp. 2015.

45nm

20
High performance III-V devices on 300mm Si

VDD=0.5V
3000
Q=30 Q=20
Rectangles: InAs Q=10
2500
Triangles: InGaAs
300mm GAA

Gmsat [S/m]
2000
QW FF
1500 FinFET
IIIVoI
300mm GAA
1000 Q=5
300mm FinFET
500 vertical
NW
IIIVoI CELO
0
50 100 150 200 250
N. Waldron et al., IEDM, 2015.
X. Zhou et al., VLSI 2016. SSsat [mV/dev]
Need for co-integration with Si
Leakage Power

N7 Si FinFET
Vdd = 0.7V N10 Si FinFET
Vdd=0.8V
25% 29%

IIIV/Ge
Vdd = 0.7V

Si-Ge-IIIV Co-integrated?

High mobility channels offer more performance but leakage span limited
Need Si-channel co-integration for SOC
What about 2D materials?

Advantages:
• Expected reduced SCE
• No dangling bonds
• Large choice of materials and
bandgaps

Challenges:
• Large scale growth of MX2
• Choice of MX2 material for
NFET and PFET
• Gate stack
• Contacts
Heterogeneous integration with base CMOS
3-D Hetero-SOC

Cu Interconnect (T~400oC)
• Can the 2-D crystals be
Sequentially selectively grown between
Processed the interconnects? Or by
transfer & bond?
2-D Crystal Devices

• Thermal budget of 2-D


Cu Interconnect (T~400oC)
device processing is
typically low-T, but
material growth is still
Base CMOS unclear
New switching mechanisms
Moving to tunnel FET
ULTRA-LOW VOLTAGE APPLICATIONS
From group IV to III-V

BTBT Generation Rate (GR)


34
10
BTBT generation (cm s )

InGaAs53 Ge (dir)
-3 -1

32
Probability of tunneling is dependent
10 (dir) [1] on bandgap Si dir
30
Ge dir
10 SiGe30 dir
28 Higher tunneling
SiGe50 dirgeneration rate for
10 SiGe80 dir
low bandgap materials
26 Ge (ind) InGaAs dir
10 Si ind
Si (ind)
10
24 Increased Ge
performance
ind expected for
SiGe30 ind
<110> direction III-V
22 SiGe50 ind
10 SiGe80 ind
0 0.5 1 1.5 2 2.5 3
Electric field (MV/cm)
Kao et al, TED 59(2), 292 (2012) & [1] Q. Smets et al, SSDM 2013

27
III-V homojunction n-TFET process and device

A. Alian et al., IEDM, 2015.


1
1010
1
100 homo-junction

Ion [µA/µm] @ Ioff= 100 pA/µm


Vd= 200 mV
0
0
1010 hetero-junction
-1 -1
70% Dewey et al., p.
45, VLSI 2012 This work
1010 10 [8]
Id (uA/um)

1010
-2 -2
53%
-3 -3 [4] [6]
1010 Noguchi et al
1 [7]
-4 -4 53%-shifted
1010 [10]
-5
[11]
-5
1010 Tomioka et al., p.47,
[5]
VLSI, 2012
1010
-6 -6 0.1
0.00.0
0.20.2
0.40.4
0.60.6
0.80.8
1.01.0 0 100 200
Vg (V) SSmin [mV/dec]

• Significant boost with 8nm strained InGaAs (70% In) (quantum confinement & bandgap)
• Very low TAT observed
• SS less degraded by Dit in TFET due to energy range for carrier exchange in TFET operations
III-V Heterostructures

• Staggered and broken gap configurations


Si InAs GaSb GaAs
Ge GaP InP InSb
E GaAsSb In0.53Ga0.47As
c

Ev GaSb0.5As0.5
InGaAs

5.43 6.06 6.1 5.65


a(A)= 5.65 5.45 5.87 6.48
Substrate

4%
0.6-0.7% Lattice
Lattice mismatch S. El Kazzi et al., EUROMBE 2015. A. Verhulst et al., IEDM, 2014.
InP
mismatch

Sb-based materials needed to allow best trade-off between


performance & electrostatics
From 3D TFET to 2D TFET

After Eli Yablonovitch 2012, UC Berkeley

3D-3D 2D-2D

Soft Transition
Abrupt
Transition

• Steepness of the swing over a wide-Vg range limited by 3-D DOS


• Investigate 2-D TFET options
2-D TFETS with 2-D MX2 (TMD) heterostructures

DFT

VG
VG
Left Right
High-k
HfS2 electrode
Device model electrod
VD e
VS intrinsi
MoS2 c

0 doped
High-k
+1013|e|/cm doped
V 2
-1013
|e|/cm2
• Broken gap devices with large bandgaps 2nm
• Lattice mismatch is no longer an issue – van der Waals stacking

31
Negative capacitance FET (NC-FET)
𝝏𝑽𝑮𝑺 𝝏𝒔
SS= = mxn
𝝏𝒔 𝝏(𝒍𝒐𝒈𝑰𝑫)
S. Salahuddin et al., Nano letters, 2008.

VG

CFE
s
CS

• Sub 60mV/dec due to negative capacitance of a ferroelectric oxide


based gate stack (m < 1)
• Tunable hysteresis behavior: non-volatile circuits and noise immune logic
Spin logic
Spin torque majority gate
Spin based devices offer different
Energy-Delay tradeoffs

D. Nikonov et al., IEEE EDL, 2011.

Spin wave devices


Summary
Summary

• Need for more energy-efficient Core Logic Devices and specialty


devices
• Lateral NW is a natural evolution from FinFET and will enable to
continue scaling beyond 7nm due to improved electrostatics
• VFET offers 30-40% SRAM area benefit: 1st step towards vertical
logic?
• Scaling of supply voltage is required to address power crisis and
higher mobility channels are needed to increase performance at
reduced VDD
• New switching mechanisms like TFET, NCFET and spin logic being
considered for ultra-low power applications