Received: 19 September 2018 Revised and accepted: 5 December 2018

DOI: 10.1002/mmce.21678

RESEARCH ARTICLE

Microwave analysis of SiGe heterojunction double-gate tunneling

field-effect transistor through its small-signal equivalent circuit
Yung Hun Jung1 | In Man Kang2 | Seongjae Cho1

1
Department of Electronics Engineering, Gachon
University, Gyeonggi-do, Korea
2
School of Electronics Engineering, Kyungpook
National University, Daegu, Korea
Correspondence
Seongjae Cho, Department of Electronics
Engineering, Gachon University, Gyeonggi-do
13120, Republic of Korea.
Email: felixcho@gachon.ac.kr
Funding information
Korea Evaluation Institute of Industrial
Technology, Grant/Award Numbers: 10052928,
10080513; Ministry of Science and ICT, Grant/
Award Number: 2017R1A2B2011570
Abstract
In this study, Si0.5Ge0.5 was used as a source junction material in a tunneling
field-effect transistor (TFET), which was analyzed using technology computer-aided
design (TCAD) simulation and a small-signal non-quasi static (NQS) equivalent
circuit. The NQS equivalent circuit with additional tunneling resistance (Rtunnel)
enables more accurate analyses. By using a de-embedding process, small-signal
parameters in the intrinsic area were obtained. This process was used to analyze the
resistance and capacitance in each section, the tendencies of the materials, and the
voltage. The error between the NQS equivalent circuit and TCAD device simulation
was within 1.9% in the 400-GHz regime. A cut-off frequency (fT) of up to
0.876 GHz and maximum oscillation frequency (fmax) of 146 GHz were obtained.

KEYWORDS

device simulation, Si0.5Ge0.5, small-signal equivalent circuit, source junction,

tunneling field-effect transistor

1 | INTRODUCTION performances of the heterojunction TFET have been

Semiconductor integrated systems more increasingly require
high-speed and low-power operation capabilities of electron
devices. Conventional metal-oxide-semiconductor field-
effect transistors (MOSFETs) based on drift and diffusion
conduction mechanisms have limit of 60 mV/dec in sub-
threshold swing (S),1–4 which makes it hard to achieve more
ideal switching performances. Tunneling field-effect transis-
tor (TFET) is one of the most promising next-generation
electron devices. TFET is operated by band-to-band tunnel-
ing and has advantages of smaller S values and low-power
operation capability.5–11 It has been pointed out that all-Si
TFET has rather low on-state current and studies have been
conducted for overcoming the weakness by material and
structure side approaches.12–14
In this study, a Si0.5Ge0.5 source junction was used to
improve the on-current, and the direct-current (DC) charac-
teristics were analyzed through technology computer-aided
design (TCAD) simulation. Also, double-gate (DG) struc-
ture is employed for higher gate controllability over
the channel. Although the improvements in the DC
reported in the previous literature, analyses in the RF
regime have been seldom studied. Therefore, in this work,
the RF parameters of the proposed TFET were carefully
analyzed using the non-quasi-static (NQS) equivalent cir-
cuit of the TFET and TCAD simulation in the cooperative
manner. Inclusion of tunneling resistance (Rtunnel) compo-
nent in the equivalent circuit ensures the high accuracy of
the NQS equivalent circuit.15
2 | S IM U L A T I O N S T R A T EG I E S
Figure 1 shows the logical flow of the simulation and model-
ing in this work. First, the device structure is designed and
simulated, and the y-parameter functions have been extracted
by the device simulation. Here, a set of approximated equa-
tions mathematically originating from the equivalent circuit
are utilized for predicting the y-parameters. These set of equa-
tions act as the master equations for the y-parameter functions
without information on the coefficients. The y-parameter func-
tions obtained from the device simulations are fed into the

Int J RF Microw Comput Aided Eng. 2019;e21678. wileyonlinelibrary.com/journal/mmce © 2019 Wiley Periodicals, Inc. 1 of 7
https://doi.org/10.1002/mmce.21678
2 of 7
FIGURE 1 Block diagram for the procedures of obtaining the small-signal
parameters utilizing the device simulation and equivalent circuit
master equations and the unknown coefficients are obtained
through fitting with the least errors. The small-signal parame-
ters are eventually attained by solving the simultaneous equa-
tions generated by the coefficients.
2.1 | Device structure and simulation models
Figure 2 shows the schematic of the simulated SiGe het-
erojunction double-gate n-type TFET. The doping concen-
trations in the source, channel, and drain junctions are p-
type 1020 cm−3, n-type 1015 cm−3, and n-type 1018 cm−3,
respectively. The gate length (Lg) is 30 nm and the chan-
nel thickness is 20 nm. The lengths of source and drain
junctions are 20 nm. The equivalent oxide thickness
(EOT) is 1.5 nm. The gate dielectric material employed
in the actual device simulation is SiO2. Thus, it should be
reasonable to express the EOT value as the SiO2 thick-
ness in this work for opening the options for other possi-
ble gate dielectric materials. TCAD simulation works
have been performed to obtain the DC and the AC char-
acteristics of the TFETs. More accurate simulation
results have been obtained by activating field-dependent
mobility model, concentration-dependent Shockley–Read–
Hall model, Auger recombination model, concentration-
dependent mobility model, bandgap narrowing model,
and non-local band-to-band calculation cooperatively at
the same time.
FIGURE 2 Schematic of the simulated SiGe heterojunction double-gate
TFET device
JUNG ET AL.
2.2 | Equivalent circuit components
Figure 3 shows the NQS equivalent circuit of the SiGe
heterojunction double-gate TFET.15 The figure can be
divided into an intrinsic area and an extrinsic area. A de-
embedding process must be performed to obtain the intrinsic
parameters.15–18 The extrinsic parameters consist of the gate
electrode resistance (Relect), source junction resistance (Rs),
drain junction resistance (Rd), gate-source capacitance (Cgse),
and gate-drain capacitance (Cgde). The intrinsic parameters
consist of the gate-drain capacitance (Cgd), gate-source
capacitance (Cgs), transconductance ( gm), Rtunnel, and chan-
nel resistance (Rch). Rtunnel is the tunneling resistance that
occurs between the source and channel junction. In conven-
tional MOSFET, the resistance generated when electrons
move from source to drain junction is called Rch. In this
work, the source-to-drain channel resistance is divided
into two series-connected resistances caused by source-to-
channel tunneling and by channel-to-drain drift.15 There
should be a parasitic capacitance between SiGe source and
Si channel and needs to be considered in building up a new
equivalent circuit for the heterojunction double-gate TFET.
However, its magnitude should be very small since the para-
sitic capacitance at the SiGe heterojunction is mainly due to
the minority carriers in the p+ SiGe source blocked by the
conduction band offset seen from source toward the channel.
More importantly, the parasitic capacitance is connected to
Rtunnel in Figure 3 in parallel since both the tunneling of
source valence electrons and the diffusion of source conduc-
tion electrons respond to the gate signal between the same
set of terminals at the same time. The parasitic capacitance is
connected to Csd in parallel. Although, the notation of Csd
from the previous equivalent circuit of TFET is preserved,
Csd in this work already include the parasitic capacitance
component across the heterojunction and there is no need to
add an independent capacitor in the equivalent circuit.
To analyze the intrinsic components, the y-parameters
were obtained from the TCAD simulation using a 2-port net-
work system. The y-parameters calculated from the equiva-
lent circuit in Figure 3 were measured after removing the
external components. The simplified passive components are
represented below from Equation (1) through (4).
Y 11 ≈ ω2 Rgd C 2gd + jωC gd ð1Þ
Y 12 ≈ − ω2 Rgd C 2gd + jωC gd ð2Þ
" #
gm Rtunnel τgm Rch R2tunnel C sd
Y 21 ≈ − ω Rgd Cgd +
2 2
Rtunnel + Rch ðRtunnel + Rch Þ2
" #
τgm Rtunnel g Rch R2tunnel C sd
− jω Cgd + + m
ðRtunnel + Rch Þ ðRtunnel + Rch Þ2
ð3Þ
JUNG ET AL. 3 of 7

FIGURE 4 Capacitances in the SiGe heterojunction double-gate TFET

FIGURE 3 NQS equivalent circuit of the SiGe heterojunction double-gate
TFET device
Inversely, Figure 6B shows that the Cgs of Si0.5Ge0.5 is
" # higher than that of Si at the same VDS. Since a large amount
1 Rch R2tunnel C 2sd
Y 22 ≈ + ω2 Rgd C2gd + of electrons are collected in the drain area after the tunneling
Rtunnel + Rch ðRtunnel + Rch Þ2 events, Cgd is eventually increased.
" # ð4Þ
R2tunnel C sd Figure 7 shows the schematic of the total channel resis-
+ jω Cgd +
ðRtunnel + Rch Þ2 tance which is made up of tunneling and channel resistances.
In the conventional MOSFETs, channel resistance can be
Using Equations (1)–(4), the intrinsic parameters are defined as the resistance which is the source for voltage drop
represented as a function of y-parameters as shown in the across the channel by drift and diffusion mechanisms and is
following equations (5) to (9): simply the total channel resistance. On the other hand, in
ImðY 12 Þ TFETs, the carriers are injected from source to drain across
Cgd ¼ − ð5Þ the channel by band-to-band tunneling and drift mechanisms
ω
in sequence. Thus, the total channel resistance can be
ImðY 11 Þ + ImðY 12 Þ
C gs ¼ ð6Þ divided into two different resistances: the resistance by
ω band-to-band tunneling is defined as the tunneling resistance
gm ¼ Re ðY 21 Þjω2 ¼0 + Re ðY 22 Þjω2 ¼0 and that caused by drift is termed as the channel resistance.
ImðY 21 Þ
! These two resistances are connected in series and make up
− ω − C gd − τ Re ðY 21 Þjω2 ¼0 ð7Þ
× ImðY 22 Þ
the total channel resistance.
ω − C gd Figure 8A shows Rtunnel as a function of VGS at different
1 Re ðY 21 Þjω2 ¼0 source junction materials of Si and Si0.5Ge0.5 and at different
Rtunnel ¼ ð8Þ VDS values. Rtunnel shows a monotonic decrease as VGS
gm Re ðY 22 Þjω2 ¼0
increases since the effective tunneling barrier width gets nar-
1 rower for higher VGS which drags down the energy bands in
Rch ¼ − Rtunnel ð9Þ
Re ðY 22 Þjω2 ¼0 the channel region and induces more drastic band bending. It
The above Equations (5)–(9) are used to extract the cor- is definitely revealed that TFETs with Si0.5Ge0.5 source junc-
responding components from the equivalent circuit. tion material show relatively smaller Rtunnel values at
the same set of VGS and VDS. There is small dependence of
Rtunnel on VDS, which can be understood as a short-channel
3 | RE SUL TS

Figure 4 shows the capacitances in the TFET. The circuit is

symmetrical across the boundary of the source and drain.
Cgde and Cgse are constant and dependent on the material, as
shown in Figure 5. The error of the circuit values of the sim-
ulation was less than 2%. The compact model of Cgd in the
intrinsic area consists of the inner fringing capacitance in the
drain area (Cdif) and the gate-inversion layer capacitance on
the drain side (Cgd,inv). Cgs consists of the inner fringing
capacitance in the source area (Csif).19
In Figure 6A, at the same drain voltage (VDS), Si0.5Ge0.5
source junction has lower Cgd than the Si source junction.
Si0.5Ge0.5 has narrow bandgap, which increases tunneling FIGURE 5 Cgde and Cgse of different source junctions and VDS obtained
electrons from source to channel area and decreases Cdif. using TCAD simulation in the off-state TFET (VGS = 0 V)
4 of 7 JUNG ET AL.

FIGURE 8 Channel resistance components dependence on source junction

materials and operating biases. A, Rtunnel. B, Rch
FIGURE 6 Capacitive components as a function of VGS at different source
materials and VDS biases. A, Cgd. B, Cgs
However, off-state current also increases since the inversion
layer between the tunneling barrier edge and drain junction
effect that can be genuinely found in TFETs. Figure 8B
is expanded, which increases carrier drifts. Table 1 summa-
depicts Rch as a function of VGS at different source junction
rizes the capacitances and resistances in the intrinsic areas of
materials and at different VDS values. The drift of tunneling
the simulated TFETs with different source materials at dif-
electrons effectively takes place by different channel and
ferent VDS values. VDS is denoted as the drive voltage (VDD)
doping concentrations, n-type 1015 cm−3 and n-type
for operating the TFETs in Table 1.
1018 cm−3, respectively. Compared with Rtunnel, Rch is more
affected by source junction material. Also, Rch of TFET with
Si source junction has relatively larger dependence on VDS
than that of TFET with Si0.5Ge0.5 source junction.
Figure 9 shows the transfer curves of TFETs with Si and
Si0.5Ge0.5 source junction materials at different VDS biases.
As VDS increases, the on-state current slightly increases.

FIGURE 7 Schematic definitions of tunneling and channel resistances in FIGURE 9 Transfer curves of TFETs with Si and Si0.5Ge0.5 source
the small-signal equivalent circuit of TFET junctions at different VDS biases
JUNG ET AL. 5 of 7

TABLE 1 Capacitances and resistances in the intrinsic areas of TFETs with different source materials at different VDD values

Source material VDD (V) Cgd (fF/μm) Cgs (fF/μm) Rch (Ω) Rtunnel (Ω)
Si 0.6 0.310 0.143 9.18 × 10 8
7.37 × 10−9
0.8 0.298 0.142 7.97 × 10 7
9.67 × 10−8
1.0 0.286 0.142 1.31 × 10 7
6.44 × 10−7
Si0.5Ge0.5 0.6 0.157 0.158 9.76 × 107 2.17 × 10−7
0.8 0.149 0.158 6.98 × 10 6
3.55 × 10−6
1.0 0.142 0.161 1.19 × 10 6
2.29 × 10−5

Figure 10A,B depicts fT and fmax of the TFETs having high accuracy with errors of within 2% up to 1 THz. The real
Si0.5Ge0.5 and Si source junctions, respectively, in compari- part of Y22 in the operations at VGS > 0 V where band-to-
sons at different driving voltages (VDD's). fT and fmax of the band tunneling comes to presence is closely investigated
TFETs are not exactly equal to those expected by the equa- in Figures 11A,B. Re(Y22) can be approximated to a
tions for MOSFET, but the trend is similar.20 fT, fmax, and quadratic function of w in Equation (10) as can be induced
Cgd decrease in the order of VDS = 0.6 V, VDS = 0.8 V, and from Equation (4). Figure 11A plots Re(Y22) as a function of
VDS = 1.0 V, and the Si0.5Ge0.5 junction has a smaller Cgd frequency from the device simulation and the mathematical
than Si. The inverse tendency of Cgd is revealed since equations in comparison up to 400 GHz with an error
Cgd is larger than Cgs in TFET. As the result, small capaci- within 1.9%.
tance is the crucial factor improving the TFET RF
performances19,21,22 " #
2 2
1 R ch R C
It was previously demonstrated in Figure 5 that the Y 22 ≈ + ω2 Rgd C 2gd + tunnel sd
ð10Þ
capacitive components in the off-state (VGS = 0 V) had
Rtunnel + Rch ðRtunnel + Rch Þ2

FIGURE 10 RF performance parameters as a function of VGS at different FIGURE 11 Comparison between Re(Y22) changes from device simulation
source junction materials and VDS values. A, fT and B, fmax and small-signal circuit. Up to (A) 400 GHz and (B) 10 THz
6 of 7
However, the deviation between actual device character-
istics and mathematical prediction gets larger as the fre-
quency goes higher above 1 THz. As shown in Figure 11B,
the curves from device characteristics obtained by device
simulation saturate above about 2 THz are no longer approx-
imated to parabolas. The upper limit where the approxima-
tion is valid depends on individual values of the resistive
and capacitive components in Equation (10). More funda-
mental reason for the coherence failure lies in the absence of
practical closed-form function successfully describing the
device behaviors in the extremely-high frequency regime
above 2 THz yet and the approximation functions need to be
developed in parallel.
4 | CON CLU SION
In this study, RF modeling has been carried out for an
advanced electron device, SiGe heterojunction double-gate
TFET. SiGe source material and double-gate structure have
been introduced for higher current drivability and stronger
gate controllability, respectively. TCAD simulation and
small-signal equivalent circuit were used to analyze DC and
RF characteristics. The extrinsic parameters Cgds and Cgse
were obtained by TCAD simulations as the device character-
istics for reference and the values from the NQS equivalent
circuit showed high accuracy with errors less than 2%
from the simulation results up to 1 THz. Cgd, Cgs, Rtunnel,
and Rch have been analyzed as a function of gate and drain
voltages. Also, the errors between device characteristics
from the TCAD simulations and the mathematical equations
were confirmed to be within 1.9% up to 400 GHz under the
on-state operation conditions. These results provide the
mathematical foundation to build up the circuit models for
heterojunction TFETs which have not been presented yet,
and at the same time, allow us to have a glance at the strong
potential of SiGe heterojunction TFET toward the advanced
VLSI systems operational in the microwave regime.
ACKNOWLEDGMENTS
This work was supported by the Ministry of Science and
ICT (MSIT) of Korea through the mid-career researcher sup-
port program (Grant No. 2017R1A2B2011570) and also
supported by the Ministry of Trade, Industry and Energy
(MOTIE) of Korea with Korea Semiconductor Research
Consortium (KSRC) program for the development of
future semiconductor devices (Grant No. 10080513 and
10052928).
ORCID
Seongjae Cho https://orcid.org/0000-0001-8520-718X
JUNG ET AL.
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A U T H O R B IO G R A P H I E S
Society (EDS) of the Institute of Electrical and Electron-
ics Engineers (IEEE).
YUNG HUN JUNG received the B.S.
degree in electronic engineering from SEONGJAE CHO received the B.S. and
Gachon University, Seongnam, Korea, Ph.D. degrees in Electronic Engineer-
where he is current pursuing the ing from Seoul National University,
M.S. degree. His research interests Seoul, Korea, in 2004 and 2010,
include design, modeling, and fabrica- respectively. He worked as an
tion of nanoscale CMOS devices and Exchange Researcher at the National
optical components such as high-speed photodetector Institute of Advanced Industrial Sci-
and resonators. He is a Student Member of the Institute ence and Technology (AIST), Tsukuba, Japan, in 2009.
of the Electronics and Information Engineering of He worked as a Postdoctoral Researcher at Seoul
Korea (IEIE). National University in 2010 and at Stanford University,
CA, USA from 2010 to 2013. He joined as a faculty
IN MAN KANG received the B.S. degree
member in the Department of Electronics Engineering at
in electronic and electrical engineering
Gachon University, Seongnam, Korea, in 2013. His
from Kyungpook National University,
research interests include group-IV-based alloy materials
Daegu, Korea, in 2001, and the Ph.D.
and their characterization, and design, modeling, and fab-
degree in electrical engineering from
rication of novel nanoscale CMOS devices, emerging
Seoul National University, Seoul,
memory technology, photonic devices and integrated cir-
Korea, in 2007. He worked as a Teach-
cuits, and neuromorphic devices and circuits. He is a Life
ing Assistance at the Inter-university Semiconductor
Member of the IEIE and a Member of IEEE (EDS).
Research Center (ISRC) at Seoul National University
from 2001 to 2006. From 2007 to 2010, he worked as a
Senior Engineer at Design Technology Team at Samsung
Electronics. He joined Kyungpook National University
How to cite this article: Jung YH, Kang IM, Cho S.
as a Full-Time Lecturer of the School of Electronics
Microwave analysis of SiGe heterojunction double-
Engineering where now he works as an Associate Profes-
gate tunneling field-effect transistor through its small-
sor. His current research interests include CMOS RF
signal equivalent circuit. Int J RF Microw Comput
modeling, silicon nanowire devices, tunneling transistors,
Aided Eng. 2019;e21678. https://doi.org/10.1002/
low-power nanoscale CMOS, and III-V compound semi-
mmce.21678
conductor devices. He is a Member of Electron Devices