PVP 14

Code: EC6T1

III B.Tech-II Semester–Regular/Supplementary Examinations–March 2019

VLSI DESIGN
(ELECTRONICS & COMMUNICATION ENGINEERING)

Duration: 3 hours Max. Marks: 70

PART – A
Answer all the questions. All questions carry equal marks
11x 2 = 22 M

1.
a) What is Latch – up in CMOS circuits?
b) What is body effect? Which parameters are responsible
for it?
c) Draw a stick diagram of CMOS inverter.
d) Define a buried contact and a butting contact of
MOSFET.
e) What is floor planning and placement in VLSI circuits?
f) Distinguish pass transistor logic and Transmission gate
logic.
g) What is the difference between PLA and PAL?
h) What is an ASIC? List out different types of ASICs.
i) What is the difference between exhaustive and random
test approaches?
j) Write about stuck open and short faults.
k) Draw the Layout encodings for NMOS and PMOS
transistors.

Page 1 of 3
 PART – B
Answer any THREE questions. All questions carry equal marks.
3 x 16 = 48 M

2. a) Derive the expression for Drain to Source current in both

Saturated and Non- saturated regions of MOS transistor.
8M

b) Explain the operation of enhancement mode MOSFET with

neat diagrams. 8M

3. a) Define standard unit of capacitance and calculate □Cg for

5 µm MOS circuits. 8M

b) Discuss briefly the λ – based design rules for layers, wires

and transistors. 8M

4. a) What are the limitations of Scaling. Derive the scaling

factors for any two device parameters. 8M

b) Design a transmission gate based inverter logic and

explain. 8M

5. a) Discuss the differences between FPGAs and CPLDs. 8 M

b) Design a Half-adder logic using programmable logic

arrays. 8M

Page 2 of 3
6. a) What is the need for testing? Discuss different types of
testing. 8M

b) Discuss scan based techniques of testing a design. 8M

Page 3 of 3
 PVP 14
Code: EC6T1

III B.Tech-II Semester–Regular/Supplementary Examinations–March 2018

VLSI DESIGN
(ELECTRONICS & COMMUNICATION ENGINEERING)

Duration: 3 hours Max. Marks: 70

PART – A
Answer all the questions. All questions carry equal marks
11x 2 = 22 M
1. a) Give the basic process of IC Fabrication.
b) What is figure of Merit of MOS transistor?
c) Define fanout of a logic gate.
d) What are the two types of layout design rules?
e) Differentiate between constant field scaling and constant
voltage scaling.
f) What is meant by transmission gate?
g) Briefly explain about PLA.
h) Write brief notes on gate arrays?
i) What do you mean by DFT?
j) What is the aim of adhoc test techniques?
k) What is a pull down device?

Page 1 of 2
 PART – B
Answer any THREE questions. All questions carry equal marks.
3 x 16 = 48 M
2. a) Describe N-well process in detail. 10 M

b) Explain the transfer characteristics of CMOS inverter

with neat sketch. 6M

3. a) Design a layout for CMOS logic for

8M

b) Explain about sheet resistance and sheet capacitance.

8M
4. a) Write the scaling factors for different types of device
parameters. 10 M

b) How switch logic can be implemented using Pass

Transistors? 6M

5. a) Design a BCD to excess-3 converter using PLA? 10 M

b) Compare PLA,PAL,PROM and CPLD. 6M

6. a) Explain the system level test techniques? 12 M

b) Explain about different fault models in VLSI testing?

4M
Page 2 of 2
 PVP 14
Code: EC6T1

III B.Tech - II Semester – Regular Examinations – May 2017

VLSI DESIGN
(ELECTRONICS & COMMUNICATION ENGINEERING)

Duration: 3 hours Max. Marks: 70

PART – A
Answer all the questions. All questions carry equal marks
11x 2 = 22 M
1.
a) Explain briefly about Depletion mode transistor action.
b) What is Body effect?
c) What are stick diagrams?
d) Define Rise time.
e) Draw the circuit diagram of a two input AND gate using
Pass transistor logic.
f) Write about limitations on scaling.
g) What is Full custom design?
h) What is FPGA?
i) What is Stuck-at model?
j) Compare CMOS and Bipolar transistor.
k) What is Programmable Logic Array?

Page 1 of 3
 PART – B
Answer any THREE questions. All questions carry equal marks.
3 x 16 = 48 M

2. a) Explain an nMOS fabrication process with suitable

diagrams. 8M

b) Explain Latch up in CMOS circuits and how to avoid this

problem? 8M

3. a) What is meant by Sheet resistance RS ? Explain the

concept of RS applied to MOS transistors. 8M

b) Realize the three-input NOR gate using CMOS technology.

8M

4. a) What are the limitations of scaling VLSI circuits and

explain them briefly. 8M

b) Realize a Logical function Y = AB + CD using

transmission gates. 8M

5. a) Design a Full Substractor using PLA. 8M

b) Explain about Gate Array Design. 8M

Page 2 of 3
6. a) Design Built-In-Self -Test (BIST) scheme for memories.
8M

b) Explain the CMOS testing principles. 8M

Page 3 of 3