PRINT - - CSC-326 Transformer Protection IED Manual V1.01 (英文) - 0000189070

CSC-326
Transformer Protection IED

Manual
CSC-326 系列数字式变压器保护装置
说明书
(英文)
编制:
Victor 程垒
校核:
标准化审查: 秦嗣友
审定: 吴书娜
YANG 杨卉卉
版本号: V1.01
文件代号: V1.01
出版日期: 2018 年 08 月
0000189070
2018年08月
Version: V1.01
Doc. Code: 0000189070
Issued Date: 2018.08
Copyright owner: Beijing Sifang Automation Co., Ltd
Note: the company keeps the right to perfect the instruction. If equipment
does not agree with the instruction at anywhere, please contact our
company in time. We will provide you with corresponding service.
®
is registered trademark of Beijing Sifang Automation Co., Ltd.
We reserve all rights to this document, even in the event that a patent is issued and a
different commercial proprietary right is registered. Improper use, in particular reproduction
and dissemination to third parties, is not permitted.
This document has been carefully checked. If the user nevertheless detects any errors, he
is asked to notify us as soon as possible.
The data contained in this manual is intended solely for the product description and is not to
be deemed to be a statement of guaranteed properties. In the interests of our customers,
we constantly seek to ensure that our products are developed to the latest technological
standards as a result; it is possible that there may be some differences between the
hardware/software product and this information product.
Manufacturer: Beijing Sifang Automation Co., Ltd.

Email: support@sf-auto.com
Website: http://www.sf-auto.com
Add: No.9, Shangdi 4th Street, Haidian District, Beijing, P.R.C.100085
Preface
Purpose of this manual
This manual describes the functions, operation, installation, and placing
into service of IED CSC-326. In particular, one will find:
 Information on how to configure the IED scope and a description of the
IED functions and setting options;
 Instructions for mounting and commissioning;
 Compilation of the technical specifications;
 A compilation of the most significant data for experienced users in the
Appendix.
Target audience
This manual mainly face to installation engineer, commissioning engineer
and operation engineer with perfessional electric and electrical knowledge,
rich experience in protection function, using protection IED, test IED,
responsible for the installation, commissioning, maintenance and taking
the protection IED in and out of normal service.
Applicability of this manual

This manual is valid for V1.00 CSC-326 transformer protection IED.
Technical support
In case of further questions concerning the CSC family, please contact
Sifang company or your local Sifang representative.
We provide the users with protection function and test training, the
warranty period is 5 years.
Safety information
Strictly follow the company and international safety regulations.

Working in a high voltage environment requires serious approch
to aviod human injuries and damage to equipment
Do not touch any circuitry during operation. Potentially lethal

voltages and currents are present
Avoid to touching the circuitry when covers are removed. The IED
contains electirc circuits which can be damaged if exposed to
static electricity. Lethal high voltage circuits are also exposed
when covers are removed
I
Using the isolated test pins when measuring signals in open
circuitry. Potentially lethal voltages and currents are present
Never connect or disconnect wire and/or linker to or from IED

during normal operation. Dangerous voltages and currents are
present. Operation may be interrupted and IED and measuring
circuitry may be damaged
Always connect the IED to protective earth regardless of the

operating conditions. Operating the IED without proper earthing
may damage both IED and measuring circuitry and may cause
injuries in case of an accident
Do not disconnect the secondary connection of current

transformer without short-circuiting the transformer’s secondary
winding. Operating a current transformer with the secondary
winding open will cause a high voltage that may damage the
transformer and may cause injuries to humans
Do not remove the screw from a powered IED or from an IED

connected to power circuitry. Potentially lethal voltages and
currents are present
Using the certified conductive bags to transport PCBs (modules).

Handling modules with a conductive wrist strap connected to
protective earth and on an antistatic surface. Electrostatic
discharge may cause damage to the module due to electronic
circuits are sensitive to this phenomenon
Do not connect live wires to the IED, internal circuitry may be

damaged
When replacing modules using a conductive wrist strap

connected to protective earth. Electrostatic discharge may
damage the modules and IED circuitry
When installing and commissioning, take care to avoid electrical

shock if accessing wiring and connection IEDs
Changing the setting value group will inevitably change the IEDs
operation. Be careful and check regulations before making the
change
II
Contents
Chapter 1 Introduction ......................................................................................................... 1
1 IED overview .............................................................................................................. 2
2 IED characteristic ....................................................................................................... 2
3 Basic function ............................................................................................................. 3
3.1 Protection function .............................................................................................. 3
3.2 Control function ................................................................................................... 7
3.3 Measurement function......................................................................................... 7
3.4 Monitoring function .............................................................................................. 8
3.5 Communication mode ......................................................................................... 8
Chapter 2 Common functions .............................................................................................. 9
1 Event record and analysis ........................................................................................ 10
1.1 Overview ........................................................................................................... 10
1.2 Fault record ....................................................................................................... 10
1.3 Waveform record ............................................................................................... 10
1.4 Sequence of event (SOE) ................................................................................. 10
1.5 Operation record ............................................................................................... 11
2 Diagnostic function ................................................................................................... 11
2.1 Overview ........................................................................................................... 11
2.2 Diagnostic principle ........................................................................................... 11
3 Time synchronization function .................................................................................. 11
3.1 Overview ........................................................................................................... 11
3.2 Synchronization principle .................................................................................. 12
3.3 IRIG-B code synchronization mode................................................................... 12
3.4 PPS synchronization mode ............................................................................... 13
3.5 SNTP time synchronization mode ..................................................................... 13
3.6 1588 synchronization mode .............................................................................. 13
4 Authorization ............................................................................................................ 13
Chapter 3 Fault phase selection component .................................................................. 15
1 Overview .................................................................................................................. 16
2 Function module description .................................................................................... 16
3 Detailed description .................................................................................................. 16
3.1 Protection principle............................................................................................ 16
3.1.1 Steady state component phase selector........................................................ 16
3.1.2 Undervoltage phase selection component ..................................................... 17
Chapter 4 Basic protection component .......................................................................... 19
1 Startup component ................................................................................................... 20
1.1 Overview ........................................................................................................... 20
1.2 Current sudden-change startup element ........................................................... 20
1.3 Differential current startup component .............................................................. 20
2 Report ...................................................................................................................... 20
Chapter 5 Differential protection (87T) ........................................................................... 21
1 Overview .................................................................................................................. 22
3 Protection principle ................................................................................................... 24
3.1 Differential and restraint current calculation ...................................................... 25
3.2 Automatic Ratio compensation ......................................................................... 26
3.3 Automatic Vector group and zero sequence current compensation .................. 29
3.4 Instantaneous differential protection characteristic ........................................... 34
3.5 Treble slope percent differential protection characteristic ................................. 35
3.6 CT failure supervision ....................................................................................... 40
3.7 CT Saturation supervision ................................................................................. 41
3.8 Differential current supervision .......................................................................... 42
3.9 Setting list ......................................................................................................... 43
3.10 Report list .......................................................................................................... 44
4 Technical data .......................................................................................................... 45
Chapter 6 Restricted earth fault protection (87REF) ...................................................... 47
III
1Overview .................................................................................................................. 48
2Function module description .................................................................................... 48
3Detailed description.................................................................................................. 48
4Protection principle................................................................................................... 50
4.1 Differential and restraint current calculation ...................................................... 50
4.2 Automatic Ratio compensation ......................................................................... 52
4.3 Positive sequence current blocking................................................................... 53
4.4 Restricted earth fault current alarm ................................................................... 54
5 Setting list ................................................................................................................ 54
6 Report list ................................................................................................................. 56
7 Technical data .......................................................................................................... 56
Chapter 7 Impedance protection (21) ............................................................................ 57
1 Overview .................................................................................................................. 58
3 Detailed description.................................................................................................. 59
3.1 Protection principle ........................................................................................... 59
3.2 Logic diagram ................................................................................................... 61
3.3 Setting list ......................................................................................................... 61
3.4 Report list .......................................................................................................... 66
3.5 Technical data ................................................................................................... 67
Chapter 8 Interturn protection ........................................................................................ 69
1 Overview .................................................................................................................. 70
3.2 Logic diagram ................................................................................................... 71
3.3 Setting list ......................................................................................................... 72
3.4 Report list .......................................................................................................... 72
3.5 Technical data ................................................................................................... 72
Chapter 9 Overcurrent Protection (50, 51, 67) ............................................................... 73
1 Overview .................................................................................................................. 74
3.1.1 Inrush blocking components .......................................................................... 75
3.1.2 Compound voltage blocking unit ................................................................... 76
3.1.3 Directional component ................................................................................... 77
3.1.4 Definite time .................................................................................................. 78
3.1.5 Inverse time ................................................................................................... 78
3.1.6 Trip characteristic .......................................................................................... 79
3.1.7 Logic diagram ................................................................................................ 80
3.2 Setting list ......................................................................................................... 80
3.3 Report list .......................................................................................................... 83
3.4 Technical data ................................................................................................... 84
Chapter 10 Earth fault protection (50N, 51N, 67N) .......................................................... 85
1 Overview .................................................................................................................. 86
3.1.1 Inrush blocking components .......................................................................... 87
3.1.2 Directional component ................................................................................... 88
3.1.3 Definite time .................................................................................................. 89
3.1.4 Inverse time ................................................................................................... 90
3.1.5 Trip characteristic .......................................................................................... 91
3.2 Setting list ......................................................................................................... 92
3.3 Report list .......................................................................................................... 98
3.4 Technical data ................................................................................................... 99
IV
Chapter 11 Negative sequence current protection (46) .................................................. 101
1 Overview ................................................................................................................ 102
2 Function module description .................................................................................. 102
3 Detailed description ................................................................................................ 102
3.1 Protection principle.......................................................................................... 102
3.1.1 Definite time ................................................................................................ 102
3.1.2 Inverse time ................................................................................................. 103
3.1.3 Trip characteristic ........................................................................................ 104
3.2 Setting list ....................................................................................................... 104
3.3 Report list ........................................................................................................ 107
3.4 Technical data ................................................................................................. 108
Chapter 12 Overvoltage protection (59) ......................................................................... 109
1 Overview ................................................................................................................ 110
3.1.1 Definite time ................................................................................................ 111
3.1.2 Inverse time ................................................................................................. 111
3.1.4 Logic diagram .............................................................................................. 112
3.2 Setting list ....................................................................................................... 113
3.3 Report list ........................................................................................................ 115
3.4 Technical data ................................................................................................. 115
Chapter 13 Zero sequence voltage protection (64) ........................................................ 117
1 Overview ................................................................................................................ 118
3.1.1 Definite time ................................................................................................ 118
3.1.2 Inverse time ................................................................................................. 119
3.2 Setting list ....................................................................................................... 120
3.3 Report list ........................................................................................................ 121
3.4 Technical data ................................................................................................. 122
Chapter 14 Negative sequence voltage protection (47) ................................................. 123
1 Overview ................................................................................................................ 124
3.1.1 Definite time ................................................................................................ 124
3.1.2 Inverse time ................................................................................................. 125
3.2 Setting list ....................................................................................................... 126
3.3 Report list ........................................................................................................ 128
3.4 Technical data ................................................................................................. 128
Chapter 15 Undervoltage protection (27) ....................................................................... 129
1 Overview ................................................................................................................ 130
3.1.1 Blocking condition........................................................................................ 131
3.1.2 Definite time ................................................................................................ 131
3.1.3 Inverse time ................................................................................................. 131
3.1.5 Logic diagram .............................................................................................. 133
3.2 Setting list ....................................................................................................... 134
3.3 Report list ........................................................................................................ 135
V
3.4 Technical data ................................................................................................. 136
Chapter 16 Thermal overload protection (49) ................................................................ 137
1 Overview ................................................................................................................ 138
3 Detailed description................................................................................................ 138
3.1 Protection principle ......................................................................................... 139
3.2 Setting list ....................................................................................................... 140
3.3 Report list ........................................................................................................ 140
3.4 Technical data ................................................................................................. 141
Chapter 17 Circuit Breaker Failure protection (50BF) .................................................... 143
1 Overview ................................................................................................................ 144
3.1 Protection function .......................................................................................... 145
3.1.1 Current check .............................................................................................. 145
3.1.2 Breaker auxiliary contacts check ................................................................. 146
3.1.3 CBF protection trip logic .............................................................................. 147
3.2 Setting list ....................................................................................................... 147
3.3 Report list ........................................................................................................ 148
3.4 Parameters ..................................................................................................... 148
Chapter 18 Dead zone protection (50DZ) ...................................................................... 149
1 Overview ................................................................................................................ 150
3.2 Setting list ....................................................................................................... 153
3.3 Report list ........................................................................................................ 153
3.4 Technical data ................................................................................................. 153
Chapter 19 Stub protection (50STUB) ........................................................................... 155
1 Overview ................................................................................................................ 156
3.2 Setting list ....................................................................................................... 157
3.3 Report list ........................................................................................................ 158
3.4 Technical data ................................................................................................. 158
Chapter 20 Pole discrepance protection (62PD) ............................................................ 159
1 Overview ................................................................................................................ 160
3.2 Logic diagram ................................................................................................. 161
3.3 Setting list ....................................................................................................... 162
3.4 Report list........................................................................................................ 162
3.5 Technical data ................................................................................................. 162
Chapter 21 Overexcitation protection (24) ..................................................................... 163
1 Overview ................................................................................................................ 164
3.2 Setting list ....................................................................................................... 167
3.3 Report list ........................................................................................................ 168
3.4 Technical data ................................................................................................. 168
Chapter 22 Underfrequency Protection (81UF).............................................................. 169
1 Overview ................................................................................................................ 170
VI
3.1.1 Protection function introduction ................................................................... 170
3.1.2 Logic diagram .............................................................................................. 172
3.2 Setting list ....................................................................................................... 172
3.3 Report list ........................................................................................................ 173
3.4 Technical data ................................................................................................. 173
Chapter 23 Overfrequency protection (81OF) ................................................................ 175
1 Overview ................................................................................................................ 176
3.1.1 Protection function introduction ................................................................... 176
3.1.2 Logic diagram .............................................................................................. 177
3.2 Setting list ....................................................................................................... 177
3.3 Report list ........................................................................................................ 178
3.4 Technical data ................................................................................................. 178
Chapter 24 Non-electric protection................................................................................. 179
1 Overview ................................................................................................................ 180
3.2 Setting list ....................................................................................................... 180
3.3 Report list ........................................................................................................ 181
Chapter 25 Side differential protection ........................................................................... 183
1 Overview ................................................................................................................ 184
4 Protection principle ................................................................................................. 185
4.1 Differential and restraint current calculation .................................................... 185
4.2 Automatic Ratio compensation ....................................................................... 187
4.3 CT failure supervision ..................................................................................... 187
4.4 Side differential CT Saturation supervision ..................................................... 188
4.5 Side differential current supervision ................................................................ 189
5 Setting list............................................................................................................... 190
6 Report list ............................................................................................................... 191
7 Technical data ........................................................................................................ 191
Chapter 26 Secondary circuit supervision ...................................................................... 193
1 Overview ................................................................................................................ 194
3.1.1. Protection function introduction ................................................................... 194
3.1.2. Logic diagram .............................................................................................. 195
3.2 Setting list ....................................................................................................... 196
3.3 Report list ........................................................................................................ 197
3.4 Technical data ................................................................................................. 197
Chapter 27 T-zone protection......................................................................................... 199
1 Overview ................................................................................................................ 200
3.1.1. Protection startup component ...................................................................... 202
3.1.2. Three-side current differential protection. .................................................... 203
3.1.3. Two-side current differential protection ........................................................ 204
3.1.4. Overcurrent protection ................................................................................. 205
3.1.5. Charging protection ..................................................................................... 205
3.1.6. Abnormality check and judgment ................................................................ 205
VII
3.2 Setting list ....................................................................................................... 206
3.3 Report list ........................................................................................................ 207
Chapter 28 Gap protection ............................................................................................. 209
1 Overview ................................................................................................................ 210
3.2 Setting list ....................................................................................................... 211
3.3 Report list ........................................................................................................ 212
Chapter 29 User-defined protection ............................................................................... 213
1 Overview ................................................................................................................ 214
3.2 Setting list ....................................................................................................... 215
3.3 Report list ........................................................................................................ 216
Chapter 30 User-defined function .................................................................................. 217
1 Overview ................................................................................................................ 218
2 User-defined configuration ..................................................................................... 218
2.1 Open project ................................................................................................... 218
2.2 Binary input configuration ............................................................................... 218
2.3 Binary output configuration ............................................................................. 219
2.4 LED configuration ........................................................................................... 221
2.5 IO Matrix configuration .................................................................................... 222
2.5.1 IO Matrix channel configuration ................................................................... 222
2.5.2 IO Matrix function configuration ................................................................... 222
2.6 Binary input switch setting group .................................................................... 222
2.6.1 Function description .................................................................................... 222
2.6.2 Setting list .................................................................................................... 223
2.7 Configuration startup....................................................................................... 223
2.8 Other configuration ......................................................................................... 224
2.9 Defined logic ................................................................................................... 225
Chapter 31 Substation communication .......................................................................... 227
1 Overview ................................................................................................................ 228
2 Communication protocol ........................................................................................ 228
2.1 IEC 61850-8-1 communication protocol .......................................................... 228
2.2 IEC 60870-5-103 communication protocol ...................................................... 228
3 Communication port ............................................................................................... 228
3.1 Front plate communication port ...................................................................... 228
3.2 RS485 communication port ............................................................................. 228
3.3 Ethernet communication port .......................................................................... 228
4 Technical data ........................................................................................................ 229
5 Typical substation communication mode................................................................ 230
6 Typical clock synchronization mode ....................................................................... 230
Chapter 32 Man-machine interface (MMI) and operation ............................................... 231
1 Overview ................................................................................................................ 232
2 Function description ............................................................................................... 232
2.1 Liquid crystal display(LCD) ............................................................................. 232
2.2 Man-machine interface (MMI) ......................................................................... 232
2.3 Menu structure ................................................................................................ 234
Chapter 33 IED hardware .............................................................................................. 239
1 Overview ................................................................................................................ 240
1.1 IED structure ................................................................................................... 240
1.1.1 4U, 19 2 inch device .................................................................................. 240
1.1.2 4U, 19inch device ........................................................................................ 241
1.2 Module arrangement diagram ......................................................................... 242
VIII
1.2.1 4U, 19 2 inch device .................................................................................. 242
1.2.2 4U, 19inch device ........................................................................................ 242
2 Analog input module .............................................................................................. 243
2.1 Overview ......................................................................................................... 243
2.2 Analog input moduleintroduction ..................................................................... 243
2.3 Technical data ................................................................................................. 244
3 BIO module ............................................................................................................ 245
3.1 Overview ......................................................................................................... 245
3.2 BIO module introduction.................................................................................. 245
3.3 Technical data ................................................................................................. 247
4 CPU module ........................................................................................................... 248
4.1 Overview ......................................................................................................... 248
4.2 CPU module terminal diagram ........................................................................ 248
4.3 Technical data ................................................................................................. 250
5 Power supply module ............................................................................................. 250
5.1 Overview ......................................................................................................... 250
5.2 Power supply module terminals diagram ........................................................ 250
5.3 Technical data ................................................................................................. 251
6 TCS Module ........................................................................................................... 251
6.1 Overview ......................................................................................................... 251
6.2 TCS Module instructions ................................................................................. 252
6.3 Technical data ................................................................................................. 254
7 Test......................................................................................................................... 256
8 Structural design .................................................................................................... 258
9 CE Certification ...................................................................................................... 258
Chapter 34 Appendix ..................................................................................................... 259
1 IED parameter ........................................................................................................ 260
2 Report list ............................................................................................................... 261
2.1 Alarm report .................................................................................................... 261
2.2 Operation Report............................................................................................. 262
4 Typical wiring .......................................................................................................... 268
5 Inverse time characteristic...................................................................................... 271
5.1 Twelve types of IEC and ANSI time inverse property curve ............................ 271
5.2 Definable properties by the user ..................................................................... 271
5.3 Explanation of abbreviations ........................................................................... 272
5.3.1 Explanation of setting abbreviations ............................................................ 272
5.3.2 Explanation of logic switch abbreviations .................................................... 284
5.3.3 Explanation of trip and alarm reoport abbreviations .................................... 291
5.3.4 Explanation of operation report abbreviations ............................................. 299
5.3.5 Explanation of device menu abbreviations .................................................. 300
IX
Chapter 1Chapter 1 Introduction
Chapter 1 Introduction
About this chapter

This chapter describes CSC-326 series transformer
protection IED.
1
1 IED overview
It is selective, reliable and high speed IED (Intelligent Electronic Device)
for transformer protection with powerful capabilities, which is suitable for
large and medium two- or three-winding transformers, and can be the
complicated application as main protection unit or full functions unit and
the communication with station automation system. The integrated and
flexible logic makes IED suitable for all winding connection mode.
Table 1 CSC-326 Application description
Type Sub-type Description
4U, 19 2 inches, two-windings, three-winding

CSC-326-EB
protection and BCU scheme; T-zone protection
CSC-326 plan.
4U, 19 inches, two-windings, three-winding
CSC-326-EBL
protection and BCU scheme.
This series of IEDs use the new design concept, all the IEDs are
established in a general hardware and software platform. All functions are
modulized designed and at the same time diagnosis and debugging tools
are also provided. According to the actual needs of the field, through the
visual chart logic, users can customize all kinds of protection and control
logic. The equipment is highly reliable, flexible and maintainable and can be
adapted to the different site conditions.
2 IED characteristic
CSC-326 series transformer protection IED contains selectivity, reliability
and speed, application range is as bellow:
1) Integrated protection function and monitor and control function.
2) Meeting demands for three-phase tripping in transmission and
distribution grid.
3) Adopt corresponding type for different bay.
a) It is applicable to low voltage side with branch of three-winding
transformer and equipped with six-side differential and three-side
backup protection.
b) Differential protection acquiescently picks up current IH1 from
high voltage side, IH2 from high voltage side 2, IM from medium
side, and IL1 from low voltage side 1, IL2 from low voltage side 2
and IL3 from low voltage side 3.
c) Backup protection of high voltage side acquiescently picks up the
sum current of IH1 and IH2, backup protection of high voltage
side acquiescently picks up IM current, backup protection of low
voltage side 1, side 2 and side 3 acquiescently picks up current of
IL1, IL2 and IL3 respectively.
d) The T protection device is mainly used for protection of T zone
under 1.5 circuit breaker connection modes of 220kV and above
voltage level. It is suitable when CT ratio of three ends is the same.
The device is configured with three-side current differential
2
protection, two-side current differential protection, two stages of

overcurrent protection and line charging protection.
e) It is equipped with overcurrent protection scheme of IEC 61850
GOOSE message.
4) It is equipped with breaker position monitoring function.
5) The device is equipped with module self-diagnosis function.
6) The device can provide complete report records, including operation
report, alarm report, start-up report and tripping report. All reports
could store no less than 40 items and are able to store during power
disruption.
7) Up to two electric/optical Ethernet ports and capable of
communicating with substation automation system through IEC 61850
or IEC 60870-5-103 (TCP103) protocol.
8) RS485 is provided to communicate with substation automatic system
by protocol IEC 60870-5-103.
9) Simple network time protocol (SNTP), pulse, IRIG-B synchronizing
modes can be selected to synchronize time.
10) A friendly MMI.
11) IEDs could be installed on screen, separately on switch panel or in
outdoor switch panel.
3 Basic function
3.1 Protection function
Functions supported by CSC-326-EB(L) and its typical application are as
follows:
Table 2 Typical application configuration
IEC 61850
Description ANSI code Remark
Logic node name
Three-winding
87T PDIF
differential
Two-winding
87T PDIF
differential
Restricted earth
87N REFPDIF HV/MV
fault protection
Impedance
21 HV
protection
Overcurrent
50,51 PTOC HV/MV/LV
protection
Directional
overcurrent 51V, 67 PTOC HV/MV
protection
Self-produced
zero-sequence 50N, 51N PEFM HV/MV/LV
current protection
External earth fault
50G, 51G PEFM HV/MV
protection
Direction earth fault
67N PEFM HV/MV
protection
3
IEC 61850
Logic node name
Negative sequence
46 PPBR HV/MV/LV
current protection
Overvoltage
59 PTOV HV/MV
protection
Zero sequence
64 LV
voltage protection
Negative sequence
47 PPBV HV/MV
voltage protection
Undervoltage
27 PTUV HV/MV
protection
Thermal overload
49 PTTR HV/MV
protection
CBF protection 50BF RBRF HV
Dead zone
50SH-Z LV
protection
Stub protection 50STUB PTOC HV/MV
Three-phase
discordance 62PD LV
protection
Overexcitation
24 HV
protection
Underfrequency
81UF PTUF HV
protection
Overfrequency
81OF PTOF HV
protection
Non-electric
(BI-BO)
protection
CT failure HV/MV/LV
VT failure 97FF HV/MV/LV
Tripping monitoring
Table 3 Typical application configuration2 (T zone protection)

IEC 61850
Logic node name
When the line isolation
is closed, the three-side
current differential
T zone differential protection is put in, and
PDIF
protection when the line isolation
is opened, the two-side
current differential
protection is put in.
When the line isolation
Overcurrent is opened, two-stage
PTOC
protection overcurrent protection
of line side;
Charging
Always put in
protection
4
Application 1 is shown as below:
Figure 1 Application 1
5
Application 2 is shown as below:
Figure 2 Application 2
6
Typical applications for T zone protection are as follows:
Busbar 1
Differential
protection
Side CB
Middle CB
T-area
protection
Busbar 2
Figure 3 Typical applications
3.2 Control function

Table 4 Control function
Description
Circuit breaker, disconnector and other switching devices control
3.3 Measurement function

Measurement is acquired through the dedicated measurement channels.
Table 5 Measurement function
Description
Current: Ia, Ib, Ic
Voltage: Ua, Ub, Uc, Uab, Ubc, Uca
Active power: P, Pa, Pb, Pc
Reactive power: Q, Qa, Qb, Qc
Power factor: COSφ
Frequency: F
7
3.4 Monitoring function

Table 6 Measurement function
Description
Position of circuit breaker, disconnector and other switching devices monitoring
Position of circuit breaker monitoring
Auxiliary contacts of circuit breaker monitoring
Self-diagnosis function
Disturbance and fault record
3.5 Communication mode

Table 7 Communication mode
Communication port on the front plate
RJ45 Ethernet communication port
Communication port on the rear plate
Isolated electrical RS485 communication port
Ethernet electrical/optical communication port
Time synchronization port
Communication protocol
IEC61850 Protocol
IEC60870-5-103 Protocol
DNP3.0
MODBUS
8
Chapter 2 Chapter 1Common functions
Chapter 2 Common functions
About this chapter

The chapter describes the general IED functions
9
1 Event record and analysis

1.1 Overview
To get fast, complete and reliable information about fault current, voltage,
binary signal and other disturbances in the power system is very important.
Through record function of fault data, operators can make better analysis
about the related primary and secondary devices during and after the fault.
Operational personnel can acquire valuable information to explain the
cause of the fault and modify the IED configuration in accordance with the
conclusion to improve IED reliability.
Disturbance data includes devices samples and calculated analogs, BI
and BO signals.
1.2 Fault record

IED can save the latest 40 times disturbance and fault records (which will
not loss during power failures). The records can be viewed through
operation interface of device, communication port or debugging software.
The types of reports include startup report, trip reports, alarm report and
operation report and BI change position report.
Main information of fault records include:
1) Fault time: Date and time
2) Time list: Trip component and time
3) Operation data: Current, voltage, frequency and phase
1.3 Waveform record

Disturbance and fault record function is used to capture the sampling data,
analog data and state data of predefined length before and after an event
(analog data is only applicable for the intermediate node, mid file), and
replay the protected equipment running track before and after the event.
Any logic component and BIO of the device can be used to trigger
recording function.
Recording contains analog channel, digital channel (BI, BO and protection
component states) as well as time standard sequence information.
IED makes data record, according to each cycle. Each record total length
can reach up to 20s and the latest 16 protection trip and 16 times startup,
total 32 records can be saved.
Disturbance and fault record file can be exported through the Ethernet
debugging port by using the debugging tool software (COMTRADE type),
it can also be uploaded to engineer station through the substation
communication network and used to analyze IED trip.
1.4 Sequence of event (SOE)

IED makes real-time monitor and record of trip event, alarm, BI, BO and
connector on or off, a total of 2000 state change events, recording event
time scale, reason and present state, and these real-time data are
transferred to the station control center through communication port. IED
can save more than 10 latest startup and operation event records and
SOE records can be viewed through debugging tools and software.
10
1.5 Operation record

IED records the latest 2000 times of important operating parameters
modification and remote trip and close operation. The operation object,
operation time, data modifications or operational reasons will be recorded
and provide the basis for the accident tracing.
Operation information is saved in operation record of the IED. User can
view these report information through MMI or export them by using
debugging software.
2 Diagnostic function
2.1 Overview
The device realizes the hardware and software self-checking and
monitoring of the device by means of energizing self-diagnosis and
operation self-monitoring to ensure the high reliability of the operation of
the device. Self-checking objects include key components of hardware
(such as analog sampling circuit, BIO output circuit, RAM and ROM) and
hardware accessories (such as backup battery, communication interface)
and important running parameters (such as settings, soft connectors), in
addition, the embedded two level software monitor can be used to monitor
the operation conditions of the software. When the device detects any
abnormal conditions, the device will record the abnormal events and drive
signal node and LED lights. For the key abnormal conditions, the device
will block the protection function and the important output circuit to prevent
the device from malfunctions.
The user can also check the important hardware circuit of the device
through the test command provided by the device, such as the AC circuit,
BI circuit and BO circuit, etc..
In order to cooperate automation system engineering implementation, the
device provides remote point test function, so the local SCADA and remote
master database can be checked, so the complicated manual point check
operation between the SCADA operator and remote operator is avoided.
Mainly includes the telesignalisation point check, telemetry point check.
2.2 Diagnostic principle

1) Measurement device power
2) Check zero drift and zero drift out-of-limits
3) Confirm alarm circuit
4) Check setting and parameter
3 Time synchronization function

3.1 Overview
The IED, as a part of the protection system, can be time synchronized by
time synchronization source. In the security automation intelligent system,
through the time synchronization, IED and other devices in the system
have the same clock source. When the system fault or abnormal, there is a
unified clock reference between the various devices.
11
3.2 Synchronization principle

Definition of time
The error of a clock is the difference between the actual time and the
synchronized clock. The rate accuracy of a clock is normally called the
clock accuracy. When the clock deviation is too large, the clock will
re-synchronize to ensure clock accuracy is within the set range.
Synchronization principle
Generally speaking, synchronization can be seen as a hierarchical
structure. A module is synchronized from a higher level and provides
synchronization to lower levels.
Synchronization from a higher level
Module
Optional synchronization of modules at

a lower level
Figure 4 Synchronization principle diagram

A module of the system is synchronized when it receives synchronization
signal from a higher level and this module is time synchronization module.
The less the clock synchronization level, the higher the final time
synchronization accuracy is. The same module may have several options
of time synchronization sources with different errors, this module can
choose the best time source and adjust the internal clock, according to the
time synchronization source. The maximum error of a clock can be defined
as:
1) The maximum error of the last synchronization information;
2) The calculated time from last time synchronization information;
3) The rate accuracy of the internal clock in the module.
Time synchronization system provides three synchronization methods:
IRIG-B code, IEEE1588 and net synchronization and second pulse
synchronization.
3.3 IRIG-B code synchronization mode

The build-in clock module receives the time information from the time
synchronization device and decodes it, and the clock module is located in
the CPU module of the device. IRIG-B (DC) code synchronization signal,
and the electrical interface is RS485.
12
3.4 PPS synchronization mode

The synchronization terminal on the CPU module of the device receives
PPS signal from substation time synchronization system. If the substation
time is not synchronized with the standard time, the present time of the
substation will be regarded as valid time and the IED time is synchronized
with it. After receiving the pulse signal, the CPU can automatically adapt to
the positive and negative pulses. The electrical interface is RS485.
3.5 SNTP time synchronization mode

SNTP time synchronization adopts question and answer type. A time
synchronization message is send from IED to SNTP-server, SNTP server
deals with the transmission delay, and then return the time information to
the device. SNTP time synchronization mode adopts IEC61850 through
Ethernet. In order to ensure SNTP time synchronization is normal, one
SNTP server must be set, it is suggested that one server can be set at one
substation. SNTP time synchronization accuracy is 1ms for binary inputs.
The IED itself can be set as a SNTP time synchronization server.
3.6 1588 synchronization mode

It supports IEEE1588 high precision network synchronization.
4 Authorization
To safeguard the interests of customers, accesses to the IED and the
debugging software are restricted in terms of authorization. In practice,
attention should be paid to the following aspects in the use of the IED and
associated debugging software:
1) There are two types of access to the IED:
a) Local, through the local HMI
b) Remote, through the communication ports
2) Different users have different authority to access to or operate device
or test the software
13
Chapter 3 Chapter 1Fault phase selection component
Chapter 3 Fault phase selection

component
About this chapter

This chapter describes the basic protection element, fault
phase selection component.
15
1 Overview
The fault phase selector component can distinguish the fault phase, and
make use of various phase selection principles to judge the different fault
conditions, so as to meet the requirements of trip phase selection.
The fault uses steady-status sequence component to judge the phase, for
power supply, terminal fault small current or no current, the low voltage
phase selector is used to judge the phase.
Phase selection function can be blocked by external binary input, VT
failure and CT failure.
2 Function module description

The I/O signals described herein only reflect the visible engineering part.
The input and output signals of fault phase selection module function are
shown as follows:
Faulty Phase Selection

1 1
BIBlk FaultPhase
2 2
VTFailBlk FaultA
3 3
CTFailBlk FaultB
4
FaultC
Figure 5 Input and output signal diagram of fault phase selector component function
Table 8 Parameter description
No. Key Unit Type Description
Input:
BIBlk BOOL BI blocking BO
VTFailBlk BOOL VT failure blocking signs
CTFailBlk BOOL CT failure blocking sign
Output:
FaultPhase SINT Fault phase

FaultA BOOL Phase A fault
FaultB BOOL Fault of phase B
FaultC BOOL Phase C fault
3 Detailed description
3.1 Protection principle
3.1.1 Steady state component phase selector
The steady status component phase selector selects the phase through
the angle between zero sequence current component and negative
sequence current components, and the phase impedance is used to
confirm whether the phase selection is correct.
16
The analysis shows that the angle between the zero sequence current
component and negative sequence current component of the fault current
can be used to select the fault phase, the analysis is shown in the following
figure:
I0a
0 0
+30 AN,BCN -30
ABN BCN
0 0
+90 -90
CN,ABN BN,CAN
0 0
+150 CAN -150
Figure 6 Relationship diagram between zero sequence current component and

negative sequence current component angle of various faults
Table 9 Steady status component phase selector table
Phase area Angle range Phase selection results
1 +30°~-30° AN or BCN
2 +90°~ +30° ABN
3 +150°~ +90° CN or ABN
4 -150°~ +150° CAN
5 -90°~ -150° BN or CAN
6 -30°~ -90° BCN
For example, the angle between the negative sequence component and
the zero sequence components is between -30 degrees and +30 degrees,
and the fault type is A phase grounding or fault between phase B and C or
grounding fault between phase B and C.
As shown in the table above, area 2, 4, and 6 directly reflect the relative
fault type, but area 1, 3, and 5 may reflect the existence of two types of
fault, at this point, it is distinguished through phase impedance calculation.
If the phase impedance is larger than that of the phase impedance setting
value, the possibility of phase fault is eliminated, and it is judged to the
corresponding single-phase grounding fault, or it is judged to the
corresponding phase fault.
3.1.2 Undervoltage phase selection component
The steady status component phase selector is not reliable in the weak
feedback system, and the low voltage phase selector is applied to the
weak feedback system.
Discriminant formula for single phase fault and interphase fault is as
follows:
Upe<k×Upe_Secondary
or
Upp <k×Upp_Secondary
17
Where:
1) Upe and Upp are phase-to-earth voltage and phase-to-phase voltage
respectively
2) U_Secondary is system secondary rated voltage value
3) k is internal coefficient
For example, if only A phase voltage is low, it is judged to be A phase fault;
if only the AB phase-to-earth voltage is low, it is judged to be AB phase
fault; if AB, BC and CA phase-to-earth voltage are all low, then it is judged
to be three-phase fault.
18
Chapter 4 Basic protection component
Chapter 4 Basic protection

component
About this chapter

This chapter describes basic protection elements including
startup elements and directional elements.
19
Chapter 4 Basic protection component
1 Startup component
1.1 Overview
Startup component is used to detect faults in power system and initiate
related programs to selectively remove faults. The main startup elements
of CSC-326 are abrupt-change current component and differential startup
component.
Startup element includes:
1) Current sudden-change startup element;
2) Differential current startup component.
1.2 Current sudden-change startup element

The abrupt-change current component is main startup component, it can
detect sensitively most faults. Criteria are as follows:
∆iϕ > I _ startup


∆i=
ϕ iϕ (t ) − 2 ∗ iϕ (t − T ) + iϕ (t − 2T )
Equation1
Where:
I_startup is fixed threshold value (when secondary value of CT is 1A,
I_startup=0.2A; when secondary value of CT is 5A, I_startup =1A).
1.3 Differential current startup component

 I dϕ max > I _ diff startup

= I dϕ max Max = I dϕ ,ϕ a, b, c Equation2

 I _ diff startup = 0.8 I _ percent diff
Where:
I_diff startup is differential protection startup threshold, I_Percent Diff is
differential protection value, Idφ is phase differential current.
2 Report
Table 10 Report list
Report Description
IED startup IED startup
20
Chapter 5 Differential protection(87T)
Chapter 5 Differential protection

(87T)
About this chapter

This chapter describes the protection principle, input and
output signals, parameter, IED report and technical data for
differential protection function.
21
Chapter 5 Differential protection (87T)
1 Overview
The numerical current differential protection represents the main protection
function of the IED. It provides a fast short-circuit protection for power
transformers. The protected zone is selectively limited by the CTs at its
ends. The device is able to perform this function on 2 or 3 winding
transformers in a variety of voltage levels and protected object types.
The IED provides numerical differential protection function which can be
used to protect power transformers in various configurations. For example,
it is possible to use it for a two-winding transformer, three-winding
transformer as well as auto-transformer. Examples for some of
applications are illustrated in the below figure.
High voltage side Low voltage side

I A.1 Ia.2
A a
I B.1 Ib .2
B b
I C .1 Ic .2
C c
CSC-326
Figure 7 Application of differential protection on a two-winding Yd transformer

I A.1
A Ia.2
a
IB.1
Ib .2
B
b
IC .1
C Ic .2
c
CSC-326
Figure 8 Application of differential protection on a two-winding Yd transformer
22
High voltage side Low voltage side

I A.1 Ia.2
A a
IB.1 Ib .2
B b
IC .1 Ic .2
C c
CSC-326
Figure 9 Application of differential protection on a two-winding Yd transformer with

earthing transformer inside the protected zone
Middle voltage side

Ia.2
a
Ib .2
b
High voltage side Ic .2
I A.1 c
A
I B.1
B
I C .1 Low voltage side
C Ia.3
a
Ib .3
b
Ic .3
c
CSC-326
Figure 10 Application of differential protection on a three-winding Ydd transformer

The input and output signals of differential protection function diagram is
shown below, left side is input and right side is output:
23
DiffTripBO
1 1
BIBlk PerDiffATrip
2
PerDiffBTrip
3
PerDiffCTrip
4
InstDiffATrip
5
InstDiffBTrip
6
InstDiffCTrip
7
CT_Fail
8
Diff_Alm
Figure 11 Transformer differential protection module

Function Identifier Description
Input:
BIBlk BIBlk
Output:
PerDiffATrip Differential phase A trip
PerDiffBTrip Differential phase B trip
DiffTripBO PerDiffCTrip Differential phase C trip
InstDiffATrip Instantaneous differential phase A trip
InstDiffBTrip Instantaneous differential phase B trip
InstDiffCTrip Instantaneous differential phase C trip
CT_Fail CT failure
Diff_Alm Differential current over limit alarm
3 Protection principle
This section describes basic principle of differential protection function.
First, the case of a single phase transformer with two windings is
considered. The basic principle is based on current comparison at two
sides of the protected object. Indeed, the differential protection function
makes use of the fact that a protected object carries always the same
current at its two sides in healthy operation condition. This current flows
into one side of the protected object and leaves it from the other side. A
difference in currents is an indication of a fault within this section. An
example of this condition is shown in below figure, when a fault inside the
protected zone causes a current I1prim. + I2prim flowing in from both sides
of the protected object.
24
IED area
I1-prim. I2-prim.
CT-1 CT-2
Protected
transformer
I1 I2
CSC-326
Figure 12 Basic principle of differential protection for two ends (single phase)
For protected objects with three or more sides, the basic principle is
expanded in that the total of all currents flowing into the protected object is
zero in healthy operation, whereas in case of a fault the total in-flowing
current is equal to the fault current.
When an external fault causes a heavy current to flow through the
protected transformer, differences in the magnetic characteristics of the
current transformers CT-1 and CT-2 under saturation condition may cause
a significant difference in the secondary currents I1+I2 connected to IED. If
the difference is greater than the pickup threshold, the differential
protection function can trip even though no fault occurred in the protected
zone. To prevent the protection function from such erroneous operation, a
restraint (stabilizing) current is brought in. For differential protection IED,
the restraint current is normally derived from the I1 and I2. The next
subsection goes on to demonstrate how the differential and restraint
currents are calculated.
3.1 Differential and restraint current calculation

The differential current Idiff and the restraining current Ires are calculated
by the following equation. The following definitions apply for each phase of
the protected object.
 N •
 I diff =

∑ i =1
Ii
 N −1 •
 1 •
 I res = 2 I j (max) −

∑
i =1
I i (i ≠ j )
Ii Where is the current vector of side i, corresponding to HV, MV and LV

windings; N is total current inputs of the IED. In other words, it is number of
the protected object sides; I j (max) is the maximum current vector among
N −1 •
the N current inputs of the IED, suppose it is side j; ∑ I i (i≠ j ) is the sum of
i =1
the other current inputs of the IED, not including side j. Idiff is derived from
the fundamental frequency current and used for the judgment of the
tripping effect, while Ires is used for the judgment of the restraining effect.
To clarify the situation, three important operating conditions with ideal and
matched measurement qualities are examined.
1) External fault:
25
I1 flows into the protected zone,I2 leaves the protected zone, i.e. I2 = –I1.
Idiff = I1 + I2 = I1 – I1 = 0
Ires = 0.5×| I1 - (–I1) | = 0.5×|2I1| = |I1|
No tripping effect (Idiff = 0); the restraint (Ires) corresponds to the external
fault current flowing through the protected object.
2) Internal fault, fed with equal currents from both sides:
that isI2 = I1
Idiff = I1 + I2 = I1 + I1 = 2 I1
Ires = 0.5×| I1 - I1| = 0
Tripping effect (Idiff) corresponds to double the fault current, and restraint
value (Ires) are equal to zero.
3) Internal fault, fed from one side only:
supposeI2 = 0
Idiff = I1 + I2 = I1 + 0 = I1
Ires = 0.5×|I1 - I2| =0.5× |I1 - 0| = 0.5×|I1|=0.5 I1
Tripping quantity (Idiff) and restraint quantity (Ires) are equal and
correspond to the single-sided fault current.
The results show that the device is capable to properly discriminate
internal and external faults by using the definitions proposed for differential
and restraint current. However, the device is still subjected to some
influences that induce differential currents even during normal operation
condition. These influences should be compensated in appropriate
manners. The specific treatments designed to cope with these influences
includes automatic ratio compensation and automatic vector group
compensation which are explored in the next subsections.
3.2 Automatic Ratio compensation

Differential protection of power transformers represents some problems in
the application of current transformers. CTs should be matched to the
current rating of each transformer winding, so that normal current through
the power transformer is equal on the secondary side of the CT on different
windings. However, because only standard CT ratios are available, this
matching may not be exact. As a result, the secondary currents of the
current transformers are not generally equal when a current flows through
the power transformer. The difference between the currents flowing
through CTs’ secondary circuit depends on the transformation ratio of the
protected power transformer, as well as the rated currents of the current
transformers. Therefore, the currents should be matched in order to
become comparable. To do so, the input currents of the IED are converted
in relation to the power transformer rated currents. This is achieved by
entering the characteristic values of the power transformer (i.e. rated
apparent power and rated voltages) and primary rated currents of CTs into
the IED by using user-entered settings. As a result, matching to various
power transformer and current transformer ratios is performed purely
mathematically inside the device. Therefore, no external matching
transformer is required. In this context, the rated primary current of each
side I1N can be calculated automatically by the following equation.
26
SN
I 1N =
3U 1N
Where SN is rated apparent power of the transformer and U1N is rated

voltage of the corresponding side.
The rated secondary current of each side I2N can be calculated by the
following equation:
I1N
I 2N =
nCT
Rated secondary current of the high voltage side is then taken as the
reference current. The currents of the other sides are automatically
matched to the rated current of the high voltage side by calculation of
correction factor KCT for MV and LV side, according to below equations,
respectively:
I 2 N − HV I 1N − HV / nCT − HV S N / 3U 1N − HV nCT − MV U 1N − MV nCT − MV
K CT − MV = = = ⋅ = ⋅
I 2 N − MV I 1N − MV / nCT − MV S N / 3U 1N − MV nCT − HV U 1N − HV nCT − HV
I 2 N − HV I 1N − HV / nCT − HV S N / 3U 1N − HV nCT − LV U 1N − LV nCT − LV
K CT − LV = = = ⋅ = ⋅
I 2 N − LV I 1N − LV / nCT − LV S N / 3U 1N − LV nCT − HV U 1N − HV nCT − HV
Where, KCT-MV is the correction coefficient on the medium voltage side

and KCT-LV is the correction coefficient on the low voltage side.
I1N is the rated primary current of the transformer (I1N-HV is the primary
current of the high voltage side, I1N-MV is the primary current of the
medium voltage side and I1N-LV is the primary current of the low voltage
side).
I2N is the rated secondary current of the transformer (I2N-HV is the
secondary current of the high voltage side, I2N-MV is the secondary
current of the medium voltage side, I2N-LV is the secondary current of the
low voltage side).
nCT is CT ratio of the transformer (nCT-HV is the ratio of the high voltage
side, nCT-MV is of the medium voltage side, nCT-LV is of the low voltage
side).
U1N is rated voltage of the transformer (U1N-HV is the rated voltage of the
high voltage side, U1N-MV is of the medium voltage side, U1N-LV is of the
low voltage side).
As mentioned previously, all of the calculations are automatically
per-formed inside the IED by its CPU. The related settings can be found
under the menu “Test Menu”.
Below figure shows an example of automatic ratio compensation in case of
a two-winding transformer. The rated currents of the high voltage and low
voltage sides, (I1N = 402A, I2N= 1466A) are calculated by the rated
apparent power(160MVA) of the transformer and the rated voltage (230kV
and 63kV) of each side. Since the rated currents of CT is based on the
rated current of transformers, the secondary current of low voltage side
shall be multiplied by the correction coefficient KCT-LV. Subsequent to this
matching, equal current magnitudes are achieved at both sides under
nominal conditions of the power transformer.
27
SN=160MVA
U1N-HV=230kV U1N-LV=63kV
CTRATIO=500/1A CTRATIO=2000/1A
Figure 13 Example of automatic ratio compensation in a three-winding transformer
160 MVA
=
I1N − HV = 402 A
3 × 230
I 1N − HV 402
I 2 N − HV = = = 0.804 A
nCT 500
160 MVA
I 1N − LV = = 1466 A
3 × 63
1466
I 2 N − LV = = 0.733 A
2000
0.804
K CT −LV = = 1.097
0.733
Concerning three-winding power transformers, the windings may have

different power ratings. In order to compare secondary currents in an
appropriate manner, all currents are matched to the rated secondary
current of HV winding having highest power rating. This apparent power is
nominated as the rated apparent power of the transformer.
Below figure shows an example of a three-winding power transformer. HV
winding and MV winding are rated for 160MVA. The rated primary and
secondary currents of these windings are calculated as shown in previous
example. However, the LV winding has 25MVA rating (e.g. for auxiliary
supply). The rated current of this winding may result in 721A. However,
differential protection has to process comparable currents. Therefore, the
currents of LV winding should be referred to the rated apparent power of
the transformer, i.e. 160MVA. This results in a rated current of 4619A. This
is the base value of the low voltage side current, which should be
multiplied by the correction coefficient KCT-LV to calculate the differential
protection.
160MVA 160MVA
U1N-HV=230kV U1N-MV=63kV
CTRATIO=500/1A CTRATIO=2000/1A
U1N-LV=20kV 25MVA
CTRATIO=2500/1A
Figure 14 Example of automatic ratio compensation in a three-winding transformer

160MVA
I 1N − LV = = 4619 A
3 × 20
28
I 1N − LV 4619
I 2N − LV = = = 1.848A
nCT 2500
0.804
K CT −LV = = 0.435
1.848
3.3 Automatic Vector group and zero sequence

current compensation
Transformers have different vector groups, which cause a shift of the
phase angles between the primary and the secondary side. Without
ad-equate correction, this phase shift would cause a false differential
current. Furthermore, the conditioning of the starpoint(s) of the power
transformer has a great impact on the resulting differential current during
through fault currents.
The IED removes this problem. To do so, all CTs at the power transformer
are connected Wye (polarity markings pointing away from the transformer).
User-entered settings in the relay are then used to characterize the power
transformer and allow the relay to automatically per-form all necessary
phase angles, and zero sequence compensation. This section describes
the procedures that perform this compensation inside the relay and
produce the required calculated quantities for transformer differential
protection. The phase angle compensation as well as zero sequence
current elimination procedure is performed by programmed coefficient
matrices which are capable to simulate the difference in phase angle of
currents flowing through transformer windings. Thus, compensation is
possible for the entire commonly used transformer vector groups. This
simplifies application of the IED in various configurations, if the setting
corresponding to vector Group Angle, “Vet Grp Angle”, is properly entered
into the device, together with the settings for connection type of
transformer windings in each side, “HVSideConnectMode/Y-0 D-1”,
“MVSideVectorGrp/Y-0 D-1”, LVSideVectorGrp/Y-0 D-1”, which could be
set to 1-delta or 0-wye. The basic principle of numerical vector group and
zero-sequence compensation is shown through some examples. A through
review of all possible connection groups as well as device treatment in
each case is explored in Appendix.
1) Take example for Yy0 connection, including similar ones of Yy0
(separate or auto-connected windings), YNy0, Yyn0, YNyn0 (separate
or auto-connected windings) and so on. Below figure shows an
example in case of Yy0 connection group with no earthed starpoint.
The figure shows the windings (left) and the vector diagrams of
symmetrical currents (right).
29
A B C
Yy0 c b
C B
a b c
Figure 15 Vector Group and zero sequence compensation for Yy0 transformer
The equations including the coefficient matrix are as follow:
 IA′  1 -1 0   IA 
  1   
 I B′  = ⋅ 0 1 -1 ⋅  IB 
 I′  3
-1 0 1   IC 
 C  
 Ia′  1 -1 0   Ia 
  1   
 I b′  =⋅ 0 1 -1 ⋅  Ib 
 I′  3 
 -1 0 1   Ic 
 c  
According to these matrices, if we deduct side one currents IA − IB , the
resulting current IA′ has the same direction as IA′ on side two.
Multiplying it with 1 3 , matches the absolute value. The matrices
describe the con-version for all three phases. Using these matrices, the
elimination of zero sequence currents are warranted regardless of starpoint
earth connection.
As mentioned previously, the two above equations can be used similarly
for auto-transformers, as the auto-connected windings in
auto-transformers can only be connected Y(N)y(n)0. If the starpoint is
earthed, both the auto-connected HV and LV windings are affected. The
zero sequence components in current flowing through both sides of the
transformer are then coupled because of the common starpoint. These
zero sequence components are eliminated by the application of the
matrices presented in the above equations.
2) Take example for Yd1 connection, including similar ones of Yd1 and
YNd1 without earthing transformer installed at delta side. Below figure
shows an example in case of Yd1 connection group with no earthed
starpoint.
30
A B C
A
a
Yd1 c
C b B
a b c
Figure 16 Vector Group compensation for Yd1 transformer

The equation including the coefficient matrix is as follows:
 IA′  1 0 -1  IA 
  1   
 I B′  = ⋅ -1 1 0  ⋅  IB 
 I′  3
0 -1 1   IC 
 C  
If an earthing transformer/reactor is installed inside the protected zone on
delta side, the IED should be informed about it by logic switch
“HVSideDeltaMinus3I0”, “MVSideDeltaMinus3I0” or
“LVSideDeltaMinus3I0”. By taking example for Yd1 connection with
earthing transformer installed at delta side, logic switch
“LVSideDeltaMinus3I0” is enabled, and thus, device performs a zero
sequence current elimination on delta side. In this case, the equations
including the coefficient matrices are as follow:
 IA′  1 0 -1  IA 
  1   
 I B′  = ⋅ -1 1 0  ⋅  IB 
 I′  3 
0 -1 1   IC 
 C  
 •′  •
I I
 a  2 − 1 − 1  a 
•  1   • 
 I ′b  = .− 1 2 − 1. I b 
 •  3 − 1 − 1 2   • 
 I ′c    I c 
   
3) Take example for Ydd3 connection, including similar ones of Ydd3 and
YNdd3 without earthing transformer installed at delta sides. Below
figure shows an example in case of Ydd3 connection group with no
earthed starpoint in Wye side.
31
A B C
A
c(c’)
Ydd3 a(a’)
C b(b’) B
c a b c' a' b'
Figure 17 Vector Group compensation for Ydd3 transformer

 IA′  0 1 -1  IA 
  1   
 I B′  = ⋅ -1 0 1  ⋅  IB 
 I′  3 
1 -1 0   IC 
 C  
4) Take example for Yd5 connection, including similar ones of Yd5 and
YNd5 with earthing transformer installed at delta side. Below figure
shows an example in case of Yd5 connection group with no earthed
starpoint.
A B C
A
c
Yd5 b
a
C B
c a b
Figure 18 Vector Group compensation for Yd5 transformer

By setting logic switch “LVSideDeltaMinus3I0”, the equations including the
coefficient matrices are as follow:
 IA′  -1 1 0   IA 
  1   
 I B′  = ⋅ 0 -1 1  ⋅  IB 
 I′  3
1 0 -1  IC 
 C  
32
 •′  •
Ia  I
 2 − 1 − 1  a 
  1
•
′ = − − . I• 
 
I b . 1 2 1  b
 •  3 − 1 − 1 2   • 
 I ′c    I c 
   
5) Take example for Dy1 connection, including similar ones of Dy1 and
Dyn1 without earthing transformer installed at delta side. Below figure
shows an example in case of Dy1 connection group with no earthed
starpoint.
A B C
Dy1 c
b
C B
a b c
Figure 19 Vector Group compensation for Dy1 transformer

 Ia′  1 -1 0   Ia 
  1   
 I b′  = ⋅ 0 1 -1 ⋅  Ib 
 I′  3 
-1 0 1   Ic 
 c  
If an earthing transformer/reactor is installed inside the protected zone on
delta side, logic switch “LVSideDeltaMinus3I0” is enabled, and thus,
device performs a zero sequence current elimination on delta side. In this
case, the equations including the coefficient matrices are as follow:
 •′  • 
I I
  A
 2 − 1 − 1  A 
•  1   • 

 I ′ B  = .− 1 2 − 1. I B 
 •  3 − 1 − 1 2   • 
 I ′C    I C 
   
 Ia′  1 -1 0   Ia 
  1   
 I b′  =⋅ 0 1 -1 ⋅  Ib 
 I′  3 
-1 0 1   Ic 
 c  
Subsequent to application of the magnitude, vector group and zero
sequence compensation, the IED use the following calculated quantities
(per phase) to discriminate between internal and external faults:
fundamental component of differential and restraint currents together with
instantaneous value, second and 5th harmonic contents of differential
current. The following sections go on to demonstrate the fault recognition
criteria using these derived quantities.
33
3.4 Instantaneous differential protection

characteristic
An instantaneous (unrestrained) differential characteristic which entails an
overcurrent protection is provided for fast tripping on heavy internal faults.
The function can be enabled or disabled by using logic switch
“InstantaneousDiffOn” and “DiffOn” (1-on, 0-off).
If “InstantaneousDiffOn”and “DiffOn” are setted as “1-on”, regardless of the
magnitude of the restraining current, a trip signal will be issued as soon as
the differential current exceeds the threshold ID> (setting "
InstantDiffCurrSet"). The signal is phase splitting trip. And the device will
issue trip reports “InstantDiffPhATrip”, “InstantDiffPhBTrip” or
“InstantDiffPhCTrip” when the calculated differential current in phase A, B
or C exceeds the threshold ID> (setting "InstantDiffCurrentSetting"). The
purpose of this stage of differential protection is extremely fast operation in
case of high magnitude internal fault currents. When the short-circuit
current is higher than IN/Uk%, a fault may occur in the transformer. It
should be noted that the flowing fault current shall be lower than IN/Uk%.
(IN is rated current and UK% is short-circuit voltage of the transformer.)
The logic diagram of instantaneous differential protection is shown in
below figure.
“DiffOn”=1
&
“InstantaneousDiffOn”=1
&
Instantaneous differential
phase A output
IDA>“InstantDiffCurrSet”
&
phase B output
IDB> “InstantDiffCurrSet”
&
phase C output
IDC> “InstantDiffCurrSet”
Figure 20 Tripping logic of the instantaneous differential protection

As mentioned previously and can be seen from the figure, the stage
operates as an unrestrained protection function. In other words, it is not
inhibited by any of harmonic stabilization features of the percent differential
element as well as the CT failure detection. This means that it can operate
even when, for example, a considerable second harmonic is present in the
differential current, which is caused by current transformer saturation by a
DC component in the fault current, and which could be interpreted by the
inrush inhibit function as an inrush current.
This high current stage evaluates the fundamental component of the
differential current as well as the instantaneous values. Instantaneous
value processing ensures fast tripping even in case the fundamental
component of the current is strongly reduced by current transformer
saturation. Fast trip is shown in Figure 16.
34
3.5 Treble slope percent differential protection

characteristic
The percent differential protection uses a treble-slope dual break-point
operating characteristic with magnetizing inrush and overexcitation and CT
failure detection inhibits integrated. The treble slope characteristics can be
enabled or disabled by using logic switch “DiffOn” (1-on, 0-off). If setting
1-on is selected, the stage calculates differential and restraint current
separately in each phase to obtain operating point in each operation
condition. Then the operating point is mapped into Idiff-Ires plane to
examine whether it lies in trip or block area which is defined according to
predefined operating characteristic. The operation characteristic is shown
in below figure.
1 differential Instantaneous
differential trip
Instantaneous area
differential current
Differential currrent
Slope 3
Trip area
Slope 2 Restraint
Slope 1 area
Differential 1 restranit
startup
1 restraint break point 1 1 restraint break point 2 Restraint current
Figure 21 Differential protection characteristics for transformers

In this characteristic, branch 1 represents the sensitivity threshold of the
differential protection. The setting of ID>(the setting is "DiffStartupSet")
defines the minimum differential current required for operation. The setting
is chosen based on the amount of differential current that might be seen
under normal operating conditions which corresponds to constant error
currents such as magnetizing currents and CT errors under no-load
conditions. The setting for slope of branch 1 is applicable for restraint
currents of zero to the first break-point indicated on restraint axis (the
setting is "BreakPoint1CurrSet"). The slope 1(the setting is
“Slope1RatioRestrCoef”) is the ratio of differential current to restraint
current above which is the percent differential protection trip area. The first
break-point on restraint axis defines the end of the slope 1 region and the
start of the second branch region. This setting should be set just above the
maximum operating current level of the transformer. This level is
somewhere between the maximum forced-cooled rated current of the
transformer and the maximum emergency overload current level.
Slope 2 considers current-proportional errors which may result from
transformation errors of the main CTs or the input CTs of the relay. This
may also contain the error caused by the influence of tap changers in
power transformers with voltage control. The setting for slope of branch 2
(the setting is” Slope2RatioRestrCoef”) is applicable for restraint currents
of the first break-point to the second one on restraint axis, and defines the
ratio of differential to restraint current above which the element will operate.
35
This slope is set to ensure sensitivity to internal faults at normal operating

current levels. This setting should be set to the level at which any of the
protection CTs is probable to saturate. The second break-point on restraint
axis (setting “I_ResPoint2 Diff”) defines the end of the slope 2 region and
the beginning of the slope 3 region. This setting should be set to the level
at which any of the protection CTs is probable to saturate.
In the range of high through fault currents which may give rise to high
differential currents as a result of CT saturation, branch 3 is applicable to
provide additional stabilization. The setting for the slope 3 (the setting is
“Slope3RatioRestrCoef”) is applicable up to the point at which the branch
intersects the characteristic of instantaneous differential protection.
As a summary of the fault detection using operating characteristics of the
above figure, the calculated differential and restraint currents, IDiff and
IRest, are compared by the differential protection with the operating
characteristic according to the following formula ,
I diff ≥ S1I res + I D > I res ≤ I R1 


I diff ≥ S2 ( I res − I R1 ) + S1 × I R1 + I D > I R1 < I res ≤ I R 2 

I diff ≥ S3 ( I res − I R 2 ) + S2 ( I R 2 − I R1 ) + S1 × I R1 + I D > I R 2 < I res 
Where, S1 is Slope 1 (the setting is "Slope1RatioRestrCoef");
S2 is Slope 2 (the setting is "Slope2RatioRestrCoef");
S3 is Slope 3 (the setting is "Slope3RatioRestrCoef");
ID> is the threshold value of the differential protection sensitivity (the
setting is “DiffStartupSet”);
IR1 is the first break point setting of restricted current
“BreakPoint1CurrSet”;
IR2 is the second break point setting of restricted current
“BreakPoint2CurrSet t”.
If the operating point calculated from the quantities of differential and
restraint current falls into the trip area, a trip signal is issued by the percent
differential protection. The issued signals are phase selective. They can be
found in event report as “DiffPhATrip”, “DiffPhBTrip” and “DiffPhCTrip”.
This stage cannot operate when there is an inrush or over-excitation
stabilization or a restraint due to CT failure detection. This is illustrated in
below logic diagram.
36
“DiffOn”=1
Phase A
I diff − A , I rest − A Ratio differential
ID>
& Phase A output
Ratio differential
blocking Phase A
Phase B
I diff − B , I rest − B
ID>
Ratio differential
& Phase B output
Ratio differential
blocking Phase B
Phase C
I diff −C , I rest −C
ID>
Ratio differential
& Phase C output
Ratio differential
blocking Phase C
“CTFailBlkDiff”=1
&
CT failure
Figure 22 Tripping logic of the percent differential protection

It should be noted that when the IED is delivered, both the instantaneous
and percent differential protection functions are switched off. Setting of
“0-off” is applied for logic switch “InstantaneousDiffOn” and “DiffOn”. This
is because the fact that these protection functions should not be used
before at least the vector group and other essential parameters for each
side is correctly set. Without these settings the equipment may show
unpredictable behavior. (E.g. tripping)
3.5.1 Excitation inrush current blocking principle

1) Second harmonic blocking principle
By selecting “1-Block” for control-word “ExcitInrushBlkDiff” and selecting
“1-second harmonic” for logic switch “2ndHRestr”, inrush current is
recognized if the second harmonic content in the differential current
exceeds a selectable threshold. The ratio between the second harmonic
and the fundamental frequency component is decisive to discriminate
inrush conditions from the other operation conditions. The ratio is
calculated by the below equation. As soon as the measured ratio exceeds
the set thresholds, a restraint is applied to the percent differential
protection in respective phase.
I diφφ −φ 2
> Kϕ 2
I diφφ −φ
Where, Idiff-φ2 is the secondary harmonic magnitude of differential current,

Kφ2 is the setting of the secondary harmonic ratio, Idiff-φ is fundamental
wave component of differential current.
2) Fuzzy recognition blocking principle
37
By selecting “1-block” in control-word “ExcitInrushBlkDiff”, and selecting

“0-waveform on” for logic switch “2ndHRestr”, inrush current is detected by
a fuzzy recognition method based on waveform. In this context, differential
current waveform is sampled in each phase by 2n number of samples per
cycle, each of the samples is nominated as I(k), k=1, 2, …, 2n. X(k) is
obtained by the calculation according to the following equation.
I ( k ) + I ( k + n)
X (k ) = , k = 1,2,..., n
I ( k ) + I ( k + n)
Equation3
The smaller values of X(k) represent that the calculated point corresponds
to fault condition with higher confidence level. Alternatively, the larger
values of X(k) gives a picture that there is large content of inrush current in
the waveform. Assume that X(k) belongs to “inrush Fuzzy class” with
membership function of A[X(k)]. Then, the fuzzy similarity coefficient for
the n calculated values of X(k) in one cycle is defined as below equation.
n
N= ∑ A[ X (k )] / n
k =1
Equation4
The derived value of N is used in the IED to assess the differential current
corresponds to inrush condition or not. To do so, the value of N is
compared with a threshold K, and inrush content is recognized in the
current waveform, if N>K.
“DiφφOn”=1
“ExcitInrushBlkDiφφ”=1 &
&
“2ndHRestr”=1 ≥1
T
I diφφ − A−φ 2
> Kϕ 2
I diφφ − A−φ
&
T 2ndHBlkDiφφ
≥1 ≥1
I diφφ − B −φ 2
> Kϕ 2
I diφφ − B −φ
≥1
I diφφ −C −φ 2 &
> Kϕ 2
I diφφ −C −φ T
Kφ 2 ：“2ndHRestrCoeφ” T：“2ndHCrossBlkTime”
Figure 23 Logic diagram of excitation inrush detected by using the secondary harmonic
mode
38
“DiffOn”=1
“ExcitInrushBlkDiff”=1 &
&
“2ndHRestr”=0 ≥1
T
Phase A Fuzzy Recognition
&
≥1 2ndHBlkDiff
T
≥1
Phase B Fuzzy Recognition
≥1
&
Phase C Fuzzy Recognition
T
T：“2ndHCrossBlkTime”
Figure 24 Logic diagram of excitation inrush detected by using fuzzy recognition mode
3.5.2 Overexcitation stabilization

Apart from the second harmonic, other harmonic contents can be selected
in the IED to cause stabilization of percent differential protection. This is
because the fact that unwanted differential currents caused by transformer
overexcitation may result in false tripping of the percent differential
protection. Since steady state overexcitation is characterized by odd
harmonics, the third or the fifth harmonic can be selected in the IED to
judge for overexcitation stabilization. If it is desired to impose a blocking
condition to percent differential protection by these harmonics, logic switch
“OEBlkDiff” should be set to “1-on”. By applying this setting, alarm report
entitled “3rd/5thHBlkDiff” is issued whenever third or fifth harmonic
detection impose a blocking condition to differential protection.
It is possible to use logic switch “OE5thHOn” to select whether 3rd or 5th
harmonic detection is utilized for detection of overexcitation condition
(1-5th harmonic, 0-3rd harmonic). It is, however, possible to set the
protection in a way that when any phase detects the third or fifth harmonic
not only the phase with the inrush current, but also the remaining phases
of the percent differential protection are blocked. This is achieved by
cross-blocking the differential protection for a certain period to avoid
spurious tripping. The setting corresponds to "3rd/5thHBlkTime". Within
this time, all three phases are blocked as soon as an 3rd or 5th harmonic is
detected in any one phase. After the timer is expired, only the phase with
3rd or 5th harmonic content is blocked.
The detection method used for 3rd or 5th harmonic is similar to those
applied for 2nd harmonic. However, setting “3rd/5thHRestrCoef” is
decisive in this case. It means that 3rd or 5th harmonic is recognized if the
ratio between third or fifth harmonic and the fundamental frequency
component of the differential current exceeds the setting threshold. The
ratio is calculated by the below equation.
I diφφ −φ 3 / 5
> Kϕ 3 / 5
I diφφ −φ
Equation5
Where, Idiff-φ3/5 is the 3rd/5th harmonic magnitude of differential current,

Kφ3/5 is the setting of the 3rd/5th harmonic ratio, Idiff-φ is fundamental
39
wave component of differential current. Below figure shows logic diagram

of overexcitation stabilization.
“OEBlkDiff”=1
“OE5thHOn”=1
“OE5thHOn”=0
I diff − A−f 3
> K ϕ −3 / 5
I diff − A−f &
&
I diff − A−f 5 ≥1
> K ϕ −3 / 5
T
T
≥1
I diff − A−f
&
I diff − B −f 3 &
> K ϕ −3 / 5 &
≥1
T
I diff − B −f T
≥1 ≥1 3rd/5thHBlkDiff
I diff − B −f 5 &
> K ϕ −3 / 5
I diff − B −f
≥1
& T
T
I diff −C −f 3 &
> K ϕ −3 / 5
I diff −C −f
≥1
I diff −C −f 5
> K ϕ −3 / 5 &
I diff −C −f
Kf −3/5 3rd/5thHBlkCoef
T：3rd/5thHBlkTime
Figure 25 Logic diagram of excitation characteristics
3.6 CT failure supervision

During steady-state operation, the CT failure supervision monitors the
transient behavior of the currents flowing through secondary circuit of each
phase and thus registers failures in the secondary circuit of the current
transformers for each side of the power transformer. The function can be
enabled or disabled by using setting “CTFailDetectOn” (1-On, 0-Off). If
setting “1-On” is applied whenever a CT failure is detected, IED issues the
alarm report. The differential protection can be configured as whether the
blocking is through CT failure by the logic switch "CTFailBlkDiff". By setting
blocking through the logic switch, the percent differential protection is
blocked immediately in all phases when CT failure occurs. Blocking
condition is cancelled as soon as the device is again supplied with a
normal current in the relevant faulty phase(s). It should be noted that this
logic switch is not useful if the differential current is very high (more than
1.2 Ie, Ie is the rated current of high voltage side). In other words, blocking
conditions takes place only for treble slope percent differential protection.
This means that the instantaneous differential protection will issue trip if a
differential current is greater than “InstantDiffCurrSet”, even if even if the
differential protection is blocked by CT.
The criteria for CT failure check are as follow:
The currents flowing through all three phases of CT secondary are normal
at each side of the protected object. As a result, the differential current is
near to zero. When one or two phase current of one side is decreased to
less than a threshold (half of the memory current), at the same time all
three phase currents in other side(s) are normal, and at least one phase
40
current is larger than a threshold (>0.3I_Percent Diff), the condition maybe

an indication of CT failure. CT failure check logic is illustrated in below
figure.
CT Failure Function On
Max {Idiff_A, Idiff_B,

Idiff_C}>0.3*“DiffStartupSet”
In {IHV_A, IHV_B, IHV_C}, only one or two

phase reduce.
&
{IMV_A, IMV_B, IMV_C}和 {ILV_A, ILV_B,
ILV_C} All current is unchanged
CT Failure
In {IMV_A, IMV_B, IMV_C}, only one or
two phase reduce. &
≥
& 1
{IHV_A, IHV_B, IHV_C} 和 {ILV_A,
ILV_B, ILV_C} All current is
unchanged
In {ILV_A, ILV_B, ILV_C}, only one or two

phase reduce.
&
{IHV_A, IHV_B, IHV_C} 和 {IMV_A, IMV_B,
IMV_C} All current is unchanged
Figure 26 Logic diagram of CT failure supervision
3.7 CT Saturation supervision

When Internal and external faults occurs, it is possible that transient and
steady fault currents induce the CT saturation. CT saturation may lead to
mal-operation of differential protection when an external fault occurs. In
order to avoid mal-operation of protection in such situations, CT saturation
supervision element is integrated in IED.
When transient saturation of CT occurs, the second harmonic content in
the corresponding phase current is dominant. Also whenever steady
saturation of CT occurs, the 3rd harmonic content in the corresponding
phase current is dominant. Both second and 3rd harmonic contents of all
phase currents of each side of the protected transformer are calculated to
judge whether CT saturation occurs or not. Comprehensive harmonic ratio
is calculated by below equation.
Iφ 2 Iφ 3
+ > K har
Iφ Iφ
Where:
Iφ2 is the secondary harmonic of current on each side;
Iφ3 is the third harmonic of current on each side;
41
Khar is the setting of comprehensive harmonic ratio,and the fixed setting of

software.
If the second and 3rd harmonic contents of any phase current are more
than Khar, then CT satisfies the above formulas and it is saturated. Before
the CT saturation status, there usually is a short time period in which CT
still works in its linear characteristic. By very fast CT saturation detection of
IED, it needs only 4ms before any CT saturation happening to detect the
fault which is internal or external fault. x In order to distinguish saturation
caused by internal faults and external faults effectively, percent differential
protection based on sample values is used. If CT saturation is induced by
external fault, differential protection will be blocked. However if CT
saturation is induced by internal fault, differential protection will send its trip
signal.
The typical saturation figure of phase A CT saturation is shown in below
figure.
Figure 27 Typical phase A current transformer Saturation waveform
3.8 Differential current supervision

In normal operation condition, zero differential current is assumed in each
phase. The differential current supervision monitors the differential
currents and checks its value to be less than a threshold. An alarm report
is generated as “DiffCurrOverLmtAlarm” after 5s, if the differential current
exceeds the threshold value. The alarm is an indication of miss-connection
in CT secondary windings, and therefore is released to remind user to
detect the faulty connection in secondary circuit and remove it. This
function can be enabled or disabled by the logic switch "DiffOn" (1-on,
0-off). The fixed threshold for releasing alarm is 0.3 “DiffStartupSet”.
However, to avoid incorrect alarm, the threshold value will increase to 0.1A
(1A CT) and to 0.3A (5A CT) if 0.3 times of "ICDDiffCurrSet" <0.1A. The
equation is shown as below:
 I D.alarm =
max{0.3 I _ Percent Diff , 0.1A} if I n 1A

 I D.alarm =
max{0.3 I _ Percent Diff , 0.3 A} if I n 5 A
Logic of differential current supervision is shown in below figure.
42
“DiffOn”=1
Idiff_A>ID.alarm
Idiff_B>ID.alarm ≥1 & Ds Differential Alarm
Idiff_C>ID.alarm
Figure 28 CT Fail detection logic

DANGER: Before Differential protection is put into operation on site,
polarity of current transformer must have been checked right by an
energizing test of every side of the transformer or a test of simulating an
external fault of the side in primary system. Otherwise a mal-operation
may occur during an external fault.
3.9 Setting list

Table 12 Differential protection setting
Default
Range
No. Setting name value Unit Remark
(In:5A/1A)
(In:5A/1A)
InstantDiffCurrSet Differential Tripping
1. 0.5In~20In 20 A
Current setting(ID>>)
DiffStartupSet Differential Startup
2. 0.05In~4In 2 A
Current Setting
BreakPoint1CurrSet The current setting of
3. 0.1In~In 0.6 A
first break point (IR1)
BreakPoint2CurrSet The 2nd breakpoint
4. 0.1In~10In 2 A
restraint current (IR2)
Ratio restraint
5. Slope1RatioRestrCoef 0.00~0.2 0.2 coefficient of the first
slope
Ratio restraint
6. Slope2RatioRestrCoef 0.2~0.7 0.5 coefficient of the
second slope
Ratio restraint
7. Slope3RatioRestrCoef 0.25~0.95 0.7 coefficient of the third
slope
2ndHRestrCoef Second
8. 0.05~0.80 0.15
harmonic(HAR) ratio
3rd/5thHRestrCoef Third or fifth
9. 0.05~0.80 0.35
harmonic(HAR) ratio
Within the delay
second harmonic
2ndHCrossBlkTime block all three phases.
10. 0.00~20 20 s
After the delay, then
only the local phase is
blocked.
Within the delay fifth
harmonic block all
11. 3rd/5thHBlkTime 0.00~20 20 s three phases. After the
delay, then only the
local phase is blocked.
43
Table 13 Differential protection logic switch

Default
No. Logic switch name Set mode Remark
value
DiffOn Enable ratio differential
1. 0/1 0
protection 1-enable, 0-disable
InstantaneousDiffOn Enable differential instaneous
2. 0/1 0
protection 1-enable, 0-disable
3. CTFailDetectOn 0/1 0 CT failure test is on 1-On, 0-Off
CTFailBlkDiff CT failure blocking differential

4. 0/1 0
1-blocking, 0-unblocking
Inrush blocking differential
5. ExcitInrushBlkDiff 0/1 0 protection
1-block; 0-not block.
Second harmonic restraint
2ndHRestr 1-2nd harmonic restraining on;
6. 0/1 0
0- fuzzy identification restraining
on
OEBlkDiff Overexcitation block differential
7. 0/1 0
protection 1-block; 0-not block.
Overexcitation stabilization
OE5thHOn judgment 3rd or 5th harmonic
8. 0/1 0
(HAR) inhibit on
1-5th harmonic; 0-3rd harmonic.
Eliminate calculated 3I0 when
HVSideDeltaMinus3I0 HV side winding is connected in
9. 0/1 0
Delta mode
1- eliminate; 0-not eliminate
MVSideDeltaMinus3I0 MV side winding is connected in
10. 0/1 0
Delta mode 1- eliminate; 0-not
eliminate
LVSideDeltaMinus3I0 LV side winding is connected in
11. 0/1 0
Delta mode 1- eliminate; 0-not
eliminate
3.10 Report list

No. Report name Remark

Trip report:
1. DiffPhATrip
2. DiffPhBTrip Three-slope ratio differential phase A/B/C trip
3. DiffPhCTrip
4. InstantDiffPhATrip
Instantaneous Differential protection (ID>>)
5. InstantDiffPhBTrip
trip for phase A/B/C
6. InstantDiffPhCTrip
Alarm report:
1. HVSideCTFail High voltage side CT failure
2. HVSide1CTFail CT failure of high voltage side 1
3. HVSide2CTFail CT failure of high voltage side 2
4. MVSideCTFail CT failure of medium voltage side
5. MVSide1CTFail CT failure of medium voltage side 1
44
6. MVSide2CTFail CT failure of medium voltage side 2

7. LVSideCTFail CT failure of low voltage side
8. LVSide1CTFail CT failure of low voltage side1
11. DiffCurrOverLmtAlarm Imbalance differential current alarm
12. 2ndHBlkDiff Blocking differential of the second harmonic
13. 3rd/5thHBlkDiff Blocking differential of third or fifth harmonic
4 Technical data
Note: In is CT rated secondary current, 1A or 5A.
Table 15 Technical data for differential protection
Content Range and value Error
0.5In to 20.00In ≤ ±3% setting or ±0.02In
current
Percentage differential
0.05In to 4.00In ≤ ±3% setting or ±0.02In,
current
Restraint current 1 0.1In to 1In ≤ ±3% setting or ±0.02In
Restraint current 2 0.1In to 10In ≤ ±3% setting or ±0.02In
Slope 1 0.0 to 0.2
Slope 2 0.2 to 0.7
Slope 3 0.25 to 0.95
Second harmonic restraint 0.05 to 0.80 fundamental
ratio wave
Third or fifth harmonic
0.05 to 0.80
restraint ratio
Reset ratio of restrained
About 0.7
differential
it ≤ 30ms when the setting is
Operating time of restraint
in 200% times, and
differential
IDifferential>2IRestraint
Typical trip time is 20ms
Operating time of
when the setting is in 200%
instantaneous differential
times
Reset time about 40ms
45
Chapter 6 Chapter 1Restricted earth fault protection
(87REF)
Chapter 6 Restricted earth fault

protection (87REF)
About this chapter

output signals, parameter, IED report and technical data of
restricted earth protection.
47
(87REF)
1 Overview
The restricted earth fault protection detects earth faults in power
trans-formers with earthed starpoint or in non-earthed power transformers
with a starpoint former (earthing transformer/reactor) installed inside the
protected zone. A precondition for using this function is that a CT should be
installed in the starpoint connection, i.e. between the starpoint and earth.
The starpoint CT and the phase CTs define the limits of the protected zone
by restricted earth fault protection. It includes a restricted earth fault
protection functional module.

The input and output signals of restricted earth fault protection function are
shown as below, the left side is input signals and right side is output
signals:
Restricted Earth-Fault
Differential Protection
1 1
BIBlk Trip
2
Alarm
Figure 29 The input and output signals of restricted earth fault protection function
diagram
Input:
BIBlk BIBlk
REF Output:
Restricted earth fault
Trip
protection trip
Restricted earth fault current
Alarm
is over limit
The IED provides two restricted differential protection functions which can
be used independently at various locations. For example, it is possible to
use them for both windings of YNyn transformer which is earthed at both
starpoints. Further, one of them can be implemented to protect an earthed
transformer winding and the other for an earthing transformer/reactor. In
case of auto-transformers, one of them is sufficient to protect the
auto-windings. Examples for some of applications are illustrated in the
below figure.
48
(87REF)
HV LV
IA.2
A a
IB.2
B b
IC .2
C c
3I02 = I A.2 + IB.2 + IC .2

3I01
CSC-326
Figure 30 Application of restricted earth fault protection on an earthed transformer

winding
HV LV
Ia′ .2
A a
Ib′ .2
B b
Ic′.2
C c
3I01
′
3I02
′ = Ia′ .2 + Ib′ .2 + Ic′.2
CSC-326
Figure 31 Application of restricted earth fault protection on an earthed transformer

winding
HV LV
IA.2
Ia′ .2
A a
IB.2
Ib′ .2
B b
IC .2 Ic′.2
C c
3I01 3I01
′
3I02 = I A.2 + IB.2 + IC .2
CSC-326
3I02
′ = Ia′ .2 + Ib′ .2 + Ic′.2
Figure 32 Application of restricted earth fault protection on both sides of transformer
49
(87REF)
IA.2
A Ia.3
a
IB.2
Ib .3
B
b
IC .2
C Ic .3
c
3I01
3I02 = I A.2 + IB.2 + IC .2
CSC-326
3I03 = Ia.3 + Ib.3 + Ic.3
Figure 33 Application of restricted earth fault protection on an auto-transformer
Under proper operation condition, no neutral point current 3I0 flows
through the neutral point CT. Furthermore, the sum of the phase currents
3I02 =IA.2 + IB.2 + IC.2 which is almost zero. In case of auto-transformer,
both the neutral point currents 3I02 =IA.2 + IB.2 + IC.2 and 3I03 =IA.3 +
IB.3 + IC.3 are zero. With an earth fault inside the protected zone, a
neutral point current 3I01 flows.
Moreover, depending on the earthing conditions of the power system
outside the protected zone, a further earth current may be recognized in
the residual current path of the phase CTs (3I02 and 3I03). Since all the
currents flowing into the protected zone are defined positive, the residual
current from the system (3I02 and 3I03) is more or less in phase with the
neutral point current (3I01). With an earth fault outside the protected zone,
a neutral point current 3I01 flows into the protected zone, together with
equal residual current 3I02 and 3I03 which flows toward outside of the
protected zone, through the phase CTs. The direction of the current flowing
into the protection zone is the positive one, the neutral point current is in
phase opposition with 3I02 and 3I03.
With the described situations, it may seem to be simple to discriminate an
internal fault from an external one. With the described situations, it may
seem to be simple to discriminate an internal fault from an external one.
However, there are some difficulties to do so. For instance, when a strong
fault without earth connection occurs outside the protected zone, a
residual current may appear in the residual current path of the phase CTs.
The residual current is caused by different degrees of saturation in phase
CTs and could simulate a fault in the protected zone. Thus, additional
measures should be taken to prevent this current to cause false tripping.
To achieve this objective, the restricted earth fault protection provides a
restraint quantity.

The differential current Idiff0 and restricted current Irest0 are calculated as
the following equation:
50
(87REF)
 I diff 0 = 3I01 + 3I02 + 3I03


{
 I rest 0 = max 3I01 , 3I02 , 3I03 } (1)
Idiff0 and Irest0 are compared by the restricted earth fault protection with a
dual-slope operating characteristic defined by below equation and shown
in below figure.
 I diff 0 ≥ I 0 D if I res 0 ≤ I 0 D / S 0 D
 (2)
 I diff 0 ≥ S 0 D × I res 0 if I res 0 > I 0 D / S 0 D
Where, I0D is the setting of sensitivity threshold of restricted earth fault

protection (the setting is “REFStartupCurr”), and S0D is slope ratio of
restricted earth fault (the setting is "REFRestrCoef”).
This characteristic can be enabled or disabled by using logic switch
(“REFTrip”). If setting “1-on” is selected, a trip signal is issued by restricted
earth fault protection when the operating point lies into tripping area (see
below figure) and the preset time delay is expired.
The trip logic for restricted earth fault protection is shown in below figure.
I Diff0
Trip Area
Slope _ REF
Restraint
Earth Fault Restraint Area
Startup
Current
I Res0
Figure 34 Characteristic of restricted earth fault protection
“REFTrip”=1
T1
T1 Restraint Earth Fault

& Trip
“REFAlarm”=1
T2
T2 Restraint Earth Fault

& Trip is over limit
Idiff0 > “REFAlarmCurr”
T1：“REFTripTime” T2：“REFAlarmTime”
Figure 35 Tripping logic of the restricted earth fault protection

To clarify the proper operation during various situations, three important
operating conditions are examined.
External fault under undisturbed conditions:
3I01 flows into protection zone, 3I02 flows out of protection zone,
51
(87REF)
according to the definition of the positive direction of current, 3I02 shall be
a minus, which means 3I02 = –3I01.
Idiff0 = |3I01 + 3I02| = |3I01 – 3I02|= 0
Ires0 = max {|3I01|, |3I02|} = |3I01|
No differential current (Idiff0 = 0), the restricted current (Irest0) is the
external fault current flowing into the neutral point.
Internal fault, fed only from the starpoint:
In this case, 3I02=0, thus,
Idiff0 = |3I01 + 3I02| = |3I01 + 0| = |3I01|
IIres0 =Max{|3I01|, |3I02|} = |3I01|
Both the tripping (Idiff0) and the restraint (Irest0) quantities correspond to
the fault current flowing through the starpoint.
Internal fault, fed from the starpoint and from the system, e.g. with equal
earth current magnitude:
Both 3I01 and 3I02 flow into the protection zone, they are positive,
therefore, 3I02 = 3I01.
Idiff0 = |3I01 + 3I02 |= |3I01 + 3I02 |= 2 ×|3I01|
Ires0 = max {|3I01|, |3I02|} = |3I01|
Tripping quantity (Idiff0) corresponds to double the fault current flowing
through the starpoint connection, and restraint quantity (Irest0) is equal to
the fault current.
The results show that the device is capable to properly discriminate
internal and external earth faults by using the definitions proposed for
differential and restraint current. However, the device is still subjected to
some influences that induce differential currents even during normal
operation condition. These influences should be compensated in
appropriate manner. The specific treatments designed to cope with these
influences includes automatic ratio compensation which is explored as
follows.

Restricted earth fault protection represents some problems in the
application of current transformers regarding to matching between phase
and starpoint CTs. The problem is originated from different ratio of phase
and starpoint CTs. The difference may result in a differential current in
normal operation condition. To remove this problem, the input currents of
the relay from starpoint CTs should be converted according to primary
rated currents of phase and starpoint CTs. In the IED, this objective is
achieved by taking a common reference value and converting all
secondary currents of starpoint CTs into the same reference. The
conversion is per-formed by calculation of ratio compensation factor for
starpoint CTs. The compensation factors are then multiplied by the
secondary current of starpoint CTs to make them comparable with those
current measured at phase CTs. The conversion procedure is performed
inside the device. For ordinary transformers, the corresponding number of
zero differential protection modules are configured according to the
measurement numbers of restricted earth fault protection needed to be
configured. The I3/I4 current input is 0. The ratio compensation factors of
52
(87REF)
secondary currents of starpoint CTs of ordinary transformers are
calculated as follow:
nStarpo int −W 1
K Starpo int −W 1 = (3)
nPhase −W 1
Where, K Starpo int −W 1 is the ratio compensation factor for winding 1
For autotransformer, in addition to the common winding starpoint CT, the

measured current from phase winding of winding 2 (MV winding) should
also be converted to the common reference current. In this context, the
ratio compensation factors are calculated as follow:
nPhase −W 2
KW 2 = (4)
nPhase −W 1
nStarpo int
K Starpo int = (5)
nPhase −W 1
Where, KW 2 is the ratio compensation factor for winding 2 (MV winding)

phase CT, is the ratio compensation factor for common winding
K Starpo int
starpoint CT.
4.3 Positive sequence current blocking

CT2 HV LV
IA.2
A a
IB.2
B b
IC .2
C c
3I02 = I A.2 + IB.2 + IC .2

3I01
CSC-326
Figure 36 Logic program of positive sequence current blocking

When an external fault causes a heavy current to flow through the
protected device, differences in the magnetic characteristics of the current
transformer CT2 under saturation condition may cause a significant
difference in the secondary currents I02 connected to the IED. If the
difference is greater than the pickup threshold, the REF protection function
can trip even though no fault occurred in the protected zone. To prevent
the protection function from such erroneous operation, a restraint
(stabilizing) ratio, zero-sequence current divides positive-sequence current,
is brought in.
I0
> 15% (6)
I1
Where, I0 is zero-sequence current, I1 is positive-sequence current.
53
(87REF)
Only when the ratio is greater than 15% can the REF protection trip.
4.4 Restricted earth fault current alarm

In normal operation condition, zero differential current is expected for
restricted earth fault protection. The restricted earth fault current
supervision monitors Idiff0 and detects whether its value is less than the
threshold or not. If the differential current exceeds the setting
“REFAlarmCurr”, then an alarm report “REFCurrOverLmt” will be issued
after the delay time "REFAlarmTime" is up. The alarm is an indication of
miss-connection in phase or starpoint CT secondary windings, and
therefore is released to remind user to detect the faulty connection in
secondary circuit and remove it. The function can be enabled or disabled
by using setting “REFAlarm". The setting range of the threshold differential
current to release restricted earth fault current alarm is on [0.08-10A].
However, to avoid incorrect alarm indications, the threshold value is
increased to 0.1A (in 1A nominal current inputs) and to 0.3A (in 5A nominal
current inputs), if the set value is less than 0.1A.
DANGER: Before earth fault protection is put into operation on site, polarity
of CT of neutral point must has been checked right by an energizing test of
every side of the transformer or a test of simulating an external fault of the
side in primary system. Otherwise a mal-operation may occur during an
external fault.
5 Setting list
Table 17 Restricted earth fault protection of high voltage side setting
Default
Range
Number Setting name value Unit Remark
(In:5A/1A)
(In:5A/1A)
1. HVSideREFStartupCurr 0.05In~2In 2 A
2. HVSideREFAlarmCurr 0.05In~2In 2 A
3. HVsideREFRestrCoef 0.2~0.95 0.5
4. HVsideREFTripTime 0~60 0.03 s
5. HVsideREFAlarmTime 0~60 0.03 s
Table 18 Restricted earth fault protection of medium voltage side setting

Range Default value
Number Setting name Unit Remark
(In:5A/1A) (In:5A/1A)
1. MVSideREFStartupCurr 0.05In~2In 2 A
2. MVSideREFAlarmCurr 0.05In~2In 2 A
3. MVSideREFRestrCoef 0.2~0.95 0.5
4. MVSideREFTripTime 0~60 0.03 s
5. MVSideREFAlarmTime 0~60 0.03 s
54
(87REF)
Table 19 Restricted earth fault protection of low volatge side setting
Default
Range
(In:5A/1A)
(In:5A/1A)
1. LVSideREFStartupCurr 0.05In~2In 2 A
2. LVSideREFAlarmCurr 0.05In~2In 2 A
3. LVSideREFRestrCoef 0.2~0.95 0.5
4. LVSideREFTripTime 0~60 0.03 s
5. LVSideREFAlarmTime 0~60 0.03 s
Table 20 Restricted earth fault protection of high voltage side logic switch
Default
Number Logic switch name Set mode Remark
value
Enable restricted earth fault
HVSideREFProtTrip protection of high voltage side
1. 0/1 0
trip
1-On, 0-Off
Enable high restricted earth fault
2. HVSideREFAlarm 0/1 0 protection alarm
1-On, 0-Off
CT failure blocking restricted
3. CTFailBlkHVSideREF 0/1 0 earth fault protection
1-On, 0-Off
Table 21 Restricted earth fault protection of medium voltage side logic switch
Default
value
MVSideREFProtTrip protection of medium voltage
1. 0/1 0
side trip
1-On, 0-Off
MVSideREFAlarm protection alarm of medium
2. 0/1 0
voltage side
1-On, 0-Off
CTFailBlkMVSideREF earth fault protection of medium
3. 0/1 0
voltage side
1-On, 0-Off
Table 22 Restricted earth fault protection of low voltage side logic switch
Default
value
LVSideREFTrip protection of low voltage side
1. 0/1 0
trip
1-On, 0-Off
LVSideREFAlarm protection alarm of low voltage
2. 0/1 0
side
1-On, 0-Off
CTFailBlkLVSideREF earth fault protection of low
3. 0/1 0
voltage side
1-On, 0-Off
55
(87REF)
6 Report list
Number Report name Remark

Trip report:
1. HVSideREFTrip /
2. MVSideREFTrip /
3. LVSideREFTrip /
Alarm report:
1. HVSideREFCurrOverLmt /
2. MVSideREFCurrOverLmt /
3. LVSideREFCurrOverLmt /
7 Technical data
Table 24 Restricted earth fault protection technical parameter
Differential current 0.05 In to 2.00 In ≤±3% setting or 0.02In
Slope 0.2 to 0.95
≤ ±1% setting or +40 ms,
Time delay 0.00 to 60.00s, step 0.01s when trip value is set as
200% setting
Reset ratio Approx. 0.7, at tripping
≤ 30ms when the setting is in
Trip time
200% times
Reset time About 40ms
56
Chapter 7 Chapter 1Impedance protection (21)
Chapter 7 Impedance protection (21)
About this chapter

output signals, setting parameters, messages and technical
parameters.
57
1 Overview
The sub-transmission lines are extended, including lots of branches and
different distance lines, so the situations are complicated. This kind of
system has higher requirement for fault isolating, in order to sustain the
stability and safety of power system.
The configuration of distance protection can meet basic requirements of
transformer and transmission line. This protection function has the
following characteristics:
It provides phase-to-phase and phase-to-earth impedance protection of 1
stage 4 times.

The input and output signals of impedance protection function are shown
as below, the left side is input signals and right side is output signals:
Impendance Protection
1 1
BIBlk Dis_PP_Trip1
2
Dis_PP_Trip2
3
Dis_PP_Trip3
4
Dis_PP_Trip4
5
Dis_PN_Trip1
6
Dis_PN_Trip2
7
Dis_PN_Trip3
8
Dis_PN_Trip4
Figure 37 The input and output signals of distance protection function diagram
Input:
BIBlk BIBlk
Output:
DISPP Dis_PP_Trip1 Phase-to-phase impedance time 1 trip
Dis_PP_Trip2 Phase-to-phase impedance time 2 trip
Input:
BIBlk 1: BI blocking
DISPN Output:
Dis_PN_Trip1 phase-to-earth distance trip 1
58
Protection startup element: there are abrupt current startup element and
negative current startup element, where the abrupt current startup element
is equal to the main protection, and the negative current startup element is
as follows:
 I 2 > I Qd 2

 I Qd 2＝0.2 I e
I
Where: I 2 is the effective value of negative current, Qd 2 is the fixed
threshold, I e rated current for transformer.
Distance measurement element: the action characteristics of phase-phase
distance protection and phase-earth distance protection can fixed as
full-distance characteristics or offset distance characteristics.
78° to 90°distance sensitivity angle can be fixed.
Phase-to-phase distance protection can adopt 0° connection, and the
voltage selects the phase-to-phase voltage, and the current takes the
• • • • • •
corresponding phase current. For example U = U A − U B , I = I A − I B , are

used to calculate the corresponding AB phase-to-phase distance, and BC
phase-to-phase distance is similar to CA phase-to-phase distance.
Phase-to-earth also adopts 0° connection, the AC quantity is taken from
the CT and VT, whose equation is as follows:
•
Uj
Z jdj = • •
I j + K ⋅3 I 0
• • •
where: U ϕ is phase-to-earth voltage, I ϕ is phase current, 3 I 0 is self
calculated zero sequence current, K is zero sequence compensation
coefficient, in which the phase-to-earth distance zero compensation
coefficient K pointing to the main transformer is fixed as 0, and the
phase-to-earth distance zero compensation coefficient K pointing to the
busbar can be fixed by the setting.
When the software calculates, it regularly adopts the compensation
coefficient K as 0 to calculate the phase-earth distance, and makes the
compensation for the setting of phase-earth distance pointing to busbar
(whose zero sequence compensation coefficient can be fixed). The
specific implementation is as the following analysis
59
jX jX
Z1 Z1
φ φ
R R
Z2
Z2P
a) b)
Figure 38 The trip characteristics of impedance components
The operation characteristics of distance protection is shown as figure 34
(φ is the sensitivity angle), in which figure a) is the circular characteristics
corresponding to the distance setting fixed according to the actual
operation; b) is the distance circular characteristics. where: Z1 is the value
of phase-earth distance pointing to main transformer, Z2 is the value of
phase-earth pointing to busbar, and the both can be fixed; Z2P is the value
after the compensation of phase-earth distance Z2 pointing to busbar,
automatically calculated by the software.
As for phase-to-earth distance pointing the main transformer, without
considering its protection range extending to the opposite busbar, its
corresponding phase-earth distance do not consider the zero
•
Uϕ
compensation, and the distance calculated by the equation Z ′ϕdϕ = •
is
Iϕ
matched with the actual setting protection value; as for the phase-earth
distance, Z2 is matched with the distance value calculated by the equation
•
Uj
Z jdj = • •
; a conversion relation between the equation and the
I j + K ⋅3 I 0
equation used in the actual calculation:
• • • •
Uj Uj Ij Ij
Z jdj = • •
= •
× • •
= Z ′jdj × • •
= Z ′jdj × M ,
Ij + K ⋅3I 0 Ij Ij + K ⋅3I 0 Ij + K ⋅3I 0
Corresponding to the use of unified equation , the setting of Z1 remains

unchanged, and Z2 needs to consider to compensation; that is:
• • .
I ϕ + K ⋅3 I 0
Z 2 P = Z 2 / M = Z 2 × •
Iϕ
In fact, considering that the phase-phase distance protection can

accurately measure the phase-phase fault and three-phase fault,
phase-earth protection need to consider certain compensation, if the
single-phase phase-earth needs to be measured correctly, therefore,
60
phase-earth distance protection as the supplement of phase-phase

distance protection, is mainly used to detect the single-phase phase-earth
• •
fault. Because while single-phase is ground, I ϕ ＝ 3 I 0 , then M can be
1 1
simplified as a real number, that is M = , = 1+ K .
1+ K M
The influence of VT failure and voltage clamp on the protection
While the local side VT failure happens, the distance protection functions
of the local side need to be blocked.
Oscillation blocking element
In order to avoid the distance protection mis-operation during the
oscillation, the distance protection is equipped with oscillating blocking
element.
Impedance protection can be set as blocked by swing or not by swing
respectively according to time.
When the fault occurs again during the oscillating process, it is equipped
with oscillating blocking opening element and the abrupt startup open
regularly within 150ms in order to ensure the correct operation of distance
protection; in addition, opening element with asymmetric fault and
symmetric fault are input conditionally.
3.2 Logic diagram

The logic of phase-phase distance protection and phase-earth distance
protection is the same, and the 1st stage distance protection logic is as the
figure:
“PPZ1On/PEZ1On”=1
I2>0.2Ie ≥1
&
T1
Phase-to-phase/
△iφ>0.2IN phase-to-earth
zone 1 trip
Zφ is within the
area
VT Failure
T：“PPZ1Time/PEZ1Time”
Figure 39 1st stage distance protection logic diagram
3.3 Setting list

Table 26 Impedance setting on high voltage side
Default
Number Setting name Range Unit Remark
value
1. PPZSensitiveAngle 78~90 80 .
2. HVSidePEZSensitiveAngle 78~90 80 .
3. HVSideImpedRstTime 0.02~20.0 0.04 s
4. HVSidePPZ1PointToTransf 0.1~125 10 Ω
5. HVSidePPZ1PointToSystem 0.1~125 10 Ω
61
Default
value
6. HVSidePPZ1Time1 0.1~20.0 20 s
22. HVSidePEZ1PointToTransf 0.1~125 10 Ω
23. HVSidePEZ1PointToSystem 0.1~125 10 Ω
24. HVSidePEZ1K0 0~1 0.67
25. HVSidePEZ1Time1 0.1~20.0 20 s
62
Default
value
Note: Impedance setting of medium voltage side is the same to that of high
voltage side
Table 27 Distance protection logic switch
Default
value
Enable
phase-to-phase
impedance stage 1
1. HVSidePPZ1Time1On 0/1 0
time 1 protection of
high voltage side
1-On, 0-Off
Enable
phase-to-phase
impedance stage 1
high voltage side
1-On, 0-Off
Enable
phase-to-phase
impedance stage 1
high voltage side
1-On, 0-Off
Enable
phase-to-phase
impedance stage 2
high voltage side
1-On, 0-Off
Enable
phase-to-phase
impedance stage 2
high voltage side
1-On, 0-Off
Enable
phase-to-phase
impedance stage 2
high voltage side
1-On, 0-Off
Enable
phase-to-phase
63
Default
value
impedance stage 3
high voltage side
1-On, 0-Off
Enable
phase-to-phase
impedance stage 3
high voltage side
1-On, 0-Off
Enable
phase-to-phase
impedance stage 3
high voltage side
1-On, 0-Off
Enable
phase-to-phase
10. HVSidePPZ4On 0/1 0 impedance stage 4 of
high voltage side
1-On, 0-Off
Phase-to-phase
impedance stage 1
blocking by power
11. HVSidePPZ1BlkByPowerSwing 0/1 0
swing of high voltage
side
1-On, 0-Off
Phase-to-phase
impedance stage 2
blocking by power
side
1-On, 0-Off
Phase-to-phase
impedance stage 3
blocking by power
side
1-On, 0-Off
Phase-to-phase
impedance stage 4
blocking by power
side
1-On, 0-Off
Enable phase-to-earth
impedance stage 1
15. HVSidePEZ1Time1On 0/1 0 time 1 protection of
high voltage side
1-On, 0-Off
16. HVSidePEZ1Time2On 0/1 0
impedance stage 1
64
Default
value
high voltage side
1-On, 0-Off
impedance stage 1
high voltage side
1-On, 0-Off
impedance stage 2
high voltage side
1-On, 0-Off
impedance stage 2
high voltage side
1-On, 0-Off
impedance stage 2
high voltage side
1-On, 0-Off
impedance stage 3
high voltage side
1-On, 0-Off
impedance stage 3
high voltage side
1-On, 0-Off
impedance stage 3
high voltage side
1-On, 0-Off
impedance stage 4 of
24. HVSidePEZ4On 0/1 0
high voltage side
1-On, 0-Off
Phase-to-earth
impedance stage 1 is
blocked by power
25. HVSidePEZ1BlkByPowerSwing 0/1 0
side
1-On, 0-Off
Phase-to-earth
blocked by power
65
Default
value
side
1-On, 0-Off
Phase-to-earth
blocked by power
side
1-On, 0-Off
Phase-to-earth
blocked by power
side
1-On, 0-Off
Note: Impedance logic switch of medium voltage side is the same to that of
high voltage side.
3.4 Report list


Trip report:
1. HVSidePPZ1Time1Trip /
10. HVSidePPZ4Trip /
11. HVSidePEZ1Time1Trip /
20. HVSidePEZ4Trip /
21. MVSidePPZ1Time1Trip /
66

30. MVSidePPZ4Trip /
31. MVSidePEZ1Time1Trip /
40. MVSidePEZ4Trip /
3.5 Technical data

Table 29 Distance protection technical parameter
≤± 5.0% static accuracy or ±0.1Ω
Distance setting 0.1Ω～25Ω, step 0.01Ω, when In=1A Condition
range 0.5Ω～125Ω, step 0.01Ω, when In=5A Voltage range: 0.01Ur to 1.2Ur
Current range: 0.12In to 20In
Time delay 0.00s to 100.00s, step 0.01s ≤±1% or+20ms
Typical time is 40ms when the setting
Trip time
is in 70% times
Dynamic
≤±5%, when 0.5<SIR<30
overreaching
67
Chapter8 Chapter 1Interturn protection
Chapter 8 Interturn protection
About this chapter

This chapter describes the inter-turn protection (Suitable for
reactor ) principle, input and output signals, setting
parameters, reports and technical data.
69
1 Overview
Inter-turn short circuit is a common internal fault form of the reactor. The
device adopts the principle of fault-tolerant recovery to adapt inter-turn
protection principle.

The input and output signals of interturn protection function are shown as
below, the left side is input signals and right side is output signals:
InterTurn Protection
1 1
BIBlk Operation
Figure 40 The input and output signals of interturn protection function diagram
Input:
BIBlk BIBlk
ITURN
Output:
Operation Interturn protection trip
Inter-turn short circuit is a common internal fault form of the reactor. The
device adopts the principle of fault-tolerant recovery to adapt inter-turn
protection principle.

The protection adopts zero sequence power directional relay consisting of
the zero sequence current at the end of the main reactor and the zero
sequence voltage of the reactor installed at the reactor, and the related
electrical quantities are fault-tolerant. Due to the inter-turn short circuit in
the reactor, the corresponding terminal measurement value always
satisfies the exceeding zero sequence voltage to zero sequence current,
and the zero sequence reactance measurement value is the zero
sequence reactance of the system. When the external fault (systematical
fault)occurs, the corresponding zero sequence voltage lags behind zero
sequence current. The zero sequence reactance is the zero sequence
impedance of the reactor. Therefore, the phase relationship between the
zero sequence current of the terminal of the main reactor and the zero
sequence voltage of the reactor installation is used to distinguish the
interturn short circuit, the internal grounding fault and the external fault of
the reactor. When the number of short circuited turns is very small, the
zero sequence current and zero sequence voltage are very small in the
zero sequence impedance of the system (the zero sequence impedance
of the system is far less than the zero sequence impedance of the reactor).
Therefore, the zero sequence voltage must be compensated in order to
70
better distinguish the inter-turn fault of the small turn number. In order to
eliminate the influence of irrelevant zero flow on sensitivity of inter turn
protection during non full phase operation, impedance criterion is used.
The forward direction of zero sequence voltage and zero sequence
current is shown below.
PT
System
*
Reactor CT
Figure 41 Zero sequence voltage and zero sequence current positive direction
definition
The action equation of the zero sequence power directional element is:
(3U 0 + K ⋅ Z ⋅ 3I02 )
0° < Arg < 180°
3I
02
The equation of impedance components:

Z < 0.66 Z 2 n
Where: Z is the secondary impedance value of the main reactor, which
is calculated in real time and according to phase identification; Z 2n is the
secondary rated impedance of the main reactor.
In order to ensure reliable operation of inter-turn protection, CT
disconnection and VT breakage detection elements are provided. When
the CT or VT is broken, the inter-turn protection of the main reactor is
withdrawn.
3.2 Logic diagram

“InterturnProtIsOn”=1
The criteria of steady-state

component and abrupt of Each & &
electric quantity satisfy conditions Inter-turn protection trip
(3U 0 + K ⋅ Z ⋅ 3I0 ) ≥1
0 < rg < 180
3I
0
Z < 0.66 Z 2 n
VT failure ≥1
CT failure
Figure 42 Logic diagram of Inter-turn protection
71
3.3 Setting list

Table 31 Inter-turn protection setting
Default
value
1. Interturn3I0StartupSet 0.05In~40In 40 A
Table 32 Inter-turn protection logic switch

Logic switch Default
Number Set mode Remark
name value
Enable interturn protection
1. InterturnProtIsOn 0/1 0
1-On, 0-Off
3.4 Report list


Trip report:
1. InterturnTrip /
3.5 Technical data

Table 34 Distance protection technical parameter
Zero sequence startup 0.05In～40.00In ≤ ±2.5% setting or
current ±0.02In
TheMaximumSensitiveAngle 90° 5°
Trip range 20°~160°
Intrinsic time delay Using inverse time characteristic,
the fastest action time is no more
than 100ms.
72
Chapter 9 Chapter 1Overcurrent protection (50, 51, 67)
Chapter 9 Overcurrent Protection

(50, 51, 67)
About this chapter

This chapter describes the overcurrent principle, the input
and output signals, setting value parameters, messages and
technical parameters.
73
1 Overview
When the power system fault occurs, the current of the system increases,
and the overcurrent protection can avoid the damage of the fault current to
the equipment. The device provides three-stage of overcurrent protection
of high, middle and low voltage side, each stage provides options of
overcurrent definite time protection or inverse time protection. Each stage
of overcurrent protection has the same logic criterion, and each stage can
be enabled or disabled independently.
Each stage of the overcurrent protection can be selectively input harmonic
blocking element and directional element, and based on the phase
measurement of the current action. In addition, each stage of the
overcurrent definite-time protection can be selectively input the complex
pressure blocking component.
Main characteristics of overcurrent protection:
1) The device provides 3 stages of overcurrent protection on each high,
medium and low voltage side, each stage adopts definite time or 12
IEC and ANSI standard curve of inverse time characteristic, and it
adopts user defined characteristic curve as well;
2) The flow direction sensitive angle can be adjusted to meet different
application occasions;
3) Each section of the overcurrent protection can be respectively set
whether it inputs direction element, whether the action area is
"forward" or "reverse" action is set by the logic switch;
whether it’s through harmonic locking;
5) Harmonic blocking can lock across;
whether it’s through re-pressing locking;
7) The protection of the input direction component needs to detect
whether the VT secondary circuit disconnects. If VT is disconnected,
the protection of the input direction component can be set as VT
disconnection protection or VT disconnection protection blocking.

The input and output signals of overcurrent protection function are shown
as below, the left side is input signals and the right side is output signals:
Directional / Non-directional Overcurrent Protection
1
Start
2
Operation
3
PhaseA
4
PhaseB
5
PhaseC
Figure 43 The input and output signals of overcurrent protection function diagram
74

Output:
Start IED startup
Operation IED trip

OC
PhaseA Phase A trip
PhaseB Phase B trip
PhaseC Phase C trip
IED is equipped with 3 stages overcurrent protection, please refer to the
setting list for details.

3.1.1 Inrush blocking components
When "OC1BlkBy2ndH"=1, carrying out inrush check, the inrush criterion
is shown as below:
I∅2
> “OC2ndHI2/I1Ratio”, (∅ = a, b, c)
I∅
When it is detected that the ratio of second harmonic and fundamental
wave is larger than "OC2ndHI2/I1Ratio" and there is a current, then the
inrush condition is satisfied in the phase.
When it is detected that there is inrush condition, within the
"HarmCrossBlkTime", one phase inrush protection fails and three phase
protection; after the "HarmCrossBlkTime", one phase inrush protection
fails and one phase protection; when the inrush criterion returns, release
each blocking.
When the maximum fundamental wave current of the three phases is
larger than "HarmUnblkOCCurr", release each blocking.
The output blocking state of each phase is caused by inrush blocking of
overcurrent stage 1 phase A, phase B and phase C. Schematic diagram is
shown below:
75
Phase A I2/I1 >“h/2ndII2/I1Ratio”

≥1
&
Phase B I2/I1 >“h/2ndII2/I1Ratio”
3 Phase Inrush Current Blocking
Phase C I2/I1 >“h/2ndII2/I1Ratio”
Time<“Iarm/rossBlkTime”
3 Phase Inrush Current Blocking &

Overcurrent Stage1-3 Phase Inrush Current Blocking
“h/1BlkBy2ndI”=1
Phase A I2/I1>“h/2ndII2/I1Ratio” &

&
Overcurrent Stage1- Phase A Inrush Current Blocking
Time>“Iarm/rossBlkTime”
Phase B I2/I1>“h/2ndII2/I1Ratio” &

&
Overcurrent Stage1- Phase B Inrush Current Blocking
Phase C I2/I1>“h/2ndII2/I1Ratio” &

&
Overcurrent Stage1- Phase C Inrush Current Blocking
Figure 44 Inrush blocking logic diagram
3.1.2 Compound voltage blocking unit

“OCStage1BlkByVolt” =1, check the voltage. The voltage blocking element
is compound voltage element, including undervoltage and negative
sequence voltage components, composite voltage criterion:
min(Uab, Ubc, Uca) < “PPVoltBlkSet” or U2 > “U2BlkSet”
When the "3PhVoltConnect" =1, the low voltage or negative sequence
voltage is detected; when the "3PhVoltConnect"=0, the negative sequence
voltage component exits.
76
min(Uab,Ubc,Uca)<“PPVoltBlkSet”
≥1
Negative Sequence Voltage>
Multi-voltage
“U2BlkSet” Component Satisfied
min(Uab,Ubc,Uca)<“PPVoltBlkSet”
Multi-voltage
Component Satisfied &
≥1
Overcurrent Stage1 Multi-voltage
“OCStage1BlkByVolt”=1 Component Satisfied
“OCStage1BlkByVolt”=0
Figure 45 Logic diagram of the characteristics of multi-voltage element
3.1.3 Directional component

"DirOCStage1"=1, check the direction. Directional elements are connected
with a 90° angle, the fault phase direction is determined by the fault phase
current and the line voltage of the sound phase.
Table 36 The judgment of the fault phase direction
Phase Current Voltage
A Ia U bc
B Ib U ca
C Ic U ab
When the three-phase fault occurs, there is no sound phase-to-earth
voltage, which is not enough to judge the fault current direction, so
memory voltage is adopted. Diagram of forward and reverse direction
characteristics of phase A current:
FWD 90° IA 90° IA
Bisector Bisector
RVD
Φ Φ
0° 0°
U BC_Ref U BC_Ref
5°
-IA -IA 5°
Figure 46 Forward and reverse direction interval graph
Sensitive angle of directional overcurrent Φ =Angle: Adjustable;
77
Positive direction overcurrent range: (-85°~ +85°), reverse direction

overcurrent range: (+95°~ +265°);
Direction discrimination logic diagram is shown below:
Phase A Direction
&
Component Satisfied
≥1
Overcurrent Stage 1 Direction
“DirOCStage1”=1 Component Satisfied
“DirOCStage1”=0
Figure 47 Direction discrimination logic diagram

In the process of direction discrimination and voltage discrimination, the
VT disconnection may lead actions or alarms that are not consistent with
the flow direction discrimination or the voltage discrimination along
overcurrent protection stages. When VT fails, the action mode is decided
according to "VTFailBlkProt"; if “VTFailBlkProt” is set to 1, overcurrent
protection with voltage or directional element is blocked; if “VTFailBlkProt”
is set to 0, voltage blocking element and directional element exit and act in
a pure overcurrent mode.
When the “3PhVoltConnect” is set to 0, the direction is satisfied
automatically.
3.1.4 Definite time
When "OCStage1Curve"=0, overvoltage is the definite time characteristic,
inverse time function is disabled.
I∅ > “OCStage1CurrSet”, (∅ = 𝑎, 𝑏, 𝑐)
When the phase-to-earth current is greater than "OCStage1CurrSet", timing
component starts and until "OCSatge1Time”, overcurrent protection trips,
when the phase-to-earth current I∅ < Dropout × ”OCStage1CurrSet” ,
Dropout is dropoff coefficient, timing component returns, overcurrent
protection resets.
3.1.5 Inverse time
When "OCStage1Curve"=1~13, inverse time overcurrent characteristic
trips, inverse time function is disabled.
 
 
 A
=t + B ⋅T
  IΦ  P 
  − 1 
  Iset  
Where:
A: "InvTimeOCStage1CoefA"
P: "InvTimeOCStage1IndexP"
B: "InvTimeOCStage1TimeB"
T: "InvTimeOCStage1ConstT"
Iφ: Phase current value in the system
Iset: "OCStage1CurrSet"
If the phase-to-earth current exceeds "OCStage1CurrSet", the timing
element starts, inverse time characteristic curve is selected by Curve, A, P,
78
B are determined when the value is from 1 to 12, see the following Table;
when the value is 13, it is user defined characteristics, calculate the trip
delay according to the setting of the A, P, B, T. while timing, overcurrent
protection trips. When the delay is less than the "InvTimeOCMinTime", the
component trip according to the "InvTimeOCMinTime".
Table 37 Curve definition
Curve Inverse time characteristic A P B

0. Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
3. IEC EXTERMELY INV. 80.0 2.0 0
4. IEC SHORT TIME INV. 0.05 0.04 0
5. IEC LONG TIME INV. 120.0 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
9. ANSI MODERATELY INV. 0.0103 0.02 0.0228
10. ANSI VERY INV. 3.922 2.0 0.0982
11. ANSI EXTERMELY INV. 5.64 2.0 0.02434
12. ANSI DEFINITE INV. 0.4797 1.5625 0.21359
13. USER DEFINE
3.1.6 Trip characteristic

When overcurrent protection function is enabled (En=1) and no BI blocking,
if the "OCStage1On"=1 , the overcurrent protection of the corresponding
stage is enabled.
If the action conditions are met, time component starts; take stage 1
protection for example, when time is over, "OCStage1Trip" is issued.
When IED trips each phase trip states will be displayed. LED and
protection trip can be configured by AESP.
When "OC1BlkBy2ndH"=1, the harmonic locking component is put into
operation, when the action timer is time out, the inrush current is checked,
and if the current is not locked, unblock overcurrent trip, otherwise it will
output “InrushBlk” report.
When "OCStage1BlkByVolt"=1, the compound voltage locking element is
put into the device. When the protection is started, the device checks the
compound voltage locking condition, unblock overcurrent protection if the it
meets the conditions, otherwise the protection is locked.
When "DirOCStage1"=1, overcurrent protection is with the directional
element, and choose the positive or negative direction characteristic
according to"OCStage1FwdDir", when the directional element is not
satisfied, overcurrent protection is blocked.
When the overcurrent component trips, at the same time, 3-phase current
value of Ia, Ib and Ic will also be displayed.
79
3.1.7 Logic diagram

Taking the overcurrent stage 1 phase as an example, the logic diagram of
inverse time is shown below:
Ia>“OCStage1CurrSet”
VT Failure Blocking &

≥1
&
Overcurrent Stage1 Phase A Startup
“VTFailProtOff”=1
Overcurrent Stage1 Direction

Component Satisfied
Overcurrent Stage 1 Compound

Voltage Component Satisfied
Overcurrent Protection Function On
Overcurrent Stage1
&
Phase A Startup T1 &
&
Binary Blocking Overcurrent Stage1 Protection Trip
Overcurrent Stage 1
3 Phase Inrush Blocking
“OCStage1On”=1
T1：“OCSatge1Time”
Figure 48 logic diagram of the inverse time overcurrent stage1
3.2 Setting list

Table 38 Overcurrent setting on high voltage side
Default
value
1. HVSideOCStage1Curve 0~13 0
2. HVSideOCStage1CurrSet 0.05In~40In 40 A
3. HVSideOCSatge1Time1 0.00~100.00 100 s
4. HVSideInvTimeOCStage1CoefA 0.001~1000 10 s
5. HVSideInvTimeOC1IndexP 0.01~10.00 10
6. HVSideInvTimeOCStage1TimeB 0.000~100.00 100 s
7. HVSideInvTimeOCStage1ConstT 0.025~1.5 0.025
9. HVSideOCSatge2Time1 0.00~100.00 100 s
12. HVSideInvTimeOCStage2IndexP 0.01~10.00 10
17. HVSideOCStage3Time 0.00~100.00 100 s
80
Default
value
19. HVSideInvTimeOC3IndexP 0.01~10.00 10
22. HVSidePPVoltBlkOCSet 1.00~120.0 30 V
23. HVSideOCU2BlkOCSet 0.05~100.0 3 V
24. HVSideDirOCSensitiveAngle 0.00~90.00 30 degree
Overcurrent harmonic crossing
25. 0.000~100.00 100 s
blocking time of high voltage side
26. HVSideOCRstTime 0.01~100 0.04 s
27. HVInvTimeOCMinTripTime 0.10~100 0.1 s
28. HVSideOCSatge1Time2 0.10~100 100 s
Note: Overcurrent rotection setting of each middle and low voltage side is
the same to that of high voltage side
Table 39 Comman setting
Number Setting name Range Default Unit Remark
value
1. HVSideHarmUnblkPhCurr 0.05In~40 In 40 A
2. HVSideOC2ndHI2/I1Ratio 0.07~0.50 0.07
3. MVSideHarmUnblkPhCurr 0.05In~40 In 40 A
4. MVSideOC2ndHI2/I1Ratio 0.07~0.50 0.07
5. LVSideHarmUnblkPhCurr 0.05In~40 In 40 A
6. LVSideOC2ndHI2/I1Ratio 0.07~0.50 0.07
Table 40 Overcurrent protection logic switch of high voltage side
Set Default
Number Logic switch name Remark
mode value
1-Enable overcurrent stage
1 time 1 of high voltage
1. HVSideOCSatge1Time1On 1/0 0 side; 0-Disable overcurrent
stage 1 time 1 of high
voltage side.
1-overcurrent stage 1
2. HVSideDirOCStage1 1/0 0 Direction on, 0-Overcurrent
stage 1 Direction off
forward direction of high
3. HVSideOCStage1Fwd 1/0 0 voltage side, 0-overcurrent
stage 1 reverse direction of
high voltage side
voltage on of high voltage
4. HVSideOCStage1BlkByVolt 1/0 0 side, 0-Overcurrent stage 1
voltage off of high voltage
side
1-overcurrent stage 1 of
high voltage side secondary
5. HVSideOCStage1BlkBy2ndH 1/0 0
harmonic on, 0-Overcurrent
stage 1 of high voltage side
81
Set Default
mode value
secondary harmonic off
time 2 time 1 of high voltage
side.
high voltage side
side
10. HVSideOCStage2BlkBy2ndH 1/0 0 harmonic on, 0-Overcurrent
time 3 time 1 of high voltage
side.
high voltage side
side
15. HVSideOCStage3BlkBy2ndH 1/0 0 harmonic on, 0-Overcurrent
HVSideOCSatge1Time2On 1/0 0 1-Enable overcurrent
16. voltage side; 0-Disable
overcurrent time 1 time 2
of high voltage side.
17. stage 1 time 3 of high
voltage side; 0-Disable
82
Set Default
mode value
HVSideOCSatge3Time3On 1/0 0 1-Enab le overcurrent
Note: Overcurrent protection logic switch of middle and low voltage side
are the same to that of high voltage side
Table 41 Common logic switch
Number Logic switch name Set mode Default value Remark

1-VT failure
1. VTFailProtOff 1/0 0 protection off, 0-VT
failure protection on
Note: it is fixed with three phase voltage connection.
3.3 Report list

Table 42 Report list(2,3 stage is the same as 1 stage)

Trip report:
1. H/M/LVSideOCSatge1Time1Trip /
2. H/M/LVSideOCStage1PhATrip /
3. H/M/LVSideOCStage1PhBTrip /
4. H/M/LVSideOCStage1PhCTrip /
5. H/M/LVSideOCSatge1Time2Trip
6. H/M/LVSideOCSatge1Time3Trip
Alarm report:
Inrush conditions meet the requirements
1. H/M/LVSideOCInrushBlk
of blocking overcurrent protection
Note: the report of each low voltage side is the same to that of low
voltageside
83
3.4 Technical data

Table 43 Overcurrent protection technical data
Definite time characteristics
Current 0.05In～40.00In ≤ ±2.5% setting or ±0.02In
≤ ±1% setting or +40 ms
Time delay 0.00s～100.00s, step 0.01s At 2 times of operating
current
Inverse time characteristic
IEC standard Normal inverse time IEC 60255-151
Very inverse time; ≤ ±5% setting or +40 ms
Extreme inverse time Under the condition 2< I Φ / I set
Long inverse time <20
ANSI Inverse time ANSI/IEEE C37.112
Short inverse time ≤ ±5% setting or +40 ms
Long inverse time Under the condition 2< I Φ / I set
Medium inverse time <20
Very inverse time;
Extreme inverse time
Definite inverse time
User-defined characteristic  IEC 60255-151
curve   ≤ ±5% setting or +40 ms
 A
=t + B ⋅T Under the condition 2< I Φ / I set
  IΦ  P 
  − 1  <20
  Iset  
Time coefficient of inverse 0.001~000, step 0.001
time : A
Time delay of inverse time: 0.000～100.00, step 0.01
B
Inverse time index: P 0.01~10.00, step 0.01
Inverse time constant: T 0.025~1.5, step 0.005
Minimum trip time 20ms
Return mode Instantaneous return
Directional component
Action angle range 170° ≤±3°,
Sensitive Angle 0°～90°, step 1° When line voltage >2V
Inrush blocking
Maximum current of open 0.05 In ~ 40.00 In
magnetizing inrush current ≤ ±2.5% setting or ±0.02In
blocking
The ratio of secondary 0.07～0.5, step 0.01
harmonic and fundamental
current
Cross blocking (IL1, IL2, 0.00s～100.00s, step 0.01s
IL3) (Time setting can be ≤ ±1% setting or +40 ms,
adjusted)
84
Chapter 10Chapter 1 Earth fault protection (50N, 51
N, 67N)
Chapter 10 Earth fault protection

(50N, 51N, 67N)
About this chapter

This chapter describes the zero sequence current principle,
the input and output signals, setting value parameters,
messages and technical parameters.
85
Chapter 10Chapter 1 Earth fault protection (50N, 51N,
67N)
1 Overview
Under the condition of high resistance grounding fault in the neutral point
grounding system, the calculated impedance located out of the distance
impedance zone and the IED maloperate. Therefore, other protection trips
are needed to isolate the fault, earth fault protection can reliably identify
high resistance grounding fault. For example, in the double circuit lines,
the directional earth fault protection simultaneously distinguishes the size
and direction of fault current and cooperates with other protection devices
in the system.
The characteristics of earth fault protection are listed as follow:
1) There are 3 stagesthree stages of definite time on each high, medium
and low voltage side of which the definite stage or inverse time can be
selected.(including all inverse time characteristics that stipulated by
IEC/ANSI standard );
2) Direction characteristics of each stage is independent (selectable);
3) Negative sequence directional component(selectable);
4) The inrush blocking feature of each stage is independent ;
5) Inrush locking is distinguished by secondary harmonic currents;
6) The maximum current of open magnetizing inrush blocking can be
adjusted;
7) Earth fault protection of VT breaking blocking direction.

The input and output signals of earth fault protection function are shown as
below, the left side is input signals and the right side is output signals:
Directional / Non-directional Zero
Overcurrent Protection
1
Start
2
Operation
Figure 49 The input and output signals diagram of earth fault protection function
Output:
EF Start IED startup
Operation IED trip
86
N, 67N)
IED is equipped with 3 stages earth fault protection on each high, medium
and low voltage side, please refer to the setting list for details. The
overcurrent protection stage 1 will be taken as an example below and the
principle will be introduced.

3.1.1 Inrush blocking components
When "3I0Stage1BlkBy2ndH"=1, inrush detects. There are two inrush
criteria:
Check phase current harmonics and external zero sequence current
harmonic.
1) Only when "3I0HarmonChkExtrI02/I01"=1, and "Extr3I0Stage1"=1,
zero-sequence current harmonic is detected. When it is detected that
the ratio of second harmonic and fundamental wave is larger than
"3I02ndHI02/I01" and there is zero sequence current, then the zero
sequence inrush condition is satisfied. When the maximum
fundamental wave of zero sequence current is larger than
"3I0UnblkHarmBlkCurr", release each blocking.
2) In addition to the first case, detect the phase current harmonic. When
it is detected that the ratio of second harmonic and fundamental wave
is larger than "OC2ndHI2/I1Ratio" and there is a current, then the
inrush condition is satisfied in the phase. When the maximum
fundamental wave of phase current is larger than "OC2ndHI2/I1Ratio",
release each blocking.
When any of the above two harmonic check method is satisfied, the
secondary harmonic current is high.
3I0>“3I0UnblkHarmBlkCurr” &
&
3I02/3I0>“3I02ndHI02/I01”
“Extr3I0Stage1”=0 & ≥1
High 2nd Harmonic Current
“3I0HarmonChkExtrI02/I01”=1
&
Imax>“HarmUnblkPhCurr”
Ia2/Ia1>“OC2ndHI2/I1Ratio”
≥1
Ib2/Ib1>“OC2ndHI2/I1Ratio”
Ic2/Ic1>“OC2ndHI2/I1Ratio”
3I02/3I0:Zero Sequence 2nd Harmonic/Zero Sequence Basic Wave

Ia2/Ia1：Phase A Current 2nd Harmonic/Phase A Current Basic Wave
Ib2/Ib1：Phase B Current 2nd Harmonic/Phase B Current Basic Wave
Ic2/Ic1：Phase C Current 2nd Harmonic/Phase C Current Basic Wave
Figure 50 Logic diagram of the secondary harmonic blocking of earth fault protection
87
67N)
3.1.2 Directional component
1) Zero sequence directional component
In order to meet the different operating conditions of power system, the
reference voltage can be clockwise rotate 0 to 90°according to the
"3I0DirectSensitiveAngle", this setting influences direction characteristics
of each stage. The reference voltage vector after rotation is closer to the
-3I0 of lag 3U0 angle Φd, which makes the direction distinguishing more
sensitive. Rotate reference voltage vector to define the forward direction
and reverse direction action zone. The direction range of the positive
direction is rotating voltage reference vector for the vertical bisector
between -80 degrees and +80 degrees. If the -3I0 vector is in this zone,
the device is considered to be in the forward direction.
An example is given to illustrate the direction discrimination of A phase
faults. In the figure, 3I0 exceeds 3U0, so the -3I0 lags 3U0, the reference
voltage 3U0 vector rotates "3I0DirectSensitiveAngle", in order to be closer
to the -3I0 vector. In addition, the yellow area in the diagram is a positive
direction.
3I 0 90° 90°
3I 0
Reverse
10°
10°
0° 0°
3 U 0_Ref 3U 0_Ref
Φ0 Φ0
Forward Bisector Bisector
-3 I 0 -3 I 0
Figure 51 Diagram of zero sequence directional element

Where:
Zero-sequence directional sensitive angle: the angle is settable, Φ 0

="Dir3I0SensitiveAngle ";
Zero sequence positive direction overcurrent range: (-80°~ +80°), zero
sequence reverse direction overcurrent range: (+100°~ +260°).
2) Negative sequence directional component
When "ZeroSeqChkU2/I2DirOn"=1, and the zero sequence voltage is
small, then enable the negative sequence directional element. For
example, zero sequence current mutual coupling or uncertain zero
sequence directional impedance happen in the double circuit line. Here, it
is necessary to input the negative sequence directional component to
detect the fault current direction, the logic switch “3I0DetectNSD” is set to
1. Here, it is still the default input zero sequence direction discrimination.
However, when 3U0 is less than 1V and 3U2 is larger than 2V, it is
converted into negative sequence direction discrimination, at this point
negative sequence component is used to discriminate the direction.
88
N, 67N)
Negative sequence directional characteristics diagram:
3I 2 90° 3I 2 90°
Reverse
10°
10°
0° 0°
3 U 2-Ref 3U 2-Ref
Φ2 Φ2
Forward Bisector Bisector
-3 I 2 -3 I 2
Figure 52 Negative-sequence directional characteristic diagram

Where:
Ф2: setting "3I0NSDSensitiveAngle".
Negative sequence positive direction overcurrent range: (-80°~ +80°),
negative sequence reverse direction overcurrent range: (+100°~ +260°).
In the process of direction discrimination, the VT disconnection may lead
actions or alarms that are not consistent with the flow direction
discrimination or the voltage discrimination along overcurrent protection
stages. When VT fails, the action mode is decided according to
"VTFailProtOff"; if “VTFailProtOff” is set to 1, earth fault protection with
voltage or directional element is blocked; if “VTFailProtOff” is set to 0,
voltage blocking element and directional element exit and act in a pure
overcurrent mode.
VT Failure Blocking &
Zero Sequence
& ≥1
Forward Zone Forward Direction
Calculated Zero
Voltage>1V
&
“ZeroSeqChkU2/I2DirOn”=1
Negative Sequence
Forward Zone
Zero Sequence Forward Zone：Calculate as 90° connection，zero sequence current is within the direction zone.
Negative Sequence Forward Zone：Calculate as 90° connection，negative current is within the direction zone.
Figure 53 Zero sequence current direction sensitive angle logic diagram
3.1.3 Definite time

When "3I0Stage1Curve"=0, zero sequence current is the inverse time
characteristic, inverse time function is disabled.
3I0 > “3I0Stage1CurrSet”
When the zero sequence current is greater than "3I0Stage1CurrSet",
timing component starts and until "3I0Satge1Time”, earth fault protection
trips, when the current <Dropout×"3I0Stage1CurrSet", Dropout is dropout
89
67N)
coefficient, timing component returns, earth fault protection resets.
3.1.4 Inverse time
When "3I0Stage1Curve"=1~13, zero sequence current is the definite time
characteristic, definite stage function is disabled.
 
 
 A 
=t  P
+ B ⋅T
  3I 0  − 1 
  3I 0set  
Where:
A: "InvTime3I0Stage1CoefA"
P: "InvTime3I0Stage1IndexP"
B: "InvTime3I0Stage1TimeB"
T: "InvTime3I0Stage1ConstT"
3I 0 : Zero sequence current setting value
3I 0set "3I0Stage1CurrSet"
If the current exceeds "3I0Stage1CurrSet", the timing element starts,
inverse time characteristic curve is selected by "3I0Stage1Curve", A, P, B
are determined when the value is from 1 to 12, see the following Table;
delay according to the setting of the A, P, B, T. While timing, earth fault
protection trips. When the calculated delay is less than the minimum trip
delay time "3I0InvTimeMinTripTime", the component trips according to the
"3I0InvTimeMinTripTime".

0 Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
10. ANSI VERY INV. 3.922 2.0 0.0982
13. USER DEFINE
90
N, 67N)
When earth fault protection function is enabled and no BI blocking, if the
"3I0Stage1On"=1 , the earth fault protection of the corresponding stage is
enabled.
If the action conditions are met, time component starts; take stage 1
protection for example, when time is over, "3I0Stage1Trip" is issued. LED
and protection trip can be configured by AESP. When IED trips each phase
trip states will be displayed.
When "3I0Stage1BlkBy2ndH"=1, the harmonic locking component is put
into operation, when the action timer is time out, the inrush current is
checked, and if the current is not blocked, unblock overcurrent trip,
otherwise it will output “InrushBlk” report.
When "Dir3I0Stage1"=1, protection is with the directional element, and
choose the positive or negative direction characteristic according to
"3I0Stage1FwdDir", when the directional element is not satisfied, earth
fault protection is blocked.
Element trip triggers action or alarm, meanwhile output analog quantity of
action time, when the element is based on the self-produce zero sequence
current judgment, self-produce zero sequence current is output; when it is
based on the external zero sequence current, external zero sequence
current is output.
&
VT Failure Blocking
3I0>“3I0Stage1CurrSet”
&
T1
Binary Blocking
&
Zero Sequence Current Stage 1
Protection Trip
&
Forward Direction ≥1
“3I0Stage1FwdDir”=1
“Dir3I0Stage1”=1
&
2nd harmonic current is high
“3I0Stage1BlkBy2ndH”=1
“3I0Stage1On”=1
Zero Sequence Overcurrent Stage 1

Protection Function On
T1：“3I0Satge1Time”
Figure 54 Logic diagram of earth fault protection function
91
67N)
3.2 Setting list
Table 46 Zero sequence current setting on high voltage side
Default
value
0: definite time
1? IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
1. HVSide3I0Stage1Curve 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. HVSide3I0Stage3CurrSet 0.05~200 40 A
3. HVSide3I0Satge1Time1 0.00~100.00 100 s
4. InvTime3I0Stage1CoefA 0.001~1000 10
5. InvTime3I0Stage1IndexP 0.01~10.00 10
6. InvTime3I0Stage1TimeB 0.000~100.00 100
7. InvTime3I0Stage1ConstT 0.025~1.5 0.025
0: definite time
1? IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
92
N, 67N)
Default
value
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
9. HVSide3I0Stage2CurrSet 0.05~200 40 A
10. HVSide3I0Satge2Time1 0.00~100.00 100 s
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
16. HVS3I0Stage3CurrSet 0.05~200 40 A
17. HVSideI3I0Stage3Time1 0.00~100.00 100 s
22. HVSideDir3I0SensitiveAngle 0.00~90.00 30 degree
93
67N)
Default
value
23. HVSide3I0NSDSensitiveAngle 0.00~90.00 30 degree
24. HVSide3I0RstTime 0.10~100 0.1 s
25. HVInvTime3I0MinTripTime 0.00~100 0.04 s
26. HVSide3I0Satge1Time2 0.10~100 100 s
Note: Earth fault protection setting of each middle and low voltage side are
Table 47 Common setting
Default
value
1. HVSideHarmUnblkPhCurr 0.05In~40 In 40 A
2. HVSideOC2ndHI2/I1Ratio 0.07~0.50 0.07
3. MVSideHarmUnblkPhCurr 0.05In~40 In 40 A
4. MVSideOC2ndHI2/I1Ratio 0.07~0.50 0.07
5. LVSideHarmUnblkPhCurr 0.05In~40 In 40 A
6. LVSideOC2ndHI2/I1Ratio 0.07~0.50 0.07
7. HVSide3I0HarmUnblkCurr 0.05In~40 In 40 A
8. HVSide3I02ndHI02/I01 0.07~0.50 0.07
9. MVSide3I0HarmUnblkCurr 0.05In~40 In 40 A
10. MVSide3I02ndHI02/I01 0.07~0.50 0.07
11. LVSide3I0HarmUnblkCurr 0.05In~40 In 40 A
12. LVSide3I02ndHI02/I01 0.07~0.50 0.07
Table 48 Earth fault protection of high voltage side logic switch
Set Default
mode value
1-Enable zero sequence
covercurrent stage 1 time 1
of high voltage side;
1. HVSide3I0Stage1Time1On 1/0 0
0-Disable zero sequence
current time 1 time 1 of high
voltage side.
1-3I0 external connection;
2. HVSide3I0Stage1Extr 1/0 0
0-3I0 calculated
1-zero sequence current
direction on, 0-zero
3. HVSideDir3I0Stage1 1/0 0
sequence current stage 1of
high voltage side direction
off
1-Zero sequence current
forward direction; 0-zero
4. HVSide3I0Stage1FowardDir 1/0 0
sequence current stage 1
of high voltage side reverse
direction
94
N, 67N)
Set Default
mode value
1-High zero sequence
current stage 1 secondary
harmonic blocking on, 0-
5. HVSide3I0Stage1BlkBy2ndH 1/0 0
high zero sequence current
stage 1 secondary
harmonic blocking off
voltage side.
0-3I0 calculated
8. HVSideDir3I0Satge 1/0 0
sequence current stage 1of
high voltage side direction
off
direction
stage 2 secondary
voltage side.
0-3I0 calculated
13. HVSideDir3I0Satge3 1/0 0
of high voltage side
direction off
direction
stage 2 secondary
95
67N)
Set Default
mode value
1= check negative
sequence direction;
16. HVSideZeroSeqChkU2/I2DirOn 1/0 1
0= don't check negative
sequence direction
harmonics checking
external connection I02/I01;
17. HVSide3I0HarmonChkExtrI02/I01 1/0 0
harmonics checking phase
current I2/I1
HVSide3I0Satge1Time2On 1/0 0 1-Enable zero sequence
covercurrent stage 1
time 2 of high voltage
18. side; 0-Disable zero
sequence current time 1
side.
side.
side.
side.
side.
side.
Note: Earth fault protection logic switch of medium voltage side is the
96
N, 67N)
same to that of high voltage side
Table 49 Low voltage side earth fault protection logic switch
Set Default
mode value
1: check negative
LVSide3I0ChkU2I2DirOn
sequence direction; 0:
1. 1/0 0
don't check negative
sequence direction
harmonics check external
connection I02/I01 of low
LVSide3I0HarmChkExtrI02/I01
voltage side;
2. 1/0 0
harmonics check Phase
current I2/I1 of low
voltage side
1-3U0 external
3. LVSideExtr3U0 1/0 0 connection; 0-3U0
calculated
current stage 1 of low
4. LVSide3I0Satge1Time1On 1/0 0 voltage side; 0-Disable zero
sequence current stage 1 of
low voltage side
1-3U0 external connection;
5. LVSide3I0Stage1Extr 1/0 0
0-3U0 calculated
stage 1 of low voltage side
6. LVSideDir3I0Stage1 1/0 0 direction on, 0-zero
low voltage side direction off
stage 1 forward of low
voltage side;
7. LVSide3I0Stage1FwdDir 1/0 0
stage 1 reserve direction of
low voltage side
8. Extr3I0Stage2 1/0 0
low voltage side
0-3U0 calculated
voltage side;
low voltage side
13. LVSide3I0Stage2BlkBy2ndH 1/0 0
97
67N)
Set Default
mode value
low voltage side
0-3U0 calculated
voltage side;
low voltage side
stage 3 secondary harmonic
blocking on, 0-zero
18. LVSide3I0Stage3BlkBy2ndH 1/0 0
secondary harmonic
blocking off
Table 50 Common logic switch
Set Default
mode value
1. VTFailProtOff 1/0 0 0-unblock; 1-lock.
3.3 Report list

Table 51 Report list (2,3 stage is the same as 1 stage)

Trip report:
1. H/M/LVSide3I0Satge1Time1Trip /
Alarm report:
Inrush conditions meet the requirements of
1. H/M/LVSide 3I0InrushBlk
blocking earth fault protection
Note: the report of each low voltage side is the same to that of low voltage side
98
N, 67N)
3.4 Technical data
Table 52 Earth fault protection technical data
≤ ±1% setting or +40 ms
Time delay 0.00s～100.00s, step 0.01s At 2 times of operating
current
IEC standard Normal inverse time IEC 60255-151
Very inverse time; ≤ ±5% setting or +40 ms
Extreme inverse time Under the condition 2< 3I 0 /
Long inverse time 3I 0set <20
ANSI Inverse time ANSI/IEEE C37.112,
Short inverse time ≤ ±5% setting or +40 ms
Long inverse time Under the condition 2< 3I 0 /
Medium inverse time
3I 0set <20
Very inverse time;
Extreme inverse time
Definite inverse time
User-defined 
characteristic  IEC 60255-151
curve   ≤ ±5% setting or +40 ms
A
=t  + B  ⋅T Under the condition 2< 3I 0 /
  IΦ  P 
  − 1  3I 0set <20
  Iset  
Time coefficient of inverse 0.005～1000.0, step 0.001
time : A
Time delay of inverse time: B 0.000～100.00, step 0.01
Inverse time index: P 0.01～10.00, step 0.005
Inverse time constant: T 0.025～1.5, step 0.01
Return mode Instantaneous return
Directional component
Zero sequence direction
160° ≤ ±3°, when 3U0≥1V
element action angle range
Directional sensitive angle 0° to 90°, step 1°
Negative sequence direction
160° ≤ ±3°, when 3U2≥2V
element action angle range
Directional sensitive angle 0° to 90°, step 1°
99
Chapter 11 Negative sequence current protection (46)
Chapter 11 Negative sequence

current protection (46)
About this chapter

This chapter describes the negative sequence current
principle, the input and output signals, setting value
parameters, messages and technical parameters.
101
1 Overview
Negative sequence current protection can detect the unbalance of power
system load. When the generator connect unbalanced load, negative
sequence current protection is particularly useful. Because the unbalanced
load will produce a reverse magnetic field in the three-phase induction
motor, resulting in overheating of the rotor end. Secondly, the negative
sequence current protection can also be used to detect the disconnection,
short circuit and polarity of current transformer. Besides, the negative
sequence current protection can also detect the single-phase or two-phase
faults in the system, and the fault statue when the fault current is less than
the load current.
The main characteristics of the negative sequence current protection: offer
3 stages on each high, medium and low voltage side, and definite time or
inverse time can be selected

The input and output signals of negative sequence current protection
function are shown as below, the left side is input signals and the right side
is output signals:
Negative Sequence Over Current
Protection
1
Start
2
Operation
Figure 55 The input and output signals diagram of negative sequence current
protection function
Output:
NSOC Start IED startup
Operation IED trip
IED is equipped with 3 stages of negative sequence current protection on
each high, medium and low voltage side, please refer to the setting list for
details. The negative sequence current protection stage 1 will be taken as
an example below and the principle will be introduced.

3.1.1 Definite time
When "3I2Stage1Curve "=0, negative sequence current is the definite time
characteristic, inverse time function is disabled.
The negative sequence current protection action current is calculated by
the three-phase current as follow:
102
İ2 = İA + a2 İB + aİC

I2 > “3I2Stage1CurrSet”
When the current is greater than "3I2Stage1CurrSet", timing component
starts and until "3I2Stage1Time”, negative sequence current protection
trips, when current I2 < Dropout × ”3I2Stage1CurrSet”, timing component
returns, negative sequence current protection resets.
Where:
I 2 : Negative sequence current;
I 2 set “3I2Stage1CurrSet”
Dropoff: Return coefficient
3.1.2 Inverse time
When "3I2Stage1Curve"=1~13, negative sequence current is the definite
time characteristic, inverse time function is disabled.
 
 
 A 
=t  P
+ B ⋅T
  I2  −1 
  I 2set  
If the negative sequence current exceeds "3I2Stage1CurrSet", the timing

element starts, inverse time characteristic curve is selected by Curve, A, P,
B are determined when the value is from 1 to 12, see the following Table;
delay according to the setting of the A, P, B, T. While timing, earth fault
protection trips. When the calculated delay time is less than the
"InvTimeI2MinTime", the component trips in accordance with the
"InvTimeI2MinTime".
Where:
A: "InvTime3I2Stage1CoefA"
P: "InvTime3I2Stage1IndexP"
B: "InvTime3I2Stage1TimeB"
T: "InvTime3I2Stage1ConstT"
I 2 : Negative sequence current;
I 2 set :”3I2Stage1CurrSet”
0. Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
103
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
10. ANSI VERY INV. 3.922 2.0 0.0982
13. USER DEFINE

When negative sequence current protection function is enabled and no BI
blocking, if the "3I2Stage1On"=1, the negative sequence current
protection of the corresponding stage is enabled.
Negative sequence current protection is tripped, after the starting of
protection trip, if the action conditions are met, timing component starts,
take stage 1 for example, when time is over, "3I2Stage1Trip" is issued.
LED and protection trip can be configured by AESP. When the zero
sequence current component trips negative sequence current value will
also be displayed.
Negative Sequence Overcurrent
Stage1 Protection Function On
&
&
“3I2Stage1On”=1 T1 Negative Sequence Overcurrent
Stage1 Protection Trip
3I2>“3I2Stage1CurrSet”
Binary Blocking
T1：“3I2Stage1Time”
Figure 56 Logic diagram of negative sequence current protection function
3.2 Setting list

Table 55 Negative sequence current setting on high voltage side
Default
value
0: definite time
1:IEC INV.
1. HVSideI2Stage1Curve 0~13 0 2:IEC VERY
INV.
3: IEC
104
Default
value
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. HVSideI2Stage1CurrSet 0.05In~40 40 A
Negative
sequence
3. HVSideI2Stage1Time 0.00~100.00 100 s current stage 1
time 1 of high
voltage side
4. HVSideInvTimeI2Stage1CoefA 0.001~1000 10
5. HVSideInvTimeI2Stage1IndexP 0.01~10.00 10
6. HVSideInvTimeI2Stage1TimeB 0.000~100.00 100
7. HVSideInvTimeI2Stage1ConstT 0.025~1.5 0.025

0: definite time
1:IEC INV.
2:IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
8. HVSideI2Stage2Curve 0~13 0 TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
105
Default
value
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
9. HVSideI2Stage2CurrSet 0.05In~40 In 40 A
Negative
sequence
10. HVSideI2Stage2Time 0.00~100.00 100 s current stage2
time 1 of high
voltage side
13. HVSideInvTimeI2Stage2TimeB 0.000~100.00 100 s

0: definite time
1:IEC INV.
2:IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
15. HVSideI2Stage3Curve 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
16. HVSideI2Stage3CurrSet 0.05In~40 In 40 A
Negative
sequence
17. HVSideI2Stage3Time 0.00~100.00 100 s current stage3
time 1 of high
voltage side
106
Default
value
20. HVSideInvTimeI2Stage3TimeB 0.000~100.00 100
22. HVSideI2RstTime 0.00~100.00 0.04 s
23. HVInvTimeI2MinTripTime 0.10~100.00 0.10 s
24. HVSideI2Satge1Time2 0.10~100.00 100 s
Note: Negative sequence current protection setting of each middle and low
voltage side are the same to that of high voltage side
Table 56 Negative sequence current protection of high voltage side logic switch
Set Default
mode value
1. HVSideIStage1Time1On 1/0 0 1-On, 0-Off
Note: Earth fault protection logic switch of each middle and low voltage
side are the same to that of high voltage side
3.3 Report list

Table 57 Report list(2,3 stage is the same as 1 stage)

Trip report:
1. H/M/LVSideISatge1Time1Trip /
Note: the report of each low voltage side is the same to that of low voltage
side
107
3.4 Technical data

Table 58 Negative sequence current protection technical data
Items Setting range Trip value error
0.05In~40In ≤ ±2.5% setting value or
Current setting
±0.02In
≤ ± 1% times of setting or
Time setting 0.00s～100.00s, step 0.01s +40ms, when trip current is
set as 200% setting
Reset time About 40ms
DropoffCoef About 0.95, when I/In > 0.5
0.05In~40In ≤ ±2.5% setting value or
Current setting
±0.02In
IEC standard curve Normal inverse time; ≤ ±5% setting or +40ms,
Very inverse time; when 2< I 2 / I 2 set <20, it
Extreme inverse time; meets IEC60255-151
Long inverse time; standard
ANSI standard curve Standard inverse time; ≤ ±5% times of setting or
Short inverse time +40ms, when 2< I 2 / I 2 set
Long inverse time; <20, it meets
Normal inverse time; ANSI/IEEEC37.112 standard
Very inverse time;
Extreme inverse time;
User-defined inverse time;
User defined curve   ≤ ±5% times of setting or
  +40ms, when 2< I 2 / I 2 set
= T= t  A
+

 ⋅T
B <20, it meets IEC 60255-151
 P
  I   standard
2
−1
  I 2set  
Time coefficient of inverse 0.001~10.0, step0.001
time : A
Time delay of inverse time: 0.000 to 100.00, step 0.01
B
Inverse time index: P 0.01 to 10.00, step 0.005
Inverse time constant :T 0.025 to 1.5, step 0.01
Reset time Approx. 40 ms
108
Chapter 12 Overvoltage protection (59)
Chapter 12 Overvoltage protection

(59)
About this chapter

This chapter describes the overvoltage principle, the input
and output signals, setting value parameters, reports and
technical parameters.
109
1 Overview
Overvoltage protection is used to prevent the impact of overvoltage on
electrical equipment. The abnormal overvoltage often occurs in low load,
long transmission line, generator voltage regulation fails in the islanded
system, or the load shedding of the generator in the system. Even if the
compensating capacitor can compensate line capacitance, lower the
overvoltage of the lines, when the compensating capacitor fails,
overvoltage will endanger the line insulation system, here the circuit must
be removed.
Overvoltage protection has the following characteristics:
1) Definite or inverse time can be selected on each 2 stages of
high/medium/low voltage side;
2) Set the alarm or trip in stage;
3) Measured voltage can be phase-to-earth voltage or phase-to-phase
voltage;
4) Dropoff coefficient is adjustable.

The input and output signals of overvoltage protection function are shown
as below, the left side is input signals and the right side is output signals:
Overvoltage Protection
1
Start
2
Operation
3
PhaseA
4
PhaseB
5
PhaseC
Figure 57 The input and output signals of overvoltage protection function diagram
Output:
Start IED startup
Operation IED trip

OV
PhaseA Phase A trip
PhaseB Phase B trip
PhaseC Phase C trip
Overvoltage protection selects the phase voltage or line voltage through
110
the on-off logic switch "OVChkPEVolt". Logic switch "OVChkPEVolt" set 1,

select the phase voltage UA-N, UB-N, UC-N; Logic switch "OVChkPEVolt"
set 0, select the line voltage UA-B, UB-C, UC-A. The overvoltage
protection of stage 1 will be taken as an example in below and the principle
will be introduced.
3.1.1 Definite time
When "OVStage1Curve"=0, overvoltage is the define time characteristic,
inverse time function is disabled.
U_∅> "OVStage1VoltSet", (∅=a, b, c)
When "OVChkPEVolt"=1, use the phase-to-earth voltage; when
"OVChkPEVolt"=0, use the phase-to-phase voltage. When the
phase-to-earth (phase-to-phase) voltage is greater than
"OVStage1VoltSet", timing component starts and until timing to the
"OVStage1Time", overvoltage protection trips, when the phase-to-earth
(phase-to-phase) voltage U_∅<overvoltage reset
coefficient×"OVStage1VoltSet", timing component returns, overvoltage
protection resets.
3.1.2 Inverse time
When "OVStage1Curve"=1-13, overvoltage is the inverse time
characteristic, define time function is disabled.
 
 
A
=t  + B  ⋅T
  UΦ P 
  −1 
  Uset  
Where:
A: "InvTimeOVStage1CoefA"
P: "InvTimeOVStage1IndexP"
B: "InvTimeOVStage1TimeB"
T: "InvTimeOVStage1ConstT"
U Φ : Phase-to-earth/phase-to-phase voltage
U set "OVStage1VoltSet"
When "OVChkPEVolt"=1, use the phase-to-earth voltage; when

"OVChkPEVolt"=0, use the phase-to-phase voltage. If the phase-to-earth
(phase-to-phase) voltage exceeds "OVStage1VoltSet", the timing element
starts, inverse time characteristic curve is selected by Curve, A, P, B are
determined when the value is from 1 to 12, see the following Table; when
the value is 13, it is user defined characteristics, calculate the trip delay
according to the setting of the A, P, B, T. When the calculated delay time is
less than "InvTimeOVMinTime", the component will trip in accordance with
the "InvTimeOVMinTime".
111

Inverse time
Curve A P B
characteristic
0. Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
4. IEC SHORT INV 0.05 0.04 0
5. IEC LONG INV. 120.0 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
10. ANSI VERY INV. 3.922 2.0 0.0982
13. User defined

When overvoltage protection is enabled and there is no binary input
blocking, if "OVStage1On"=1, then overvoltage protection of the
corresponding stage is enabled.
Negative sequence voltage protection is tripped, after the starting of
protection trip, if the action conditions are met, timing component starts,
take stage 1 for example, when time is over, "OVStage1Trip" is issued.
LED and protection trip can be configured by AESP.
The three-phase analog quantity U1, U2 and U3 of the trip time issued
when the overvoltage protection trips, the element is based on the
phase-to-earth voltage judgment, it issues three-phase phase-to-earth
voltage; when it is based on the phase-to-phase voltage judgment, it
issues three-phase phase-to-phase voltage.
3.1.4 Logic diagram
The logic diagram of overvoltage protection is shown in following figure.
112
max(Ua,Ub,Uc)>“OVStage1VoltSet” &
“OVChk1Ph”=1 ≥1
min(Ua,Ub,Uc)>“OVStage1VoltSet” &
“OVChk1Ph”=0
&
“OVChkPEVolt”=1
max(Uab,Ubc,Uca)>“OVStage1VoltSet” &
min(Uab,Ubc,Uca)>“OVStage1VoltSet” &
& &
T1 Overvoltage Stage 1
Protection Trip
“OVChkPEVolt”=0
Overvoltage Stage 1 Protection Function On
“OVStage1On”=1
T1：“OVStage1Time”
Figure 58 The logic diagram of overvoltage protection
3.2 Setting list

Table 61 Overvoltage protection setting of high voltage side
Default
value
0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
1. HVSideOVStage1Curve 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. HVSideOVStage1VoltSet 40.00~200.0 110 V
3. HVSideOVStage1Time 0.00~120.00 120 S
113
Default
value
Inverse time
4. HVSideInvTimeOVStage1CoefA 0.001~1000 10 s
characteristic
5. HVSideInvTimeOVStage1IndexP 0.01~10.00 10
6. HVSideInvTimeOVStage1TimeB 0.000~100.00 100 s
7. HVSideInvTimeOVStage1ConstT 0.025~1.5 0.025

0: definite time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8. HVSideOVStage2Curve 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
9. HVSideOVStage2VoltSet 40.00~200.0 110 V
10. HVSideOVStage2Time 0.00~120.00 120 S

Inverse time
11. HVSideInvTimeOVStage2CoefA 0.001~1000 10 s
characteristic
12. HVSideInvTimeOVStage2IndexP 0.01~10.00 10
13. HVSideInvTimeOVStage2TimeB 0.000~100.00 100 s
14. HVSideInvTimeOVStage2ConstT 0.025~1.5 0.025
15. HVSideOVDropoffCoef 0.95~1 1
16. HVSideOVRstTime 0.00~100.00 0.04 s
17. HVInvTimeOVMinTripTime 0.10~100 0.10 s
Note: Overvoltage protection setting of medium voltage side is the same to

that of high voltage side
114
Table 62 Overvoltage protection logic switch of high voltage side

Set Default
mode value
1. HVSideOVStage1On 1/0 0 /
2. HVSideOVStage2On 1/0 0 /
3. HVSideOVChkPEVolt 1/0 0 /
4. HVSideOVChk1Ph 1/0 0 /
Note: Overvoltage protection logic switch of medium voltage side is the
3.3 Report list

Table 63 Report list(2 stage is the same as 1 stage)

Trip report:
1. HVSideOVStage1Trip /
2. HVSideOVStage2Trip /
3. MVSideOVStage1Trip /
4. MVSideOVStage2Trip /
3.4 Technical data

Table 64 Overvoltage protection technical data
Voltage wiring type PPVolt or phase-to-earth ≤ ±2.5% setting or ±1V
voltage
Phase voltage setting value 40V～100V, step 0.01V ≤ ±2.5% setting or ±1V
Line voltage setting 80V～200V, step 0.01V ≤ ±2.5% setting or ±1V
DropoffCoef 0.95～1, step 0.01 ≤ ±3% setting
Time delay setting 0.00s～120.00s, step 0.01s ≤ ±1% setting or +60 ms,
At 1.2 times of trip voltage
Reset time <40ms
Phase voltage setting value 40V～100V, step 0.01V ≤ ±2.5% setting or ±1V
Line voltage setting 80V～200V, step 0.01V ≤ ±2.5% setting or ±1V
IEC standard curve Normal inverse time; U U
Very inverse time; In the case of 2< Φ / set <20,
Extreme inverse time; the allowable trip time error is:
Long inverse time; ± 5% or +60 ms;
ANSI standard curve Standard inverse time; U U
Short inverse time In the case of 2< Φ / set <20,
Long inverse time; the allowable trip time error is:
Normal inverse time; ± 5% or +60 ms;
Very inverse time;
User defined curve   U U
In the case of 2< Φ / set <20,
 
 A  it meets the IEC60255-151
=T= t  + B ⋅T
P standard
  I2  −1 
  I 2set  
115

Time coefficient of inverse 0.001 to 10.0, step 0.001
time : A
Time delay of inverse time 0.000 to 100.00, step 0.01
B
Inverse time constant: T 0.025 to 1.5, step 0.01
116
Chapter 13 Zero sequence voltage protection(64)
Chapter 13 Zero sequence voltage

protection (64)
About this chapter

This chapter describes the zero sequence voltage principle,
the input and output signals, setting value parameters,
117
Chapter 13 Zero sequence voltage protection (64)
1 Overview
Zero sequence voltage protection is generally used in the power network
with small grounding fault current.
The main features of zero sequence voltage protection are as follows:
1) It provides 1 stages of reverse time and reverse time selective
protection;
2) Fault phase selection function;
3) Zero sequence voltage 3U0 can be selected as self-produce zero
sequence voltage (the total of three phase measurement voltage), or
external zero sequence voltage (zero sequence residual voltage).

The input and output signals of zero sequence voltage protection function
diagram is shown below, left side is input and right side is output:
Voltage Displacement Protection
1
Start
2
Operation
Figure 59 The input and output signals diagram of zero sequence voltage protection
function
Output:
ZSOV Start IED startup
Operation IED trip
Zero sequence voltage protection is used for ground fault check. Zero
sequence voltage protection can be set as alarm or trip, reverse and
reverse time are selective.
Compare the external or self-produce zero sequence voltage and the
corresponding setting value, if it is greater than the setting, trip timer starts.
Timer starts timed to the user defined time delay. The time delay setting
can be adjusted independently by settings. When time delay defined by
the users is over, the protection device sends out a trip command. The
zero sequence voltage protection stage 1 will be taken as an example
below and the principle will be introduced.
3.1.1 Definite time
When "3U0Stage1CurveSel" =1~0, zero sequence voltage is inverse time
118
characteristic.
3U0 > “3U0Stage1VoltSet”
If the zero sequence voltage exceeds the inverse time starting setting
"3U0Stage1VoltSet", the start signal is triggered and timing component
starts, time to "3U0Stage1Time", zero sequence voltage protection trips.
3.1.2 Inverse time
When "3U0Stage1CurveSel" =1~13, zero sequence voltage is the inverse
time characteristic.
 
 
 A 
=t  P
+ B ⋅T
  3U 0  − 1 
  3U 0set  
Where:
A:”InvTime3U0Stage1CoefA”
P:”InvTime3U0Stage1IndexP”
B: "InvTime3U0Stage1TimeB"
T: "InvTime3U0Stage1ConstT"
3U 0 : 3U0
3U 0set : "3U0Stage1VoltSet"
If the zero sequence voltage exceeds "3U0Stage1VoltSet", Start signal is

triggered and the timing component starts, inverse time characteristic
curve is selected by curve, A, P, B are determined when the value is from
1 to 12, see the following table; when the value is 13, it is the user defined
characteristic, calculate the trip delay in accordance with the setting of the
A, P, B, T. the time overing, and zero sequence voltage protection trips.
When the calculated delay time is less than the "InvTime3U0MinTime", the
component will trip according to the "InvTime3U0MinTime".
0. Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
4. IEC SHORT INV 0.05 0.04 0
5. IEC LONG INV. 120.0 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
119
8. ANSI LONG INV. 5.6143 1 2.18592
10. ANSI VERY INV. 3.922 2.0 0.0982
13. User defined

When zero sequence voltage protection is enabled and no binary input
blocking, if "3U0Stage1On"=1, then zero sequence voltage protection is
enabled.
Zero sequence voltage protection is tripped, after the starting of protection
trip, if the action conditions are met, timing component starts, take stage 1
for example, when time is over, "3U0Stage1Trip" is issued. LED and
Zero sequence voltage protection simultaneously outputs the trip value at
the corresponding time during operation.
3.2 Setting list

Table 67 Low voltage side zero sequence voltage protection setting
Numbe Defaul Uni
Setting name Range Remark
r t value t
0:reverse time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
1. LVSide3U0Stage1CurveSel 0~13 0
SHORT INV.
8: ANSI LONG
INV.
9: ANSI
MODERATEL
Y INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE
120
Numbe Defaul Uni

Setting name Range Remark
r t value t
INV.
13: User
defined
2. LVSide3U0Stage1Set 2.00~100.0 100 V
3. LVSide3U0Stage1Time 0.00~120.00 120 s
4. LVSideInvTime3U0Stage1CoefA 0.001~1000 10
5. InvTime3U0Stage1IndexP 0.01~10.00 10
6. LVSideInvTime3U0Stage1TimeB 0.000~100.00 100

LVSideInvTime3U0Stage1Const
7. 0.025~1.5 0.025
T
8. LVSide3U0RstTime 0.0~100 0.04 s
LVInvTime3U0MinTripTime 0.100~100.0 0.1 s
9.
0
Table 68 Low voltage side zero sequence voltage protection logic switch
Default
Number Logic switch name Range Remark
value
1. LVSide3U0Stage1On 1/0 0
3.3 Report list

Table 69 Report list(other stages are the same as 1 stage)

Trip report:
1. LVSide3U0Trip /
side
121
3.4 Technical data

Table 70 Zero sequence voltage protection technical data
Operating voltage 3V0 2V to 100V, step 1V ≤ ±5% setting or ±1V
(self-produced)
Trip time 0.00 - 60.00s, step 0.01s ≤ ±1% setting or +50 ms,
when trip voltage is set as
120% of setting
DropoffCoef About 0.95
Operating voltage 3V0 2V～100V, step 0.01V, ≤ ±5% setting or ±1V
(self-produced)
IEC standard curve Normal inverse time; 3U 3U 0set
Very inverse time; In the case of 2< 0 /
Extreme inverse time; <20, the allowable trip time
Long inverse time; error is: ± 5% or +60 ms;
ANSI standard curve Standard inverse time; 3U 3U 0set
Short inverse time In the case of 2< 0 /
Long inverse time; <20, the allowable trip time
Normal inverse time; error is: ± 5% or +60 ms;
Very inverse time;
User defined curve   3U 3U 0set
In the case of 2< 0 /
 
 A  <20, it meets the
= T= t  + B ⋅T
P IEC60255-151 standard
  3U 0  − 1 
  3U 0set  
time : A
Time delay of inverse 0.000 to 100.00, step 0.01
time: B
122
Chapter 14 Negative sequence voltage protection (47)
Chapter 14 Negative sequence

voltage protection (47)
About this chapter

This chapter describes the negative sequence voltage
principles, the input and output signals, setting parameters,
123
1 Overview
In normal operating three-phase system, the negative sequence voltage is
almost 0, and the negative sequence voltage will occur when there is
asymmetrical situation in the system. Negative sequence voltage
protection is operated by checking negative sequence voltage.
The main features of negative sequence voltage protection are as follows:
High/medium voltage sides provide 2 stages of protection on each side
and definite or inverse time can be selected.

The input and output signals of negative sequence voltage protection
function are shown below, left side is input and right side is output:
Negative Sequence Over Voltage
Protection
1
Start
2
Operation
Figure 60 The input and output signals diagram of negative sequence voltage
protection function
Output:
NSOV Start IED startup
Operation IED trip
The negative sequence voltage protection stage 1 will be taken as an
example below and the principle will be introduced.
3.1.1 Definite time
When "3U2Stage1Curve"=0, negative sequence voltage is the inverse
The negative sequence voltage protection trip voltage is calculated by the
three-phase voltage as follow:
U̇ 2 = U̇ A + a2 U̇ B + aU̇ C
U2 > “3U2Stage1VoltSet”
If the voltage is exceeds "3U2Stage1VoltSet", timing component starts and
until timing to "3U2Stage1Time", negative sequence voltage protection
trips.
Where:
124
U 2 :Negative sequence voltage
3.1.2 Inverse time

When "3U2Stage1Curve"=1~13, negative sequence voltage is the inverse
 
 
 A 
=t  P
+ B ⋅T
  U2  −1 
 U 2set  
If the voltage exceeds "3U2Stage1VoltSet", the timing component starts,

inverse time characteristic curve is selected by inverse time characteristic
curve, A, P, B are determined when the value is from 1 to 12, see Table 3;
when the value is 13, it is the user defined characteristics, calculate the trip
delay in accordance with the setting of the A, P, B, T. timing, negative
sequence voltage protection trips. When the calculated delay time is less
than the "InvTimeU2MinTime", the component will trip in accordance with
the "InvTimeU2MinTime".
Where:
A: "InvTime3U2Stage1CoefA"
P: "InvTime3U2Stage1IndexP"
B: "InvTime3U2Stage1TimeB"
T: "InvTime3U2Stage1ConstT"
U 2 : Negative sequence voltage
U 2 set : "3U2Stage1VoltSet"
0. Definite time
1. IEC INV. 0.14 0.02 0
2. IEC VERY INV. 13.5 1.0 0
6. ANSI INV. 8.9341 2.0938 0.17966
7. ANSI SHORT INV. 0.2663 1.2969 0.03393
8. ANSI LONG INV. 5.6143 1 2.18592
125
10. ANSI VERY INV. 3.922 2.0 0.0982
13. USER DEFINE

When negative sequence voltage protection function is enabled and there
is no binary input blocking, if "3U2Stage1On"=1, then the negative
sequence voltage protection is enabled.
After the protection trip starts, if the trip conditions are satisfied, timing
component starts, and works till the IED issues "U2Trip". LED and
3.2 Setting list

Table 73 Negative sequence voltage protection setting of high voltage side
Default
value
0:reverse time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
1. HVSideU2Stage1Curve 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
2. HVSideU2Stage1VoltSet 40~100.00 100 V
3. HVSideU2Stage1Time 0.00~100.00 100 s
4. HVSideInvTimeU2Stage1CoefA 0.001~1000 10
126
Default
value
5. HVSideInvTimeU2Stage1IndexP 0.01~10.00 10
6. HVSideInvTimeU2Stage1TimeB 0.000~100.00 100
7. HVSideInvTimeU2Stage1ConstT 0.025~1.5 0.025

0:reverse time
1: IEC INV.
2: IEC VERY
INV.
3: IEC
EXTERMELY
INV.
4: IEC SHORT
TIME INV.
5: IEC LONG
TIME INV.
6: ANSI INV.
7: ANSI
SHORT INV.
8. HVSideU2Stage2Curve 0~13 0
8: ANSI LONG
INV.
9: ANSI
MODERATELY
INV.
10: ANSI
VERY INV.
11: ANSI
EXTERMELY
INV.
12: ANSI
DEFINITE INV.
13: User
defined
9. HVSideU2Stage2VoltSet 40~100.00 100 V
10. HVSideU2Stage2Time 0.00~100.00 100 s
11. HVSideInvTimeU2Stage1CoefA 0.001~1000 10 s
12. HVSideInvTimeU2Stage1IndexP 0.01~10.00 10
13. HVSideInvTimeU2Stage1TimeB 0.000~100.00 100 s
14. HVSideInvTimeU2Stage1ConstT 0.025~1.5 0.025
15. HVSideU2RstTime 0.000~100.00 0.04 s
16. HVInvTimeU2MinTripTime 0.100~100.00 0.1 s
Note: Negative sequence voltage protection logic switch of medium

voltage side is the same to that of high voltage side
Table 74 Negative sequence voltage protection logic switch on high voltage side (2 stage is
the same as 1 stage)
1. HVSideU2Stage1On 1/0 0 1-On, 0-Off

2. HVSideU2Stage2On 1/0 0 1-On, 0-Off
127
Note: Negative sequence voltage protection logic switch of medium

voltage side is the same to that of high voltage side
3.3 Report list


Trip report:
1. HVSideU2Stage1Trip /
2. HVSideU2Stage2Trip /
3. MVSideU2Stage1Trip /
4. MVSideU2Stage2Trip /
3.4 Technical data

Table 76 Negative sequence voltage protection technical data
Trip voltage 3U2 40.0V to 100V, step 0.01V ≤ ±5% setting or ±1V
(self-produce)
Time setting 0.00 to 100.00s, step 0.01s ≤ ±1% setting or +60 ms,
when trip voltage is set as
120% of setting
Trip voltage 3U2 40V～100V, step 0.01V, ≤ ±5% setting or ±1V
(self-produce)
IEC standard curve Normal inverse time; U U set
Very inverse time; In the case of 2< 2 / 2
Extreme inverse time; <20, the allowable trip time
Long inverse time; error is: ± 5% or +60 ms;
ANSI standard curve Standard inverse time; U U set
Short inverse time In the case of 2< 2 / 2
Long inverse time; <20, the allowable trip time
Normal inverse time; error is: ± 5% or +60 ms;
Very inverse time;
User defined curve   U U set
In the case of 2< 2 / 2
 
 A  <20, it meets the
= T= t  + B ⋅T
P IEC60255-151 standard
  U2  −1 
 U 2set  
time : A
Time delay of inverse time B 0.000 to 100.00, step 0.01
128
Chapter 15 Undervoltage protection (27)
Chapter 15 Undervoltage protection

(27)
About this chapter

This chapter describes the principles of undervoltage
protection, the input and output signals, setting parameters,
129
1 Overview
Undervoltage protection can effectively protect the power equipment from
the impact of voltage drop.
The main features of undervoltage protection are as follows:
1) It provides 2 stages of protection, and definite and inverse time can be
selected.
2) Undervoltage protection voltage can be selected as phase-to-earth
voltage or phase-to-phase voltage.
3) Undervoltage blocking current check.
4) Detection of circuit breaker state
5) VT failure detection, VT failure blocking undervoltage protection.
6) Dropoff coefficient is adjustable.

The input and output signals of undervoltage protection function diagram
are shown below, left side is input and right side is output:
Undervoltage Protection
1
Start
2
Operation
Figure 61 The input and output signal diagram of undervoltage protection function
Output:
UV Start IED startup
Operation IED trip
IED consists of four stages of undervoltage protection, phase-to-earth
voltage or phase-to-phase voltage, alarm or tirp and definite time or
inverse time are selectable, please refer to setting list for details. The
undervoltage protection stage 1 will be taken as an example below and the
principle will be introduced.

Undervoltage protection can provide three stages protection, with the
changeable definite/inverse time. Take the undervoltage 1 stage as the
example, it can be enabled or disabled via the enabled/disabled platen
"UVStage1On". With the enabled logic switch "UVChkPEVolt", the
undervoltage protection operation voltage setting can choose
phase-to-earth voltage UA-N, UB-N, UC-N, otherwise, it chooses
phase-to-phase voltage UA-B, UB-C, UC-A.
130
With the limit of field condition, the voltage transformer of the circuit
breaker may be connected to the power supply side or the load side. The
installation position of VT is different, and the operation characteristics of
undervoltage protection are different. As the undervoltage protection starts
tripping and the breaker is off, the voltage beside power supply stays
unchangeable but the voltage beside load drops to zero, now undervoltage
protection resets. If the voltage transformer is installed on the power
supply side, and does not want to protect the undervoltage detection
current, the setting of "UVChkCurrOn" can be set to 0. In addition, the
undervoltage protection can also be controlled by the word
"UVChkCBState" to choose whether the action logic is to detect the circuit
breaker status. When the undervoltage protection is required to check the
circuit breaker state, the undervoltage protection sends out the trip
command only when the circuit breaker is closed. If the voltage
transformer is installed on the power supply side, and does not want the
undervoltage protection to check circuit breaker status, the logic switch
"UVChkCBState" is set to 0.
3.1.1 Blocking condition
When "UVChkCBState"=1, circuit breaker will be checked at blocking
protection during the trip, with non-blocking protection starting and
blocking protection delaying.
When the maximum value of the three-phase current is less than
"UVCurrSet", the blocking is protected, the non-blocking protection starts,
and the blocking is delayed.
As VT failure blocking is 1, the blocking is protected, the non-blocking
protection starts, and the blocking is delayed.
When "UVChkPEVolt"=1, and three-phase voltage is lower than
"3PhUVBlkSet", or when "UVChkPEVolt"=0 and three-phase voltage is
lower than the 1.732 times of "3PhUVBlkSet", the blocking is protected,
and the blocking protection starts.
3.1.2 Definite time
When "UVStage1CurveSel"=0, undervoltage is the definite time
characteristic, and inverse time function is disabled.
U < “UVStage1VoltSet”
When the voltage is lower than the setting "UVStage1VoltSet", ther timing
component will start and work until the setting "UVStage1Time", and
undervoltage protection trips. When
current U < Dropout × ”UVStage1VoltSet” , timing component drops out,
undervoltage protection drops out.
3.1.3 Inverse time
When "UVStage1CurveSel"=1~4, undervoltage is the definite time
characteristic, and inverse time function is disabled.
 
 
A
=t  + B  ⋅T
  U P 
1 −   
 Uset  
131
If the voltage is lower than "UVStage1VoltSet", the timing component

starts, inverse time characteristic curve is selected by
"UVStage1CurveSelection", A, P, B are determined when the value is from
1 to 3, see Table 3; when the value is 4, it is the user defined
characteristics, calculate the trip delay in accordance with the setting of the
A, P, B, T. timing, undervoltage protection trips. When the calculated delay
time is less than the "InvTimeUVMinTime", the component will trip in
accordance with the "InvTimeUVMinTime".
Where:
A: "InvTimeUVStage1CoefA"
P: "InvTimeUVStage1IndexP"
B: "InvTimeUVStage1TimeB"
T: "InvTimeUVStage1ConstT"
U : Voltage
Uset :"UVStage1VoltSet"
0. Definite time
1. Curve1 1 1 0
2. Curve2 40 2 1
3. Curve3 5 2 2
4. User defined

When undervoltage protection is enabled and there is no binary input
blocking, if "UVStage1On"=1, then undervoltage protection of the
corresponding stage is enabled.
When "UVChkPEVolt"=1, check phase-to-earth voltage; when
"UVChkPEVolt"=0, check phase-to-phaser voltage.
While "3PhVoltConnect"=1, three phases can be equipped with "OR" logic
and the protection starts while at least one voltage is lower than the setting;
it can also be equipped with "AND" logic, and the protection starts while
three voltages are all lower than the setting.
While "3PhVoltConnect"=0, that is, the single phase VT is connected, it is
fixed as the "AND" logic and need to take the maximum phase-to-earth
(phase-to-phase) voltage to judge.
Undervoltage protection is tripped, after the starting of protection trip, if the
action conditions are met, timing component starts, take stage 1 for
example, when time is over, "UVStage1Trip" is issued. LED and protection
trip can be configured by AESP.
The three-phase analog quantity U1, U2 and U3 of the trip time issued
when the undervoltage protection trips, the element is based on the
phase-to-earth voltage judgment, it issues three-phase phase-to-earth
132
voltage; when it is based on the phase-to-phase voltage judgment, it

issues three-phase phase-to-phase voltage.
3.1.5 Logic diagram
Ua<“UVStage1VoltSet”
≥1
&
Ub<“UVStage1VoltSet”
Uc<“UVStage1VoltSet”
“UVChk1Ph”=1 ≥1
“UVChk1Ph”=0
Ua<“UVStage1VoltSet”
& &
&
Ub<“UVStage1VoltSet”
Uc<“UVStage1VoltSet”
≥1
“UVChkPEVolt”=1 Undervoltage Stage 1
Protection Startup
“UVChkPEVolt”=0
Uab<“UVStage1VoltSet”
≥1
Ubc<“UVStage1VoltSet” & &
Uca<“UVStage1VoltSet”
“UVChk1Ph”=1
≥1
“UVChk1Ph”=0
Uab<“UVStage1VoltSet”
&
&
Ubc<“UVStage1VoltSet”
Uca<“UVStage1VoltSet”
133
“UVStage1On”=1
Under Voltage Stage1 Protection Startup
Binary Blocking
CB Trip Position &

≥1
“UVChkCBState”=1 &
T1 Under Voltage Stage1
Protection Trip
“UVChkCBState”=0
max(Ia,Ib,Ic)>“UVCurrSet” &
≥1
≥1
“UVChkCurrOn”=1
“UVChkCurrOn”=0
VT Failure blocking
Ua<“3PhUVBlkSet”
Ub<“3PhUVBlkSet”
&
Uc<“3PhUVBlkSet”
“UVChkPEVolt”=1
≥1
“UVChkPEVolt”=0
Uab<“1.732×3PhUVBlkSet”
&
Ubc<“1.732×3PhUVBlkSet”
Uca<“1.732×3PhUVBlkSet”
T1：“UVStage1Time”
Figure 62 Low current protection logic diagram
3.2 Setting list

Table 79 Undervoltage protection setting on high voltage side
Default
value
0:reverse time
1: A-1;P-1;B-0
1. HVSideUVStage1CurveSel 0~4 0 2: A-40;P-2;B-1
3: A-5;P-2;B-2
4: User defined
2. HVSideUVStage1VoltSet 5.00~150 100 V
3. HVSideUVStage1Time 0.00~120.0 120 S
4. HVSideInvTimeUVStage1A 0.001~1000 10
5. HVSideInvTimeUVStage1P 0.01~10.00 10
6. HVSideInvTimeUVStage1B 0.000~100.00 100 s
7. HVSideInvTimeUVStage1tT 0.025~1.5 0.025
0:reverse time
1: A-1;P-1;B-0
8. HVSideUVStage2CurveSel 0~4 0 2: A-40;P-2;B-1
3: A-5;P-2;B-2
4: User defined
9. HVSideUVStage2VoltSet 5.00~150 100 V
10. HVSideUVStage2Time 0.00~120.0 120 S
134
Default
value
11. HVSideInvTimeUVStage2A 0.001~1000 10
12. HVSideInvTimeUVStage2IndexP 0.01~10.00 10
13. HVSideInvTimeUVStage2TimeB 0.000~100.00 100 s
14. HVSideInvTimeUVStage2ConstT 0.025~1.5 0.025
15. HVSideUVChkCurrSet 0.0 5n ~ 40 In 10 A
16. HVSideUVMinVoltSet 0.000~40.00 2 V
17. HVSideUVDropoffCoef 1.00~2.00 1
18. HVSideUVRstTime 0.000~100.00 0.0 s
19. HVInvTimeUVMinTripTime 0.100~100.00 0.1 s
Note: Undervoltage common setting of medium voltage side is the same to
Table 80 Undervoltage protection logic switch of high voltage side
Set Default
mode value
1-low voltage stage 1 of high voltage
1. HVSideUVStage1On 1/0 0 side on, 0-low voltage stage 1 of high
voltage side off
1-low voltage stage 2 of high voltage
2. HVSideUVStage2On 1/0 0 side on, 0-low voltage stage 2 of high
voltage side off
1-Enable undervoltage check current
of high voltage side; 0-Disable
3. HVSideUVChkCurrOn 1/0 0
undervoltage check current of high
voltage side
1-undervoltage check CB state of high
4. HVSideUVoltChkCBState 1/0 0 voltage side on; 0-undervoltage check
CB state of high voltage side off
1-undervoltage check phase 1 voltage
of high voltage side; 0- undervoltage
5. HVsideUVChk1Ph 1/0 0
check phase 3 voltage of high voltage
side
1-undervoltage check phase-to-earth
voltage of high voltage side; 0-
6. HVSideChkPEVolt 1/0 0
undervoltage check phase-to-phase
voltage of high voltage side
Note 1: it is fixed with three phase voltage connection.
Note 2: Undervoltage protection logic switch of medium voltage side is the
3.3 Report list

Table 81 Report list (2 stage is the same as 1 stage)

Trip report:
1. HVSideUVStage1Trip /
2. HVSideUVStage2Trip /
3. MVSideUVStage1Trip /
4. MVSideUVStage2Trip /
135
3.4 Technical data

Table 82 Undervoltage protection technical data
Accessed voltage PPVolt or phase-to-earth ≤ ±2.5% setting or ±1V
voltage
Phase voltage setting value 5V～75V, step 0.01V, ≤ ±2.5% setting or ±1V
Line voltage setting 10V～150V, step 0.01V, ≤ ±2.5% setting or ±1V
DropoffCoef 1.00～1.05, step 0.01 ≤±3% setting
Time setting 0.00s～120.00s, step 0.01s ≤ ± 1% times of setting or
+60ms, when trip value is set
at 80% of setting
Reset time ≤ 50ms
Phase voltage setting value 5V～75 V, step 0.01V, ≤ ±2.5% setting or ±1V
Line voltage setting 10V～150V, step 0.01V, ≤ ±2.5% setting or ±1V
IEC 60255-127
In the case of 0.05< U / Uset
<0.5, the allowable trip time
error is: ± 5% or +60 ms;
User defined curve   ≤ ±5% setting or +40ms,
  when 2< U / Uset <20, it
A
=t  + B  ⋅T
meets IEC60255-151
  U P 
1 −    standard
 Uset  
time : A
Time delay of inverse time 0.000 to 100.00, step 0.01
B
136
Chapter 16 Thermal overload protection (49)
Chapter 16 Thermal overload

protection (49)
About this chapter

This chapter describes the principles of thermal overload
137
1 Overview
Thermal overload protection protects the device against overheating
caused by overload. Overheating can affect insulation characteristics of
insulation material between transformers, lines and other electrical
equipment. In fact, if the device temperature exceeds the allowable
operating temperature, the insulation material will accelerate aging.
Therefore, special protection should be provided to prevent the protected
equipment from excessive temperature. Since the temperature is
proportional to the square of the current, the thermal overload protection is
based on the square of the measured current flowing through the
protected device. In addition, due to the cumulative effect of over
temperature, the thermal overload protection needs to consider the
historical thermal effect of the device. The device realizes the above
functions by providing a thermal model of the simulated protected device.
In this way, the thermal overload protection of the device has the ability of
memory, which can consider the historical overload and heat loss.

The input and output signals of thermal overload protection function are
Thermal Overload Protection
1
Start
2
ACT1
3
ACT2
4
ACT3
Figure 63 The input and output signals of thermal overload protection function diagram
Output:
Start IED startup

Stage 1 alarm of thermal
ThermOL ACT1
overload
Stage 2 alarm of thermal
ACT2
overload
Protection trip of thermal
ACT3
overload
The device provides 1 stage thermal overload trip stage and 2 stage
thermal overload alarm stage. The alarm stage needs to adjust the
"ThermalOLAlarmCoef", which means that the value of the alarm stage trip
setting is the product of the setting of the trip stage and the overload alarm
coefficient. The thermal overload protection function is realized by a
temperature model equivalent to the protected device. Temperature model
(low temperature curve or high temperature curve) is selected from
IEC60255-8 standard. Temperature model can be used to calculate the
138
temperature rise of each phase current. The maximum temperature rise

calculated from the three-phase current is the trip value of thermal
overload protection.

The temperature rise of each phase is calculated by the following formula:
dΘ I
τ + Θ = ( )2
dτ Iϑ
In which, τ is "ThermalTimeConst", and s is the unit; Iθ is

"ThermalOLCurrSet" that is the maximum permissible continuous thermal
overload current, Θ is the temperature rise of unit per unit time under
maximum allowable thermal overload current, I is the fundamental current
that is measured through the phases of the protected device.
Based on the difference model, the calculation formula of overload trip
time:
 I 2  I 2 
   −  P  
 I 
τ = τ ln   ϑ  2 ϑ  
I
  I  − 1 
  I ϑ  
 
Where, IP is the steady current before the overload, the formula is the heat
curve in the IEC60255-8 specification, and the trip time is calculated in
accordance with the cold curve, which is shown as follows:
  I 2 
   
 I 
τ = τ ln   ϑ 2 
  I  − 1
  I ϑ  
 
Thermal overload protection can reflect the current fundamental frequency
component or RMS value trip, which are divided into stage 1 trip and stage
2 alarm, whenI > “ThermalOLCurrSet”, over heat protection starts, take
stage 1 alarm for example, when the thermal overload percentage reaches
"ThermalOLAlarmCoef1", the report "ThermalOLAlarmCoef1" is sent out;
when the thermal load percentage reaches 100%, the report
"ThermalOLTrip" is sent out. Light, protection trip and others can be
configured by AESP after the alarm or trip report is issued.
While alarming or tripping, three-phase current value Ia, Ib, Ic of trip
moment and each phase of trip moment are sent out.
When overheating protection is enabled, three-phase thermal
accumulative percentage is sent out timely by ThermalA, ThermalB, and
ThermalC.
The stop load current is 0, and the time coefficient of the equipment in the
process of heat dissipation is the product of "ThermalOLCoolingCoef" and
"ThermalTimeConst".
139
3.2 Setting list

Table 84 Thermal overload protection setting of high voltage side
Default
value
0.05In~40
1. HVSideThermalOLCurrSet 10 A
In
2. HVSideThermalTimeConst 6~9999 60 s
3. HVSideThermalOLCoolingCoef 0.1~10 10
4. HVSideThermalOLAlarmCoef1 0.5~1 1
5. HVSideThermalOLAlarmCoef2 0.5~1 1
Note: Thermal overload protection setting of medium voltage side is the

Table 85 Thermal overload logic switch of high voltage side
Set Default
mode value
Thermal overload of high voltage
1. HVSideThermalOLOn 1/0 0
side input or output
Enabled and disabled thermal
2. HVSideThermalOLAlarm1On 1/0 0 overload of high voltage alarm
stage
Enabled and disabled thermal
3. HVSideThermalOLAlarm2On 1/0 0 overload of high voltage alarm
stage
1: hot curve of high voltage side; 0:
4. HVSideThermalCurve 1/0 0
cool curve
Note: Thermal overload logic switch of medium voltage side is the same to
3.3 Report list


Trip report:
Thermal overload protection of high voltage
1. HVSideThermalOLTrip
side sends off tripping order
Thermal overload protection of medium
2. MVSideThermalOLTrip
voltage side sends off tripping order
Alarm report:
1. HVSideThermalOLStage1Alarm
side sends off alarm 1 order
2. HVSideThermalOLStage2Alarm
side sends off alarm 2 order
3. MVSideThermalOLStage1Alarm
voltage side sends off alarm 1 order
4. MVSideThermalOLStage2Alarm
voltage side sends off alarm 2 order
140
3.4 Technical data

Table 87 Thermal overload protection technical data
Current setting 0.05In～40.00In ≤ ±2.5% setting or ±0.02In
Thermal overload protection
6s～9999s
heating time constant
Cooling coefficient of thermal
0.1～10
overload
 I eq2  IEC 60255–8,
IEC low-temperature curve τ = τ ln  2 2 
≤ ±5% times of setting or
 I eq − I θ  +40ms,
 I eq2 − I P2  IEC 60255–8,

IEC high-temperature curve τ = τ ln  2 2
≤ ±5% times of setting or
 I eq − I θ  +40ms,
141
Chapter 17 Circuit Breaker Failure protection (50BF)
Chapter 17 Circuit Breaker Failure

protection (50BF)
About this chapter

circuit breaker failure protection function.
143
1 Overview
CBF protection can detect whether CBF is operating or not during the fault
clearance. This protection can clear the fault by tripping the breaker of
corresponding busbars as fast backup protection. Once there is a breaker
failure on feeder or transformer, the connected busbar can be
disconnected from the power grid by CBF protection. In addition, the
device sends out a trip order to the protection of other end of the feeder. In
the event of a circuit breaker failure with a busbar fault, IED sends the trip
command to the opposite of the feeder.
In order to improve the reliability of circuit breaker failure protection, the
current criterion is added. Three phase current, zero sequence current and
negative sequence current can be selected.
In order to avoid the other around circuit breaker trip caused by the error of
judgment, circuit breaker failure protection can be set to issue a trip
command to the local circuit breaker once again.
CBF protection has the characteristics as below:
1) 2 trip stages (local breaker retrip and trip the busbar)
2) Transfer trip command to the remote line end in second stage
3) Internal/ external initiation
4) Three-phase initiating failure
5) Breaker auxiliary contact check
6) Current criteria checking (including phase current, zero and negative
sequence currents)

The input and output signals of CBF protection function are shown below,
left side is input and right side is output:
Circuit-Breaker Failure Protection

1
CBOpenA
2 1
CBOpenB CBF_Init
3 2
CBOpenC BIAlarm
4 3
CBClose3P Trip1
5 4
BIInitCBF3P Trip2
6
BICBFail
7
TrInit3P
Figure 64 CBF protection function input and output signal diagram
144
Input:
CBOpenA Circuit breaker trip position A
CBOpenB Circuit breaker trip position B
BIConfig CBOpenC Circuit breaker trip position C
CBClose Circuit breaker close position
BIInitCBF3P External BI Initiation CBF

CBF Spring discharge binary
BICBFFail
input
Input:
TrInit3P Internal initiating failure signal
Output:
Circuit breaker failure startup
CBF CBF_Init
signal
Circuit breaker failure binary input
BIAlarm
is abnormal
Trip1 Circuit breaker failure stage I trip
Trip2 Circuit breaker failure stage II trip
3.1 Protection function
CBF protection can be enabled or disabled by setting the logic switch In
the case of the protection function is enabled, the protection function trips,
the relevant protection function start failure protection, and the timing of
the counter works until to setting time delay, and the time delay is set
to”CBFTime1". If the circuit breaker is still closed after the setting time,
circuit breaker failure protection will send trip command to trip the circuit
breaker (for example, through the secondary trip coil) If the breaker has no
response when the other time delay ”CBFTime2", then IED will send off trip
command to trip the corresponding breakers to isolate the fault (e.g. other
breakers on the same busbar connected with the failure circuit breaker).
After tripping, light, protection trip and others can be configured by AESP.
The internal and external protection function can both start circuit breaker
failure protection. If the external initiating function protection is failed, then
it needs to be equipped with "3PhaseCBFStartup".
CBF check includes two criteria. The first criterion is detecting the
disappeared current after issuing the trip command. The second criterion
is detecting the auxiliary contacts of breaker.
3.1.1 Current check
When the current is disappeared, the breaker is considered to be on the
open position. the first criterion (current criterion) is the most effective way
to detect the position of breaker. The current check, therefore, is used to
detect the breaker position in CBF protection. At this time, the current
145
measurement of each phase compares with the the setting of

'CBFCurrentValue'. Besides, the zero sequence ( 3İ0 = İA + İB + İC ) or
negative sequence (I2=IA+a2IB+aIC) current can also be used as current
criteria by setting the logic switch. If the IED is set to detect zero and
negative sequence current, then the zero and negative currents should be
compared with the corresponding settings separately.
&
Ia >“CBFCurrSet”
Calculate3I0 >“CBF3I0Set” ≥1
&
≥1 &
3I2 > “CBFI2Set”
Ib >“CBFCurrSet”
Ic >“CBFCurrSet”
“CBFChk3I0/I2”=1
&
Calculate3I0 >“CBF3I0Set” ≥1 ≥1
& CB Failure Current
≥1 & judged
3I2 > “CBFI2Set” by 3 Phase Current
&
Calculate3I0 >“CBF3I0Set” ≥1
&
≥1 &
3I2 > “CBFI2Set”
Figure 65 Breaker current detection logic diagram
3.1.2 Breaker auxiliary contacts check

The IED trip logic does not take the current component as the criterion and
the current criterion is not suitable for CBF protection. Circuit breaker
auxiliary contact position can be used to judge whether the circuit breaker
trips or not. If the logic switch “CBFChkPosn” is set as1, then breaker
auxiliary contact criterion is on. If the current criterion is not used in the IED,
then breaker auxiliary contact criterion is used to judge breaker position.
CB Trip Position &
3 Phase CB
Internal/External 3 & Close Position
Phase Initiating CBF
CBF Current Judged ≥1

By 3 Phase Current
Figure 66 Breaker auxiliary contact judgment logic diagram
146
3.1.3 CBF protection trip logic

T_alarm CBF BI Abnormal
External Startup &
Failure Signal
≥1
3 Phase Startup Failure
Internal Startup Failure Signal
T_alarm：“CBFBIAlarmTime”
Figure 67 The internal and external initiating CBF logic diagram
“CBFailureCheck
CBPosition” &
CB closed
≥1
Failure current determine &

3 phase with current 3 phase
failure initiation
3 phase initiation failure
Figure 68 Initiating CBF logic diagram

3-phase T1 Failure stage 1 trip
failure initiation
T1：“CircuitBreakerFailureTime1”
Figure 69 CBF state 1 trip logic diagram

3 phase T2
failure initiation ≥1
Failure stage 2 trip
&
0
CBFail input
T2：“CircuitBreakerFailureTime2”
Figure 70 CBF state 2 trip logic diagram
3.2 Setting list

Table 89 The settings of circuit-breaker failure protection of high voltage side
Default
value
1. HVSideCBFCurrSet 0.05In~40 In 40 A
2. HVSideCBF3I0Set 0.05In~40 In 40 A
3. HVSideCBFI2Set 0.05In~40 In 40 A
4. HVSideCBFTime1 0.00~100.00 100 s
5. HVSideCBFTime2 0.00~100.00 100 s

HVSideCBF
6. 0.00~100.00 100 s
BIAlarmTime
Note: Circuit breaker failure protection setting of middle and low voltage
side are the same to that of high voltage side
147
Table 90 CBF protection logic switch of high voltage side

Set Default
mode value
Enable/Disable
circuit breaker
1. HVSideCBFOn 1/0 1
failure of high
voltage side
Enable/Disable
circuit breaker
2. HVSideCBFChk3I0/I2 1/0 1 failure check zero
sequence current of
high voltage side
3. HVSideCBFChkPosn 1/0 1
Note: Circuit breaker failure protection logic switch of middle and low
voltage side are the same to that of high voltage side
3.3 Report list


Trip report:
1. HVSideCBFStarup /
2. HVSideCBFStage1Trip /
3. HVSideCBFStage2Trip /
4. MVSideCBFStartup /
5. MVSideCBFStage1Trip /
6. MVSideCBFStage2Trip /
7. LVSideCBFStarup /
8. LVSideCBFStage1Trip /
9. LVSideCBFStage2Trip /
Alarm report:
1. HVSideCBF BIErr /
2. MVSideCBF BIErr /
3. LVSideCBF BIErr /
3.4 Parameters
Table 92 CBF protection technical data
Current setting 0.05 In ~ 40.00 In ≤ ±2.5% setting or ±0.02In
Negative sequence current
setting
Zero sequence current
setting
Time 1 of circuit breaker 0.00s~100.00 s, step 0.01s ≤ ± 1% times of setting or +40
failure ms, when trip current is set
Time 2 of circuit breaker 0.00s~100.00 s, step 0.01s as 200% setting
failure
Reset time Less than20 ms
148
Chapter 18 Dead zone protection (50DZ)
Chapter 18 Dead zone protection

(50DZ)
About this chapter

dead zone protection.
149
1 Overview
IED provides dead zone protection to detect dead zone fault, i.e. when
breaker is in open position, a fault occurs between CT and breaker. So,
when breaker auxiliary contact shows that the breaker is in open position,
IED can detect fault current of dead zone.
For busbar side CT, when dead zone fault occurs, IED trips all breakers on
the busbar where the fault bay is located. Trip logic is shown as below:
TrIp
Busbar
IFAULT
Line 1 Line 2 Line N
Example:
CB open position
CB close position
Figure 71 Busbar side trip logic diagram

For CT at line side, when dead zone fault occurs, IED sends remote trip
command to the IED on the opposite side to isolate fault. Trip logic is
shown as below:
Interal trip
Busbar
IFAULT
Line
Line 2 Line N
1
Trip
装置
Example:
CB open position
CB close position
Figure 72 Line side trip logic diagram

The input and output signals of dead zone protection function diagram is
150
Dead Zone Protection

1 1
CBOpenA Start
2 2
CBOpenB Operation
3 3
CBOpenC Alarm
4
CBClose
5
BI_IntDZ
6
SigIntDZ
Figure 73 The input and output signals of dead zone protection function diagram
Input:

BIConfig
CBOpenC Circuit breaker trip position C
CBClose Circuit breaker close position

External startup dead zone binary
BIInitDZ
input
Input:
SinInitDZ Internal startup dead zone signal
Output:
CBF
Start IED startup
Operation IED trip

Abnormal alarm of external binary
Alarm
input
When dead zone protection function is enabled (En=1) and binary input
blocking is disabled, if "DZProtOn"=1, then the corresponding dead zone
protection is enabled.
The trip conditions are shown below:
1) Trip initiates dead zone flag SigIntDZ =1, or external IB initiates dead
zone 'BI_IntDZ =1' and no abnormal alarm of external BI;
2) There should be open position but no close position;
3) I∅ > “DZCurrSet”, (∅ = a, b, c);
4) Enabled or disabled the criterion of zero current and negative sequence current
by setting the logic switch " DZChk3I0/3I2 ". If the logic switch is set as 1, the
zero or negative sequence current is also necessary to be larger than the
corresponding setting.
If the trip conditions are met, time component starts, when time is over,
"DZTrip" is issued. LED and protection trip can be configured by AESP. At
the same time, the three-phase fundamental current values Ia, Ib, Ic, zero
151
and negative sequence current of trip time are displayed. When current or
breaker position is not satisfied, timing component returns, dead zone
protection resets. When the existing time of external BI initiating dead zone
is longer than the alarm time, "DZ BIErrAlarm”will be issued. LED and
&
“DZChk3I0/I2”=0
Ia>“DZCurrSet”
Ib>“DZCurrSet”
& ≥1
≥1 &
Ic>“DZCurrSet”
3I0>“DZ3I0Set”
3I2>“DZI2Set”
“DZChk3I0/I2”=1
“DZChk3I0/I2”=0
&
Ib>“DZCurrSet”
Ic>“DZCurrSet”
& ≥1 ≥1
≥1 & Dead zone current
Ia>“DZCurrSet” condition satisfied
3I0>“DZ3I0Set”
3I2>“DZI2Set”
“DZChk3I0/I2”=1
“DZChk3I0/I2”=0 &
Ic>“DZCurrSet”
Ib>“DZCurrSet”
& ≥1
≥1 &
Ia>“DZCurrSet”
3I0>“DZ3I0Set”
3I2>“DZI2Set”
“DZChk3I0/I2”=1
Dead zone protection on
BI blocking
Dead zone current condition satisfied

&
&
3 phase trip T
Dead zone protection trip
≥1
Protection trip initiate dead zone
&
Outside initiate T_BIErr

dead zone BI
Dead zone protection

BI abnormal alarm
“DZProtOn”=1
T：“DZTripTime”
T_BIErr：“BIErrTime”
Figure 74 Dead zone logic diagram
152
3.2 Setting list

Table 94 Dead zone protection setting of low voltage side
Default
value
1. LVSideDZCurrSet 0.05In~40 In 40 A
2. LVSideDZTime 0~100 100 s
3. LVSideDZProt3I0Set 0.05In~40 In 40 A
4. LVSideDZProtI2Set 0.05In~40 In 40 A
5. LVSideDZ BIErrTime 0.00~100 100 s
Note: dead zone protection setting of low voltage side 1 is the same to that of low
voltage side
Table 95 Dead zone logic switch
Default
value
1. LVSideSideDZOn 1/0 0
2. LVSideDZChk3I0/I2 1/0 0
Note: dead zone protection logic switch of low voltage side 1 is the same to that of low
voltage side
3.3 Report list


Trip report:
1. LVSideDZTrip /
Alarm report:
1. LVSideDZ BIErrAlarm /
3.4 Technical data

Table 97 Dead zone protection technical data
Current setting 0.05In～40.00In ≤ ±2.5% setting or ±0.02In
Time setting 0.00s～100.00s, step 0.01s ≤ ±1% times of setting or
+40ms, when trip current is
set as 200% setting
153
Chapter 19 Stub protection (50STUB)
About this chapter

This chapter describes the protection principle, the input and
output signals, fixed value parameters, messages and
technical parameters for stub protection.
155
1 Overview
The stub protection protects the zone between the CTs and the
dis-connectors. The stub protection is enabled when the open position of
the dis-connector is informed to the IED through connected binary input.
The function has 2 stages of definite time at high voltage and medium
voltage side seperately.

The input and output signals of differential protection function diagram are
STUB-Bus Overcurrent Stage

1 1
STUB_Enable Start
2
Operation
3
APhase
4
BPhase
5
CPhase
Figure 75 The input and output signals of stub protection function diagram
Input:
BIConfig STUB_Enab
Isolation position signal input
le
Output:
Start IED startup
Operation IED trip

STUB
APhase Phase A trip
BPhase Phase B trip
CPhase Phase C trip
The stub protection is an overcurrent protection which is only in service if
the status of the line disconnector indicates the open condition. Stub
protection is disabled while the disconnector is at the close position. The
stub protection stage provides one definite time stage with settable delay
time. This protection function can be enabled or disabled via the logic
switch. Corresponding current setting value can be inserted in setting.
When the current is greater than the setting value and the time delay is
over, the IED sends out "StubTrip". LED and protection trip can be
156
configured by AESP.
Ia>“StubCurrSet”
≥1
Ib>“StubCurrSet”
Ic>“StubCurrSet”
&
Isolator in the open position T
Stub protection trip
BI blocking
“StubOn”=1
T：“StubTime”
Figure 76 Stub protection function logic

Bus line A
CB1
STUB-Bus
CT1 Overcurrent fault
Line1
Switch1
CB3
CT3
Line2
Switch2
CT2
CB2
Bus line B
Figure 77 Logic diagram of application scenarios
3.2 Setting list

Table 99 Stub protection setting of high voltage side
Default
value
Current setting of stub
0.05In~40
1. protection stage 1 of high 40 A
In
voltage side
2. HVSideStubStage1ProtTime 0~100 100 s
0.05In~40
3. HVSideStubStage2ProtTime 40 A
In
4. HVSideStubStage1ProtTime 0~100 100 s
5. HVSideStubRstTime 0~100 40 s
157
Note: Stub protection setting of medium voltage side is the same to that of
high voltage side
Table 100 Stub protection logic switch of high voltage side
Set Default
mode value
1. HVSideStubStage1On 0/1 0 0: Off; 1: On;
2. HVSideStubStage2On 0/1 0 0: Off; 1: On;
Note: Stub protection logic switch of medium voltage side is the same to
3.3 Report list


1. HVSideStubStage1Trip /
2. HVSideStubStage1PhATrip /
3. HVSideStubStage1PhBTrip /
4. HVSideStubStage1PhCTrip /
5. HVSideStubStage2Trip /
6. HVSideStubStage2PhATrip /
7. HVSideStubStage2PhBTrip /
8. HVSideStubStage2PhCTrip /
9. MVSideStubStage1Trip /
10. MVSideStubStage1PhATrip /
11. MVSideStubStage1PhBTrip /
12. MVSideStubStage1PhCTrip /
13. MVSideStubStage2Trip /
14. MVSideStubStage2PhATrip /
15. MVSideStubStage2PhBTrip /
16. MVSideStubStage2PhCTrip /
3.4 Technical data

Table 102 Stub protection technical parameters
Current setting 0.05 In～40.00In ≤ ±2.5% times of setting or
±0.02In
Time setting 0.00s～100.00s, step 0.01s ≤ ±1% times of setting or
+40ms, when trip current is
set as 200% setting
158
Chapter 20 Pole discrepance protection (62PD)
Chapter 20 Pole discrepance

protection (62PD)
About this chapter

pole discrepance protection.
159
1 Overview
Under normal operating condition, all three poles of the circuit breaker
must be closed or open at the same time. The split phase operating circuit
breakers can be in different positions (close-open) due to electrical or
mechanical failures. This can cause negative and zero sequence currents
which gives thermal stress on rotating machines and can cause unwanted
operation of zero sequence or negative sequence current functions.
Single pole opening of the circuit breaker is permitted only in the short
period related to single pole dead times, otherwise the breaker is tripped
three pole to resolve the problem. If the problem still remains, the remote
end can be intertripped via circuit breaker failure protection function to
clear the unsymmetrical load situation.
The pole discrepance function operates based on information from
auxiliary contacts of the circuit breaker for the three phases with additional
criteria from unsymmetrical phase current.

The pole discrepancy protection function diagram is shown below, left side
is input and right side is output:
Pole-Discrepancy Protection
1 1
CBOpenA Start
2 2
CBOpenB Operation
3
CBOpenC
Figure 78 Pole discrepancy protection function input and output signals diagram
Input:

BIConfig
CBOpenC Circuit breaker trip position C
Output:
PD Start IED startup: timer starts

Operation IED trip
The CB position signals are connected to IED via binary input in order to
monitor the CB status. Poles discordance condition is established when
logic switch of three-pole discrepance is enabled, and at least one pole is
160
open and at the same time not all three poles are closed. The auxiliary
contact of the circuit breaker is inspected by the corresponding phase
current. When the auxiliary contact signal of the breaker is indicated as a
division, the current is in phase, and after the 5S, the device alarm is made
of "PDProtTripPosnErr". LED and protection trip can be configured by
AESP.
In addition, criterion for zero sequence current and negative sequence
current can be enabled or disabled through logic switch under this function.
Pole discrepance can be detected when current is not flowing through all
three poles. When current is flowing through all three poles, all three poles
must be closed even if the breaker auxiliary contacts indicate a different
status.
3.2 Logic diagram

Pole discrepance protection logic diagram is as below:
Circuit breaker trip positionA &
Ia > 0.06In
Circuit breaker trip positionB & ≥1
Ib > 0.06In
Circuit breaker trip positionC &
Ic > 0.06In
&
5s
“PDProtOn” 3 phase PD trip abnormal
Circuit breaker trip positionA
&
Circuit breaker trip positionB
Circuit breaker trip positionC
Circuit breaker trip positionA &
&
Ia < 0.06In T_PD 3 phase PD
protection trip
Circuit breaker trip positionB & ≥1
Ib < 0.06In
Circuit breaker trip positionC &
Ic < 0.06In
3I2 > 3I2Set ≥1
3I0 > f3I0Set
&
≥1
“PDChk3I0/3I2”=1
“PDProtOn”=1
3I2Set：“PD3I2Set”
3I0Set：“PD3I0Set”
T_PD：“PDTripTime”
Figure 79 Pole discrepance protection logic diagram
161
3.3 Setting list

Table 104 Three-phase unbalanced protection setting of low voltage side
Default
Range
(In:5A/1A)
(In:5A/1A)
1. LVSidePD3I0Set 0.05In~40In 40 A
2. LVSidePDI2Set 0.05In~40In 40 A
3. LVSidePDTripTime 0~60 10 s
Note: dead zone protection three-phase unbalanced setting of low voltage side 1 is the
same to that of low voltage side
Table 105 Three-phase unbalanced protection logic switch of low voltage side
Set Default
mode value
1. LVSidePDOn 0/1 0 1-On, 0-Off
2. LVSidePDChk3I0/I2 0/1 0 1-Check, 0-Not check
Note: dead zone protection three-phase unbalanced logic switch of low voltage side 1 is
the same to that of low voltage side
3.4 Report list


Trip report:
1. LVSidePDTrip /
2. LVSidePDProtTripPosnErr /
3.5 Technical data

Table 107 Pole discrepance protection technical parameter
Current 0.05In to 40.00In ≤ ±3% setting or ±0.02In
Time delay 0.00s to 100.00s, step 0.01s ≤ ±1% setting or +40 ms,
when 200% setting
DropoffCoef >0.95
162
Chapter 21 Overexcitation protection（24）
Chapter 21 Overexcitation protection

(24)
About this chapter

This chapter describes the Overexcitation protection principle,
the input and output signals, fixed value parameters,
163
1 Overview
The overexcitation protection is used to detect impermissible
overexcitation conditions which can endanger power transformers. The
saturation of the iron core and large eddy current losses led by the
situation that the transformer flux exceeds the related values can cause
impermissible temperature rise in transformer core.
This protection function has the following characteristics:
1) The alarm or trip of the three stages of definite time can be selected
respectively, the alarm or trip of one stage of inverse time can be
selected respectively.
2) Phase voltage and line voltage is available.

The input and output signals of overexcitation protection function diagram
Overexcitation Protection
1
bDefStart
2
bDefAlarm
3
bDefOp
4
bInvStart
5
bInvAlarm
6
bInvOp
Figure 80 The input and output signals of overexcitation protection function diagram
Output:
bDefStart Definite time start
bDefAlarm Definite time alarms
bDefOp Definite time trips

Inverse time startup (used only to
OFlux
bInvStart configure the number of inverse
time stages)
Inverse time alarm (used only to
bInvAlarm configure the number of inverse
time stages)
Inverse time trip (used only to
bInvOp configure the number of inverse
time stages)
Overexcitation will occur when the load uncouples from system and
voltage regulator can't control the increase of voltage promptly. Similarly,
the overexcitation condition may occur as result of a decrease in frequency,
164
e.g. isolated system. To protect the power transformer in such conditions,

the overexcitation protection function should start operating when the flux
exceeds the permissible limit value of transformer core. The ratio of
overexcitation protection function measures the voltage to frequency (U/f)
is proportional to the flux density B in transformer core, comparing to the
rated flux density BN. The decision is then made based on the calculated
ratio as is shown in below equation.
B U f
N= =
BN U N f N
Where N is the comparation bnetween the voltage and the frequency

calculated by the device.
U and f are the measured voltage and frequency
UN and fN are the rated voltage and frequency of the device.
While the rated frequency is fixed to 50Hz or 60Hz in software, device is
informed about rated voltage by setting “ReferenceVolt” which
corresponds to nominal phase-neutral voltage of the protected transformer
when is transferred to secondary value, using the turn ratio of voltage
transformer. Thus, the use of the overexcitation protection presumes that
measured voltage is connected to the device. Calculation of voltage/hertz
ratio above is performed based on the maximum voltage of the three
phase-neutral or phase-phase voltages. Logic switch “OEUsePEVolt”
determines that overexcitation protection should use phase-to-phase
voltage or phase-to-earth voltage. "3PhVoltConnect" is 0, a line voltage is
input to the external, then the over excitation needs to check the line
voltage, namely "OEUsePEVolt" is 0
The overexcitation protection includes two inverse characteristics (alarm
and trip are optional)) and one thermal characteristic. The latter
characteristic provides an approximate replica of the temperature rise
caused by overexcitation in the protected object. The inverse time alarm
stage can be enabled or disabled by using logic switch "InvTimeOExcitOn".
Thermal characteristic can be enabled or disabled by "InvTimeOExcitOn".
It should be mentioned that the overexcitation protection can be applied at
HV, MV or LV side of the protected transformer. However, it is not
recommended to apply the function on the transformer side with variable
winding turns such as the transformer side with an installed tap changer.
The overexcitation protection uses phase-to-phase voltage or
phase-to-earth voltage of the corresponding side in their calculations,
based on the setting applied at logic switch “OEUsePEVolt”.
Take protection stage1 as an example, if the inverse time alarm is enabled,
and the calculated volt/hertz ration exceeds the setting value, then a report
“InvTimeOEAlarm” will be sent by the device after the time delay setting.
Similarly, if the trip inverse time is enabled, and the calculated volt/hertz
ration exceeds the setting value, a report “InvTimeOETrip” will be sent by
the device after the time delay expiration. Light of alarm and protection trip
can be configured by AESP.
If thermal characteristic is enabled in one of transformer sides, it uses the
measured voltage and frequency of the corresponding side, together with
the data from the manufacturer. The points correspond to the desired
tripping times for a given volt/hertz ratios. Intermediate values are
165
determined by performing linear interpolation by the device. The

overexcitation 1 stage factor can be set to 1.05, and the rest stages
increases by differential 0.05. Ratio range is
1.05~1.70(“InvTimeOEStage14Time”,1.70) The inverse times are set as
below: "InvTimeOEStage1Time", "InvTimeOEStage2Time",
"InvTimeOEStage3Time", "InvTimeOEStage4Time",
"InvTimeOEStage13Time", "InvTimeOEStage14Time", These points are
used to draw the inverse time characteristic curve, as shown in the
following figure:
u/f
V/F(T14)
V/F( T13)
V/F( T12)
V/F( T11)
V/F( T10)
V/F( T9)
V/F( T8)
V/F( T7)
V/F( T6)
V/F( T5)
V/F( T4)
V/F( T3)
V/F( T2)
V/F(T1)
T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 t(s)

Figure 81 Overexcitation characteristics
It can be observed from the above picture, N=1.05 is the starting threshold
of thermal characteristics stage; the calculated ratio of voltage/frequency is
lager than starting threshold and the thermal model increases from 0% to
100% through the counter. If the counter reaches to 100%, then IED trips.
When the voltage / frequency ratio is lower than the start threshold, the trip
signal will be canceled. According to the transformer cooling time, the
counter will be reduced to zero (the value of thermal model counter is from
100% to 0%). The cooling time is set as "OECoolingTime".
The inverse time characteristics shall take less than or equal to 14 points.
If the time delay setting of T1-T3 are set as 9999 seconds, then the inverse
time characteristic from the setting stage to stage T14 will be disabled.
166
3.2 Setting list

Table 109 Overexcitation protection setting
Default
Number Setting Range Unit Description
value
Voltage frequency
1. InvTimeOEStage1Time 0.1~9999 10 s
T1 time
Voltage frequency
T2 time
Voltage frequency
T3 time
Voltage frequency
T4 time
Voltage frequency
T5 time
Voltage frequency
T6 time
Voltage frequency
T7 time
Voltage frequency
T8 time
Voltage frequency
T9 time
Voltage frequency
T10 time
Voltage frequency
T11 time
Voltage frequency
T12 time
Voltage frequency
T13 time
Voltage frequency
T14 time
15. InvTimeOERstTime 0.00~100.00 0.04 s
Cooling time of
16. OECoolingTime 0.1~9999 25 s
overexcitation
17. DefTimeOEStage1TripSet 1~1.4 1.1
18. DefTimeOEStage1Time 0.1~9999 100 s
23. DefTimeRstTime 0.00~100.00 0.04 s
24. OEDropoffCoef 0.95~1.0 1.0

Rated value of
25. OEVoltRatedVal 10~120 57.74 V phase-to-earth
voltage
167
Table 110 Logic switch of overexcitation protection

Set Default
mode value
1. InvTimeOExcitOn 1/0 0 1-On, 0-Off
2. InvTimeOEAlarm 1/0 0 1-alarm, 0-trip
3. DefTimeOEStage1On 1/0 0 1-On, 0-Off
4. DefTimeOEStage1Alarm 1/0 0 1-alarm, 0-trip

1-phase-to-earth voltage;
9. OEUsePEVolt 1/0 0
0-phase-to-phase voltage
3.3 Report list


Trip report:
1. InvTimeOETrip /
2. DefTimeOEStage1Trip /
3. DefTimeOEStage2Trip /
4. DefTimeTimeOEStage3Trip /
Alarm report:
1. InvTimeOEAlarm /
2. DefTimeOEStage1Alarm /
3.4 Technical data

Table 112 Overexcitation protection technical data
Reference voltageUN 10V～120V ≤ ±3% setting or ±1V
Ratio: 1.00～1.70 ≤±2.5% setting or 0.01
Time delay 0.1s～9999s ≤ ±5% setting or ±70ms
1.05 /1.10 /1.15 /1.20 /1.25
V/F characteristics /1.30 /1.35 /1.40 /1.45 /1.50 ≤ ±5% setting or ±70ms
/1.55 /1.60 /1.65 /1.7
Dropoff ratio ≥0.96
≤±5% setting or ±70ms, under
time delay T 0.1s～9999s
the circumstance of twice trip
Dropoff ratio ≥0.96
168
Chapter 22 Underfrequency protection (81UF)
Chapter 22 Underfrequency
Protection (81UF)
About this chapter

This chapter describes the principles of underfrequency
169
1 Overview
Underfrequency protection is used to monitor whether the network is
normal by detecting the frequency. When the frequency is lower than the
underfrequency protection setting value and meet other conditions, the
underfrequency protection trips to remove the specified load.
The main features of underfrequency protection are as follows:
1) Undervoltage blocking
2) Frequency changing rate(df/dt) blocking;
3) Circuit breaker position check and loaded current blocking;
4) VT secondary circuit failure blocking.
5) Underfrequency protection configuring 1 stage protection, can be
enabled or disabled respectively.

The input and output signals of underfrequency protection function
diagram are shown below, left side is input and right side is output:
Under Frequency protection
1 1
CBOpen Start
2
Operation
Figure 82 The input and output signals of underfrequency protection function diagram
Input:
BinaryInput
CBOpen Circuit breaker trip position
Output:
UF Start IED startup
Operation IED trip
3.1.1 Protection function introduction
The principle of underfrequency and load shedding protection is "shed in
the line of interval". Specifically, the principle means that each interval will
be configured with underfrequency load shedding protection rather than
the incoming line interval will be configured with underfrequency load
shedding protection and send off tripping command through outlet line
interval. Then, every interval can be set with appropriate frequency
170
settings to start protection and with appropriate time settings to trip

protection. Based on "the principle of shedding in the line of intervals", the
device will be offered with 1 stages underfrequency load shedding
protection. Each stage will be enabled or disabled through corresponding
connector and underfrequency load shedding protection will be enabled
and disabled by principal connector, companying with each connector to
enable and disable. Trip frequency of underfrequency load shedding
protection can be tested by input three-phase voltage or single-phase
voltage. By enabling and disabling logic switch "3PhVoltConnect" to
choose the input voltage mode. Take underfrequency load shedding stage
1 as example, as the measured frequency is lower than settings
"UFLSStage1FreqSet", the timing component will start working; however,
as it delays to the definite time "UFLSStage1Time", the IED will send out a
command "UFStage1Trip". LED and protection trip can be configured by
AESP.
As the trip frequency of underfrequency load shedding protection is
calculated by measuring voltage, underfrequency load shedding protection
will be blocked with meeting the following requirement.
1) When three-phase voltage is connected, the lowest line voltage is
lower than settings, "LoadShedVoltBlkSet".
2) The device detects VT disconnection or the device will detect
high-level from VT disconnection;
3) When "UFLSChkCurrOn ", check current meets the blocking condition.
Loaded current is lower than settings, "LoadShedVoltBlkSet". As
voltage transformer is configured at the side of power supply, it is
useful to detect current setting. As the circuit is blocking,
"LoadShedVoltBlkSet" refers to as the smallest loaded current.
4) Circuit breaker is at open position. If it is in the same case, as voltage
transformer is configured at the side of power supply, it is useful to
detect current setting. Meanwhile, although the frequency is lower
than the underfrequency load shedding setting, the protection will not
send off trip command.
5) The frequency changing rate (Δf/Δt) succeeds setting value
"Df/dtBlkSet".
171
3.1.2 Logic diagram

“UFOn”=1 &
frequency<“UFFreqSet”
frequency<54Hz
&
or frequency>66Hz
System frequency=60Hz ≥1
frequency<45Hz
&
or frequency>55Hz
System frequency=50Hz
VT failure blocking
≥1
switch trip position
BI blocking
&
max(Ia,Ib,Ic)< ≥1 T1 Underfrequency
&
“LoadShedCurrBlkSet” protection trip
“UFLSChkCurrOn”=1
min(Uab,Ubc,Uca)<
&
“LoadShedVoltBlkSet”
“3PhVoltConnect”=1 ≥1
Frequency changing rate absolute value>

“Df/dtBlkSet” &
“UFLSChkDf/dt”=1
T1：“UFTime”
Figure 83 logic diagram of underfrequency protection
3.2 Setting list

Table 114 Underfrequency protection setting of high voltage side
Default
value
1. HVSideUFFreqSet 0.9Fn~1.0Fn 49.5 Hz
2. HVSideUFLoadShedTime 0.10~100.00 100 s

The frequency is
greater than the
3. HVSideDf/dtBlkFreqSet 0.9Fn~1.0Fn 49.5 Hz setting value, and
slippage locking
returns
4. HVSideFreqDf/dtBlkSet 0.30~20.00 20 Hz/s

Default
value
1. HVSideLoadShedVoltBlkSet 10.00~120.00 120 V
2. HVSideLoadShedCurrBlkSet 0.05In~10.0In 10 A
172
Table 116 Underfrequency protection logic switch of high voltage side

Set Default
mode value
Enable/Disable
underfrequency
1. HVSideUFOn 1/0 0
stage 1 protection
function
0: check current off;
2. HVSideUFLoadShedChkCurrOn 1/0 0
1: Check current
0: no check df/dt; 1:
3. HVSideUFChkDf/dt 1/0 0
Check df/dt
3.3 Report list


Trip report:
1. HVSideUFTrip /
3.4 Technical data

Table 118 Underfrequency protection technical parameter
Underfrequency load shedding
Rated frequency fn=50Hz 45.00Hz～50.00Hz, step 0.01Hz ≤±20mHz
Rated frequency fn=60Hz 54.00Hz～60.00Hz，step 0.01Hz ≤±20mHz
≤ ± 1.5% times of setting
Time setting 0.1s～100.00s, step 0.01
or +60ms
Blocking condition
Frequency changing rate
0.3Hz/s～20Hz/s ≤±0.5Hz/s
Δf/Δt
Blocking voltage setting 1.0V～120V, step 1V ≤ ±2.5% setting or ±1V
Blocking current setting 0In～10In ≤ ±2.5% setting or ±0.01In
173
Chapter 23 Overfrequency protection (81OF)
Chapter 23 Overfrequency protection

(81OF)
About this chapter

This chapter describes the principles of overfrequency
175
1 Overview
Overfrequency protection is used to monitor whether the network is normal
by detecting the frequency. When the frequency is higher than the
overfrequency protection setting value and meet other conditions, the
overfrequency protection trips to remove the specified load.
Main characteristics of overfrequency protection are as follow:
1) Undervoltage blocking;
2) VT secondary circuit failure blocking;
3) Overfrequency protection configuring 1 stage protection.

The input and output signals of overfrequency protection function diagram
Over Frequency protection
1
Start
2
Operation
Figure 84 The input and output signals of overfrequency protection function diagram
Output:
OF Start IED startup
Operation IED trip
3.1.1 Protection function introduction
The device offers 1 stages of overfrequency protection. Function of each
stage will be enabled or disabled through corresponding logic switch with
logic switch of each stage. The overfrequency protection trip frequency
can be measured by the input three-phase voltage or single phase voltage.
Enable/Disable logic switch "3PhVoltAccess" to choose the input voltage
mode. Note that if the access voltage is a single-phase voltage, then the A
phase or B phase voltage is required to be accessed to measure the
system frequency. Similarly, if the access voltage is a single phase
phase-to-phase voltage, then it needs to access the phase-to-phase
voltage UAB. No matter what kind of voltage access, the measurement
frequency is obtained by the measurement of the voltage frequency. Take
overfrequency stage 1 as example, if the measured frequency is higher
than setting value "OFFreqSet", the timing component will start timing. As
time delay reaches "OFTime", trip command will be sent.
176
As the trip frequency of overfrequency protection is calculated by

measuring voltage, overfrequency protection will be blocked with meeting
the following requirement.
1) When three-phase voltage is connected, the lowest line voltage is
lower than settings, "LoadShedVoltBlkSet".
2) The device detects VT disconnection or the device will detect
high-level from VT disconnection.
3.1.2 Logic diagram
“OFStage1On”=1 &
frequency>“OFFreqSet”
frequency<54Hz
&
or frequency>66Hz
System frequency=60Hz ≥1
frequency<45Hz
&
or frequency>55Hz
System frequency=50Hz
VT failure blocking
&
≥1 ≥1 T1 Over frequency
Protection trip
3 phase trip
BI blocking
min(Uab,Ubc,Uca)<
“LoadShedVoltBlkSet” &
“3PhVoltConnect”=1
T1：“OFTime”
Figure 85 Logic diagram of overfrequency protection
3.2 Setting list

Table 120 Overfrequency protection setting of high voltage side
Default
value
1. HVSideOFSet 1.00Fn~1.10Fn 50.5 Hz
2. HVSideOFTime 0.10~100.00 100 s

Default
value
1. HVSideLoadShedVoltBlkSet 10.00~120.00 120 V
2. HVSideLoadShedCurrBlkSet 0.05In~10.0In 10 A
Table 122 Logic switch of overfrequency protection of high voltage side

name value
Enable or disable overfrequency
1. HVSideOFOn 1/0 0
stage 1 protection function
177
3.3 Report list


Trip report:
1. HVSideOFTrip /
3.4 Technical data

Table 124 Overfrequency protection technical parameter
Overfrequency
≤ ±1.5% times of setting or
Time setting 0.1s～100.00s, step 0.01
+60ms
Blocking condition
Blocking voltage setting 10V～120V, step 1V ≤ ±2.5% setting or ±1V
178
Chapter 24 Non-electric protection
About this chapter

This chapter describes the principles of non-electric
179
1 Overview
Non-electric protection supports eight groups of consumer non-electric
tripping.

The input and output signals of non-electric protection function diagram
External trip initiation

1 1
BI Start
2
Operation
Figure 86 The input and output signals of non-electric protection function diagram
Input:
BI Non electric BI
ExtBI Output:
Start IED startup
Operation IED trip
External BI stay time reaches non-electric time setting, protection will trip.
“NonElectricGrp1On”=1 &
T1
Non-electric 1 protectin trip
Non-electric 1 BI
T1：“NonElectric1Time”
Figure 87 Non-electric protection 1 logic diagram
3.2 Setting list

Table 126 Non-electric protection setting
Default
value
1. NonElectric1Time 0~100 100 s
180
Default
value
9. NonElectricRstTime 0~100 0.04 s
Table 127 Non-electric protection logic switch

Logic switch Set Default
Number Remark
name mode value
1. NonElectric1On 1/0 1 1-On, 0-Off
3.3 Report list


Trip report:
1. NonElectric1Trip /
181
Chapter 25 Side differential protection
Chapter 25 Side differential

protection
About this chapter

This chapter describes the side differential protection
principle, input and output signals, parameter, IED report and
technical data for differential protection function.
183
1 Overview
The side differential protection detects earth faults in power trans-formers
with earthed starpoint or in non-earthed power transformers with a
starpoint former (earthing transformer/reactor) installed inside the
protected zone. A precondition for using this function is that a CT should be
installed in the starpoint connection, i.e. between the starpoint and earth.
The starpoint CT and the phase CTs define the limits of the protected zone
by side differential protection. It includes a side differential protection
functional module.

The input and output signals of restricted side differential protection
function are shown as below, the left side is input signals and right side is
output signals:
Side Differential Protection

1 1
En bStart
2 2
BIBlk Trip
3
Alarm
Figure 88 The input and output signals of side differential protection function diagram
No. Key Unit Type Description
Input:
1: function is on; 0: function is
1. En BOOL
off;
2. BIBlk BOOL 1: BI blocking
Output:
1. bStart BOOL IED startup
2. Trip BOOL IED trip
3. Alarm BOOL IED alarm
The side differential protection provided by the protection device can be
applied to the auto-transformer of CT in the common winding.
184
IA.2
A Ia.3
a
IB.2
Ib .3
B
b
IC .2
C Ic .3
c
3I01
3I02 = I A.2 + IB.2 + IC .2
CSC-326
3I03 = Ia.3 + Ib.3 + Ic.3
Figure 89 Application of side differential protection on an auto-transformer
The differential current Idiff and restricted current Irest are calculated as
the following equation:
 • • • •
I
 diff = I h1 + I h2 + I m + I g
 (1)
 • • • •
Irest = max{| I h 1 |,| I h 2 |,| I m |,| I g |}
• •
Where: I h1 is high voltage side 1 phase current; I h 2 is high voltage
•
side 2 phase current; I m is medium voltage side current by phase current
•
balance coefficient after conversion; I g is public winding current by

phase current balance coefficient after conversion.
Idiff and Irest are compared by the side differential protection with a
dual-slope operating characteristic defined by below equation and shown
in below figure.
I diff ≥ S1I res + I D > I res ≤ I R1 

I diff ≥ S2 ( I res − I R1 ) + S1 × I R1 + I D > I R1 < I res ≤ I R 2 

I diff ≥ S3 ( I res − I R 2 ) + S2 ( I R 2 − I R1 ) + S1 × I R1 + I D > I R 2 < I res 
(2)
Where, S1 is the slope 1 (setting "SideDiffSlope1RatioRestrCoef").
ID> is the threshold value of the side differential protection sensitivity (the
setting is “SideDiffStartupSet”);
IR1 is the first break point setting of restricted current
“SideDiffBreakPoint1CurrSet”;
185
IR2 is the second break point setting of restricted current

“SideDiffBreakPoint2CurrSet”;
If the operating point calculated from the quantities of differential and
restraint current falls into the trip area, a trip signal is issued by the percent
differential protection. The issued signals are phase selective. They can be
found in event report as “SideDiffPhATrip”, “SideDiffPhBTrip” and
“SideDiffPhCTrip”.
This side differential characteristic can be enabled or disabled by using
logic switch “SideDiffOn”). If setting “1-on” is selected, a trip signal is
issued by side differential protection when the operating point lies into
tripping area (see below figure).
The trip logic for side differential protection is shown in below figure.
I
differ
ential
Differential
Slope3
Trip area
current
Slope2 restraint
Slope1
area I
Differential restra
int
startup setting
I restraint point1 I restraint point2 Restraint current
Figure 90 Characteristic of side differential protection
186
“SideDiffOn”=1
Phase A
I diff − A , I rest − A
& Phase A trip of
ID
> side differential
Phase B
I diff − B , I rest − B
ID
>
Phase B trip of
&
side differential
Phase C
I diff −C , I rest −C
ID
>
Phase C trip of
&
side differential
“ CTFailBlkSideDiff”=1
&
CTFail
Figure 91 Tripping logic of the side differential protection

Side differential protection represents some problems in the application of
current transformers regarding to matching between phase and CTs of
common winding. The problem is originated from different ratio of phase
and CTs of common winding. The difference may result in a differential
current in normal operation condition. To remove this problem, the input
currents of the relay from CTs of common winding should be converted
according to primary rated currents of phase and CTs of common winding.
In this context, the ratio compensation factors are calculated as follow:
n Phase −W 2
KW 2 = (4)
n Phase −W 1
n Phase −WG
K WG = (5)
n Phase −W 1
Where, KW 2 is the ratio compensation factor for winding 2 (MV winding)
phase CT, is the ratio compensation factor for common winding CTs.
K WG
4.3 CT failure supervision
During steady-state operation, the CT failure supervision monitors the
transient behavior of the currents flowing through secondary circuit of each
phase and thus registers failures in the secondary circuit of the current
transformers for each side of the power transformer. The function can be
187
enabled or disabled by using setting “SideDiffCTFailDetectOn” (1-On,

0-Off). If setting “1-On” is applied whenever a CT failure is detected, IED
issues the alarm report. The differential protection can be configured as
whether the blocking is through CT failure by the logic switch
"SideDiffCTFailBlkDiff". By setting blocking through the logic switch, the
percent differential protection is blocked immediately in all phases when
CT failure occurs. Blocking condition is cancelled as soon as the device is
again supplied with a normal current in the relevant faulty phase(s).
The criteria for CT failure check are as follow:
The currents flowing through all three phases of CT secondary are normal
at each side of the protected object. As a result, the differential current is
near to zero. When one or two phase current of one side is decreased to
less than a threshold (half of the memory current), at the same time all
three phase currents in other side(s) are normal, and at least one phase
current is larger than a threshold (>0.3I_Percent Diff), the condition maybe
an indication of CT failure. CT failure check logic is illustrated in below
figure.
“SideDiffCTFailDetectOn”=1
Max {Idiff_A, Idiff_B, Idiff_C}>0.3*IDiffSet
{IHV_A, IHV_B, IHV_C}

only one phase or two phases
reduce.
&
{IMV_A, IMV_B, IMV_C}和 {IG_A, IG_B,
IG_C}
All current is unchanged.
{IMV_A, IMV_B, IMV_C} &

CT failure
reduce.
& ≥1
{IHV_A, IHV_B, IHV_C} 和 {IG_A, IG_B,
IG_C}
{IG_A, IG_B, IG_C}

reduce.
&
{IHV_A, IHV_B, IHV_C} 和 {IMV_A, IMV_B,
IMV_C}
IDiffSet“SideDiffStartupSet”
Figure 92 Logic diagram of side differential CT failure supervision
4.4 Side differential CT Saturation supervision

When Internal and external faults occurs, it is possible that transient and
steady fault currents induce the CT saturation. CT saturation may lead to
mal-operation of differential protection when an external fault occurs. In
order to avoid mal-operation of protection in such situations, CT saturation
supervision element is integrated in IED.
188
When transient saturation of CT occurs, the second harmonic content in

the corresponding phase current is dominant. Also whenever steady
saturation of CT occurs, the 3rd harmonic content in the corresponding
phase current is dominant. Both second and 3rd harmonic contents of all
phase currents of each side of the protected transformer are calculated to
judge whether CT saturation occurs or not. Comprehensive harmonic ratio
is calculated by below equation.
Iφ 2 Iφ 3
+ > K har
Iφ Iφ
Where:
Iφ2 is the secondary harmonic of current on each side;
Iφ3 is the third harmonic of current on each side;
Khar is the setting of comprehensive harmonic ratio, and the fixed setting
of software.
If the second and 3rd harmonic contents of any phase current are more
than Khar, then CT satisfies the above formulas and it is saturated. Usually
before the CT saturation status. there is a short time period in which CT
still works in its linear characteristic. By very fast CT saturation detection of
IED, it needs only 4ms before any CT saturation happening to detect the
fault which is internal or external fault. x In order to distinguish saturation
caused by internal faults and external faults effectively, percent differential
protection based on sample values is used. If CT saturation is induced by
external fault, differential protection will be blocked. However if CT
saturation is induced by internal fault, differential protection will send its trip
signal.
The typical saturation figure of phase A CT saturation is shown in below
figure.
Figure 93 Typical phase A current transformer Saturation waveform
4.5 Side differential current supervision

In normal operation condition, zero differential current is assumed in each
phase. The differential current supervision monitors the differential
currents and checks its value to be less than a threshold. An alarm report
is generated as “SideDiffCurrOverLmtAlarm” after 5s, if the differential
current exceeds the threshold value. The alarm is an indication of
189
miss-connection in CT secondary windings, and therefore is released to

remind user to detect the faulty connection in secondary circuit and
remove it. This function can be enabled or disabled by the logic switch
"SideDiffOn" (1-on, 0-off). The fixed threshold for releasing alarm is 0.3
times of “SideDiffStartupSet”. However, to avoid incorrect alarm, the
threshold value will increase to 0.1A (1A CT) and to 0.3A (5A CT) if 0.3
times of "DiffCurrSet" <0.1A. The equation is shown as below:
 I D.alarm =
max{0.3 I _ Percent Diff , 0.1A} if I n 1A

 I D.alarm =
max{0.3 I _ Percent Diff , 0.3 A} if I n 5 A
Logic of side differential current supervision is shown in below figure.
“SideDiffOn”=1
Idiff_A>ID.alarm
Current overlimit
Idiff_B>ID.alarm ≥1 & 5s alarm of side
differential
Idiff_C>ID.alarm
Figure 94 CT Fail detection logic

DANGER: Before side differential protection is put into operation on
site, polarity of current transformer must have been checked right by
an energizing test of every side of the transformer or a test of
simulating an external fault of the side in primary system. Otherwise
a mal-operation may occur during an external fault.
5 Setting list
Table 130 Side differential protection setting
Default
Range
(In:5A/1A)
(In:5A/1A)
Differential
1. SideDiffStartupSet 0.05In~4In 2 A Startup
Current Setting
The current
setting of first
2. SideDiffBreakPoint1CurrSet 0.1In~In 0.6 A
break point
(IR1)
The 2nd
breakpoint
3. SideDiffBreakPoint2CurrSet 0.1In~10In 2 A
restraint
current (IR2)
Ratio restraint
4. SideDiffSlope1RatioRestrCoef 0.00~0.2 0.2 coefficient of
the first slope
Ratio restraint
coefficient of
5. SideDiffSlope2RatioRestrCoef 0.2~0.7 0.5
the second
slope
Ratio restraint
6. SideDiffSlope3RatioRestrCoef 0.25~0.95 0.7 coefficient of
the third slope
190
Table 131 Side differential protection logic switch

Set Default
mode value
Enable ratial differential protection
1. SideDiffOn 0/1 0
1-enable, 0-disable
2. SideDiffCTFailDetectOn 0/1 0 CT failure test is on 1-On, 0-Off
CT failure blocking differential
3. SideDiffCTFailBlkDiff 0/1 0
1-blocking, 0-unblocking
6 Report list

Trip report:
1. SideDiffPhATrip
2. SideDiffPhBTrip Three-slope ratio differential phase A/B/C trip
3. SideDiffPhCTrip
Alarm report:
1. HVSideCTFail High voltage side CT failure
2. MVSideCTFail CT failure of medium voltage side
3. CommonWindCTFail Common winding CT failure
4. SideDiffCurrOverLmtAlarm Imbalance differential current alarm
7 Technical data
Table 133 Technical data for side differential protection
Side ratio differential current 0.05In to 4.00In ≤ ±3% setting or ±0.02In,
Side differential restraint
0.1In to 1In ≤ ±3% setting or ±0.02In
current 1
Side differential restraint
0.1In to10In ≤ ±3% setting or ±0.02In
current 2
Side differential slope 1 0.0 to 0.2
Side differential Reset ratio of
About 0.7
restrained differential
it ≤ 30ms when the setting is
Side differential operating
in 200% times, and
time of restraint differential
IDifferential>2IRestraint
191
Chapter 26 Secondary circuit supervision
Chapter 26 Secondary circuit

supervision
About this chapter

This chapter describes VT failure secondary circuit
monitoring function.
193
1 Overview
When the secondary circuit of the voltage transformer is broken or short
circuit, the measured voltage is zero by the protections based on the
undervoltage criterion and this can cause the mis-operation of IED. VT
failure check provides voltage monitoring for such protections. VT
monitoring is used to monitor the voltage transformer circuit, single-phase
VT failure, two-phase VT failure and three-phase VT failure. Main
characteristics is as follows:
1) Symmetry/ asymmetry (asymmetric) VT failure;
2) Three-phase AC voltage miniature transformer failure monitoring;
3) It is used in grounding system, non-direct grounding system and
ungrounded system.

The input and output signals of VT failure check function diagram is shown
below, left side is input and right side is output:
Symmetrical and asymmetrical
VT Fuse Fail Detection
1 1
V3P_BI VTFail
Figure 95 VT failure check function input and output signal diagram

Input:
BIConfig
V3P_BI Three-phase VT failure BI
Output:
VTFail
VTFail VT failure alarm
3.1.1. Protection function introduction
VT failure function can be enabled or disable by setting the logic switch
“VTFailOn”, when the logic switch is set as 1, VT failure protection is
enabled, it can be used to detect single-phase, two-phase and
three-phase VT failure.
There are three main criteria for detecting VT failure, which are the check
of the three phase failure, the check of the asymmetric failure of the
grounding system, and the check of the asymmetry of the non-direct
grounding system. The prerequisite is that the protection device starting
194
component does not start and the zero sequence current and negative
sequence current are less than "VTFail3I03I2Set" Specifically as follows:
1) Three-phase (symmetry) VT failure: when the secondary side
three-phase of VT failure occurs, if the stating component does not
start, then the maximum of compounded zero sequence voltage
3U0 and three-phase phase-to-earth voltage are both less than
"VTFailPEVoltSet" and the maximum of three-phase current
exceeds "VTFailCurrSet".
2) Single-phase/ two-phase (asymmetric) VT failure
a) When the secondary side single-phase or two-phase of VT failure
occurs, if the system is directly grounded and the stating
component does not start, then the maximum of compounded
zero sequence voltage 3U0 exceeds "VTFailPEVoltSet".
b) When the secondary side single-phase or two-phase of VT failure
occurs, if the system is not directly grounded and the stating
component does not start, then then compounded zero sequence
voltage 3U0 exceeds "VTFailPEVoltSet" and the difference
between the maximum and minimum of voltage exceeds
"VTFailPPVoltSet".
In addition, when the device detects V3P_BI, then it is judged as
"3PhVTFail". If the device detects V3P_BI and the voltage exceeds
"VTFailPEVoltSet", it is judged as abnormal BI signal.
After "InstantVTFail", "VTFailAlarm" or "VTFailBIErrAlarm" are issued,
3.1.2. Logic diagram
If the secondary circuit failure of VT is detected, the protection based on
the standard of direction or undervoltage will be blocked and it will send off
the report "VTFailAlarm" through the delay of "VTFailDelayAlarm". When
one of the following conditions is met within the delay of
"VTFailAlarmTime" (that is, before sending off the report "VTFailAlarm"),
VT failure blocking opens.
1) While the protection does not start, the minimum phase-to-phase
voltage exceeds "VTFailNormalVolt" with 500ms delay.
2) While the protection does not start, the minimum phase-to-phase
voltage exceeds "VTFailNormalVolt" and the zero sequence current
and negative current exceed "VTFail3I03I2Set".
3) While the protection does not start after the "VTFailAlarm" is sent off ,
the minimum phase-to-phase voltage exceeds "VTFailNormalVolt", VT
failure blocking opens through 10s delay.
The report "VTFailRst" is issued when the third VT failure recovery is
checked.
195
max(Ia,Ib,Ic)>“VTFailCurrSet”
&
max(Ua,Ub,Uc)<“VTFailPEVoltSet”
Calculated3U0<
“VTFailPEVoltSet”
“NutrPointEarth”=1 & ≥1
Calculated3U0>=
“VTFailPEVoltSet”
“NutrPointEarth”=0 &
Max(PPVoltage)-Min(PPVoltage)>
“VTFailPPVoltSet”
&
Current type ≥1
protection start-up &
InstantVTFailure=1
3PhaseVTFailureBI
VTFailureFunctionOn
“VTFailOn”=1
“VTFailOn”=0
&
Calculated3I0>“VTFail3I0/3I2Set” ≥1 &
≥1
InstantVTFailure=0
3I2>“VTFail3I0/3I2Set”
min(Ua,Ub,Uc)>“VTFailNormalVolt”
&
VTFailureAlarm=1
&
&
T
T
InstantVTFailure=1 VTFailureAlarm=1
T：“VTFailAlarmTime”
Figure 96 VT failure protection logic diagram

Minimum value of PE voltage>
“VTFailPEVoltSet” &
T_Err
VT failure BI abnormal alarm
3 phase VT failure BI
T_Err：“VTFailBIErrTime”
Figure 97 Binary input VT failure protection logic diagram
3.2 Setting list

Table 135 VT failure check setting
Number Setting name Range Default value Unit Remark

1. HVSideVTFailCurrSet 0.05In~40.0In 0.25 A
2. HVSideVTFail3I03I2Set 0.05In~40.0In 0.25 A
3. HVSideVTFailPEVoltSet 5.00~20.00 8 V
4. HVSideVTFailPPVoltSet 10.00~30.00 16 V
5. HVSideVTFailNormalVolt 40.00~120.0 40 V
6. HVSideVTFailAlarmTime 0.04~100 10 s
7. HVSideVTFailBIErr 0~100 10 s
Note: VT Failure protection setting of each middle and low voltage side is
196

Table 136 VT failure check logic switch
Set Default
mode value
1. HVSideNutrPointEarth 1/0 0
2. HVSideVTFailOn 1/0 0
Note: VT Failure protection logic switch of each middle and low voltage
side is the same to that of high voltage side
3.3 Report list

Alarm report:
1. HVSideVTFail /
2. HVSideVTFailBIErr /
3. MVSideVTFail /
4. MVSideVTFailBIErr /
5. LVSideVTFail /
6. LVSideVTFailBIErr /
side
3.4 Technical data
Note: In: CT secondary rated current, 1A or 5A.
Table 138 VT failure check technical data
VT Failure Current 0.05In～40In, step 0.01A ≤ ±3% setting or ±0.02In
Zero and negative sequence 0.05In～40In, step 0.01A ≤ ±5% setting or ±0.02In
currents of VT failure
VT failure phase-to-earth 5.0V～20.0V, step 0.01V ≤ ±3% setting or ±1V
voltage
VT failure phase-to-phase 10.0V～30.0V, step 0.01V ≤ ±3% setting or ±1V
voltage
return to VT normal voltage 40.0V～120.0V, step 0.01V ≤ ±3% setting or ±1V
197
Chapter 27 T-zone protection
About this chapter

The chapter describes T-zone protection function.
199
1 Overview
T-zone function includes three-side current differential protection, two-side
current differential protection, overcurrent protection and line charging
protection.
As shown in Figure 98 , when the isolator G1 of the outlet line is closed
(the isolator is closed, the position contact of isolator is open), T-zone
protection adopts three-side differential current mode. When there is fault
in T-zone, two breakers will be tripped and the signal will be sent to the
opposite end.
When the isolator G1 of the outlet line is open (when the isolator is open,
the position contact of it is closed), the three-side current differential
protection will convert to two-side current differential protection
automatically (if the dia is needed to operate, then the stub differential
protection should be enabled). And at the same time, the two stages of
current protection should be enabled on the line side and work as line-end
protection. When there is fault in T-zone, the two-side current differential
protection will trips two breakers (side and intermediate beakers). When
the two stages of overcurrent protection trips, and then remote tripping
signal will be sent to the opposite end.
The line charging protection should be enabled all the time.
Busbar 1
Differential
protection
Side CB
Middle CB
T-area
protection
Busbar 2
Figure 98 T-zone protection function diagram
200

The input and output signals in this manual only show the visible part of
the project, and the input and output signals of T-zone protection diagram
are shown as below, the left side is input signals.
STUBDiff
1 1
En St_IAssist
2 2
CHGBIBlk St_IHL
3 3
OCBIBlk Startup
4 4
DiffBIBlk CHGOp
5 5
SwitchPos OC1Op
6
OC2Op
7
UnbalanceDiff
8
CTFailM
9
CTFailN
10
CTFailT
11
Diff2side
12
Diff3side
13
SwitchErr
14
SEQErr
15
TrFail
16
FaultI1
17
FaultI2
18
FaultI3
Figure 99 The input and output signals of T-zone protection diagram

Table 139 Parameter description of input and output
Input:
BinaryInput SwitchPo
Isolator open
s
Input:
CHGBIBlk Binary input blocking charging protection
OCBIBlk Binary input blocking overcurrent protection
DiffBIBlk Binary input blocking T-zone differential protection
Output:
St_IAssist Differential current auxiliary startup
STUBFault St_IHL Current sum auxiliary startup
Startup IED startup
CHGOp Charging protection trip
OC1Op Overcurrent stage 1 protection trip
OC2Op Overcurrent stage 2 protection trip

Unbalanc
Long-term differential current
eDiff
CTFailM M end circuit breaker CT failure
201
CTFailN N end circuit breaker CT failure
CTFailT Circuit breaker CT failure of medium voltage side
Diff2side Differential trip of two-side
Diff3side Differential trip of three-side
SwitchErr Isolator position error
SEQErr Sequence of three-phase is unmatched
TrFail Trip failure
FaultI1 Fault phase current 1
The device is configured with three-side current differential protection,
two-side current differential protection, two stages of overcurrent
protection and line charging protection.

3.1.1. Protection startup component
The startup component is mainly used for fault monitoring, protection
startup and unblocking positive power supply of output relay. Once the
startup component acts, all of the other components cannot act and the
reset time of them is 5 seconds.
1) Differential sample value startup component
Differential sample value startup criterion is:
△ (i1+i2+i3) min > {"StubDiffCurrSet", "OCStage1CurrSet",
"OCStage2CurrSet"}
Where: △(i1+i2+i3)= | |(i1+i2+i3)K － (i1+i2+i3)K-T| － |(i1+i2+i3)K-T －
(i1+i2+i3)K-2T| |;
K, K-T and K-2T stand for the present moment, one week ago and two
weeks ago respectively;
T stands for sampling numbers per cycle and sampling numbers per cycle
of this device is 24;
△ (i1+i2+i3) stands for differential current of abrupt change sampling value;
Where, min {"StubDiffCurrSet", "OCStage1CurrSet", "OCStage2CurrSet"}
are the minimum value when the corresponding functions are enabled.
When the sampling values of differential current meet the condition for 4
times continuously and respectively in phase A, B and C , the protection
starts up.
2) Differential current auxiliary startup component
Differential current auxiliary startup criterion is:
202
. . .
│ I 1 + I 2+ I 3│> 0.9 × min {"StubDiffCurrSet", "OCStage1CurrSet",
"OCStage2CurrSet"}
Where, min {"StubDiffCurrSet", "OCStage1CurrSet", "OCStage2CurrSet"}
are the minimum value when the corresponding functions are enabled.
. . .
I 1, I 2 and I 3 stand for CT currents of two circuit breakers and outlet
line respectively.
When the differential current of phase A or phase B or phase C meets the
condition, the protection starts up.
3) Current sum startup component
When the charge protection logic switch is enabled, current sum startup
component of two circuit breakers is set, the criterion is:
. .
│ I 1 + I 2│＞ 0.9 ×"ChargingProtCurrSet"
When the current sum of phase A or phase B or phase C meets the
condition, the protection starts up.
3.1.2. Three-side current differential protection.
After the enabling of differential protection soft and hard connectors and
logic switch, when the isolator G1 of the outlet line is closed (when the line
switch is closed, the position contact of isolator is open), three-side current
differential protection is enabled.
Three-side protection is a current differential protection with restraint
characteristic, which takes into account the characteristic differences of
the three groups of CTs.
The three-side differential protection are composed of A, B and C
respectively, when any differential current meets the condition, the
three-side differential protection starts up, the equation is:
. . .
│ I 1 + I 2+ I 3│>"StubDiffCurrSet"
. . . . . .
│ I 1 + I 2+ I 3│> K*（│ I 1│+│ I 2│+│ I 3│）/2
. . .
Where, I 1, I 2 and I 3 stand for CT currents of two circuit breakers and
outlet line respectively, K stands for restraint coefficient, differential current
. . . . . .
＝│ I 1 + I 2+ I 3│, restraint current＝（│ I 1│+│ I 2│+│ I 3│）/2.
Three-side differential protection characteristic curve is Figure 100 shown
as below.
203
Trip area
Figure 100 Characteristic curve diagram of three-side differential protection.

Three-side differential protection trips two circuit breakers on the local side,
the trip signal will be sent to the opposite end and trips the circuit breaker
of the line. After the tripping, the output and indication light can be
configured on IO Matrix.
3.1.3. Two-side current differential protection
After the enabling of differential protection soft and hard connectors and
logic switch, when the isolator G1 of the outlet line is open (when the line
isolator is open, the position contact of it is closed), two-side current
differential protection is enabled.
Two-side protection is a current differential protection with restraint
characteristic, which takes into account the characteristic differences of
the two groups of CTs.
The two-side differential protection are composed of A, B and C
respectively, when any differential current meets the condition, the
two-side differential protection starts up, the equation is:
│1 +2│>"StubDiffCurrSet"
│1 + 2│> K*（│ 1│+│ 2│）/2
Where, 1, and 2 stand for CT currents of two circuit breakers, K stands for
restraint coefficient, differential current ＝ │1+2│, restraint current ＝
（│1│+│2│）/2.
Two-side differential protection characteristic curve is shown Figure 101 .
Trip area
Figure 101 Characteristic curve diagram of two-side differential protection
204
Two-side differential protection trips two circuit breakers on the local side.
After the tripping, the output and indication light can be configured on IO
Matrix.
In order to prevent from incorrect trip of two-side differential protection
caused by the abnormal position of the switch, the three-side differential
protection is also required to meet the trip condition, when two-side
differential trips.
3.1.4. Overcurrent protection
After the enabling of overcurrent protection soft and hard connectors and
logic switch, when the isolator G1 of the outlet line is open (when the
isolator is open, the position contact of it is closed), overcurrent protection
is enabled.
There are two stages of overcurrent protection. The equation is:
IGL > IGLDZn
. . .
│ I 1 + I 2+ I 3│> 0.9 × IGLDZn
Where, IGL is any phase current for line CT, IGLDZn is
. . .
"OCStage1CurrSet", "OCStage2CurrSet",. n is 1 or 2, I 1, I 2 and I 3
stand for two circuit breakers and outlet line CT current, and overcurrent is
composed of phase A, phase B and phase C.
The current of any phase satisfies the above conditions, and the
overcurrent 1 or 2 stages are output according to their respective setting
time. After the tripping, the output and indication light can be configured on
IO Matrix.
When overcurrent protection trips, the trip signal will be sent to the
opposite end and trips the circuit breaker of the line.
3.1.5. Charging protection
After the enabling of the logic switch of line charge protection, when the
current of any phase meets the following conditions, the charge protection
trips in accordance with setting time.
The equation is:
. .
│ I 1 + I 2│＞"ChargingProtCurrSet"
. .
Where, I 1 and I 2 are CT currents of the two circuit breakers and are
.
composed of the three phase A, phase B and phase C, current sum=│ I 1
.
+ I 2│.
Charge protection trips the two circuit breakers on the local side. After the
tripping, the output and indication light can be configured on IO Matrix.
3.1.6. Abnormality check and judgment
1) CT failure supervision
It is calculated that the differential current in the normal operation is greater
than the min {0.1In or “StubDiffCurrSet”} for 12 continuous seconds, while
205
the phase current of CT failure phase is less than 0.06In.

2) CT Saturation supervision
The fuzzy check principle is used to detect CT saturation. When CT is
judged to be saturated, the restraint coefficient of the current differential
protection component will be automatically higher.
3) Self detection of current sequence
By judging whether the phase sequence is correct by comparing the phase
of the three-phase current. If it is not the normal phase sequence, it issues
alarm "3PhSeqUnmatch".
4) Self detection of the switch position
If the switch position binary input is activated and the outlet line has live
current, it issues alarm "IsoPosnErr" after 10 seconds.
3.2 Setting list

Table 140 T-zone protection setting
Default
value
1. StubDiffCurrSet 0.05In~40.0In 40 A
2. RestrCoef 0.3～1.0
3. OCStage1CurrSet 0.05In~40.0In 40 A
4. OCSatge1Time 0~100 100 s
5. OCStage2CurrSet 0.05In~40.0In 40 A
6. OCSatge2Time 0~100 100 s
7. ChargingProtCurrSet 0.05In~40.0In 40 A
8. ChargingProtTime 0~100 100 s
Table 141 T-zone protection logic switch

name value
1. StubDiffOn 1/0 0
2. OCStage1On 1/0 0
3. OCStage2On 1/0 0
4. ChargingProtOn 1/0 0
Table 142 T-zone equipment parameter

Default
value
1. IEDCTPriVal 1～9999 8000 A
2. IEDCTSecVal 1 or 5 1 A
3. BISwitchSetGrp 1/0 0
206
3.3 Report list


Trip report:
1. IED startup
2. DiffCurrAuxStartup
3. CurrSumAuxStartup
4. OCStage1Trip
5. OCStage2Trip
6. ChargingTrip
7. 2SideDiffTrip
8. 3SideDiffTrip
9. FaultPhCurr1
10. FaultPhCurr2
11. FaultPhCurr3

Alarm report:
If IED trips the circuit breaker, but the current can also
1. TripFail be measured, this report will be issued after a time
delay
Confirm the CT failure of the side circuit breaker and
2. MEndSideCB CTFail
tackle with it in time.
Confirm the CT failure of the side circuit breaker and

3. NEndSideCB CTFail
Confirm the CT failure of the middle circuit breaker and

4. MiddleCB CTFail
Check the current circuit and the current converter
5. LongTermDiffCurr
polarity
Check the current circuit and the current converter
6. 3PhSeqUnmatch
polarity
If the switch position binary input is activated and the
7. IsoPosnErr outlet line has live current, it issues alarm "IsoPosnErr"
after 10 seconds.

Operation report:
1. IsoOpen
2. IsoClose
207
Chapter 28 Gap protection
About this chapter

This chapter describes gap protection function.
209
1 Overview
Gap protection is a backup protection for single-phase grounding fault
when the neutral point of a non fully insulated transformer is grounded by
discharge gap.

the project, and the input and output signals of user defined protection
diagram are shown as below, the left side is input signals.
JX Function
1 1
BIBlk Start
2
bOperationLL1
3
bOperationLL2
4
bOperationLY1
5
bOperationLY2
Figure 102 The input and output signals of gap protection diagram
Input:
BIBlk Binary input blocking
Output:
Start IED startup
JX
bOperationLL1 Time 1 trip of gap zero sequence voltage
bOperationLL2 Time 2 trip of gap zero sequence voltage
bOperationLY1 Time 1 trip of gap zero sequence current
BOperationLY2 Time 2 trip of gap zero sequence current
Gap protection includes zero sequence voltage protection and gap
overcurrent protection.
Zero sequence voltage protection trip voltage can be selected as external
or self-calculated by logic switch. When self-calculated is selected, it is
blocked by VT failure logic.
The trip current of gap overcurrent protection is taken from the gap zero
sequence CT current of the transformer earthing circuit through the gap,
and forms “OrLogic” time trip together with the zero sequence voltage.
The logic diagram of gap protection trip is shown in.
210
Calculated3U0>“GapOVSet”
&
VTfailure
≥1
“GapCalc3U0”=1 3U0Component Trip
&
Calculated3U0> “GapOVSet”
“GapOVOn”=1
&
T_JXU0 Gap overvoltage
protection trip
3U0Component Trip
≥1
&
T_JXI0 Gap overcurrent
protection trip
Gap current>ISet_JX
“GapOCOn”=1
Iset_JX：“GapOCSet”
T_JXU0：“GapOVTime”
T_JXI0：“GapOCTime”
Figure 103 The logic diagram of gap protection
3.2 Setting list

Table 147 Gap protection setting of high voltage side
Number Setting name Range Default value Unit Remark

1. HVSideGapOCSet 0.05In~40In 40 A
2. HVSideGapOCTime1 0.1~100 100 s
3. HVSideGapOCTime2 0.1~100 100 s
4. HVSideGapOVSet 10~200 180 V
5. HVSideGapOVTime1 0.1~100 100 s
6. HVSideGapOVTime2 0.1~100 100 s
Note: Gap protection setting of medium voltage side is the same to that of
high voltage side
Table 148 Gap protection logic switch

1. HVSideGapCalc3U0 1/0 1 1-On, 0-Off
2. HVSideGapOCTime1On 1/0 1 1-On, 0-Off
3. HVSideGapOCTime2On 1/0 1 1-On, 0-Off
4. HVSideGapOVTime1On 1/0 1 1-On, 0-Off
5. HVSideGapOVTime2On 1/0 1 1-On, 0-Off
Note: Gap protection logic switch of medium voltage side is the same to
211
3.3 Report list


Trip report:
1. HVSideGapOCTime1Trip /
2. HVSideGapOCTime2Trip /
3. HVSideGapOVTime1Trip /
4. HVSideGapOVTime2Trip /
212
Chapter 29 User-defined protection
About this chapter

This chapter describes user-defined protection function.
213
1 Overview
User-defined protection includes overload protection, start fan protection
and blocking voltage adjustment protection.

the project, and the input and output signals of user defined protection
diagram are shown as below, the left side is input signals.
Define Function
1
Alarm
Figure 104 The input and output signals of user-defined protection diagram
OL/QDTF/B Output:
STY Alarm IED alarm
The device is equipped with overload protection, delayed action on signal,
and overload protection to detect three-phase current.
In addition, user-defined protection is provided with overload start fan
protection and blocking voltage adjustment protection, and the
three-phase current of the high voltage side can be detected, and the
setting value can be set.
Overload alarm trip logic diagram is shown below:
Ia>“OLCurrSet”
≥1
&
Ib>“OLCurrSet” T
Overload
Ic>“OLCurrSet”
“OLOn”=1
T：“OLTime”
Figure 105 Overload logic diagram

Start fan trip logic diagram is shown below:
214
Ia>“StartFanCurrSet”
≥1
&
Ib>“StartFanCurrSet” T
StartFan
Ic>“StartFanCurrSet”
“StartFanOn”=1
T：“StartFanTime”
Figure 106 Start fan logic diagram

Blocking voltage adjustment trip logic diagram is shown below:
Ia>“BlkVoltAdjCurrSet”
≥1
&
Ib>“BlkVoltAdjCurrSet” T Blocking voltage
adjustment
Ic>“BlkVoltAdjCurrSet”
“BlkVoltAdjOn”=1
T：“eBlkVoltAdjTime”
Figure 107 Blocking voltage adjustment logic diagram
3.2 Setting list

Table 151 Overload protection setting of high voltage side
Default
value
1. HVSideOLCurrSet 0.05In~40In 40 A
2. HVSideOLTime 0.1~100 100 s
Note: Overload protection setting of middle and low voltage side are the
Table 152 Overload protection logic switch of high voltage side
Number Remark
name mode value
1. HVSideOLOn 1/0 1 1-On, 0-Off
Note: Overload protection logic switch of middle and low voltage side are
Table 153 Start fan protection setting of high voltage side
Default
value
1. HVSideStartFanStage1CurrSet 0.05In~40In 40 A
2. HVSideStartFanStage1Time 0.1~100 100 s
3. HVSideStartFanStage2CurrSet 0.05In~40In 40 A
4. HVSideStartFanStage2Time 0.1~100 100 s
215
Table 154 Start fan protection logic switch of high voltage side
Set Default
mode value
1. HVStartFanStage1On 1/0 1 1-On, 0-Off
2. HVStartFanStage2On 1/0 1 1-On, 0-Off
Table 155 Blocking voltage adjustment protection setting of high voltage side
Default
value
1. HVSideBlkVoltAdjCurrSet 0.05In~40In 40 A
2. HVSideBlkVoltAdjTime 0.1~100 100 s
Table 156 Blocking voltage adjustment logic switch of high voltage side
Set Default
mode value
1. HVSideBlkVoltAdjOn 1/0 1 1-On, 0-Off
3.3 Report list


Trip report:
1. HVSideOL /
2. MVSideOL /
3. LVSideOL /
4. HVSideStartFan /
5. BlkVoltAdj /
side
216
Chapter 30 User-defined function
About this chapter

This chapter describes BI, BO, LED configuration and user
defined logic function.
217
1 Overview
The binary input and output, report, LED of device can be defined
secondly in accordance with demands. According to the actual situation of
the project, the user can user-definedize the logic. This chapter mainly
describes the function of the AESPStudio tool software which may be used
in engineering application to perform the user defined function and the
matters needing attention.
2 User-defined configuration
2.1 Open project
Click the file→open, in the open file dialog box, open the file named
aespro.
2.2 Binary input configuration

The title of BI can be modified by engineering example. The property of
each BI can be set in BI configuration according to demand.
Table 158 Binary input configuration
Binary input configuration
Configuration Description
item
Binary input Excitation changes from 0 to 1, and close position of binary input is defined
time 1 by time 1
Binary input Excitation changes from 1 to 0, and open position of binary input is defined
time 2 by time 2
Waveform Configure "DFR", "RisingEdgeTrigger", "FallingEdgeTrigger"

record set
Property 1: Configuration "SirenBit", "BellBit", "PulseQuantity", "SendSOE",

"DualPosnBI", "ACInput" and "BCUProtocol"
Property 2: Configure "NonSmartModule", "24V", "48V", "110V", "125V", "220V", "250V"
Property 3: Configure "OrdinaryBI", "MaintState", "Rmt/Local", "Invalid"
Bay control
unit and
Configure "Prot", "BCU"
protection
property
218
Note: when setting waveform record, if "DFR" is configured, then the BI will
be in the waveform recording; if "RisingEdgeTrigger" is configured, when
the BI changes from 0 into 1, the waveform record will be generated; if
"FallingEdgeTrigger" is configured, when the BI changes from 1 into 0, the
waveform record will be generated. The generated waveform record file
will be saved into the list of startup waveform records.
The work voltage can only be configured within ranges defined by this
module unit. Hardware board contains high power voltage level and low
power voltage level, respectively marked with the work voltage of DC
"110V", "125V", "220V", "250V" and "24V", "48V".
The time sequence explanation of "BITime1" and "BITime2" is shown as
below.
Excitation
Binary input time delay 1
Binary input
Binary input time delay 1
Figure 108 Binary input time delay sequence

Configuration way of double position binary input:
Two single-position binary inputs can be used to describe the
double-position binary input, and the close position of single input
accesses to the n hardware binary input, and then the open position of
single input accesses to the n+1 hardware binary input. "DualPosnBI" can
be selected for the property 1 of binary input n; but it cannot be selected for
the property 1 of binary input n+1; and "Invalid “can be selected for the
property 3.
The logic state of a pair of binary inputs (binary input n and n+1)
configured with double-0position will no longer be that of the hardware
binary input. Only when (hardware binary input n, n+1) = (1, 0), the logic
binary input n refers to the close position state; only when (hardware
binary input n, n+1) = (0, 0) or (1, 1), the property of double-position of
binary input is 1, which means the invalid state.
Both the BI state and BI state in IO Matrix of double-position hardware BI
and logic BI are shown below
Table 159 State list for hardware binary input of double position and logic binary input
Binary input of hardware (binary
0, 0 0, 1 1, 0 1, 1
input, binary inputn+1)
Logic binary input(binary input,
0, 1 0, 0 1, 0 0, 1
binary inputn+1)
2.3 Binary output configuration

The title of BI can be modified by engineering example. The property of
each BI can be set in BI configuration according to demand,\/.
219
Table 160 Binary output configuration
Binary output configuration
item
Holding time Excitation returns and BO also returns experiencing retention time.
Waveform Configure "DFR", "RisingEdgeTrigger", "FallingEdgeTrigger"

record set
Binary output Configure "ElectricLatched", "TripRedundancy", "ReclaimRedundancy",

property "BlkedByStartup", "NCContact"
To configure "ElectricLatched" property, the electric relay will return only

after the signals recovering. The movement sequence is shown as below.
When the device is powered down and then power up, the electric relay
can recover the state before power down.
Excitation
Reset
Relay
Figure 109 Electric latched relay trip sequence

Configuration is the node of electric retention, which can't
"BlkedByStartup"; otherwise startup relay will return and so does BI.
Non "ElectricLatched" BI can configure "LatchedTime", excitation will
return, after the set time, the relay returns.
Excitation
Relay
Figure 110 Non-electric latched relay trip sequence

Please configure in line with the hardware jumper of BO, and determine
whether BO is "BlkedByStartup" or not, and whether "NCContact" or not.
As CPU and other redundant CPU will send off command; the
configuration as "Trip Redundancy" of node relay trips; as CPU and other
redundant CPU retreat all the command, the configuration as
"ReclaimRedundancy" of node relay will trip. If the protection configuration
doesn't configure redundancy, "ReclaimRedundancy" and “Trip
220
Redundancy" can't be set.

See Figure 111 one of configuration properties of BO "BlkedByStartup"
must be linked with the contact of hardware, and every three BOs shall
form a group to be configured similarly. Which means BO1, BO2 and BO3
shall form a group; BO4, BO5 and BO6 form a group and so on.
Figure 111 Diagram of binary output configuration
2.4 LED configuration

The title of LED can be modified by engineering example. On control plate,
the calibrated LED indicator tag can be embedded into the corresponding
position of the indicator light. The property of each LED can be set in LED
configuration according to demand.
Table 161 Light configuration.
Light configuration.
item
Holding Configuration "Latched", "NonLatched", and configuration is "Latched",

property recovery action should be enacted to eliminated light state.
Light color The color of LED is "yellow", "green" and "red"
Flashing The LED is flashing or constant on, n represents the flash frequency is
n*50ms; when it is 0 or 1, the LED is always on.
Redundancy As the configuration is "Redundancy" property, multiple CPU will trigger light
at the same time and the LED will be enlightened
As CPU and other redundant CPU all send out lighting commands, the
LED configured with "Redundancy" can be enlightened. If LED doesn't
have redundancy property, "Redundancy" property can not be set.
221
2.5 IO Matrix configuration

The IO Matrix configuration achieves a fast correlation between virtual and
real points in the software. Virtual point comes from the application
software, corresponding to the functional software to modify the data
points, the real point from the limited resources provided by the device.
2.5.1 IO Matrix channel configuration
The IO Matrix channel configuration is used to specify the source of the
required input information for the application, the AC or DC excitation of
the device is configured as AC sampling or SV data.
“X” means the valid selection.
Figure 112 Diagram of channel configuration
2.5.2 IO Matrix function configuration

The IO Matrix function configuration is used to specify the protection action
of the device. External input signal is dependent on each function of the
device and external manifestations of action include the opening and the
lights, etc., through the configuration to achieve the definition.
“U” refers to the valid high power level ,”L” is valid low power level.
Figure 113 Diagram of function configuration
2.6 Binary input switch setting group

2.6.1 Function description
IED can switch the setting zone in two ways. When the setting
"BISwitchSetGrp" is set as 0, IED will response to the panel or SCADA to
222
switch the setting group; when the setting "BISwitchSetGrp" is set as 1,

IED will not response to the panel or SCADA to switch the setting group, it
will switch the setting group automatically according to the status of binary
input.
The device provides four default configurable BI to switch setting group, in
BIToSetGrp, BI1, BI2, BI3, BI4 can be set by users in the engineering
research and development version.
Table 162 Four binary input switch setting group configuration examples
Number BIToSetGrp4/2/1 Setting group

1. 0000 1
2. 0001 2
3. 0010 3
4. 0011 4
5. 0100 5
6. 0101 6
7. 0110 7
8. 0111 8
9. 1000 9
10. 1001 10
11. 1010 11
12. 1011 12
13. 1100 13
14. 1101 14
15. 1110 15
16. 1111 16
If the various BI groups designate target setting group randomly, and the
user-defined logic of engineering research and development is realized,
then write the target setting group to **::ChangeSettingGrp.InSettingZone.
IED provides up to 32 setting groups.
Figure 114 Diagram of binary input switch setting group configuration
2.6.2 Setting list

Table 163 Logic switch of binary input switching setting group diagram
mark mode value
1 BISetGrp BISwitchSetGrp 1/0 0
2.7 Configuration startup

The function configuration of IO Matrix offers a settable startup trip to
223
decide whether the protection trip of IED should be blocked by starting.

Taking the overcurrent stage 1 as an example, the diagram is shown
below:
Figure 115 Diagram of initiated blocking configuration

Protection trip of overcurrent stage 1 is configured via startup relay
blocking:
The corresponding Start of OC1 is the startup trip of overcurrent stage 1,

which is connected with the node PickupContact of startup relay, and the
output of BIO module is set as initiation by jumper.
Figure 116 Diagram of non-initiating blocking configuration

Protection trip of overcurrent stage 1 is configured without startup relay
blocking:
The corresponding Start of OC1 is not connected with the node
PickupContact of startup relay, and the output of BIO module is set as
non-initiation by jumper.
If the protection trip of overcurrent stage 1 doesn't connect with the node
PickupContact of startup relay, but the output of BIO module is set as
initiated by jumper, then the output of overcurrent stage 1 will be blocked.
2.8 Other configuration

The name of the device can be changed according to the requirements of
the project, and it can be named in accordance with the project schedule,
so as to facilitate the maintenance of the project.
The default length of waveform recording file generated by IED is 2.5
cycles before fault and 20 cycles before and after the fault together. It
224
supports to instantiate RS_WAVEPARAM by AESP tool and the users can

define the length of waveform records according to their needs. The length
of single waveform record cannot be longer than 200ms before fault, the
total length of waveform records can not be longer than 20s. Single
waveform record can not be greater than 512k.
If there are new setting values, reports or connectors which code number
in the range of 1001~1999 and they should not be repeated with the
existed settings, reports and connectors.
Figure 117 Setting configuration figure
2.9 Defined logic

The AESP tool provides the basic elements of the module to support
user-defined simple engineering logic. The intermediate data and the
intermediate nodes in the application software which is open to the user
can be used conveniently in the configuration interface, and the logical
application of the project is realized.
Figure 118 AESPStudio working interface
225
Chapter 31 Substation communication
Chapter 31 Substation
communication
About this chapter

This chapter describes functions such as substation
communication and protocol, clock synchronization and so
on.
227
1 Overview
Each IED provides communication port to communicate with one or more
substation system. IED supports following communication protocols:
1) IEC 61850-8-1 communication protocol
2) IEC 60870-5-103 communication protocol
3) DNP 3.0
4) MODBUS
2 Communication protocol
2.1 IEC 61850-8-1 communication protocol
Protocol IEC61850-8 allows two or more IED in one or more factories to
communicate and cooperate on the basis of their functions.
Standard IEC 61850-8-1 rules GOOSE (generic object of substation event).
By publishing and subscribing mechanism, GOOSE standardizes
communication state and control information between IEDs. That is to say,
if event is tested to happen, IED shall send information to devices which
have subscribed the event by multi cast.
2.2 IEC 60870-5-103 communication protocol

IEC 60870-5-103 is master-slave type protocol and communicate with
control system through serial port. According to IEC rules, main station is
the master and substation is the slave. Communication is carried out on
the basis of point-to-point principle. Main station should be equipped with
the software that is able to receive IEC 60870-5-103 communication report.
For a more comprehensive understanding of the IEC60870-5-103 protocol,
you can refer to the fifth part of "IEC60870 standard": 103 section of
"communication protocol": "the standard of information communication
interface for IED protection"
3 Communication port
3.1 Front plate communication port
Front plates of all IEDs have a RJ45 communication port respectively. By
this port, users can use PC to operate Sifang debug software to connect
IED for setting, testing, configuring and so on.
3.2 RS485 communication port

IED provides an independent electric RS485 communication port
connecting to automatic system for substation. The port supports protocol
IEC60870-5-103 and other ports could be used for clock synchronization.
3.3 Ethernet communication port

IED provides three electric or two optical Ethernet ports to connect to
substation's automatic system, in which two of them can support the same
protocol at the same time, IEC61850 or IEC60870-5-103.
228
4 Technical data
Table 164 Front plate communication port
Items Data
No. 1
Connection mode Debugging RJ45 port for software
Communication rate 100Mbit/s
Table 165 RS485 communication port

Items Data
No. 1
By two conductors
Connection mode
Communication port of rear plate
Maximum communication distance 1.0 km
Test voltage 500V AC earthing
Support protocol IEC 60870-5-103
Parameter is set as 9600 baud,
Communication rate Minimum 1200 baud rate, maximum 19200
baud rate
Table 166 Ethernet communication port
Items Data
Ethernet communication port
No. Three RJ45 or two optical ports
Cable or optical fibers/backboard
Connection mode
communication port
Maximum communication distance 100m
Support IEC 61850 protocol
Support protocol IEC 60870-5-103
Table 167 Time synchronization port
Items Data
Time synchronization mode Pulse or optical signal time synchronization
IRIG-B signal format IRIG-B000
Connected by two conductors or optical fibers
Connection mode
Communication port of rear plate
Volt level Differential signal
229
5 Typical substation communication

mode
Through communication protocols supported by communication port, IED
is able to communicate with one or more substation system or device.
Server or Server or
Work Station 1 Work Station 2
Switch
Work Station 3
Net 1: IEC61850/IEC103,Ethernet Port A
Switch Net 2: IEC61850/IEC103,Ethernet Port B Switch

Switch
Gateway Switch
or
converter
Net 3: IEC103, RS485 Port A
Figure 119 Multiple network substation automatic system connection case
6 Typical clock synchronization mode

All IEDs provide a clock synchronization port ( as diagram 87 shows), it is
able to choose IRIG-B code or pulse time synchronization. For pulse time
synchronization, IED can automatically adapt to second or minute pulse
time synchronization mode. Meanwhile IED could adopt SNTP mode to
synchronize.
SNTP IRIG-B Pulse
Ethernet port IRIG-B port Binary input
Figure 120 Clock synchronization mode
230
Chapter 32 Man-machine interface (MMI) and operation
Chapter 32 Man-machine interface

(MMI) and operation
About this chapter

This chapter describes the relative display of man-machine
interface and its operation.
231
1 Overview
The MMI is composed of liquid crystal display (LCD), LED, panel buttons
and panel Ethernet port. Users can view information, set parameters and
debug through MMI.
2 Function description
2.1 Liquid crystal display(LCD)
The LCD back light of HMI is blue, 9 lines can be displayed. When
operating Sifang key or IED issuing alarm or trip report, background blue
light automatically lights up. Soon after the latest trip or alarm, background
blue light dies out after 5 minutes of time setting.
2.2 Man-machine interface (MMI)

MMI is man-machine interface. LCD screen displays the device running
information, such as measured value for current and voltage, connector
state and BI, BO and bay signal line diagram.
If there is no key operation, the MMI main cycle interface shows part of
device information. User could press “ESC” to lock current display, and
press “ESC” again to restore circulation display.
The description of faceplate area is as follows: zone one is for the
user-defined indicator area; zone two is for the key area of the control
function; zone three is for the debugging of net port; zone four is for the
key district of the basic key.
CSC-326
Figure 121 MMI schematic diagram

The user-defined indicator area consists of 24 lights, where the position of
232
running lights and alarm light are fixed, and the functions of other 22 lamps
can carry out the configuration of light color, light property according to the
needs of the user ; in key areas, there is indicator indicating device state
on each of the remote, local and blocking key respectively.
RUN: When running lights, the green light is lightened during the normal
operation, while the running light is off if there is an alarm of class 1.
ALARM: alarm indicator, the device alarm lightens the red light.
The faceplate uses the Ethernet port to connect PC and device, which
supports setting device parameter, measuring function, downloading
programs and analyzing data. The debugging IP address of Ethernet port
is 196.178.111.1 which is unchangeable.
The key includes basic key and control functional key. Basic key is on the
right of the screen and control functional key is below the screen to realize
human-computer interaction. Keys for IED of CSC series contain the same
appearance and operation mode, for details in below table.
Table 168 IED MMI Key
Key Function
Move to the next line in menu
Move to the next line in menu
Move left in the menu
Move right in the menu
 Reseting LED light

 Directly back to normal circulation display interface
 Entering main menu or sub-menu

 Affirming revised setting
 Back to previous menu

 Exit revising setting
 Back to circulation display interface
 Blocking or unlocking circulation display interface (when
blocking, top right corner of LCD displays an icon of a
small key)
 Value adds 1
+ 

Page down
Logic switch shift from the present value to the opposite
value; namely "1" to "0", or "0" to "1"
233
Key Function
 Value minus 1
- 

Page up
Logic switch shift from the present value to the opposite
value; namely "1" to "0", or "0" to "1"
F1
F2  User-defined function key

 The shortcuts for menu options are able to set to relate
with menu items to execute functions of this menu.
F3  as the input signal to participate in logic
F4
 Switching to remote operation mode, and earthing control
shall be blocked.
 Switching to earthing control mode, remote operation shall
be blocked.
 It is used for locking and unlocking control key and
user-defined key so as to prevent mistakenly touching.
 Breaker closes
 Breaker opens
2.3 Menu structure

Click the key MMI to enter the IED menu, and view information or take
some related operations. Due to the differences in the function of various
type of IED, the following lists show the maximum menu configuration; the
value of related setting information and various type of IED is on the basis
of actual display.
Table 169 IED menu
L1 menu L2 menu L3 menu L4 menu Description

Read the measure
input
PriVal
primary-value of
the IED
Calc
Read the measure
input
SecVal
second-value of
the IED
ViewInfo IEDState Read the measure
input
PriVal
primary-value of
the IED
Measure
Read the measure
input
SecVal
second-value of
the IED
Analog Read the analog
234

input of the IED
Read the power
PowerMetr metering of the
IED
Read the binary
ConventionalBI
input of the IED
Read the original
BIO GOOriginBI binary input state
of GOOSE
Read the binary
ConventionalBO
output of the IED
Read state
information of
GOOSESubState
GOOSE
subscription
GOState
Read state
information of
GOOSEPubState
GOOSE
publishing
Read state
StateMon information of the
IED
Read the current
AlarmInfo
alarm information
Read the IED
ProtSet
setting
Read the
CalcSet
calculation setting
Read the
ViewSet EquipParm equipment
parameters
Read the
measurement and
BCUParm
control
parameters
Read the function
FunctionCon connector
information
Read connector
state information
GOOSEPubCon
ConState of GOOSE
publishing
Read connector
state information
GOOSESubSoftCon
of GOOSE
subscription
Read the unique
IED IDCode
code of IED
Read the version
VerInfo IEDVer
information of IED
Read the VT
VrtlTrmlChkCode
check code
Read the
SyncMode synchronization
IEDSet mode of IED
Read the Ethernet
CommParm EthernetSet
information of IED
235

Set function
FunctionCon
connector state
Set state
information of
GOOSEPubCon
GOOSE
ConOn/Off
publishing
Set state
information of
GOOSESubSoftCon
GOOSE
Operate subscription
Switch current
SwitchSetGrp operation setting
area
Switch
LocalCtrl remote/local
control mode
Bay single line
Bay0
SLDCtrl diagram control
…
Read the startup
StartupRpt
report
Read the trip
TripRpt
Report
Read the alarm
AlarmRpt
report
Read the
OperationRpt
operation report
ViewRpt
Read the BI
BIChangeRpt
change report
Startup waveform
StartupDFRList record shown in
list
Trip waveform
TripDFRList record shown in
list
Setting the
ProtSet ProtSet
ProtSet
Copy setting of
GrpCopy
setting zone
Set substation
SubstationName
name
WriteSet Set the protected
EquipParm ProtEquipName
equipment name
Set equipment
EquipParm
parameters
Set measurement
BCUParm and control
parameters
Test the BO
ConventionalBO
BOTest contacts
GOOSE BO TestGOOSEsignal
FnAlarmChk
TestMenu TripChk Test
CommChk GOAlarmChk communication
BIChk signal
MSTAlarmChk
236

ConChk
AnalogChk
MeasureChk
LEDTest TestLEDlight
Manual triggering
to generate fault
MC DFR
and disturbance
record
ViewZeroDrift
ViewScale
AdjZeroDrift
FactoryTest AdjScale
AngleCorrection
SystemSet
IntrSet
SetClock Set time
Choose
SyncMode synchronization
mode
TimeSet NetTimeSyncIPSet Set SNTP address
Set the local time
TimeZone
zone
Mode1 Set daylight
DST
Mode2 saving time
Set the Ethernet
EthernetSet
information of IED
Serial1Set
IEDSet Set serial port
CommParm SerialSet Serial2Set
parameters
Serial3Set
Set the protocol
ProtocolSet
information
Password Set IED password
Contrast Set the contrast
Set the mode that
OtherSet sending
DisplayMode
primary-secondary
value to SCADA
Set the power
PowerMetrZeroing
metering as 0
CHN Confirm
Language ENG Confirm Switch language
RUS Confirm
Click the key in the recycle main interface, the menu tree will be shown
in the MMI interface; click the key or to select menu items, when the
cursor stays in the corresponding menu item, if there is a symbol ""
behind this menu item, it can click the key or to enter the next menu; if
there is no signal "", it can click the key to enter the menu items.
237
Figure 122 Menu tree diagram

The following diagram is an example of "ConventionalBO" menu.
Figure 123 Menu diagram
238
Chapter 33 IED hardware
About this chapter

This chapter describes hardware for device.
239
1 Overview
1.1 IED structure
19
1.1.1 4U, 2 inch device
Height for IED crate is 4U and width is 19 2 inches. The whole is for
embedded installation with back-wiring mode.
Figure 124 Installation size diagram (unit mm)

1) The front panel of IED is aluminum alloy by founding in integer and
overturn downwards. LCD, LED and setting keys are mounted on the
plate. There is a RJ45 interface on faceplate supporting PC
connection.
2) Back plug mode, module is fixed by screw spike.
3) Module is connected through bus of rear plate.
240
1.1.2 4U, 19inch device

Height for IED crate is 4U and width is 19 inches. The whole is for
embedded installation with back-wiring mode.
Figure 125 Installation size diagram (unit mm)

1) The front panel of IED is aluminum alloy by founding in integer and
overturn downwards. LCD, LED and setting keys are mounted on the
plate. There is a RJ45 interface on faceplate supporting PC
connection.
2) Back plug mode, module is fixed by screw spike.
3) Module is connected through bus of rear plate.
241
1.2 Module arrangement diagram

19
1.2.1 4U, 2 inch device
Figure 126 IED rear plate module layout diagram
1.2.2 4U, 19inch device
Figure 127 IED rear plate module layout diagram
242
2 Analog input module

2.1 Overview
AC module contains voltage and current transformers. The module
converts two-side current and voltage to processable signal for IED data
collecting system and serves as electrical isolation. IED in different type
shall be with different current and voltage transformers. The module is
optional according to different project requirements.
2.2 Analog input moduleintroduction

The following figure shows the AC module terminal diagram of a certain
type of configuration, the module supports the access of 4 channels of
protective current, 1 measuring voltage and 4 channels of voltage.
The 4 channels of protection current channels Ia, Ib, Ic, I0 support 1A or
rated 5A current access, and each current channel provides 3 wiring
terminals. The terminal identification without ' suffix is shared inlet positive
terminal, while that with' suffix is the outlet negative terminal. For example,
the use of rated 1A shift of Ia should access the amount of current from the
Ia terminal to the Ia_1’ terminal, with Ia_5 ' terminal suspended; the use of
rated 5A shift should access the amount of current from the Ia terminal to
Ia_5' terminal with the Ia_1' terminal suspended; the wiring principle of
other protection type of current channels is same.
Is in the following figure is measured current channel, automatic
compatible of rated 1A/5A input, the terminal identification without ' suffix is
shared inlet positive terminal, while that with' suffix is the outlet negative
terminal, the magnitude of current should always be accessed from Is
terminal, and extracted from Is' terminal.
U4, Ua, Ub, Uc in the following figure are voltage channels, and the
terminal identification without ' suffix is shared inlet positive terminal, while
that with' suffix is the outlet negative terminal.
243
Figure 128 AC module terminal diagram
2.3 Technical data

Table 170 Current transformer parameters
Items Executive standard Data
Rated current IEC 60255-1 1A or 5A
Protection CT is 0.05 In to
Sampling range for nominal current
40 In, while measurement
transformer
CT is 0.05 In to 1.2 In.
Sampling range for high sensitive
0.005 to 1.2A
current transformer
When In=1A,≤0.2VA;
Power consumption (per phase)
When In=5A,≤0.5VA
Thermal overload capacity of nominal IEC 60255-1 100In overload 1s
current transformer IEC 60255-27 Continuous 4 In
Thermal overload capacity for high IEC 60255-27 100A overload 1s
sensitive current transformer DL/T 478-2013 3A continuous
Table 171 Voltage transformer parameter
Items Executive standard Data

Rated voltage Vr (line voltage) IEC 60255-1 100V/110V
Sampling range (phase-to-earth voltage) 0.4V~180V
IEC 60255-27
Power consumption (Vr = 110V) ≤ 0.1VA each phase
DL/T 478-2013
Thermal overload capacity (phase-to-earth IEC 60255-27 400V, overload 60s

voltage) DL/T 478-2013 200V, continuous
244
3 BIO module
3.1 Overview
BIO module provides a certain of protection tripping and closing control so
as to realize telecontrol switching of the switch and isolator.
The BIO hardware of BI module includes two types of welding : 1) high
power voltage level, adaptive 110V, 220V, 125V, 250V and 2) low power
voltage level, adaptive 24V and 48V. Work rated power source of device
BI is modified by configuration file before applying.
3.2 BIO module introduction

There are three indication lights on the BIO panel to show the status of the
board, the indication light definition is shown in the following.
Table 172 Definition of BIO module indicator
Serial
number of
Indicator function Indicator state introduction
indicator
light
1 Power supply light Light is on when power on
2 Running light Flash when operating properly
3 Spare Off
Due to the different location of the slot, the BIO module can be set at
different address of board cards, and the address is set through the jumper
J6. Take the side away from single board as L side, the side near single
board as H side, from bottom to top is AD0, AD1, AD2, AD3.
Table 173 Definition of BIO module address
Slot
Jumper Control content Jumper settings
location
BIO1 J6 BIO1 address AD3~AD0 are short connected to the L side
AD3 and AD1 are short connected to the L
BIO2 J6 BIO2 address
side, AD0 is short connected to the H side
AD3, AD2, AD0 are short connected to the L
BIO3 J6 BIO3 address
side, AD1 is short connected to the H side
AD3, AD2 are short connected to the L side,
BIO4 J6 BIO4 address AD1 and AD0 are short connected to the H
side
Each BIO board has 6 BI and 12 BO. 6 BI are divided into 2 groups, and
each of 3 BI shares a common terminal.
12 BO are divided into 4 groups, and each group can be set as whether
through the starting through jumper, with total four groups of jumpers
J11~J14. The jumper inserting into 1, 2 pin represents through starting
relay outlet, inserting into 2, 3 pin represents not through starting relay
outlet.
245
Table 174 Description 1 for jumper of BIO module

BIO module
address
Binary output 1 and 2 pin 2 and 3 pin
definition
jumper
J11 BO1~ BO3 Start Without start
BO12 can switch normally open or normally closed node by JP1 jumper ,
that is, jumper jumping to the NC side is the normally closed node, while
jumper jumping to the NO side is the normally open node.
Table 175 Description 2 for jumper of BIO module
Jumper Binary output NC NO
Normally closed
JP1 BO12 Normally open node
node
Figure 129 BIO module terminal diagram
246
3.3 Technical data

Table 176 BI parameter
Executive
Items Data
standard
110V/125V/220V/250V DC
Rated voltage IEC 60255-1
24V/48V DC
70%Ur, rated DC 24V/48V,
Startup voltage IEC 60255-1
110V/125V/220V/250V
55%Ur, rated DC 24V/48V,
Return voltage IEC 60255-1
110V/125V/220V/250V
286V, rated DC voltage 110V/125V/220V
The maximum BI voltage IEC 60255-1 /250V;
62V, rated DC voltage 24V/48V;
Maximum 0.5W/ input, 110V DC
Power consumption IEC 60255-1
Maximum 1W/ input, 220V DC
Table 177 BO parameter
Executive
Items Data
standard
Maximum work voltage IEC 60255-1 250V current
5A continuous,
Current carrying capacity IEC 60255-1
30A, 200ms On, 15s Off
1100W(DC) at inductive load L/R>40 ms

Closing capacity IEC 60255-1
1000VA(AC)
220V(DC), 0.15A, L/R≤40ms

Arc breaking capacity IEC 60255-1
110V(AC),0.30A, L/R≤40ms
50,000,000 times (switching frequency is

Mechanical endurance IEC 60255-1
3HZ)
Opening times IEC 60255-1 ≥1000
Closing times IEC 60255-1 ≥1000
IEC 60255-1
Authentication IEC 60255-23 UL/CSA, TŰV
IEC 61810-1
IEC 60255-1
Contact circuit resistance IEC 60255-23 30mΩ
IEC 61810-1
Contact insulation test (AC IEC 60255-1
AC1000V 1min
dielectric strength ) IEC 60255-27
Maximum temperature that

IEC 60255-1 55℃
operation allows
247
4 CPU module
4.1 Overview
CPU module is the core of the IED and responsible for running all
protection logic to carry out the hardware self-check and communication
with external devices such as MMI, PC, measurement, substation
automatic system, working station, RTU, printers and so on. Besides, CPU
module sends telemetry, telesignalisation, SOE, event report and recorded
wave to backstage, it provides time synchronization and communication
port.
CPU module provides multiple configuration for user's need. Differences
lie in quantities for Ethernet port, optical/electric port, time synchronization
mode, storage capacity and so on.
4.2 CPU module terminal diagram

The CPU module panel has six indicators to indicate the operation status
of the board and the definition of indicator is shown as below table.
Table 178 Definition of indicator of CPU module
No. of
indicator Indicator function Indicator state introduction
light
Indicator 1 of Ethernet Flash when communicating normally while close
1
Plate when communicating abnormally
2
3
Flash when operating normally while close when
4 Running light of core 1
operating abnormally
248
Figure 130 CPU module terminal diagram

Table 179 Definition of CPU module in serial communication terminal
Terminal Definition
01 485-1A
02 485-1B
03 485-1GND
04
05 485-2A
06 485-2B
07 485-2GND
08
09 RS232-TXD
10 RS232-RXD
11 RS232-GND
Table 180 Ethernet port configuration
Number Configuration
1 RJ45 electrical port+RJ45 electrical port+RJ45

electrical port
2 Light port+RJ45 electrical port+RJ45 electrical port
3 Light port+light port+RJ45 electrical port
249
4.3 Technical data

Table 181 RS485 communication port
Items Data
Number 2
Lead by double wires, on the CPU module
Port type
bottom plate
Maximum transmission distance 1.0km
Test voltage 500V earthing AC voltage
Used for IEC 60870-5-103 protocol
Default setting 9600 bps
Transmission rate
Minimum: 1200bps; maximum: 19200bps
Table 182 Ethernet communication port
Items Data
Ethernet port
Number 3
RJ45 or optical Ethernet port, on the CPU
Port type
module bottom plate
Maximum transmission distance 100m
Used for IEC 61850 protocol
Transmission rate 100Mbit/s
Used for IEC 60870-5-103 protocol
Transmission rate 100Mbit/s
Table 183 Time synchronization
Items Data
Synchronization mode IRIG-B time synchronization
IRIG-B signal format IRIG-B000
Double wire conductor or optical fibers
Port type
connector, on the CPU module bottom plate
Voltage level Differential signal input
5 Power supply module

5.1 Overview
The input of the power supply module is the working voltage of the device,
and the output is the working voltage of the other boards of the device. The
input and output circuits of the power supply module are not common,
which plays the electric isolation role. In order to improve anti-interference
ability for power supply module circuit, the power supply module is
equipped with anti-interference filter inside the device. What's more, the
module is equipped with sophisticated power protection function
(undervoltage, overvoltage, overcurrent, overpower, etc.) to prevent IED
breakdown from power supply module failure. Power supply module
provides 11 channels BI and 4 channels relay BO, and provides reliable
electric isolation.
5.2 Power supply module terminals diagram

There is a power indicator on the power supply module panel to indicate
250
the status of the board, which is light during normal operation.

BI 10 on the power supply module is defined fixedly as “IEDRst”, BI 11 is
defined fixedly as “MaintState”, BI 1 is defined fixedly as "IEDFaultAlarm",
and BO 2 is defined fixedly as "RunErrAlarm". Other BI and BO can be
user-defined according to different functional requirements by the user.
Each channel has two sets of nodes, respectively, corresponding to BO
common terminal 1 and BI common terminal 2, and BO relays are all
unlatched type.
Note: BO 3 and BO 4 are fixed without starting relay exit.
Table 184 The definition of power supply module terminals
Number c a
2 Binary input 7 BI1
4 Binary input 8 Binary input 2
6 Binary input 9 Binary input 3
8 Device reset Binary input 4
Condition based
10 Binary input 5
maintenance
BI common
12 Binary input 6
terminal
BO common port BO common
14
1 port 2
16 IED fault alarm 1 IED fault alarm2
Abnormal
Abnormal
18 operation alarm
operation alarm 1
2
20 BO3-1 BO3-2
22 BO4-1 BO4-2
Power supply Power supply
24
positive positive
26 Undefined Undefined
Negative power Negative power
28
supply supply
30 Undefined Undefined
32 Grounding Grounding
5.3 Technical data

Table 185 Technical data
Item number Executive standard Data
Rated voltage Uaux IEC 60255-1 110 to 250V
Input voltage error range IEC 60255-1 ±%20, Uaux
Static power consumption IEC 60255-1 ≤ 50W for each power module
Maximum load power
IEC 60255-1 ≤ 60W for each power module
consumption
6 TCS Module
6.1 Overview
It shall be noticed that the facia shall be assembled and welded according
to the different rated working power, please make sure before use.
The built-in TCS function is applicable to the occasion when the trip
contacts in device are used for trip directly; generally, it is applied to the
occasion when installing protection device with medium voltage in switch
251
cabinet. In 80% occasions, only the trip circuit is monitored, the closing
circuit doesn't get monitored. Therefore, the device provides a module with
TCS circuit and trip relay cooperating with each other.
6.2 TCS Module instructions

TCS plate provides one tripping monitoring circuit, two large capacity BI
circuits and two pairs of relays and four outlet contacts.
Figure 131 TCS module terminal diagram

There are three indication lights on the TCS panel to show the status of the
board, the indication light definition is shown in the following.
Table 186 Definition of indicators of TCS module
Serial
number of
Indicator function Indicator state introduction
indicator
light
1 Power supply light Light is on when power on
2 Running light Flash when operating properly
3 Spare Off
252
1) TCS trip monitoring circuit

TCSmodule can monitor the open circuit of breaker the whole time,
including various operating conditions.
Figure 132 TCS circuit schematic diagram

Terminal a2, c4, a4 are connected with tripping circuit via auxiliary contact,
when failure occurs in circuit, K1 and K2 open simultaneously, and send
alarm signal; block can be realized through external circuit connection.
Figure 133 TCS circuit wiring diagram

2) Binary output circuit with large capacity
Taking the binary output circuit with large capacity PO1 as an example, the
schematic diagram and wiring instruction are as follows, open PO1 to drive
trip coil or closing coil.
253
Figure 134 Binary output circuit with large capacity schematic diagram
When the binary output current is larger than 6A, then the terminals of list
and list c need to be connected in parallel.
3) Ordinary BO circuit
Figure 135 Ordinary BO circuit schematic diagram

Table 187 Binary output instruction
Relay BO name Terminal BO type
c26～a26 Normally open

RELAY3A BO1

RELAY4A BO2
c32～a32 Always close
6.3 Technical data

Table 188 Binary output circuit with large capacity parameters
Items Executive Data
standard
Maximum work voltage IEC 60255-1 250V AC
8A continuous,
240W (DC)
2000VA(AC)
254

standard
220V(DC), 0.15A, L/R≤40ms
110V(DC), 0.30A, L/R≤40ms
Mechanical endurance IEC 60255-1 10100,000 times (resistive load)

IEC 60255-1
IEC 61810-1
IEC 60255-1
IEC 61810-1
AC1000V 1min

IEC 60255-1 55℃
operation allows
Table 189 TCS circuit (binary input) parameter

Executive
Items Data
standard
Rated voltage IEC 60255-1 110V, 220V DC
Startup voltage IEC 60255-1 70%Ur
Return voltage IEC 60255-1 55%Ur
143V, rated DC voltage 110V
The maximum BI voltage IEC 60255-1
286V, rated DC voltage 220V
Power consumption IEC 60255-1
Table 190 BO parameter
standard
Maximum work voltage IEC 60255-1 250V AC
8A continuous,
240W(DC) inductive load L/R>40 ms
2000VA (AC)
220V(DC), 0.15A, L/R≤40 ms
110V(DC), 0.30A, L/R≤40 ms
Mechanical endurance IEC 60255-1 10100,000 times (resistive load)

IEC 60255-1
IEC 61810-1
IEC 60255-1
IEC 61810-1
255

standard
AC1000V 1min

IEC 60255-1 55℃
operation allows
7 Test
Table 191 Insulation test
Items Executive standard Measurement methods
Front panel: IP54
IEC 60255-27
Protection level (IP) Side panel: IP52
IEC 60529
back panel: IP30
2KV, 50Hz (rated
voltage >63V) tested between
the following circuits:
 Power supply
 CT / VT input
IEC 60255-5
 Binary input
EN 60255-5
 Binary output
Dielectric Strength ANSI C37.90
Case grounding 500V ，
GB/T 15145-2008
50Hz(rated voltage ≤63V)
DL/T 478-2013
Test between the following
circuits,
 Communication port
 Time synchronization port
 Case earthing
5kV (rated voltage>60V)
1kV (rated voltage≤60V)
1.2/50Μs, 0.5J
IEC 60255-5 Test between the following
IEC 60255-27 circuits,
EN 60255-5  Power supply
Impulse voltage
ANSI C37.90  CT / VT input
GB/T 15145-2008  Binary input
DL/T 478-2013  Binary output
 Communication port
 Time synchronization port
 Case earthing
IEC 60255-5
IEC 60255-27
EN 60255-5
Insulation resistance ≥ 100MΩ，500V DC
ANSI C37.90
GB/T 15145-2008
DL/T 478-2013
Earthing resistance IEC 60255-27 ≤0.1Ω
Flame rating IEC 60255-27 Level V2
256
Table 192 EMC test

IEC 60255-22-1
IEC 60255-26 Level III
1MHz pulse group
IEC 61000-4-18 2.5kV CM;
interference test
EN 60255-22-1 1kV DM
ANSI/IEEE C37.90.1
IEC 60255-22-2 Level IV
Electrostatic discharge
IEC 61000-4-2 ±8kV electro-contact discharge;
immunity
EN 60255-22-2 15kV air discharge;
Level IV
Radiated electromagnetic IEC 60255-22-3
10V/m, 80MHz~1GHz,
field immunity EN 60255-22-3
1.4GHz~2.7GHz
IEC 60255-22-4,
Immunity degree of Level IV
IEC 61000-4-4
electrical fast transient pulse Communication port: 4KV;
EN 60255-22-4
group Other ports: 2KV
ANSI/IEEE C37.90.1
Level IV
IEC 60255-22-5
Surge (impact) immunity 4.0kV CM;
IEC 61000-4-5
2.0kV DM
Scanning frequency : 150kHz–80MHz
Calibration frequency: 27MHz and
Radio frequency IEC 60255-22-6
68MHz
interference test IEC 61000-4-6
10V
AM, 80%, 1kHz
Level A
Power frequency immunity
IEC 60255-22-7 300V CM
test
150V DM
Class V
Power frequency magnetic
IEC 61000-4-8 100 A / m > 30s
field immunity test
1000 A/m, from 1s to 3s
Level III
100KHz pulse-group noise
IEC 61000-4-18 Communication port: 2KV;
immunity
Other ports: 4KV
Damped oscillation Class V
IEC 61000-4-10
magnetic field immunity test 100A/m
Pulse magnetic field Class V
immunity IEC 61000-4-9 1000A/m
Conducted emission IEC 60255-25 0.15MHz~30MHz, class A
Radiated emission IEC 60255-25 30MHz~1000MHz, class A
Table 193 Mechanical experiment
Sinusoidal vibration IEC 60255-21-1
Grade 1
response test EN 60255-21-1
Sinusoidal vibration and IEC 60255-21-1
Grade 1
endurance test EN 60255-21-1
IEC 60255-21-2
Impact response test Grade 1
EN 60255-21-2
IEC 60255-21-2
Impact and endurance test Grade 1
EN 60255-21-2
Collision test IEC 60255-21-2 Grade 1
Aseismic test IEC 60255-21-3 Grade 1
257
Table 194 Environmental test

Items Data
High and low temperature test -40°C to +70°C
Temperature storage test -40°C to +70°C
Maximum relative humidity 95%, no
Humidity test
condensation
8 Structural design
Table 195 1Structural design
Items Data
Dimension 4U×1/2 19 inches
Weight ≤ 9kg
9 CE Certification
Table 196 CE Certification
Items Data
EN 61000-6-2 and EN61000-6-4(EMC guide
EMC
committee 2004/108/EC)
LVD EN 60255-27(LVD 2006/95 EC)
258
Chapter 34 Appendix
Chapter 34 Appendix
259
Chapter 34 Appendix
1 IED parameter
Table 197 IED parameter
Number Name Range Default Unit Remark
1. HVSideRatedCapacity 1~3000 120 MVA

2. MVSideRatedCapacity 1~3000 120 MVA
3. LVSideRatedCapacity 1~3000 120 MVA
4. HVSideConnectMode 0~1 0
5. MVSideVectorGrp 1~12 12
6. LVSideVectorGrp 1~12 11
7. HVSideRatedVolt 1~1000 150 kV
8. MVSideRatedVolt 1~1000 75 kV
9. LVSideRatedVolt 1~1000 75 kV
10. HVSideVTRatio 1~9999 150 kV
11. MVSideVTRatio 1~9999 75 kV
12. LVSideVTRatio 1~9999 75 kV
13. HVSideCTPriVal 1~9999 1000 A
14. HVSideCTSecVal 1~5 1 A
15. MVSideCTPriVal 1~9999 1000 A
16. MVSideCTSecVal 1~5 1 A
17. LVSideCTPriVal 1~9999 1000 A
18. LVSideCTSecVal 1~5 1 A
19. HVSideExtrCT(REF)PriVal 1~9999 1000 A
20. HVSideExtrCT(REF)SecVal 1~5 1 A
21. HVSideExtrCT(Spare)PriVal 1~9999 1000 A
22. HVSideExtrCT(Spare)SecVal 1~5 1 A
23. MVSideExtrCT(REF)PriVal 1~9999 1000 A
24. MVSideExtrCT(REF)SecVal 1~5 1 A
25. MVSideExtrCT(Spare)PriVal 1~9999 1000 A
26. MVSideExtrCT(Spare)SecVal 1~5 1 A
27. LVSideExtrCT(REF)PriVal 1~9999 1000 A
28. LVSideExtrCT(REF)SecVal 1~5 1 A
29. LVSideExtrCT(Spare)PriVal 1~9999 1000 A
30. LVSideExtrCT(Spare)SecVal 1~5 1 A
31. MeasureCTPriVal 1~9999 1000 A
32. MeasureCTSecVal 1~5 1 A
33. BISwitchSetGrp 0/1 0
260
Chapter 34 Appendix
2 Report list
About operation report and protection alarm report, please see the report
list in the protection chapter.
2.1 Alarm report

IED contains three kinds of alarm reports, showing as follows:
1) Alarm I belongs to IED alarm. When alarm I happens, the alarm LED
on the front panel of the IED will flash, all of protection function will be
out of service and the trip power of protection will be blocked by the
IED.
2) Alarm II belongs to other alarm. When class II alarms triggered, IED's
LED alarm light shall be lightened (except configurating setting group).
Alarm II won't block the trip power of protection. About alarm II
protection functions report list, please see alarm report lists in the
protection chapter.
Table 198 Alarm report list of class I
Number Report name Alarm code Description

1 SampleValErr 32769
2 IEDParmErr 32770
3 ROMSumChkErr 32771
4 SetErr 32772 Need to rewrite setting
5 UnconfirmConnMode 32773
6 SoftConnErr 32774
7 SystemCfgErr 32775
8 IED CPUModuleErr 32778
9 SetGrpPointerErr 32780
10 LogicFileErr 32798 Need to reload sf、esdc file
11 CfgFileErr 35769
12 CfgFileInconsist 35770
13 IOMatrixErr 35771 Need to reload sf、esdc file

The setting of binary output module
jumper is not consistent with the
14 BOChkNoResponse 33769
software configuration, and the
jumper should be reset.
15 BOBreakdown 33770
16 BIBreakdown 33784
17 BIO CPUErr 33789
18 BIO ROMSumErr 33790

The module of BI and BO is
19 BIO EEPROMErr 32779
unmarked, please remark it.
20 BIOCfgErr 32777
261
Chapter 34 Appendix
21 BISelfChkCircuitErr 33787
22 BOLatchedPropertyCfgErr 33793
You need to confirm the module
address jumper, module should be
23 BICommInterrupt 33781
plugged tightly, and confirm that the
program of BI is correct.
You need to confirm the module
address jumper, module should be
24 BOCommInterrupt 33782
plugged tightly, and confirm that the
program of BI is correct.
Table 199 Alarm report list of class I
Number Alarm report Alarm code Description

1 SRAMSelfChkErr 33771
2 TestStateNotRst 33772
3 OperFail 33773
4 CanCommInterrupt 33775
5 FLASHSelfChkErr 33776
6 WorkInTestSetGrp 33783
7 BIInputErr 33785
8 DualPosnInputIncosist 33786
9 BIOInputPowerErr 33788
2.2 Operation Report

Table 200 operation report list
Number Report Alarm code

1 32769
SwitchSetGrpSuccess
2 32789
CopySetGrpSuccess
3 32770
WriteIEDSetSuccess
4 32771
WriteParmSuccess
5 32772
WriteCfgSuccess
6 32773
AdjScaleSuccess
7 32788
AdjAngleSuccess
8 32774
HardConnOn/OffSuccess
9 32775
SoftConnOn/OffSuccess
10 32776
ClearCfg
11 32778
IEDRst(CPUReboot)
12 32779
FactoryRst
13 32780
BOTestSuccess
262
Chapter 34 Appendix
Number Report Alarm code

14 32782
ZeroDriftAdjSuccess
15 32783
ClearAllRptSuccess
16 32785
MaintModeOn
17 32786
MaintModeOff
18 32868
AutoRebootAfterCfg
3 Analog list
Table 201 Analog list
Number LCD display Description Remark
1 Uha Phase A voltage of high voltage side
2 Uhb Phase B voltage of high voltage side
3 Uhc Phase C voltage of high voltage side
4 Uh0 Zero sequence voltage of high voltage side
5 Uma Phase A voltage of medium voltage side
6 Umb Phase B voltage of medium voltage side
7 Umc Phase C voltage of medium voltage side
Zero sequence voltage of medium voltage

8 Um0
side
9 Ula Phase A voltage of low voltage side
10 Ulb Phase B voltage of low voltage side
11 Ulc Phase C voltage of low voltage side
Phase A Protection current of low voltage

12 Ul1a
branch1
13 Ul1b Phase B voltage of low voltage branch1
14 Ul1c Phase C voltage of low voltage branch1
15 Ul2a Phase A voltage of low voltage branch2
16 Ul2b Phase B voltage of low voltage branch2
17 Ul2c Phase C voltage of low voltage branch2
External Zero sequence voltage of low

18 U0
voltage side
Phase A Protection current of high voltage

19 Iha
side
263
Chapter 34 Appendix
Phase B Protection current of high voltage

20 Ihb
side
Phase C Protection current of high voltage

21 Ihc
side

22 Ih1a
branch1

23 Ih1b
branch1

24 Ih1c
branch1

25 Ih2a
branch2

26 Ih2b
branch2

27 Ih2c
branch2
The currents of
each branch of
the high voltage
side should be
converted to the
currents of first
Calculated Zero sequence current of high branch of high
28 Ih_3I0Cal
voltage side voltage side,
and then
calculate the
zero sequence
current by using
the sum
currents.
External Zero sequence current of high

29 Ih0REF
voltage side (Restricted earth fault)

30 Ih0BU
voltage side (Backup)

31 Ih0Gap
voltage side (Gap)
Phase A Protection current of medium voltage

32 Ima
side
Phase B Protection current of medium

33 Imb
voltage side
Phase C Protection current of medium

34 Imc
voltage side
264
Chapter 34 Appendix

35 Im1a
branch1

36 Im1b
voltage branch1

37 Im1c
voltage branch1

38 Im2a
branch2

39 Im2b
voltage branch2

40 Im2c
voltage branch2
The currents of
each branch of
the medium
voltage side
should be
converted to the
currents of first
Calculated Zero sequence current of medium
41 Im_3I0Cal branch of
voltage side
medium voltage
side, and then
calculate the
zero sequence
current by using
the sum
currents.
External Zero sequence current of medium

42 Im0REF

43 Im0BU

44 Im0Gap
voltage side (Gap)

45 Ila
side
Phase B Protection current of low voltage

46 Ilb
side
Phase C Protection current of low voltage

47 Ilc
side
Calculated Zero sequence current of low

48 Il_3I0Cal
voltage side
49 Il1a Phase A Protection current of low voltage
265
Chapter 34 Appendix

branch1

50 Il1b
branch1

51 Il1c
branch1

52 Il1_3I0Cal
voltage branch1

53 Il2a
branch2

54 Il2b
branch2

55 Il2c
branch2

56 Il2_3I0Cal
voltage branch2

57 Il3a
branch3

58 Il3b
branch3

59 Il3c
branch3

60 Il3_3I0Cal
voltage branch3
External Zero sequence current of low

61 Il0REF
External Zero sequence current of low

62 Il0BU
63 Iga Phase A current of the common winding
64 Igb Phase B current of the common winding
65 Igc Phase C current of the common winding
66 IDA Differential current of differential phase A
67 IDB Differential current of differential phase B
68 IDC Differential current of differential phase C
Restraint current of longitudinal differential

69 IResA
phase A
266
Chapter 34 Appendix

70 IResB
phase B

71 IResC
Phase C
Secondary harmonic of differential phase A

72 ID2A
Secondary harmonic of differential phase B

73 ID2B
Secondary harmonic of differential phase C

74 ID2C
Third harmonic of differential phase A

75 ID3A
Third harmonic of differential phase B

76 ID3B
Third harmonic of differential phase C

77 ID3C
Fifth harmonic of differential phase A

78 ID5A
Fifth harmonic of differential phase B

79 ID5B
Fifth harmonic of differential phase C

80 ID5C
81 IDSideA Side differential phase A differential current
82 IDSideB Side differential phase B differential current
83 IDSideC Side differential phase C differential current
Restricted earth fault differential current of the

84 ID0H
high voltage side
Restrict earth fault differential current of

85 ID0M
medium voltage side
Restrict earth fault differential current of low

86 ID0L
voltage side
Phase A thermal accumulated percentage of

87 HThermalA
the high voltage side
Phase B thermal accumulated percentage of

88 HThermalB
Phase C thermal accumulated percentage of

89 HThermalC
267
Chapter 34 Appendix
Phase A thermal accumulated percentage of

90 MThermalA
the medium voltage side
Phase B thermal accumulated percentage of

91 MThermalB
Phase C thermal accumulated percentage of

92 MThermalC
93 VFA Phase A over excitation multiple
94 VFB Phase B over excitation multiple
95 VFC Phase C over excitation multiple
4 Typical wiring
As for transformer backup protection IED, the typical wiring is shown as
below:
A
B
C
AIM2
I01
I02 IA
I03
I04 IB
* * * I05
I06 IC
I07
I08 IN
AIM1
* I01
I02
I1
Figure 136 Apply to transformer backup protection measurement three phase current,
zero sequence current and neutral point earth current
268
Chapter 34 Appendix
A
B
C
AIM2
U01
UA
U02
UB
U03
UC
U04
UN
AIM2
I01
I02 IA
I03
I04 IB
* * * I05
I06 IC
I07
I08 IN
AIM1
* I01
I02 I1
Figure 137 Apply to transformer backup protection measurement three-phase current,

zero sequence current and neutral point earth current and three-phase voltage beside
busbar
A
B
C
AIM2
I01
I02 IA
I03
I04 IB
* * * I05
I06 IC
I07
I08 IN
AIM2
U01
UA
U02
UB
U03
UC
U04
UN
AIM1
* I01
I02 I1
Figure 138 Apply to transformer backup protection measurement three-phase current,

zero sequence current and neutral point earth current and three-phase voltage beside line
269
Chapter 34 Appendix
A
B
C
AIM2
U01
UA
U02
UB
U03
UC
U04
UN
AIM2
I01
I02 IA
I03
I04 IB
* * * I05
I06 IC
I07
I08 IN
AIM1
* I01
I02 I1
zero sequence current and neutral point earth current and single line voltage beside
busbar
A
B
C
AIM2
U01
UA
U02
UB
U03
UC
U04
UN
AIM2
I01
I02 IA
I03
I04 IB
* * * I05
I06 IC
I07
I08 IN
AIM1
* I01
I02 I1
zero sequence current and neutral point earth current and single-phase voltage beside
busbar
270
Chapter 34 Appendix
5 Inverse time characteristic

5.1 Twelve types of IEC and ANSI time inverse
property curve
In setting, if time inverse property curve is set, the corresponding curve will
be related. Curve which can support IEC and ANSI standard.
Table 202 Twelve types of inverse time property of IEC and inverse time characteristics of
ANSI
Serial
number of Inverse time curve Parameter A Parameter B Parameter B
curve
1 IEC inverse time 0.14 0.02 0
IEC abnormal inverse
2 13.5 1.0 0
time
IEC extreme inverse
3 80.0 2.0 0
time
4 IEC short inverse time 0.05 0.04 0
5 IEC long inverse time 120.0 1.0 0
6 ANSI inverse time 8.9341 2.0938 0.17966
7 ANSI short inverse time 0.2663 1.2969 0.03393
8 ANSI long inverse time 5.6143 1 2.18592

ANSI moderate inverse
9 0.0103 0.02 0.0228
time
10 ANSI very inverse time 3.922 2.0 0.0982
ANSI extreme inverse
11 5.64 2.0 0.02434
time
ANSI definite inverse
12 0.4797 1.5625 0.21359
time
5.2 Definable properties by the user

For inverse time characteristic, when the curve No. is set 13, it is
user-defined characteristic.
A
t= � i p
+ B�T
� � −1
I
Where:
A: time coefficient of inverse time
B: time delay of inverse time
P: inverse time index
T: inverse time constant
271
Chapter 34 Appendix
5.3 Explanation of abbreviations

5.3.1 Explanation of setting abbreviations
Table 203 Explanation of setting abbreviations
Abbreviations Explanation
InstantDiffCurrSet Instantaneous differential current setting
DiffStartupSet Differential startup setting
BreakPoint1CurrSet Current setting of break point 1
BreakPoint2CurrSet Current setting of break point 2
Slope1RatioRestrCoef Restricted coefficient of slope 1
2ndHRestrCoef Restraint coefficient of the second harmonic
3rd/5thHRestrCoef Restraint coefficient of the third/fifth harmonic
2ndHBlkTime Blocking time of the second harmonic
3rd/5thHBlkTime Blocking time of 3rd/5th harmonic
HVSideREFStartupCurr Restricted earth fault startup current of high voltage side
HVSideREFAlarmCurr Restricted earth fault alarm current of high voltage side
HVsideREFRestrCoef Restricted earth fault restraint coefficient of high voltage side
HVSideREFTripTime Restricted earth fault trip time of high voltage side
HVSideREFAlarmTime Restricted earth fault alarm time of high voltage side
MVSideREFStartupCurr Restricted earth fault startup current of middle voltage side
MVSideREFAlarmCurr Restricted earth fault alarm current of middle voltage side

Restricted earth fault restraint coefficient of middle voltage
MVSideREFRestrCoef
side
MVSideREFTripTime Zero differential trip time of middle voltage side
MVSideREFAlarmTime Restricted earth fault alarm time of middle voltage side
LVSideREFStartupCurr Current of restricted earth fault startup of low voltage side
LVSideREFAlarmCurr Current of restricted earth fault alarm of low voltage side

Restraint coefficient of restricted earth fault of low voltage
LVSideREFRestrCoef
side
LVSideREFTripTime Restricted earth fault trip time of low voltage side
272
Chapter 34 Appendix
LVSideREFAlarmTime Restricted earth fault alarm time of low voltage side

Phase-to-phase impedance sensitive angle of high voltage
PPZSensitiveAngle
side
Phase-to-earth impedance sensitive angle of high voltage
HVSidePEZSensitiveAngle
side
HVSideImpedRstTime Impedance reset time of high voltage side
Phase-to-phase zone 1 point to transformer of high voltage
HVSidePPZ1PointToTransf
side
HVSidePPZ1PointToSystem Phase-to-phase zone 1 point to system of high voltage side
Time 1 of phase-to-phase impedance zone 1 of high voltage
HVSidePPZ1Time1
side
HVSidePPZ1Time2
side
HVSidePPZ1Time3
side
side
HVSidePPZ2Time1
side
HVSidePPZ2Time2
side
HVSidePPZ2Time3
side
side
HVSidePPZ3Time1
side
HVSidePPZ3Time2
side
HVSidePPZ3Time3
side
side
HVSidePPZ4Time Phase-to-phase impedance zone 4 time of high voltage side

Phase-to-earth zone 1 point to transformer of high voltage
HVSidePEZ1PointToTransf
side
HVSidePEZ1PointToSystem Phase-to-earth zone 1 point to system of high voltage side
HVSidePEZ1ImpedK0 Phase-to-earth zone 1 impedance K0 of high voltage side

Time 1 of phase-to-earth impedance zone 1 of high voltage
HVSidePEZ1Time1
side
HVSidePEZ1Time2
side
HVSidePEZ1Time3
side
273
Chapter 34 Appendix
side

HVSidePEZ2Time1
side
HVSidePEZ2Time2
side
HVSidePEZ2Time3
side
side

HVSidePEZ3Time1
side
HVSidePEZ3Time2
side
HVSidePEZ3Time3
side
side

Time of phase-to-earth impedance zone 4 of high voltage
HVSidePEZ4Time
side
Interturn3I0StartupSet Interturn zero sequence startup current setting
HVSideOCStage1Curve Overcurrent stage 1 curve of high voltage side
HVSideOCStage1CurrSet Current setting of overcurrent stage 1 of high voltage side
HVSideOCSatge1Time1 Time 1 of overcurrent stage 1 of high voltage side

Coefficient A of inverse time overcurrent stage 1 of high
HVSideInvTimeOCStage1CoefA
voltage side
Index P of inverse time overcurrent stage 1 of high voltage
HVSideInvTimeOC1IndexP
side
Time B of inverse time overcurrent stage 1 of high voltage
HVSideInvTimeOCStage1TimeB
side
HVSideInvTimeOCStage1Const Constant T of inverse time overcurrent stage 1 of high
T voltage side

voltage side
274
Chapter 34 Appendix
HVSideInvTimeOCStage2IndexP
side
side
T voltage side
HVSideOCSatge3Time Time of overcurrent stage 3 of high voltage side

voltage side
HVSideInvTimeOC3IndexP
side
side
T voltage side
Phase-to-phase voltage blocking current setting of high
HVSidePPVoltBlkOCSet
voltage side
Overcurrent negative sequence voltage blocking setting of
HVSideOC U2BlkOCSet
high voltage side
Sensitive angle of directional overcurrent of high voltage
HVSideDirOCSensitiveAngle
side
Overcurrent harmonic crossing blocking time of high voltage
HVSideHarmCrossBlkOCTime
side
HVSideOCRstTime Overcurrent reset time of high voltage side
Minimum trip time of inverse time overcurrent of high voltage
HVInvTimeOCMinTripTime
side

Overcurrent harmonic unblocking phase current of high
HVSideHarmUnblkPhCurr
voltage side
HVSideOC2ndHI2/I1Ratio Overcurrent second harmonic I2/I1 ratio of high voltage side
Harmonic unblocking phase current of overcurrent of middle
MVSideHarmUnblkPhCurr
voltage side
I2/I1 ratio of overcurrent 2nd harmonic of middle voltage
MVSideOC2ndHI2/I1Ratio
side
Harmonic unblocking phase current of overcurrent of low
LVSideHarmUnblkPhCurr
voltage side
LVSideOC2ndHI2/I1Ratio Overcurrent second harmonic I2/I1 ratio of low voltage side
275
Chapter 34 Appendix
HVSide3I0Stage1Curve Zero sequence current stage 1 curve of high voltage side

Zero sequence current stage 1 current setting of high
HVSide3I0Stage1CurrSet
voltage side
HVSide3I0Satge1Time1 Time 1 of zero sequence current stage 1 of high voltage side
Coefficient A of inverse time zero sequence current stage 1
HVSideInvTime3I0Stage1CoefA
Index P of inverse time zero sequence current stage 1 of
HVSideInvTime3I0Stage1IndexP
high voltage side
Time B of inverse time zero sequence current stage 1 of
HVSideInvTime3I0Stage1TimeB
high voltage side
Constant T of inverse time zero sequence current stage 1 of
HVSideInvTime3I0Stage1ConstT
high voltage side
voltage side
high voltage side
HVSideInvTime3I02TimeB
high voltage side
high voltage side
HVSide3I0Stage3Set
voltage side
high voltage side
HVSideInvTime3I0Stage3TimeB
high voltage side
high voltage side
Zero sequence current negative direction sensitive angle of
HVSide3I0DirSensitiveAngle
high voltage side
Negative sequence direction sensitive angle of zero
HVSide3I0NSDSensitiveAngle
sequence current of high voltage side
HVSide3I0RstTime Zero sequence current reset time of high voltage side
Minimum trip time of inverse time earth fault of high voltage
HVInvTime3I0MinTripTime
side
276
Chapter 34 Appendix

Harmonic unblocking phase current of overcurrent of high
HVSideHarmUnblkPhCurr
voltage side
HVSideOC2ndHI2/I1Ratio Overcurrent second harmonic I2/I1 ratio of high voltage side
Harmonic unblocking phase current of overcurrent of middle
MVSideHarmUnblkPhCurr
voltage side
I2/I1 ratio of overcurrent 2nd harmonic of middle voltage
MVSideOC2ndHI2/I1Ratio
side
Harmonic unblocking phase current of overcurrent of low
LVSideHarmUnblkPhCurr
voltage side
LVSideOC2ndHI2/I1Ratio Overcurrent second harmonic I2/I1 ratio of low voltage side
Harmonic unblocking phase current of zero sequence of
HVSide3I0HarmUnblkCurr
high voltage side
Zero sequence current 2nd harmonic I02/I01 ratio of high
HVSide3I02ndHI02/I01
voltage side
Harmonic unblocking phase current of zero sequence of
MVSide3I0HarmUnblkCurr
middle voltage side
I02/I01 ratio of zero sequence current secondary harmonic
MVSide3I02ndHI02/I01
of middle voltage side
Harmonic unblocking phase current of zero sequence of low
LVSide3I0HarmUnblkCurr
voltage side
Second harmonic I02/I01 ratio of zero sequence current of
LVSide3I02ndHI02/I01
low voltage side
Negative sequence current stage 1 curve of high voltage
HVSide3I2Stage1Curve
side
Current setting of negative sequence current stage 1 of high
voltage side
Time 1 of negative sequence current stage 1 of high voltage
HVSideI2Stage1Time1
side
Constant A of inverse time negative sequence current stage
HVSideInvTimeI2Stage1A
1 of high voltage side
Constant P of inverse time negative sequence current stage
HVSideInvTimeI2Stage1P
Constant B of inverse time negative sequence current stage
HVSideInvTimeI2Stage1B
Constant T of inverse time negative sequence current stage
HVSideInvTimeI2Stage1T
side
voltage side
HVSideI2Stage2Time1
side
277
Chapter 34 Appendix
side
voltage side
HVSideI2Stage3Time1
side
HVSideI2RstTime Negative sequence current reset time of high voltage side
Minimum trip time of inverse time negative sequence current
HVInvTimeI2MinTripTime
HVSideI2Satge1Time2
side
HVSideI2Satge1Time3
side
HVSideI2Satge2Time2
side
HVSideI2Satge2Time3
side
HVSideI2Satge3Time2
side
HVSideI2Satge3Time3
side
HVSideOVStage1Curve Overvoltage stage 1 curve of high voltage side
HVSideOVStage1VoltSet Voltage setting of overvoltage stage 1 of high voltage side
HVSideOVStage1Time Time of overvoltage stage 1 of high voltage side

Coefficient A of inverse time overvoltage stage 1 of high
HVSideInvTimeOVStage1CoefA
voltage side
Index P of inverse time overvoltage stage 1 of high voltage
HVSideInvTimeOVStage1IndexP
side
Time B of inverse time overvoltage stage 1 of high voltage
HVSideInvTimeOVStage1TimeB
side
Constant T of inverse time overvoltage stage 1 of high
HVSideInvTimeOVStage1ConstT
voltage side
HVSideOVStage2Curve Overvoltage stage 2 curve of high voltage side
HVSideOVStage2VoltSet Voltage setting of overvoltage stage 2 of high voltage side
HVSideOVStage2Time Time of overvoltage stage 2 of high voltage side

Coefficient A of inverse time overvoltage stage 2 of high
HVSideInvTimeOVStage2CoefA
voltage side
Index P of inverse time overvoltage stage 2 of high voltage
HVSideInvTimeOVStage2IndexP
side
278
Chapter 34 Appendix
Time B of inverse time overvoltage stage 2 of high voltage
HVSideInvTimeOVStage2TimeB
side
Constant T of inverse time overvoltage stage 2 of high
HVSideInvTimeOVStage2ConstT
voltage side
HVSideOVDropoffCoef Overvoltage dropoff coefficient of high voltage side
HVSideOVRstTime Overvoltage reset time of high voltage side

Minimum trip time of inverse time overvoltage of high
HVInvTimeOVMinTripTime
voltage side
Curve selection of zero sequence voltage stage 1 of low
LVSide3U0Stage1CurveSel
voltage side
LVSide3U0Stage1Set Voltage setting of zero sequence stage 1 of low voltage side
LVSide3U0Stage1Time Time of zero sequence voltage stage 1 of low voltage side

Coefficient A of inverse time zero sequence voltage stage 1
LVSideInvTime3U0Stage1CoefA
of low voltage side
Index P of inverse time zero sequence voltage stage 1 of
InvTime3U0Stage1IndexP
low voltage side
Time B of inverse time zero sequence voltage stage 1 of low
LVSideInvTime3U0Stage1TimeB
voltage side
LVSideInvTime3U0Stage1Const Constant T of inverse time zero sequence voltage stage 1 of
T low voltage side
LVSide3U0RstTime Zero sequence voltage reset time of low voltage side
Minimum trip time of inverse time zero sequence voltage of
LVInvTime3U0MinTripTime
low voltage side
Negative sequence voltage stage 1 curve of high voltage
HVSide3U2Stage1Curve
side
Voltage setting of negative sequence voltage stage 1 of high
HVSide3U2Stage1VoltSet
voltage side
Time of negative sequence voltage stage 1 of high voltage
HVSide3U2Stage1Time
side
Coefficient A of inverse time negative sequence voltage
HVSideInvTimeU2Stage1A
Index P of inverse time negative sequence voltage stage 1
HVSideInvTimeU2Stage1P
Time B of inverse time negative sequence voltage stage 1 of
HVSideInvTimeU2Stage1B
high voltage side
Constant T of inverse time negative sequence voltage stage
HVSideInvTimeU2Stage1T
Negative sequence voltage stage 2 curve of high voltage
HVSide3U2Stage2Curve
side
Voltage setting of negative sequence voltage stage 2 of high
HVSide3U2Stage2VoltSet
voltage side
Time of negative sequence voltage stage 2 of high voltage
HVSide3U2Stage2Time
side
Coefficient A of inverse time negative sequence voltage
HVSideInvTimeU2Stage2A
Index P of inverse time negative sequence voltage stage 2
HVSideInvTimeU2Stage2P
Time B of inverse time negative sequence voltage stage 2 of
HVSideInvTimeU2Stage2B
high voltage side
Constant T of inverse time negative sequence voltage stage
HVSideInvTimeU2Stage2T
279
Chapter 34 Appendix
HVSideU2RstTime Negative sequence voltage reset time of high voltage side

Minimum trip time of inverse time negative sequence voltage
HVInvTimeU2MinTripTime
HVSideUVStage1CurveSel Curve selection of undervoltage stage 1 of high voltage side
HVSideUVStage1VoltSet Voltage setting of undervoltage stage 1 of high voltage side
HVSideUVStage1Time Time of undervoltage stage 1 of high voltage side

Coefficient A of inverse time undervoltage stage 1 of high
HVSideInvTimeUVStage1A
voltage side
Index P of inverse time undervoltage stage 1 of high voltage
HVSideInvTimeUVStage1P
side
Time B of inverse time undervoltage stage 1 of high voltage
HVSideInvTimeUVStage1B
side
Index T of inverse time undervoltage stage 1 of high voltage
HVSideInvTimeUVStage1T
side
HVSideUVStage2CurveSel Curve selection of undervoltage stage 2 of high voltage side
HVSideUVStage2VoltSet Voltage setting of undervoltage stage 2 of high voltage side
HVSideUVStage2Time Time of undervoltage stage 2 of high voltage side

Coefficient A of inverse time undervoltage stage 2 of high
HVSideInvTimeUVStage2A
voltage side
Index P of inverse time undervoltage stage 2 of high voltage
HVSideInvTimeUVStage2P
side
Time B of inverse time undervoltage stage 2 of high voltage
HVSideInvTimeUVStage2B
side
Index T of inverse time undervoltage stage 2 of high voltage
HVSideInvTimeUVStage2T
side
HVSideUVoltChkCurrSet Undervoltage check current setting of high voltage side
HVSideUVMinVoltSet Undervoltage minimum voltage setting of high voltage side
HVSideUVDropoffCoef Undervoltage dropoff coefficient of high voltage side
HVSideUVRstTime Undervoltage reset time of high voltage side

Minimum trip time of inverse time undervoltage of high
HVInvTimeUVMinTripTime
voltage side
HVSideThermalOLCurrSet Thermal overload current setting of high voltage side
HVSideThermalTimeConst Thermal time constant of high voltage side
HVSideThermalOLCoolingCoef Thermal overload cooling coefficient of high voltage side
HVSideThermalOLAlarmCoef1 Thermal overload alarm coefficient 1 of high voltage side
HVSideThermalOLAlarmCoef2 Thermal overload alarm coefficient 2 of high voltage side
HVSideCBFCurrSet Circuit breaker failure current setting of high voltage side

Zero sequence current setting of circuit breaker failure of
HVSideCBF3I0Set
high voltage side
280
Chapter 34 Appendix
Negative sequence current setting of circuit breaker failure
HVSideCBFI2Set
HVSideCBFTime1 Time of circuit breaker failure 1 of high voltage side
HVSideCBFTime2 Time of circuit breaker failure 2 of high voltage side

Circuit breaker failure binary input alarm time of high voltage
HVSideCBF BIAlarmTime
side
LVSideDZCurrSet Dead zone protection current setting of low voltage side
LVSideDZTripTime Dead zone trip time of low voltage side
LVSideDZ3I0Set Dead zone zero sequence current setting of low voltage side
Dead zone negative sequence current setting of low voltage
LVSideDZI2Set
side
LVSideDZ BIErrTime Dead zone binary input error time of low voltage side
HVSideStubStage1CurrSet Current setting of stub stage 1 of high voltage side
HVSideStubStage1Set Time of stub stage 1 of high voltage side
HVSideStubStage2CurrSet Current setting of stub stage 2 of high voltage side
HVSideStubStage2Time Time of stub stage 2 of high voltage side

Zero sequence current setting of pole discrepancy of low
LVSidePD3I0Set
voltage side
Negative sequence current setting of pole discrepancy of
LVSidePD3I2Set
low voltage side
LVSidePDTripTime Pole discrepancy trip time of low voltage side
InvTimeOEStage1Time Inverse time overexcitation stage 1 time
281
Chapter 34 Appendix
InvTimeOERstTime Reset time of inverse time overexcitation
OECoolingTime Cooling time of overexcitation
DefTimeOEStage1TripSet Trip setting of definite time overexcitation stage 1
DefTimeOEStage1Time Time of definite time overexcitation stage 1
DefTimeOEStage2TripSet Trip setting of definite time overexcitation stage 2
DefTimeOE3TripSet Trip setting of definite time overexcitation stage 3
DefTimeRstTime Reset time of definite time
OEDropoffCoef Dropoff coefficient of overexcitation
OERatedVoltVal Rated voltage of overexcitation
HVSideUFFreqSet Underfrequency setting of high voltage side
HVSideUFTime Underfrequency time of high voltage side
HVSideDf/dtBlkFreqSet Df/dt blocking frequency setting of high voltage side

Rate of change of frequency blocking setting of high voltage
HVSideFreqDf/dtBlkSet
side
HVSideLoadShedVoltBlkSet Load shedding voltage blocking setting of high voltage side
HVSideLoadShedCurrBlkSet Load shedding current blocking setting of high voltage side
HVSideOFSet Overfrequency setting of high voltage side
HVSideOFTime Overfrequency time of high voltage side
HVSideLoadShedVoltBlkSet Load shedding voltage blocking setting of high voltage side
HVSideLoadShedCurrBlkSet Load shedding current blocking setting of high voltage side
NonElectric1Time Non-electric 1 time
282
Chapter 34 Appendix
NonElectricRstTime Non-electric reset time
SideDiffStartupSet Startup setting of side differential
SideDiffBreakPoint1CurrSet Break point 1 current setting of side differential
SideDiffBreakPoint2CurrSet Break point 2 current setting of side differential
SideDiffSlope1RatioRestrCoef Slope 1 restricted coefficient of side differential
SideDiffSlope2RatioRestrCoef Slope 2 ratio restricted coefficient of side differential
SideDiffSlope3RatioRestrCoef Slope 3 ratio restricted coefficient of side differential
HVSideVTFailCurrSet VT failure current setting of high voltage side

Zero sequence current setting and negative voltage setting
HVSideVTFail3I03I2Set
of VT failure of high voltage side
HVSideVTFailPEVoltSet VT failure phase-to-earth voltage setting of high voltage side
VT failure phase-to-phase voltage setting of high voltage
HVSideVTFailPPVoltSet
side
HVSideVTFailNormalVoltSet VT failure normal voltage setting of high voltage side
HVSideVTFailAlarmTime VT failure alarm time of high voltage side
HVSideVTFailBIErrTime VT failure binary input error time of high voltage side
StubDiffCurrSet Current setting of stub differential
RestrCoef Restraint coefficient
OCStage1CurrSet Current setting of overcurrent stage 1
OCSatge1Time Time of overcurrent stage 1
OCStage2CurrSet Current setting of overcurrent stage 2
OCSatge2Time Time of overcurrent stage 2
ChargingProtCurrSet Charge protection current setting
ChargingProtTime Charge protection time
IEDCTPriVal IED CT primary value
IEDCTSecVal IED CT secondary value
BISwitchSetGrp Binary input switches setting group
HVSideGapOCSet Gap overcurrent setting of high voltage side
HVSideGapOCTime1 Gap overcurrent time 1 of high voltage side
283
Chapter 34 Appendix
HVSideGapOCTime2 Gap overcurrent time 2 of high voltage side
HVSideGapOVSet Gap overvoltage setting of high voltage side
HVSideGapOVTime1 Gap overvoltage time 1 of high voltage side
HVSideGapOVTime2 Gap overvoltage time 2 of high voltage side
HVSideOLCurrSet Overload current setting of high voltage side
HVSideOLTime Overload time of high voltage side
HVSideStartFanStage1CurrSet Current setting of startup airing stage 1 of high voltage side
HVSideStartFanStage1Time Time of startup airing stage 1 of high voltage side
HVSideStartFanStage2CurrSet Current setting of startup airing stage 2 of high voltage side
HVSideStartFanStage2Time Time of startup airing stage 2 of high voltage side
HVSideBlkVoltAdjCurrSet Blocking voltage adjustment current setting of high voltage
HVSideBlkVoltAdjTime Blocking voltage adjustment time of high voltage side
BISwitchSetGrp Binary input switches setting group
5.3.2 Explanation of logic switch abbreviations

Table 204 Explanation of logic switch abbreviations
DiffOn Enable differential protection
InstantaneousDiffOn Enable instantaneous differential
CTFailDetectOn Enable CT failure detection
CTFailBlkDiff Block Diff CT_Fail
ExcitInrushBlkDiff Excitation inrush current blocking differential
2ndHRestr Second harmonic restraint
OEBlkDiff Overexcitation block differential
OE5thHOn Enable fifth harmonic of overexcitation

Delta connection minus zero sequence current of high
HVSideDeltaMinus3I0
voltage side
MVSideDeltaMinus3I0 Delta minus zero sequence current of medium voltage side
LVSideDeltaMinus3I0 Delta minus zero sequence current of low voltage side
HVSideREFProtTrip Restricted earth fault protection trip of high voltage side
284
Chapter 34 Appendix
HVSideREFAlarm Restricted earth fault alarm of high voltage side
HVSideCTFailBlkREF CT failure blocking restricted earth fault of high voltage side
MVSideREFProtTrip Restricted earth fault protection trip of middle voltage side
MVSideREFAlarm Restricted earth fault alarm of middle voltage side

CT failure blocking restricted earth fault of middle voltage
MVSideCTFailBlkREF
side
LVSideREFTrip Restricted earth fault trip of low voltage side
LVSideREFAlarm Restricted earth fault alarm of low voltage side
LVSideCTFailBlkREF CT failure blocking restricted earth fault of low voltage side

Enable time 1 of phase-to-phase impedance zone 1 of high
HVSidePPZ1Time1On
voltage side
HVSidePPZ1Time2On
voltage side
HVSidePPZ1Time3On
voltage side
HVSidePPZ2Time1On
voltage side
HVSidePPZ2Time2On
voltage side
HVSidePPZ2Time3On
voltage side
HVSidePPZ3Time1On
voltage side
HVSidePPZ3Time2On
voltage side
HVSidePPZ3Time3On
voltage side
Enable phase-to-phase impedance zone 4 of high voltage
HVSidePPZ4On
side
Phase-to-phase impedance zone 1 is blocked by power
HVSidePPZ1BlkByPowerSwing
swing of high voltage side
Enable phase-to-earth impedance zone 1 time 1 of high
HVSidePEZ1Time1On
voltage side
HVSidePEZ1Time2On
voltage side
HVSidePEZ1Time3On
voltage side
HVSidePEZ2Time1On
voltage side
HVSidePEZ2Time2On
voltage side
HVSidePEZ2Time3On
voltage side
285
Chapter 34 Appendix
HVSidePEZ3Time1On
voltage side
HVSidePEZ3Time2On
voltage side
HVSidePEZ3Time3On
voltage side
Enable phase-to-earth impedance zone 4 of high voltage
HVSidePEZ4On
side
Phase-to-earth impedance zone 1 is blocked by power
HVSidePEZ1BlkByPowerSwing
InterturnProtIsOn Enable interturn protection
HVSideOCSatge1Time1On Enable time 1 of overcurrent stage 1 of high voltage side
HVSideDirOCStage1 Directional overcurrent stage 1 of high voltage side

Forward direction of overcurrent stage 1 of high voltage
HVSideOCStage1FwdDir
side
Overcurrent stage 1 is blocked by voltage of high voltage
HVSideOCStage1BlkByVolt
side
Overcurrent stage 1 of high voltage side is blocked by
HVSideOCStage1BlkBy2ndH
second harmonic

side
side
second harmonic

side
side
second harmonic
286
Chapter 34 Appendix
VTFailProtOff Disable VT failure protection

Enable time 1 of zero sequence current stage 1 of high
HVSide3I0Satge1Time1On
voltage side
External zero sequence current stage 1 of high voltage
HVSide3I0Stage1Extr
side
Directional zero sequence current stage 1 of high voltage
HVSideDir3I0Stage1
side
Forward direction of zero sequence current stage 1 of high
HVSide3I0Stage1FwdDir
voltage side
Zero sequence current stage 1 of high voltage side is
HVSide3I0Stage1BlkBy2ndH
blocked by second harmonic
voltage side
MVSide3I0Stage2Extr
side
HVSideDir3I0Stage2
side
voltage side
HVSide3I0tg2BlkBy2ndH
voltage side
HVSide3I0Stage3Extr
side
HVSideDir3I0Stage3
side
voltage side
HVSide3I0Stage3BlkBy2ndH
Enable zero sequence check U2/I2 direction of high
HVSide3I0ChkU2I2DirOn
voltage side
zero sequence current harmonic of high voltage side
HVSide3I0HarmChkExtrI02/I01
checks external I02/I01
voltage side
voltage side
voltage side
voltage side
voltage side
voltage side
Enable zero sequence checks U2/I2 direction of low
voltage side
Zero sequence current harmonic of low voltage side
287
Chapter 34 Appendix
LVSideExtr3U0 External zero sequence voltage of low voltage side

Enable time 1 of zero sequence current stage 1 of low
LVSide3I0Satge1Time1On
voltage side
LVSide3I0Stage1Extr External zero sequence current stage 1 of low voltage side
Directional zero sequence current stage 1 of low voltage
LVSideDir3I0Stage1
side
Forward direction of zero sequence current stage 1 of low
LVSide3I0Stage1FwdDir
voltage side
Zero sequence current stage 1 of low voltage side is
LVSide3I0Stage1BlkBy2ndH
voltage side
LVSideDir3I0Stage2
side
voltage side
voltage side
LVSideDir3I0Stage3
side
voltage side
Enable zero sequence check U2I2 direction of low voltage
side
Zero sequence current harmonic of low voltage side
LVSideExtr3U0 External zero sequence voltage of low voltage side
VTFailProtOff Disable VT failure protection

Enable time 1 of negative sequence current stage 1 of high
HVSideI2Stage1Time1On
voltage side
voltage side
voltage side
voltage side
voltage side
HVSI2Stage2Time2On
voltage side
HVSI2Stage2Time3On
voltage side
HVSI2Stage3Time2On
voltage side
288
Chapter 34 Appendix
voltage side
HVSideOVStage1On Enable stage 1 of overvoltage of high voltage side
HVSideOVStage2On Enable stage 2 of overvoltage of high voltage side

Overvoltage checks phase-to-earth voltage of high voltage
HVSideOVChkPEVolt
side
HVSideOVChk1Ph Overvoltage checks phase 1 of high voltage side
Enable stage 1 of zero sequence voltage of low voltage
LVSide3U0Stage1On
side
Enable stage 1 of negative sequence voltage of high
HVSide3U2Stage1On
voltage side
Enable stage 2 of negative sequence voltage of high
HVSide3U2Stage2On
voltage side
HVSideUVStage1On Enable stage 1 of undervoltage of high voltage side
HVSideUVStage2On Enable stage 2 of undervoltage of high voltage side
HVSideUVChkCurrOn Enable undervoltage checking current of high voltage side

Undervoltage checks circuit breaker state of high voltage
HVSideUVoltChkCBState
side
HVsideUVChk1Ph Undervoltage checks 1 phase 1 of high voltage side
Undervoltage checks phase-to-earth voltage of high
HVSideChkPEVolt
voltage side
HVSideThermalOLOn Enabled thermal overload of high voltage side
HVSideThermalOLStage1AlarmO
Enable thermal overload stage 1 alarm of high voltage side
n
HVSideThermalOLStage2AlarmO
Enable thermal overload stage 2 alarm of high voltage side
n
HVSideThermalCurve Thermal curve of high voltage side
HVSideCBFOn Enable circuit breaker failure of high voltage side

Circuit breaker failure check negative zero sequence
HVSideCBFChk3I0/I2
current of high voltage side
HVSideCBFChkPosn Circuit breaker failure check position of high voltage side
LVSideSideDZOn Enable dead zone protection of low voltage side

Dead zone checks zero or negative sequence current of
LVSideDZChk3I0/I2
low voltage side
HVSideStubStage1On Enable stub stage 1 of high voltage side
HVSideStubStage2On Enable stub stage 2 of high voltage side
LVSidePDOn Enable pole discrepancy of low voltage side

Pole discrepancy of low voltage side checks zero or
LVSidePDChk3I0/3I2
negative sequence current
InvTimeOExcitOn Enable inverse time overexcitation
289
Chapter 34 Appendix
InvTimeOEAlarm Inverse time overexcitation alarm
DefTimeOEStage1On Enable stage 1 of definite time overexcitation
DefTimeOEStage1Alarm Alarm of finite time overexcitation stage 1
OEUsePEVolt Overexcitation uses phase-to-earth voltage
HVSideUFOn Enable underfrequency of high voltage side

Underfrequency load shedding checking current of high
HVSideUFLSChkCurrOn
voltage side
HVSideUFChkDf/dt Underfrequency check df/dt of high voltage side
HVSideOFOn Enable overfrequency of high voltage side
NonElectric1On Enable non-electric 1
SideDiffOn Enable side differential protection
SideDiffCTFailDetectOn Enable CT failure detection of side differential
SideDiffCTFailBlkDiff CT failure blocking differential of side differential
HVSideNutrPointEarth Neutral point earthing of high voltage side
HVSideVTFailOn Enable VT failure of high voltage side
StubDiffOn Enable stub differential
OCStage1On Enable overcurrent stage 1
OCStage2On Enable overcurrent stage 2
ChargingProtOn Enable charge protection
290
Chapter 34 Appendix
HVSideGapCalc3U0 Calculated gap zero sequence voltage of high voltage side
HVSideGapOCTime1On Enable gap overcurrent time 1 of high voltage side
HVSideGapOCTime2On Enable gap overcurrent time 2 of high voltage side
HVSideGapOVTime1On Enable gap overvoltage time 1 of high voltage side
HVSideGapOVTime2On Enable gap overvoltage time 2 of high voltage side
HVSideOLOn Enabled overload of high voltage side
HVSideStartFanStage1On Enable stage 1 of startup airing of high voltage side
HVStartStartFanStage2On Enable stage 2 of startup airing of high voltage side
HVSideBlkVoltAdjOn Enable blocking voltage adjustment of high voltage side
5.3.3 Explanation of trip and alarm reoport abbreviations

Table 205 Explanation of trip and alarm reoport abbreviations
IEDStartup IED startup
DiffPhATrip Trip of differential phase A
DiffPhBTrip Trip of differential phase B
DiffPhCTrip Trip of differential phase C
InstantDiffPhATrip Trip of instantaneous differential phase A
InstantDiffPhBTrip Trip of instantaneous differential phase B
InstantDiffPhCTrip Trip of instantaneous differential phase C
HVSideCTFail CT failure of high voltage side
HVSide1CTFail CT failure of high voltage side 1
HVSide2CTFail CT failure of high voltage side 2
MVSideCTFail CT failure of middle voltage side
MVSide1CTFail CT failure of middle voltage side 1
MVSide2CTFail CT failure of middle voltage side 2
LVSideCTFail CT failure of low voltage side
LVSide1CTFail CT failure of low voltage side 1
291
Chapter 34 Appendix
DiffCurrOverLmtAlarm Differential current overlimit alarm
2ndHBlkDiff Blocking differential of the second harmonic
3rd/5thHBlkDiff Blocking differential of third or fifth harmonic
HVSideREFTrip Restrict earth fault trip of high voltage side
MVSideREFTrip Restrict earth fault trip of medium voltage side
LVSideREFTrip Restrict earth fault trip of low voltage side r
HVSideREFCurrOverLmt Restrict earth fault overlimit of high voltage side
MVSideREFCurrOverLmt Restrict earth fault overlimit of medium voltage side
LVSideREFCurrOverLmt Restrict earth fault overlimit of low voltage side

Time 1 trip of phase-to-phase impedance zone 1 of high
HVSidePPZ1Time1Trip
voltage side
HVSidePPZ1Time2Trip
voltage side
HVSidePPZ1Time3Trip
voltage side
HVSidePPZ2Time1Trip
voltage side
HVSidePPZ2Time2Trip
voltage side
HVSidePPZ2Time3Trip
voltage side
HVSidePPZ3Time1Trip
voltage side
HVSidePPZ3Time2Trip
voltage side
HVSidePPZ3Time3Trip
voltage side
Trip of Phase-to-phase impedance zone 4 of high voltage
HVSidePPZ4Trip
side
Time 1 trip of phase-to-earth impedance protection zone 1
HVSidePEZ1Time1Trip
HVSidePEZ1Time2Trip
HVSidePEZ1Time3Trip
HVSidePEZ2Time1Trip
HVSidePEZ2Time2Trip
HVSidePEZ2Time3Trip
HVSidePEZ3Time1Trip
HVSidePEZS3Time2Trip
292
Chapter 34 Appendix
HVSidePEZ3Time3Trip
Trip of phase-to-earth impedance protection zone 4 of high
HVSidePEZ4Trip
voltage side
Time 1 trip of phase-to-phase distance zone 1 of middle
MVSidePPZ1Time1Trip
voltage side
MVSidePPZ1Time2Trip
voltage side
MVSidePPZ1Time3Trip
voltage side
MVSidePPZ2Time1Trip
voltage side
MVSidePPZ2Time2Trip
voltage side
MVSidePPZ2Time3Trip
voltage side
MVSidePPZ3Time1Trip
voltage side
MVSidePPZ3Time2Trip
voltage side
MVSidePPZ3Time3Trip
voltage side
Trip of phase-to-phase impedance stage 4 of middle
MVSidePPZ4Trip
voltage side
MVSidePEZ1Time1Trip Time 1 trip of phase-to-earth zone 1 of middle voltage side

Trip of phase-to-earth impedance protection stage 4 of
MVSidePEZ4Trip
middle voltage side
InterturnTrip Interturn protection trip
Time 1 trip of overcurrent stage 1 of high/middle/low voltage
H/M/LVSideOCSatge1Time1Trip
side
Phase A trip of overcurrent stage 1 of high/middle/low
H/M/LVSideOCStage1PhATrip
voltage side
Phase B trip of overcurrent stage 1 of high/middle/low
H/M/LVSideOCStage1PhBTrip
voltage side
Phase C trip of overcurrent stage 1 of high/middle/low
H/M/LVSideOCStage1PhCTrip
voltage side
side
293
Chapter 34 Appendix
side
H/M/LVSideOCInrushBlk Overcurrent inrush blocking of high/middle/low voltage side
Time 1 trip of zero sequence stage 1 of high/middle/low
H/M/LVSide3I0Satge1Time1Trip
voltage side
voltage side
voltage side
Zero sequence inrush blocking of high/middle/low voltage
H/M/LVSide3I0InrushBlk
side
Time 1 trip of negative current stage 1 of high/middle/low
H/M/LVSideI2Satge1Time1Trip
voltage side
voltage side
voltage side
HVSideOVStage1Trip Trip of overvoltage stage 1 of high voltage side
HVSideOVStage2Trip Trip of overvoltage stage 2 of high voltage side
MVSideOVStage1Trip Trip of overvoltage stage 1 of middle voltage side
MVSideOVStage2Trip Trip of overvoltage stage 2 of middle voltage side
LVSide3U0Trip Zero sequence voltage trip of low voltage side

Trip of negative sequence voltage stage 1 of high voltage
HVSide3U2Stage1Trip
side
Trip of negative sequence voltage stage 2 of high voltage
HVSide3U2Stage2Trip
side
Trip of negative sequence current stage 1 of middle voltage
MVSide3U2Stage1Trip
side
Trip of negative sequence current stage 2 of middle voltage
MVSide3U2Stage2Trip
side
HVSideUVStage1Trip Trip of undervoltage stage 1 of high voltage side
HVSideUVStage2Trip Trip of undervoltage stage 2 of high voltage side
MVSideUVStage1Trip Trip of undervoltage stage 1 of middle voltage side
MVSideUVStage2Trip Trip of undervoltage stage 2 of middle voltage side
HVSideThermalOLTrip Trip of thermal overload of high voltage side
MVSideThermalOLTrip Thermal overload trip of middle voltage side
HVSideThermalOLStage1Alarm Alarm of thermal overload stage 1 of high voltage side
HVSideThermalOLStage2Alarm Alarm of thermal overload stage 2 of high voltage side
MVSideThermalOLStage1Alarm Alarm of thermal overload stage 1 of middle voltage side
MVSideThermalOLStage2Alarm Alarm of thermal overload stage 2 of middle voltage side
294
Chapter 34 Appendix
HVSideCBFStarup Circuit breaker failure startup of high voltage side
HVSideCBFStage1Trip Trip of circuit breaker failure stage 1 of high voltage side
HVSideCBFStage2Trip Trip of circuit breaker failure stage 2 of high voltage side
MVSideCBFStartup Crcuit breaker failure startup of medium voltage side

Trip of circuit breaker failure stage 1 of middle voltage side
MVSideCBFStage1Trip
failure
Trip of circuit breaker failure stage 2 of middle voltage side
MVSideCBFStage2Trip
failure
LVSideCBFStarup Circuit breaker failure startup of low voltage side
LVSideCBFStage1Trip Trip of circuit breaker failure stage 1 of low voltage side
LVSideCBFStage2Trip Trip of circuit breaker failure stage 2 of low voltage side

Binary input error of circuit breaker failure of high voltage
HVSideCBF BIErr
side
Binary input error of circuit breaker failure of middle voltage
MVSideCBF BIErr
side
Binary input error of circuit breaker failure of low voltage
LVSideCBF BIErr
side
LVSideDZTrip Trip of dead zone of low voltage side
LVSideDZ BIErrAlarm Binary input error alarm of dead zone of low voltage side
HVSideStubStage1Trip Trip of stub stage 1 of high voltage side
HVSideStubStage1PhATrip Trip of stub stage 1 phase A of high voltage side
HVSideStubStage1PhBTrip Trip of stub stage 1 phase B of high voltage side
HVSideStubStage1PhCTrip Trip of stub stage 1 phase C of high voltage side
HVSideStubStage2Trip Trip of stub stage 2 of high voltage side
HVSideStubStage2PhATrip Trip of stub stage 2 phase A of high voltage side
HVSideStubStage2PhBTrip Trip of stub stage 2 phase B of high voltage side
HVSideStubStage2PhCTrip Trip of stub stage 2 phase C of high voltage side
MVSideStubStage1Trip Trip of stub stage 1 of middle voltage side
MVSideStubStage1PhATrip Trip of stub stage 1 phase A of middle voltage side
MVSideStubStage1PhBTrip Trip of stub stage 1 phase B of middle voltage side
MVSideStubStage1PhCTrip Trip of stub stage 1 phase C of middle voltage side
MVSideStubStage2Trip Trip of stub stage 2 of middle voltage side
MVSideStubStage2PhATrip Trip of stub stage 2 phase A of middle voltage side
295
Chapter 34 Appendix
MVSideStubStage2PhBTrip Trip of stub stage 2 phase B of middle voltage side
MVSideStubStage2PhCTrip Trip of stub stage 2 phase C of middle voltage side
LVSidePDTrip Pole discrepancy trip of low voltage side
LVSidePDProtTripPosnErr Pole discrepancy protection trip error of low voltage side
InvTimeOETrip Trip of overexcitation inverse time
DefTimeOEStage1Trip Trip of overexcitation definite time stage 1
InvTimeOEAlarm Inverse time overexcitation alarm
HVSideUFTrip Underfrequency trip of high voltage side
HVSideOFTrip Overfrequency trip of high voltage side
NonElectric1Trip Non-electric 1 trip
SideDiffPhATrip Phase A trip of side differential
SideDiffPhBTrip Phase B trip of side differential
SideDiffPhCTrip Phase C trip of side differential
HVSideCTFail CT failure of high voltage side
MVSideCTFail CT failure of middle voltage side
CommonWindCTFail CT failure of common winding
SideDiffCurrOverLmtAlarm Current overlimit alarm of side differential
296
Chapter 34 Appendix
HVSideVTFail VT failure of high voltage side
HVSideVTFailBIErr Binary input error of VT failure of high voltage side
MVSideVTFail VT failure of medium voltage side
MVSideVTFailBIErr Binary input error of VT failure of medium voltage side
LVSideVTFail VT failure of low voltage side
LVSideVTFailBIErr Binary input error of VT failure of Low voltage side
TripFail Trip failure
MEndSideCB CTFail CT failure of side circuit breaker of M end
NEndSideCB CTFail CT failure of side circuit breaker of N end
MiddleCB CTFail CT failure of circuit breaker of middle voltage side
LongTermDiffCurr Long-term differential current
3PhSeqUnmatch Sequence of three-phase is unmatched
IsoPosnErr Isolator position error
IEDStartup IED startup
DiffCurrAuxStartup Differential current auxiliary startup
CurrSumAuxStartup Current sum auxiliary startup
OCStage1Trip Trip of overcurrent stage 1
OCStage2Trip Trip of overcurrent stage 2
ChargingProtTrip Charging protection trip
2SideDiffTrip Differential trip of two-side
3SideDiffTrip Differential trip of three-side
FaultPhCurr1 Fault phase current 1
IsoOpen Isolator open
IsoClose Isolator close
HVSideGapOCTime1Trip Time 1 trip of gap overcurrent of high voltage side
HVSideGapOCTime2Trip Time 2 trip of gap overcurrent of high voltage side
HVSideGapOVTime1Trip Time 1 trip of gap overvoltage of high voltage side
297
Chapter 34 Appendix
HVSideGapOVTime2Trip Time 2 trip of gap overvoltage of high voltage side
HVSideOL Overload of high voltage side
MVSideOL Overload of middle voltage side
LVSideOL Overload of low voltage side
HVSideStartFan Startup airing of high voltage side
BlkVoltAdj Blocking voltage adjustment
SampleValErr Error of sampling value
IEDParmErr Error of IED parameter
ROMSumChkErr Error of ROM sum check
SetErr Error of setting
UnconfirmConnMode Unconfirmed connector mode
SoftConnErr Error of soft connector
SystemCfgErr Error of system configuration
IED CPUModuleErr Error of IED CPU module
SetGrpPointerErr Error of setting group pointer
LogicFileErr Error of logic file
CfgFileErr Error of configuration file
CfgFileInconsist Configured files are inconsistent
IOMatrixErr Error of IOMatrix
BOChkNoResponse Binary output checking has no response
BOBreakdown Binary output breakdown
BIBreakdown Binary input breakdown
BIO CPUErr The CPU of binary input and output works improperly
BIO ROMSumErr ROM summing error of binary input and output
BIO EEPROMErr EEPROM error of binary input and binary output
BIOCfgErr Configuration error of binary input and binary output
BISelfChkCircuitErr Selfcheck circuit error of binary input
BOLatchedPropertyCfgErr Configuration error of binary output latched property
BICommInterrupt Binary input communication is interrupted
298
Chapter 34 Appendix
BOCommInterrupt Binary output communication is interrupted
SRAMSelfChkErr Self-check error of SRAM
TestStateNotRst Test state is not reset
OperFail Operate unsuccessfully
CanCommInterrupt Can communication is interrupted
FLASHSelfChkErr Self-check error of FLASH
WorkInTestSetGrp Work in test setting group
BIInputErr Input error of binary input
DualPosnInputIncosist Double position inputs are not consistent
BIOInputPowerErr Input power error of binary input and binary output
5.3.4 Explanation of operation report abbreviations

Table 206 Explanation of operation report abbreviations
SwitchSetGrpSuccess Switch the setting group successfully
CopySetGrpSuccess Copy the setting group successfully
WriteIEDSetSuccess Write IED setting successfully
WriteParmSuccess Write IED parameter successfully
WriteCfgSuccess Write the configuration successfully
AdjScaleSuccess Adjust the scale successfully
AdjAngleSuccess Adjust the angle successfully
HardConnOn/OffSuccess Enable/disable hard connector successfully
SoftConnOn/OffSuccess Enable/disable soft connector successfully
ClearCfg Clear configuration
IEDRst(CPUReboot) IED reset (CPU reboot)
FactoryRst Factory reset
BOTestSuccess Test binary output successfully
ZeroDriftAdjSuccess Adjust zerp drift successfully
ClearAllRptSuccess Clear all report successfully
299
Chapter 34 Appendix
MaintModeOn Enable check mode
MaintModeOff Disable maintenance mode
AutoRebootAfterCfg Automatic reboot after configuration
5.3.5 Explanation of device menu abbreviations

Table 207 Explanation of device menu abbreviations
ViewInfo View information
RunOper Running operation
ViewRpt View report
WriteSet Write setting
TestMenu Test menu
IEDSet Set IED
Language Set Language
IEDState Protection state
ViewSet View setting
ConnState Connector state
VerInfo Version information
IEDSet Set IED
ConnOn/Off Enable/Disable connector
SwitchSetGrp Switch setting group
LocalCtrl Local control
SLDCtrl Single line diagram control
StartupRpt Startup report
TripRpt Trip report
AlarmRpt Alarm report
OperRpt Operation report
BIChgRpt Binary input change report
StartDFRList Startup disturbance and fault record list
TripDFRList Trip disturbance and fault record list
ProtSet Protection setting
300
Chapter 34 Appendix
GroupCopy Copy setting group
EquipParm Equipment parameter
BCUParm Bay control unit parameter
BOTest Binary output test
CommChk Communication check
LEDTest LED Test
MC DFR Manually controlled disturbance and fault record
FactoryTest Factory test
TimeSet Set time
CommParm Communication parameter
OtherSet Set Other
CHN Chinese
ENG English
RUS Russian
Analog Analog
Measure Measurement
AnalogInput Analog input
PowerMeter Power metering
BIO Binary input output
GOState GO state
StateMon State monitor
AlarmInfo Alarm information
CalcSet Calculated setting
BCUParm Bay control unit parameter
FcnConn Function connector
GOOSEPubSoftConn GOOSE publishing soft connector
GOOSESubSoftConn GOOSE subscription soft connector
IED IDCode IED identification code
IEDVer IED version
VrTrmlChkCode Check code of virtual terminal
301
Chapter 34 Appendix
TimeSyncMode Time synchronization mode
CommParm Communication parameter
FcnConn Function connector
GOOSEPubSoftConn GOOSE publishing soft connector
GOOSESubSoftConn GOOSE subscription soft connector
Bay0 Bay 0
StationName Substation name
ProtEquipName Protection equipment name
ConventionalBO Conventional binary output
GOOSE BO GOOSE binary output
FnAlarmChk Protection function alarm check
TripAlarmChk Trip alarm check
GOAlarmChk GO alarm check
BIChk Binary input check
MSTAlarmChk MST alarm check
ConnChk Connector check
AnalogChk Analog check
MeasureChk Measurement check
ViewZeroDrift View zero drift
ViewScale View scale
AdjZeroDrift Adjust zero drift
AdjScale Adjust scale
AngleCorrection Angle correction
SetClock Set clock
TimeSyncMode Time synchronization mode
NetTimeSyncIPSet Set Network time synchronization IP
TimeZone Set time zone
TimeSyncService Time synchronization service
DST Daylight saving time
EthernetSet Set Ethernet
302
Chapter 34 Appendix
SerialSet Set serial port
ProtocolSet Protocol setting
SetPassword Set password
Contrast Contrast
DisplayMode Display mode
PowerMeterZeroing Power metering reset
Confirm Confirm switching
PriVal Primary value
SecVal Secondary value
PriVal Primary value
SecVal Secondary value
ConventionalBI Conventional binary input
GOOriginBI GOOSE original binary input
ConventionalBO Conventional binary output
GOOSESubState Goose subscription state
GOOSEPubState GOOSE publication state
EthernetSet Set Ethernet
Mode1 Mode 1
Mode2 Mode 2
Serial1Set Set serial port 1
303

PRINT - - CSC-326 Transformer Protection IED Manual V1.01 (英文) - 0000189070

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

PRINT - - CSC-326 Transformer Protection IED Manual V1.01 (英文) - 0000189070

Caricato da

Copyright:

Formati disponibili

CSC-326

Transformer Protection IED

Manufacturer: Beijing Sifang Automation Co., Ltd.

Applicability of this manual

Strictly follow the company and international safety regulations.

Do not touch any circuitry during operation. Potentially lethal

Never connect or disconnect wire and/or linker to or from IED

Always connect the IED to protective earth regardless of the

Do not disconnect the secondary connection of current

Do not remove the screw from a powered IED or from an IED

Using the certified conductive bags to transport PCBs (modules).

Do not connect live wires to the IED, internal circuitry may be

When replacing modules using a conductive wrist strap

When installing and commissioning, take care to avoid electrical

About this chapter

4U, 19 2 inches, two-windings, three-winding

protection, two-side current differential protection, two stages of

VT failure 97FF HV/MV/LV

Table 3 Typical application configuration2 (T zone protection)

Application 1 is shown as below:

Application 2 is shown as below:

Typical applications for T zone protection are as follows:

Figure 3 Typical applications

3.2 Control function

3.3 Measurement function

3.4 Monitoring function

Position of circuit breaker, disconnector and other switching devices monitoring

Position of circuit breaker monitoring

Auxiliary contacts of circuit breaker monitoring

Disturbance and fault record

3.5 Communication mode

Communication port on the front plate

RJ45 Ethernet communication port

Communication port on the rear plate

Isolated electrical RS485 communication port

Ethernet electrical/optical communication port

Time synchronization port

Chapter 2 Common functions

About this chapter

1 Event record and analysis

1.2 Fault record

1.3 Waveform record

1.4 Sequence of event (SOE)

1.5 Operation record

2.2 Diagnostic principle

3 Time synchronization function

3.2 Synchronization principle

Synchronization from a higher level

Optional synchronization of modules at

Figure 4 Synchronization principle diagram

3.3 IRIG-B code synchronization mode

3.4 PPS synchronization mode

3.5 SNTP time synchronization mode

3.6 1588 synchronization mode

Chapter 3 Fault phase selection

About this chapter

2 Function module description

Faulty Phase Selection

No. Key Unit Type Description

BIBlk BOOL BI blocking BO

VTFailBlk BOOL VT failure blocking signs

CTFailBlk BOOL CT failure blocking sign

FaultPhase SINT Fault phase