PCS-978 Transformer and Reactor Relay PDF

PCS-978
Transformer Relay
Instruction Manual
NR Electric Co., Ltd.

Preface
Preface
Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.
Documentation for equipment ordered from NR Electric Co., Ltd. is dispatched separately from
manufactured goods and may not be received at the same time. Therefore this guide is provided
to ensure that printed information normally present on equipment is fully understood by the
recipient.
Before carrying out any work on the equipment the user should be familiar with the contents of this
manual, and read relevant chapters carefully.
This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.
Health and Safety
The information in this chapter of the equipment documentation is intended to ensure that
equipment is properly installed and handled in order to maintain it in a safe condition.
When electrical equipment is in operation, dangerous voltages will be present in certain parts of
the equipment. Failure to observe warning notices, incorrect use, or improper use may endanger
personnel and equipment and cause personal injury or physical damage.
Before working in the terminal strip area, the equipment must be isolated.
Proper and safe operation of the equipment depends on appropriate shipping and handling,
proper storage, installation and commissioning, and on careful operation, maintenance and
servicing. For this reason only qualified personnel may work on or operate the equipment.
Qualified personnel are individuals who:
 Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;
 Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;
 Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;
 Are trained in emergency procedures (first aid).
PCS-978 Transformer Relay I

Date: 2011-06-27
Preface
Instructions and Warnings
The following indicators and standard definitions are used:
DANGER means that death, severe personal injury, or considerable equipment damage will
occur if safety precautions are disregarded.
WARNING means that death, severe personal, or considerable equipment damage could occur
if safety precautions are disregarded.
CAUTION means that light personal injury or equipment damage may occur if safety
precautions are disregarded. This particularly applies to damage to the device and to
resulting damage of the protected equipment.
WARNING!
The firmware may be upgraded to add new features or enhance/modify existing features, please
make sure that the version of this manual is compatible with the product in your hand.
WARNING!
During operation of electrical equipment, certain parts of these devices are under high voltage.
Severe personal injury or significant equipment damage could result from improper behavior.
Only qualified personnel should work on this equipment or in the vicinity of this equipment. These
personnel must be familiar with all warnings and service procedures described in this manual, as
well as safety regulations.
In particular, the general facility and safety regulations for work with high-voltage equipment must
be observed. Noncompliance may result in death, injury, or significant equipment damage.
DANGER!
Never allow the current transformer (CT) secondary circuit connected to this equipment to be
opened while the primary system is live. Opening the CT circuit will produce a dangerously high
voltage.
WARNING!
 Exposed terminals
Do not touch the exposed terminals of this equipment while the power is on, as the high
voltage generated is dangerous
 Residual voltage
Hazardous voltage can be present in the DC circuit just after switching off the power supply. It
takes a few seconds for the voltage to discharge.
II PCS-978 Transformer Relay

Date: 2010-06-27
Preface
CAUTION!
 Earthing
The earthing terminal of the equipment must be securely earthed
 Operating environment
The equipment must only be used within the range of ambient environment detailed in the
specification and in an environment free of abnormal vibration.
 Ratings
Before applying AC voltage and current or the power supply to the equipment, check that they
conform to the equipment ratings.
 Printed circuit board
Do not attach and remove printed circuit boards when the power supply to the equipment is
on, as this may cause the equipment to malfunction.
 External circuit
When connecting the output contacts of the equipment to an external circuit, carefully check
the supply voltage used in order to prevent the connected circuit from overheating.
 Connection cable
Carefully handle the connection cable without applying excessive force.
Copyright
Version: 2.02 NR ELECTRIC CO., LTD.
69 Suyuan Avenue. Jiangning, Nanjing 211102, China
P/N: EN_YJBH5100.0086.0203 Tel: +86-25-87178185, Fax: +86-25-87178208
Website: www.nrelect.com, www.nari-relays.com
Copyright © NR 2011. All rights reserved Email: nr_techsupport@nari-relays.com
We reserve all rights to this document and to the information contained herein. Improper use in particular reproduction and dissemination
to third parties is strictly forbidden except where expressly authorized.
The information in this manual is carefully checked periodically, and necessary corrections will be included in future editions. If
nevertheless any errors are detected, suggestions for correction or improvement are greatly appreciated.
We reserve the rights to make technical improvements without notice.
PCS-978 Transformer Relay III

Date: 2011-06-27
Preface
IV PCS-978 Transformer Relay

Date: 2010-06-27
Preface
Documentation Structure
The manual provides a functional and technical description of this relay and a comprehensive set
of instructions for the relay’s use and application.
The chapter contents are summarized as below:
1 Introduction
Briefly introduce the application, functions and features about this relay.
2 Technical Data
Introduce the technical data about this relay, such as electrical specifications, mechanical
specifications, ambient temperature and humidity range, communication port parameters, type
tests, setting ranges and accuracy limits and the certifications that our products have passed.
3 Operation Theory
Introduce a comprehensive and detailed functional description of all protective elements.
4 Supervision
Introduce the automatic self-supervision function of this relay.
5 Meaurement and Recording

Introduce the management function (measurment and recording) of this relay.
6 Hardware
Introduce the main function carried out by each module of this relay and providing the definition of
pins of each module.
7 Settings
List settings including equipment settings, communication settings, description settings, display
settings, VEBI settings and etc., and some notes about the setting application.
8 Human Machine Interface

Introduce the hardware of the human machine interface (HMI) module and a detailed guide for the
user how to use this relay through the HMI. It also lists all the information which can be view
through the HMI, such as settings, measurements, all kinds of reports etc.
9 Configurable Function
Introduce how to make system configuration, function configuration, binary input and binary output
configuration, LED indicator configuration and programming logic through PCS-PC software.
10 Communication
Introduce the communication port and protocol which this relay can support, the IEC60970-5-103,
IEC61850 and DNP3.0 protocols are introduced in details.
PCS-978 Transformer Relay V

Date: 2011-06-27
Preface
11 Installation
Introduce the recommendations on unpacking, handling, inspection and storage of this relay. A
guide to the mechanical and electrical installation of this relay is also provided, incorporating
earthing recommendations. A typical wiring connection to this relay is indicated.
12 Commissioning
Introduce how to commission this relay, comprising checks on the calibration and functionality of
this relay.
13 Maintenance
A general maintenance policy for this relay is outlined.
14 Decommissioning and Disposal

A general decommissioning and disposal policy for this relay is outlined.
15 Manual Version History

List the instruction manual version and the modification history records.
Typographic and Graphical Conventions
Deviations may be permitted in drawings and tables when the type of designator can be obviously
derived from the illustration.
The following symbols are used in drawings:
&
AND gate
≥1
OR gate
Comparator
BI Binary signal via opto-coupler
SET I> Input signal from comparator with setting
EN Input signal of logic setting for function enabling
Input of binary signal except those signals via opto-coupler

SIG
VI PCS-978 Transformer Relay

Date: 2010-06-27
Preface
Input of other signal

OTH
XXX Output signal
Timer
t Timer (optional definite-time or inverse-time characteristic)
t
10ms 0ms
Timer [delay pickup (10ms), delay dropoff (0ms), non-settable]
[t1] 0ms
Timer (t1: delay pickup, settable)
0ms [t2]
Timer (t2: delay dropoff, settable)
[t1] [t2]
Timer (t1: delay pickup, t2: delay dropoff, settable)
IDMT Timer (inverse-time characteristic)

*
Instrument current transformer

*
Instrument voltage transformer
PCS-978 Transformer Relay VII

Date: 2011-06-27
Preface
VIII PCS-978 Transformer Relay

Date: 2010-06-27
1 Introduction
1 Introduction
Table of Contents
1.1 Application ....................................................................................................... 1-1

1.2 Functions ......................................................................................................... 1-4
1.3 Features............................................................................................................ 1-8
1.3.1 General Features ................................................................................................................1-8
1.3.2 Transformer Current Differential Protection ........................................................................1-9
1.3.3 Restricted Earth Fault Protection ......................................................................................1-10
1.3.4 Winding Differential Protection .........................................................................................1-10
1.3.5 Reactor Current Differential Protection ............................................................................. 1-11
1.3.6 Reactor Inter-Turn Fault Protection .................................................................................. 1-11
1.3.7 Overexcitation Protection.................................................................................................. 1-11
1.3.8 Mechanical Protection ......................................................................................................1-12
1.3.9 Phase Overcurrent Protection ..........................................................................................1-12
1.3.10 Ground Overcurrent Protection .......................................................................................1-12
1.3.11 Phase Overvoltage Protection ........................................................................................1-12
1.3.12 Residual Overvoltage Protection ....................................................................................1-13
1.3.13 Undervoltage Protection .................................................................................................1-13
1.3.14 Thermal Overload Protection ..........................................................................................1-13
List of Figures
Figure 1.1-1 2-winding and 3-winding applications ................................................................1-2
Figure 1.1-2 Autotransformer applications .............................................................................1-3
Figure 1.2-1 Function diagram 1 for a three-winding transformer ........................................1-5
Figure 1.2-2 Function diagram 2 for an auto-transformer ......................................................1-6
Figure 1.2-3 Function diagram 3 for reactor............................................................................1-6
List of Tables
PCS-978 Transformer Relay 1-a

Date: 2011-07-19
1 Introduction
Table 1.2-1 Protective functions in PCS-978 ...........................................................................1-4
Table 1.2-2 Miscellaneous functions in PCS-978 ....................................................................1-7
1-b PCS-978 Transformer Relay

Date: 2011-07-19
1 Introduction
1.1 Application
PCS-978 is a microprocessor-based relay designed for the protection of a two-winding transformer,

three-winding transformer or auto-transformer in any voltage level, oprotection of a shunt reactor,
which provides up to 36 analog input channels including current and voltage inputs.
PCS-978 provides full transformer protections configurable by user. Ancilary functions of fault
diagnostic, disturbance records, event records and communication function are integrated in the
relay.
Applications of PCS-978 are shown as below:
PCS-978 Transformer Relay 1-1

Date: 2011-07-19
1 Introduction
Figure 1.1-1 2-winding and 3-winding applications
1-2 PCS-978 Transformer Relay

Date: 2011-07-19
1 Introduction
(a) autotransformer with 1 circuit (d) autotransformer with 1 circuit

breaker at two sides breaker at each sides
(b) autotransformer with 1½ circuit breakers (e) autotransformer with 1½ circuit breakers
arrangement on one side and 1 circuit breaker arrangement on one side and 1 circuit breaker
at the other side at the other two sides
(f) autotransformer with 1½ circuit breakers

(c) autotransformer with 1½ circuit breakers arrangement on two sides and 1 circuit breaker at
arrangement on two sides one side
(g) autotransformer with 1½ circuit breakers

arrangement on each side
Figure 1.1-2 Autotransformer applications

Date: 2011-07-19
1 Introduction
1.2 Functions
z Protective Functions
Protective functions of PCS-978 are listed in the following table
NOTE! The protective functions listed in following table are equipped for standard
PCS-978, the functions can be configured according to user request.
Table 1.2-1 Protective functions in PCS-978
Protective function
Transformer biased current differential protection 87T
Transformer unrestrained current differential protection 50/87UT
Transformer DPFC* baised current differential protection. 7/87DT
Reactor biased current differential protection 87R
Reactor unrestrained current differential protection 50/87UR
Reactor DPFC biased current differenital protection 7/87DR
Biased restricted earth fault protection 64REF
Biased winding differential protection 87W/87N
Inter-turn fault protection 32G, 21G,
Definite-time overexciation protection

24
Inverse-time overexcitation protection
Underfrequency protection 81U

Overfrequency protection 81O
Mechanical protection MR
Definite-time phase overcurrent protection

50P,51P,67P
Inverse-time phase overcurrent protection
Definite-time ground overcurrent protection

50G,51G,67G
Inverse-time ground overcurrent protection
Definite-time residual overvoltage protection

59G
Inverse-time residual overvoltage protection
Definite-time phase overvoltage protection

59P
Inverse-time phase overvoltage protection
Undervoltage protection 27
Thermal overload protection 49
Breaker failure protection 50BF
Pole disagreement protection 62PD
Phase overcurrent alarm element 50PAlm

Date: 2011-07-19
1 Introduction
Protective function
CT saturation detection
Inrush current detection
Overexcitation detection
Harmonic blocking function
VT circuit failure supervision VTS
CT circuit failure supervision CTS
NOTE! DPFC* is the abbreviation of “Deviation of Power Frequency Component”. In case
of a fault occured in the power system, the fault component could be analysed into three
parts: the power frequency components before the fault, the power frequency variables
during the fault and the transient variables during the fault. DPFC is the power frequency
variable during the fault.
z Function Diagram
The function diagrams for protecting a three-winding transformer, an auto-transformer and a

reactor are respectively shown below.
HVS PCS-978
50G,51G.67G
DT, IDMT
ROC
*
Mechanical signals
*
from transformer
Cal
LVS 3I0
*
*
MVS
87T 50PAlm
50P, 51P, 67P
* * 7/87DT
64REF DT, IDMT
50BF 49 62PD DT
BFP THEM PoleDisag OC Alarm
50/87UT OC
DIFF
26,63,71 24 59G 27 59P

MR U * / f* > DT, IDMT DT DT, IDMT
81U,81O ROV UV OV
UF,OF 3U0 Cal
Figure 1.2-1 Function diagram 1 for a three-winding transformer

Date: 2011-07-19
1 Introduction
*
*
*
*
*
U * / f* >
Figure 1.2-2 Function diagram 2 for an auto-transformer
Bus I
52
Line
VT
PCS-978
Cal
3I0
CT1 * * *
52
Cal
3I0
Mechanical
signals from
50N, 51N
reactor DT, IDMT
26,63,71 87R OC
Shunt 32G 50P, 51P
52 reactor MR 7/87DR 87N 49
21G DT, IDMT THEM
50/87UR NeuDiff OC 50G, 51G
IntTurn
DIFF DT, IDMT
OC
Bus II Cal
3I0
CT2
* * *
CT3
Neutral
earthing reactor
Figure 1.2-3 Function diagram 3 for reactor
z Miscellaneous functions
Miscellaneous functions are listed in the following table, such as metering, self-supervision and
oscillography, communication functions, and etc.

Date: 2011-07-19
1 Introduction
Table 1.2-2 Miscellaneous functions in PCS-978
Miscellaneous functions
Programmable tripping output matrix
Programmable binary input
Configurable function Programmable binary output
Programmable LED indicators
Configurable protection function
Self-supervision Relay hardware supervision and secondary circuit supervision
Metering 24 samples per cycle
Disturbance
64 fault reports, 64 disturbnace waveforms
recording
Oscillography
(1) Protection picks up to trig
function
Trigger mode (2) Manually trigger on keypad.
(3) Remotely trigger through PCS-PC software
1024 supervison alarm events
Event recording 1024 binary input events
1024 eqiupment log events
Local HMI LCD and keypad
Remote HMI PCS-PC software or substation automation system software
IEC 60870-5-103
Rear IEC 61850-8-1
Ports type
communication DNP 3.0 (Serial port)
ports to host (Specified when order)
Protocol type IEC 60870-5-103
Rear communication port to printer One RS-485 or RS-232
Pulse per second/minute (PPS/PMS) via binary input

Time synchronisation Clock message via communication ports
IRIG-B via RS-485 differential level
Up to 36 AC analog input channels

6 DC analog input channels
Up to 18 binary inputs
2 equipment alarm and fail output contacts (alarm N.O. and fail
Input and output
N.C.)
11 signal output contacts (N.O.)
Up to 22 output contacts (N.O.) for tripping
(Specified when order)
10 setting groups are available
Voltage and current drift auto-adjustment

Date: 2011-07-19
1 Introduction
1.3 Features
1.3.1 General Features

z Configurable Function
Modules of PCS-978 equipment adopt intelligent design, amount of input and output modules and
module slot position are configurable. User can increase or decrease the amount of AC input
module, binary input module and binary output module, and terminals of those modules can be
defined according to actual requirement. Besides, configurability is also reflected in software
design of equipment, which means that user can hide the protective element not used or add new
protective module not in standard configuration.
z Parallel Calculation of Double DSP system
The hardware of equipment comprises a 64-bit microprocessor and two 32-bit digital signal
processors (DSP). Those processor can operate in parallel companied by fast A/D converter. The
64-bit microprocessor performs logic calculation and the DSP performs the protection calculation.
High performance hardware ensures real time calculation of all protection relays within a sampling
interval.
On the premise of 24 samples per cycle, all data measurement, calculation and logic
discrimination could be done within one sampling period. The event recording and protection logic
calculation are completed simultaneously.
z Independent Fault Detector
Independent fault detectors in fault detector DSP module for connecting power supply of output
relays. The relay can drive a tripping output only when protection element on protection DSP
module operates with the fault detector in the fault detector DSP module operating simultaneously.
This kind of independent supervision of tripping outputs using fault detectors can avoid any
maloperation possibly caused by any hardware component faulure. This highly increases the
security. Please refer to Chapter 6 Hardware for details.
z Configurable Tripping output
The tripping output contacts can be configured by tripping matrix and suitable to any mode of
tripping.
z Fault Recording Function
¾ Event records including 1024 binary input events and 1024 alarm events
¾ Disturbance records including 64 fault reports, and 64 disturbance waveforms, and file
format of waveform is compatible with international COMTRADE91 and COMTRADE99
file. Up to 80 analog inputs and 200 binary inputs can be recorded, and three
oscillograph triggering mode are supported, which are protection pickup triggering,
manual triggering, and remote triggering through PCS-PC software.
z User HMI Interface

Date: 2011-07-19
1 Introduction
The HMI interface with a LCD and a 9-button keypad on the front panel is very friendly to the user.
z Communication Ports
¾ One front RS-232 port
¾ RS-485 ports and Ethernet ports communication with SCADA or RTU
¾ One rear RS-485 with clock synchronization.
¾ One rear RS-232 or RS-485 with printer.
¾ GOOSE communication function (optional module)
z Clock Synchronizations
Various GPS clock synchronizations: second/minute pulse via binary input or RS-485, message
via communication ports and IRIG-B synchronization.
1.3.2 Transformer Current Differential Protection

z Maximum six group CT inputs for differential protection.
z Protection for 2-winding, 3-winding transformer and auto-transformer.
z 24 vector groups available for two-winding transformer.
z 288 vector groups available for 3-winding transformer.
z Optional inrush current distinguished principles: harmonic criterion (second harmonic and
third harmonic) or waveform distortion.
z There are two optional modes for harmonic criterion: self-adaptive blocking mode and
phase-to-phase cross blocking mode. Self-adaptive blocking mode can enhance ability of
differential protection to avoid maloperation during transformer energization effectively and
ensure high speed of differential protection for faults under normal operation.
z Fifth harmonic or third harmonic criterion applied continuously to detect overexciation

condition.
z Three slopes biase differential protection are settable by users.
z Unrestrained instantaneous differential protection is equipped.
z Distinct Method of Phase Shifting
During transformer energization, ᇞ→Y transfer method is used to adjust phase angle of
secondary current on each side of the transformer, and thus the faulty and healthy phase can
possess its characteristic. Therefore, restraint current and differential current can be
phase-segregated, which can distinguish the faulty phase from phase only with inrush current
characteristic when transformer is energized.
z High sensitive and securable DPFC biased differential protection
DPFC biased current differential protection is regardless of the load current and is sensitive to

Date: 2011-07-19
1 Introduction
small internal fault current within the transformer. Its performance against current transformer
saturation is also good.
z Reliable biased current differential protection
Biased current differential protection with initial restraint slope consists of sensitive and
conventional differential elements as well as independent CT saturation criterion.
z Differential CT Circuit Failure Detection
With the adoption of voltage and current combination method, CT secondary circuit failure can
be distinguished.
1.3.3 Restricted Earth Fault Protection

z Maximum 4 group CT and 1 neutral CT inputs for REF protection, and the maximum current
inputs applied for an auto-transformer with two circuit breakers at HV and MV sides
respectively.
z Maximum 3 REF protections for each side of a three-winding transformer
z Inrush current has no effect on REF protection.
z RFE protection has high sensitivity to internal earth faults because there is no load current in
the restraint current.
z The tap of transformer has no effect on REF protection.
z CT Transient detection function based on the ratio of residual current to positive-sequence

current is adopted to eliminate the influence of difference of transient characteristic to REF
protection.
z CT saturation detection function based on 2nd and 3rd harmonics is adopted to avoid
maloperation of REF protection during an external fault.
1.3.4 Winding Differential Protection

z Maximum 5 group CT inputs applied for an auto-transformer with two circuit breakers at HV
and MV sides respectively.
z Maximum 3 winding differential protections for each side of a three-winding transformer
z Inrush current has no effect on winding differential protection.
z Winding differential protection has high sensitivity to internal earth faults because there is no
load current in the restraint current.
z The tap of transformer has no effect on winding differential protection.
z CT Transient detection function based on the ratio of residual current to positive current is
adopted to eliminate the influence of difference of transient characteristic to winding
differential protection.

Date: 2011-07-19
1 Introduction
maloperation of winding differential protection during an external fault.
1.3.5 Reactor Current Differential Protection

z Reliable CT transient characteristic distinguishing method
During reactor energization, inrush current similar to that of transformer occurs. There is great
decaying DC component in inrush current, which may result in the difference of transient
transfer characteristics between CTs at two ends of reactor, and therefore differential current
occurs. Inrush current can be distinguished to avoid maloperation of current differential
protection by detecting harmonic of differential current and measured current and adopting
asynchronous method for recognition of CT saturation.
small internal fault current within the reactor. Its performance against current transformer
conventional differential elements as well as independent CT saturation criterion and
harmonic blocking.
be distinguished.
1.3.6 Reactor Inter-Turn Fault Protection

z Current of CT at head end of reactor is adopted for the protection calculation.
z Inter-turn protection consists of zero-sequence power directional element and zero-sequence

impdence element with high reliability.
z The amplitude of residual voltage is compensated to ensure zero-sequence power directional

element can distinguish direction correctly when system impedance is too low.
z Interturn protection is blocked by CT and VT circuit failure.
1.3.7 Overexcitation Protection

z Voltage for protection calculation is RMS of three phase voltages and not affected by
frequency fluctuation.
z Overexcitation multiple is calculated by voltge and frequence.
z Two-stage definite-time overexcitation protection and one-stage definite-time overexcitation

alarm element are equipped.
z One-stage inverse-time overexcitation protection including tripping and alarm funxtions is

Date: 2011-07-19
1 Introduction
equipped.
z Overexcitation inverse-time curve is sectional linear curve, which has hight adaptivity.
1.3.8 Mechanical Protection
z High-power relays are adopted to improve the anti-interfence ability of mechanical protection.
z Mechanical protection does not maloperate if 110Vac (or 220Vac) voltage is connected to the
terminal of mechanical relay signal input by mistake.
z Provide 4 mechancial signal input channels for tripping instantaneously or with time delay.
1.3.9 Phase Overcurrent Protection

z Four-stage phase overcurrent protection with independent logic, current and time delay
settings.
z Stage 1, stage 2 and stage 3 are definite-time characteristic, stage 4 can be selected as
definite-time or inverse-time characteristic. The inverse-time characteristic is selectable,
among IEC and ANSI/IEEE standard inverse-time characteristics and a user-defined
inverse-time curve.
z Voltage control element can be selected to control each stage phase overcurrent protection.
z Directional element can be selected to control each stage phase overcurrent protection with
three options: no direction, forward direction and reverse direction.
z Second harmonic can be selected to block each stage phase overcurrent protection.
1.3.10 Ground Overcurrent Protection

z Four-stage ground overcurrent protection with independent logic, current and time delay
settings.
inverse-time curve.
z Directional element can be selected to control each stage ground overcurrent protection with
z Second harmonic can be selected to block each stage ground overcurrent protection.
z Measured neutral current or calculated residual current can be selected for the calculation of
ground overcurrent protection.
1.3.11 Phase Overvoltage Protection

z Two-stage phase overvoltage protection with independent logic, voltage and time delay

Date: 2011-07-19
1 Introduction
settings.
z Stage 1 and stage 2 definite-time characteristic, stage 2 can be selected as definite-time or
inverse-time characteristic. T The inverse-time characteristic is selectable among IEC and
ANSI/IEEE standard inverse-time characteristics and a user-defined inverse-time curve.
z Phase voltage or phase-to-phase voltage can be selected for protection calculation.
z “1 out of 3” or “3 out of 3”logic can be selected for protection criterion.
1.3.12 Residual Overvoltage Protection

z Two-stage residual overvoltage protection with independent logic, voltage and time delay
settings.
z Stage 1 is definite-time characteristic, stage 2 can be selected as definite-time or

inverse-time characteristic. The inverse-time characteristic is selectable among IEC and
1.3.13 Undervoltage Protection
z Four-stage definite-time undervotlage protection with independent voltage and time delay
settings.
z The rate of change of voltage blocking function is equipped.
1.3.14 Thermal Overload Protection

Thermal overload protection has following functions:
z Thermal time characteristic of IEC 60255-8 is adopted.
z One stage for alarm and one stage for trip.
z Funermental current or 1st to 7th harmonic current is used for protection calculation.
NOTE! Users muse declare current value calculation for thermal overload protection,
fundermental current or 1st to 7th harmonic current before making an order.

Date: 2011-07-19
1 Introduction

Date: 2011-07-19
2 Technical Data
2 Technical Data
Table of Contents
2.1 Electrical Specifications ................................................................................. 2-1

2.1.1 Analog Input Ratings ..........................................................................................................2-1
2.1.2 Power Supply .....................................................................................................................2-1
2.1.3 Transducer Input .................................................................................................................2-3
2.1.4 Binary Input ........................................................................................................................2-3
2.1.5 Binary Output ......................................................................................................................2-3
2.2 Mechanical Specifications .............................................................................. 2-4

2.3 Ambient Temperature and Humidity Range .................................................. 2-5
2.4 Communication Port ....................................................................................... 2-5
2.4.1 EIA-485 Port .......................................................................................................................2-5
2.4.2 Ethernet Port ......................................................................................................................2-5
2.4.3 Optical Fibre Port ................................................................................................................2-5
2.4.4 Print Port.............................................................................................................................2-6
2.4.5 Clock Synchronization Port.................................................................................................2-6
2.5 Type Tests ........................................................................................................ 2-6

2.5.1 Environmental Tests ...........................................................................................................2-6
2.5.2 Mechanical Tests ................................................................................................................2-6
2.5.3 Electrical Tests ....................................................................................................................2-6
2.5.4 Electromagnetic Compatibility ............................................................................................2-7
2.6 Certifications .................................................................................................... 2-7

2.7 Protective Functions ....................................................................................... 2-8
2.7.1 Transformer Current Differential Protection ........................................................................2-8
2.7.2 Restricted Earth Fault Protection ........................................................................................2-9
2.7.3 Winding Differential Protection .........................................................................................2-10
2.7.4 Reactor Differential Protection ..........................................................................................2-10
PCS-978 Transformer Protection 2-a

Date: 2011-08-18
2 Technical Data
2.7.5 Reactor Inter-turn Fault Protection ...................................................................................2-10
2.7.6 Overexcitation Protection..................................................................................................2-10
2.7.7 Mechanical Protection ...................................................................................................... 2-11
2.7.8 Phase Overcurrent protection ........................................................................................... 2-11
2.7.9 Ground Overcurrent Protection .........................................................................................2-12
2.7.10 Phase Overvoltage Protection ........................................................................................2-13
2.7.11 Residual Overvoltage Protection.....................................................................................2-14
2.7.12 Undervoltage Protection .................................................................................................2-14
2.7.13 Thermal Overload Protection ..........................................................................................2-15
2.7.14 Breaker Failure Initiation .................................................................................................2-15
2.7.15 Pole Disagreement Protection ........................................................................................2-16
2.7.16 Phase Overcurrent Alarm Element .................................................................................2-16
2-b PCS-978 Transformer Protection

Date: 2011-08-18
2 Technical Data
2.1 Electrical Specifications

2.1.1 Analog Input Ratings
1. Alternating Analog current
Phase rotation ABC

Nominal frequency 50±5Hz, 60±5Hz
Rated Current (In) 1A 5A
Linear to 0.05In~40In
Thermal withstand
-continuously 4In
-for 10s 30In
-for 1s 100In
-for half a cycle 250In
Burden < 0.15VA/phase @In < 0.25VA/phase @In
Accuracy ±0.5%In
Current input channel Maximum 36
2. Alternating Analog voltage
Phase rotation ABC

Nominal frequency 50±5Hz, 60±5Hz
Rated Voltage (Un) 100~130V 200V (residual voltage input)
Linear to 1~170V 1-233V
Thermal withstand
-continuously 200V 220
-10s 260V 380
-1s 300V 420
Burden at rated < 0.20VA/phase @Un < 0.80VA/phase @Un
Accuracy ±0.5%Un ±0.5%Un
Voltage input channel Maximum 18 Maximum 9
2.1.2 Power Supply

Standard IEC 60255-11:2008
Rated Voltage 110Vdc/125Vdc, 220VDC/250Vdc
Variation 80% ~120%
Permissible AC ripple voltage ≤15% of the nominal auxiliary voltage
Conventional
< 25W @ Quiescent condition without binary input signals
substation
Burden
Digital substation <40W @ Quiescent condition without binary input signals
NOTE! Following table list burden of each part of PCS-978 device, user can calculate
weight of device according to the acutual hardware configuration. After calculate the total
PCS-978 Transformer Protection 2-1

Date: 2011-08-18
2 Technical Data
burdent of each module
Module Description Module Type Burden (W)

MON Module (Management) 64M DDR
NR1102A 6
(2 x RJ45 Ethernet + RS485 (Syn) + RS232 (printer))
NR1102B 6
NR1102C 6
NR1102D 6
(2 x RJ45 + 2 x FO(SC)) Ethernet + RS485 (Syn) + RS232 NR1102H 6
(printer)
NR1102I 6
(2 x RJ45 + 2 x FO(ST)) Ethernet + RS485 (Syn) + RS232 (printer)
NR1101E 6
(2 x RJ45 Ethernet + 2 x RS485 + RS485 (Syn) + RS232 (printer))
DSP Module
NR1156A 3.5
(36 analog sampling channels, for conventional CT/VT.)
DSP Module
(No analog sampling channel, ECVT signal from NR1136 via NR1151D 3.5
motherboard)
DSP Module
NR1152A 3.5
(8 stream channels from ECVT directly.)
0.3
Mechanical Relay Module NR1533A
(without IO burden)
0.3
BO Module (11 output contacts) NR1521A
(without BO burden)
0.3
Signal Output Module (11 signal contacts in 4 groups) NR1523B
(without BO burdent)
BI Module (11 individual binary inputs) NR1503 0.3
BI Module (18 binary inputs, common negative) NR1504 0.3
PWR Module (Power Supply) NR1301A *
0
AI Module (AC Analogue Input Module 12 channels) NR1401A
(AC Anolog input module)
DC Analogue Input Module (6 channels) NR1410B 2.5

NET-DSP 2 (8 stream ECVT AI)
(total 8 ports connected, 0.35W/port, i.e. one port is disconnected NR1136A 6.7
and 0.35W is reduced)
NET-DSP 2 (6 stream ECVT AI + 1 x FO (IRIG-B syn))
(total 6 ports connected, 0.35W/port, i.e. one port is disconnected NR1136C 6
and 0.35W is reduced)
Chassis+Bus+HMI module - -
NOTE! “*”: NR1301A is the power moule of PCS-978 device, the burden of which is not a
fixed value but realted to the burden of other modules. After all other parts burden are
added to get a vajue and then the value is divided by 0.8 to get the total burden of device.
2-2 PCS-978 Transformer Protection

Date: 2011-08-18
2 Technical Data
2.1.3 Transducer Input

Standard IEC 60255-1: 2009
Input range 4-20mA 0-5V
Input resistance 235Ω 20kΩ
Accuracy 0.5 class 0.5 class
Transducer nput channel 6
2.1.4 Binary Input

Rated Voltage 24Vdc 48Vdc 110Vdc 125Vdc 220Vdc 250Vdc
Rated current drain 1.2mA 2.4mA 1.1mA 1.25mA 2.2mA 2.5mA
Pickup voltage range 55%~70% rated voltage
Dropout voltage ≤55% rated voltage
Maximum permissible voltage 120% rated voltage
Withstand voltage 2000Vac, 2800Vdc
Resolving time for logic input <1ms
Binary input channel Maximum 18
2.1.5 Binary Output

Contact Type Trip output Signal output
Output mode Potential free contact
5A@380Vac 8A@380Vac
Continuous carry
5A@250Vdc 8A@250Vdc
Pickup time <8ms (typical 3ms) <10ms
Dropoff time <5ms <8ms
0.6A@48Vdc 0.7A@48Vdc
Breaking capacity (L/R=40ms) 0.2A@110Vdc 0.3A@110Vdc
0.1A@220Vdc 0.2A@220Vdc
Burden 300mW 240mW
Making capacity 2000VA 3040VA
380Vac
Maximal system voltage
250Vdc
Test voltage across open
1000V RMS for 1min 1200V RMS for 1min
contact
6A@3s 10A@3S
Short duration current
15A@0.5s 20A@0.5S
Contact number Maximum 22 Maximum 22
NOTE! Signal contacts include watchdog contacts.
NOTE! Tripping output contacts are not connected to trip circuit breakers directly. They are
connected to interposing relays or lockout relays contacts which are connected to trip
circuit breakers.

Date: 2011-08-18
2 Technical Data
2.2 Mechanical Specifications

Enclosure dimensions
482.6mm×177.0mm×291.0mm
(W×H×D)
Mounting Way Flush mounted
Trepanning dimensions (W×H) 450.0mm×179.0mm, M6 screw
Chassis color Silver grey
Weight per device Approx. 15kg (Including 2 AC AI modules)
Chassis material Aluminum alloy
Location of terminal Rear panel of the device
Device structure Plug-in modular type @ rear side, integrated frontplate
Protection class
Front side IP40, up to IP51 (With cover)
Other sides IP30
Rear side, connection terminals IP20
NOTE! Following table list weight of each module of PCS-978 device, user can calculate
weight of device according to the acutual hardware configuration.
Module Description Module Type Weight(kg)

NR1102A 0.4
NR1102B 0.4
NR1102C 0.4
NR1102D 0.4
NR1102H 0.4
(2 x RJ45 + 2 x FO(SC)) Ethernet + RS485 (Syn) + RS232 (printer)
NR1102I 0.4
(2 x RJ45 + 2 x FO(ST)) Ethernet + RS485 (Syn) + RS232 (printer)
NR1101E 0.4
(2 x RJ45 Ethernet + 2 x RS485 + RS485 (Syn) + RS232 (printer))
DSP Module
NR1156A 0.2
(36 analog sampling channels, for conventional CT/VT.)
DSP Module
(No analog sampling channel, ECVT signal from NR1136 via NR1151D 0.2
motherboard)
DSP Module
NR1152A 0.2
(8 stream channels from ECVT directly.)
Mechanical Relay Module NR1533A 0.35
BO Module (11 output contacts) NR1521A 0.2
Signal Output Module (11 signal contacts in 4 groups) NR1523B 0.3
BI Module (11 individual binary inputs) NR1503 0.2
BI Module (18 binary inputs, common negative) NR1504 0.2
PWR Module (Power Supply) NR1301A 0.6
AI Module (AC Analogue Input Module 12 channels) NR1401A 2.4
DC Analogue Input Module (6 channels) NR1410B 2.4

Date: 2011-08-18
2 Technical Data
Module Description Module Type Weight(kg)

NET-DSP 2 (8 stream ECVT AI)
(total 8 ports connected, 0.35W/port, i.e. one port is disconnected and NR1136A 0.3
0.35W is reduced)
NET-DSP 2 (6 stream ECVT AI + 1 x FO (IRIG-B syn))
(total 6 ports connected, 0.35W/port, i.e. one port is disconnected and NR1136C 0.3
0.35W is reduced)
Chassis+Bus+HMI module - 6.8
2.3 Ambient Temperature and Humidity Range

Standard IEC 60225-1: 2009
Operating temperature -40°C to +70°C
Transport and storage
-40°C to +70°C
temperature range
Permissible humidity 5%-95%, without condensation
Pollution degree 2
Altitude <3000m
2.4 Communication Port

2.4.1 EIA-485 Port
Baud rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Protocol IEC 60870-5-103:1997
Maximal capacity 32
Transmission distance <500m
Safety level Isolation to ELV level
Twisted pair Screened twisted pair cable
2.4.2 Ethernet Port

Connector type RJ-45
Transmission rate 100Mbits/s
Transmission standard 100Base-TX
Protocol IEC 60870-5-103:1997, DNP3.0 or IEC 61850
2.4.3 Optical Fibre Port

2.4.3.1 For Station Level
Characteristic Glass optical fiber

Connector type ST, SC
Fibre type Multi mode
Transmission distance <2km
Wave length 1310nm
Transmission power Min. -20.0dBm

Date: 2011-08-18
2 Technical Data
Minimum receiving power Min. -30.0dBm

Margin Min +3.0dB
2.4.3.2 For Process Level
Characteristic Glass optical fiber

Connector type LC
Fibre type Multi mode
Transmission distance <2km
Wave length 1310nm
Transmission power Min. -20.0dBm
Minimum receiving power Min. -30.0dBm
Margin Min +3.0dB
2.4.4 Print Port

Type RS-232
Baud Rate 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s
Printer type EPSON® 300K printer
2.4.5 Clock Synchronization Port

Type RS-485
Maximal capacity 32
Timing standard PPS, IRIG-B
2.5 Type Tests

2.5.1 Environmental Tests
Dry cold test Per IEC60068-2-1:2007
Dry heat test Per IEC60068-2-2:2007
Damp heat test, cyclic Per IEC60068-2-30:2005
2.5.2 Mechanical Tests

Vibration Per IEC 60255-21-1:1988 Class I
Shock and bump Per IEC 60255-21-2:1988 Class I
2.5.3 Electrical Tests

Dielectric tests Test voltage 2kV, 50Hz, 1min
Impulse voltage tests Test voltage 5kV
Overvoltage category III

Date: 2011-08-18
2 Technical Data
Insulation resistance
Isolation resistance >100MΩ@500VDC
measurements
2.5.4 Electromagnetic Compatibility

IEC 60255-22-1:2007
1MHz burst disturbance test Common mode: class III 2.5kV
Differential mode: class III 1.0kV
IEC60255-22-2:2008 class IV
Electrostatic discharge test For contact discharge: 8kV
For air discharge: 15kV
IEC 60255-22-3:2007 class III
Frequency sweep
Radiated amplitude-modulated
10V/m (rms), f=80~1000MHz
Radio frequency interference
Spot frequency
tests
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
Radiated pulse-modulated
10V/m (rms), f=900MHz
IEC 60255-22-4:2008
Fast transient disturbance tests Power supply, I/O, Earth: class IV, 4kV, 2.5kHz, 5/50ns
Communication terminals: class IV, 2kV, 5kHz, 5/50ns
Per IEC 60255-22-5:2008
Power supply, AC input, I/O port: class IV, 1.2/50us
Surge immunity test
Common mode: 4kV
Differential mode: 2kV
Conducted RF Electromagnetic IEC 60255-22-6:2001
Disturbance Power supply, AC, I/O, Comm. Terminal: Class III, 10Vrms, 150 kHz~80MHz
Power Frequency Magnetic IEC 61000-4-8:2001
Field Immunity class V, 100A/m for 1min, 1000A/m for 3s
IEC 61000-4-9:2001
Pulse Magnetic Field Immunity
class V, 6.4/16μs, 1000A/m for 3s
Damped oscillatory magnetic IEC 61000-4-10:2001
field immunity class V, 100kHz & 1MHz–100A/m
IEC60255-11: 2008
Auxiliary power supply
Voltage dips: Up to 500ms for dips to 40% of rated voltage without reset
performance
Voltage short interruptions: 100ms for interruption without rebooting
2.6 Certifications
z ISO9001: 2000
z ISO14001:2004
z OHSAS18001: 1999

Date: 2011-08-18
2 Technical Data
z ISO10012:2003
z CMMI L4
z EMC: 2004/108/EC, EN50263:1999
z Products safety(PS): 2006/95/EC, EN61010-1: 2001
2.7 Protective Functions
NOTE! There are some symbols mentioned in the following sections and the meaning of
them is given here.
Un – rated secondary voltage of VT.
In – rated secondary current of CT, also the unit of setting and current for restricted earth
fault protection and winding differential protection.
pu – unit of setting and current for current differential protection.
Id – differential current
I0d – residual differential current.
Iwd – winding differential current.
ΔI d -- DPFC differential current.
U * / f* – the overexcitation multiple.
2.7.1 Transformer Current Differential Protection
2.7.1.1 Biased Differential Protection
Current setting of knee point 1 [87T.I_Knee1] 0.1~1pu, 0.001pu steps
Current setting of knee point 2 [87T.I_Knee2] 4~8pu, 0.001pu steps
Pickup up setting [87T.I_Biased] 0.05 ~ 5pu, 0.001pu steps
Slope 1 setting [87T.Slope1] 0.1~0.9, steps 0.001

nd
2 harmonic setting for inrush current
0.05~0.3, steps 0.001
[87T.K_Hm2_Inrush]
3rd harmonic setting for inrush current

0.05~0.3, steps 0.001
[87T.K_Hm3_Inrush]
3rd or 5th harmonic setting for overexcitation

0.05~0.3, steps 0.001
[87T.K_Hm3/Hm5_OvExc]

Date: 2011-08-18
2 Technical Data
Tolerance of 2nd and 3rd harmonic settings 0.01

th
Tolerance of 5 harmonic settings 0.02
Tolerance of operating current ≤5% or 0.02pu, whichever is greater
Drop-off to pickup ratio ≥95%
50Hz: ≤ 30ms( Id>2x[87T.I_Biased])

Operating time (Without blocking criteria)
60Hz: ≤ 25ms( Id>2x[87T.I_Biased])
Drop-off time ≤30ms
2.7.1.2 Instantaneous Differential Protection
Current setting [87T.I_Instant] 0.05 ~ 20pu, 0.001pu steps
Tolerance of current setting ≤2.5%xSetting or 0.02pu, whichever is greater
50Hz: ≤ 20ms( Id>1.5x[87T.I_Instant])

Operating time
60Hz: ≤ 20ms( Id>1.5x[87T.I_Instant])
2.7.1.3 DPFC Current Differential Protection
Pickup current value 0.2pu
Tolerance of operating current ≤10%
Slope 1 value 0.6 (fixed)
Slope 2 value 0.75 (fixed)
50Hz: ≤30ms ( ΔI d >2x0.2pu)

Operating time
60Hz: ≤25ms ( ΔI d >2x0.2pu)
2.7.2 Restricted Earth Fault Protection
Current setting of knee point [64REF.I_Knee] 0.1~4In, 0.001In steps
Pickup up setting [64REF.I_Biased] 0.05 ~ 5In, 0.001In steps
Time delay setting [64REF.Slope] 0~20s, 0.001s steps
Restraint slope setting [64REF.t_Op] 0.20~0.75. steps 0.001
Tolerance of operating current ≤5% or 0.02×In, whichever is greater
Operating time 50Hz: ≤30ms (I0d>2×[64REF.I_Biased])

(Wthout time delay, without blocking criterion) 60Hz: ≤25ms (I0d>2×[64REF.I_Biased])
Tolerance of time setting ≤1% of Setting +30ms (I0d>2x[64REF.I_Biased])

Date: 2011-08-18
2 Technical Data
2.7.3 Winding Differential Protection
Current setting of knee point [87W.I_Knee] 0.1~4In, 0.001In steps
Pickup up setting [87W.I_Biased] 0.05 ~ 5In, 0.001In steps
Restraint slope setting [87W.Slope] 0.20~0.75. steps 0.001
Tolerance of operating current ≤5% or 0.02×In, whichever is greater
50Hz: ≤30ms (Iwd>2×[87W.I_Biased])

Operating time (Without blocking criterion)
60Hz: ≤25ms (Iwd>2×[87W.I_Biased])
Tolerance of time setting ≤1% of Setting +30ms (I0d>2x[87W.I_Biased])
2.7.4 Reactor Differential Protection
2.7.4.1 Biased Differential Protection
Pickup up setting [87R.I_Biased] 0.05 ~ 5pu, 0.001pu steps
Slope setting [87R.Slope] 0.1~0.9, steps 0.001
Tolerance of operating current ≤5% or 0.02pu, whichever is greater
50Hz: ≤ 30ms( Id>2x[87R.I_Biased])

Operating time (Without blocking criterion)
60Hz: ≤ 25ms( Id>2x[87R.I_Biased])
2.7.4.2 Instantaneous Differential Protection
Current setting [87R.I_Instant] 0.05 ~ 20pu, 0.001pu steps
Tolerance of current setting ≤2.5%xSetting or 0.02pu, whichever is greater
50Hz: ≤ 20ms( Id>1.5x[87R.I_Instant])

Operating time
60Hz: ≤ 20ms( Id>1.5x[87R.I_Instant])
2.7.5 Reactor Inter-turn Fault Protection
Operating time without delay ≤60ms
2.7.6 Overexcitation Protection
Definite time U * / f* setting [24DT1.K_Set] 1.0～1.7 pu, 0.001 steps

Date: 2011-08-18
2 Technical Data
Definite time delay setting [24DT1. t_Op] 0.1 s～9999s, 0.001s steps
Inverse time U * / f* setting

1.0～1.7 pu, 0.001 steps
[24IDMT.Kn_Set], n=0,1…,9
Inverse time delay setting

0.1 s～9999s, 0.001s steps
[24IDMT.t0_Op], n=0,1…,9
Tolerance of U * / f* setting ≤2.5% of Setting or 0.01 whichever is greater
Cooling time setting [24IDMT.t_Cooling] 0.1~9999s, 0.001s teps
Drop-off to pickup ratio of definte-time overexcitation

≥97%
protection
Tolerance of operating time of definite-time

≤1% of Setting +30ms (at 1.5 times U * / f* setting)
overexciation protection
Tolerance of operating time of inverse-time

≤2.5% operating time or 30ms, whichever is greater
overexcitation protection
Drop-off time of definite-time overexcitation protection ≤30ms
2.7.7 Mechanical Protection
Delay picku up time setting [MR.t_DPU_n], n=1,2,3,4 0~3600s, steps 0.001s
Pulse width setting [MR.t_PW_1], n=1,2,3,4 0~10s, steps 0.001s
Time setting tolerance ≤1% of Setting +30ms
2.7.8 Phase Overcurrent protection
2.7.8.1 Instantaneous and Definte-time Phase Overcurrent Protection
Current setting [50/51Pn.I_Set], n=1, 2, 3 0.04In~30In, 0.001A steps
Tolerance of current setting of DT OC ≤2.5% of Setting or 0.02In, whichever is greater
50Hz: ≤25 ms (at 2 times current setting)

Operating time of instantaneous OC
Time delay setting [50/51Pn.t_Op], n=1, 2, 3 0.00~3600s, 0.001s steps
Tolerance of time setting of DT OC ≤1% of Setting +30ms (at 2 times current setting)
2.7.8.2 Inverse-time Phase Overcurrent
Pickup current setting [50/51P4.I_Set] 0.04In~30In, 0.001A steps
Tolerance of current setting of IDMT OC ≤2.5% of Setting or 0.02Un, whichever is greater
Multiple of the maximum operating current to the pikcup 10~40, 0.001 setps

Date: 2011-08-18
2 Technical Data
setting [50/51P4.K_Iset]
Time multipler setting [50/51P4.TMS] 0.05~3.2, 0.001 steps
Minimum delay setting [50/51P4.tmin] 0.0~20s, 0.001s steps
Constant K [50/51P4.K] 0.0~120, 0.001 steps
Constant C [50/51P4.C] 0.0~20s, 0.001s steps
Exopnent alpha [50/51P4.Alpha] 0.02~5, 0.001 steps
≤2.5% operating time or 30ms, whichever is greater(for

Operating time of IDMT OC
current between 1.2 and 20 multiples of pickup)
2.7.8.3 Control and Blocking Element
Phase-to-phase undervoltage setting

2~200V, steps 0.001V
[50/51P.Upp_VCE]
Negative-sequence voltage setting

2~200V, steps 0.001V
[50/51P.U2_VCE]
Tolerance of voltage setting ≤2.5% of setting or 0.01Un, whichever is greater
Drop-off to pickup ratio of voltage element ≥95%
Relay characteristic angle [50/51P.RCA] 0~360 deg, steps 1 deg
Tolerance of relay characteristic angle ≤3 deg
Minimum polarizing voltage 2% of rated voltage of VT
2nd harmonic for inrush [50/51P.K_Hm2] 0.05~1.0, steps 0.001
Current setting of releasing inrush blocking

0.04~30In, steps 0.001
[50/51P.I_Rls_HmBlk]
Tolerance of current setting of releasing inrush blocking ≤2.5% of Setting or 0.02In, whichever is greater
2.7.9 Ground Overcurrent Protection
2.7.9.1 Instantaneous and Definte-time Ground Overcurrent Protection
Current setting [50/51Gn.I_Set], n=1, 2, 3 0.04In~30In, 0.001A steps
Tolerance of current setting of DT ROC ≤2.5% of Setting or 0.02In, whichever is greater

Operating time of instantaneous ROC
Time delay setting [50/51Gn.t_Op], n=1, 2, 3 0.00~3600s, 0.001s steps
Tolerance of time setting of DT ROC ≤1% of Setting +30ms (at 2 times current setting)
2.7.9.2 Inverse-time Ground Overcurrent Protection
Pickup current setting [50/51G4.I_Set] 0.04In~30In, 0.001A steps

Date: 2011-08-18
2 Technical Data
Tolerance of current setting of DT ROC ≤2.5% of Setting or 0.02In, whichever is greater
Multiple of the maximum operating current to the pikcup

10~40, 0.001 setps
setting [50/51G4.K_Iset]
Time multipler setting [50/51G4.TMS] 0.05~3.2, 0.001 steps
Minimum delay setting [50/51G4.tmin] 0.0~20s, 0.001s steps
Constant K [50/51G4.K] 0.0~120, 0.001 steps
Constant C [50/51G4.C] 0.0~20s, 0.001s steps

Operating time of IDMT ROC
residual current between 1.2 and 20 multiples of pickup)
2.7.9.3 Control and Blocking Element
Relay characteristic angle [50/51G.RCA] 0~360 deg, 1 deg steps
Tolerance of relay characteristic angle ≤3 deg
Minimum polarizing voltage 2% of rated voltage of VT
2nd harmonic for inrush [50/51G.K_Hm2] 0.05~1.0, steps 0.001
Current setting of releasing inrush blocking

0.04~150A, steps 0.001
[50/51G.I_Rls_HmBlk]
Tolerance of current setting of releasing inrush blocking ≤2.5% of Setting or 0.02In, whichever is greater
2.7.10 Phase Overvoltage Protection
2.7.10.1 Instantaneous and Definte-time Phase Overvoltage Protection
Voltage setting [59P1.U_Set] 2~200V, 0.001V steps
Tolerance of voltage setting of DT OV ≤2.5%xSetting or 0.1V, whichever is greater
50Hz: ≤35ms(at 1.2 times voltage setting)

Operating time of instantaneous OV
60Hz: ≤30ms(at 1.2 times voltage setting)
Time delay setting [59P1.t_Op] 0.00~3600s, 0.001s steps
Tolerance of time setting of DT OV ≤1% of Setting +30ms (at 1.2 times voltage setting)
Droup-off time ≤30ms
2.7.10.2 Inverse-time Phase Overvoltage Protection
Pickup voltage setting [59P2.U_Set] 2~200V, 0.001V steps
Tolerance of voltage setting of IDMT OV ≤2.5% of Setting or 0.02In, whichever is greater

10~40, 0.001 setps
setting [59P2.K_Iset]

Date: 2011-08-18
2 Technical Data
Time multipler setting [59P2.TMS] 0.05~3.2, 0.001 steps
Minimum delay setting [59P2.tmin] 0.0~20s, 0.001s steps
Constant K [59P2.K] 0.0~120, 0.001 steps
Constant C [59P2.C] 0.0~20s, 0.001s steps
≤2.5% operating time or 30ms, whichever is greater (for

Operating time of IDMT OV
voltage between 1.2 and 2 multiples of pickup)
2.7.11 Residual Overvoltage Protection
2.7.11.1 Instantaneous and Definte-time Residual Overvoltage Protection
Voltage setting [59G1.U_Set] 2~200V
Tolerance of voltage setting of DT ROV ≤2.5% of Setting or 0.1V, whichever is greater
50Hz: ≤35ms (at 1.2 times voltage setting)

Operating time of instantaneous ROV
60Hz: ≤30ms (at 1.2 times voltage setting)
Time delay setting [59G1.t_Op] 0.00~3600s, 0.001s steps
Tolerance of time setting of DT ROV ≤1% of Setting +30ms (at 1.2 times voltage setting)
2.7.11.2 Inverse-time Residual Overvoltage Protection
Pickup voltage setting [59G2.U_Set] 2~200V
Tolerance of voltage setting of IDMT OV ≤2.5% of Setting or 0.1V, whichever is greater

10~40, 0.001 setps
setting [59G2.K_Iset]
Time multipler setting [59G2.TMS] 0.05~3.2, 0.001 steps
Minimum delay setting [59G2.tmin] 0.0~20s, 0.001s steps
Constant K [59G2.K] 0.0~120, 0.001 steps
Constant C [59G2.C] 0.0~20s, 0.001s steps
≤2.5% operating time or 30ms, whichever is greater (for

Operating time of IDMT OV
residual voltage between 1.2 and 2 multiples of pickup)
2.7.12 Undervoltage Protection
Voltage setting of DT UV [27.UVn.U_Set] n=1,2,3,4 10~100V
Lowest voltage threshold of voltage recovery

10~100V
[27.U_Recov]
Tolerance of voltage setting ≤2.5% of Setting or 0.1V, whichever is greater

Date: 2011-08-18
2 Technical Data
Drop-off to pickup ratio ≤102%
50Hz ≤20ms (at 0.8 times voltage setting)

Operating time of UV at zero time delay
60Hz:≤20ms (at 0.8 times voltage setting)
Time setting of DT UV [27.UVn.t_Op] n=1,2,3,4 0.05~100s
Time setting of fault recovery [27.t_Recov] 0~100s
Tolerance of time setting ≤1% of Setting +30ms (at 0.8 times voltage setting)
du/dt setting [27.du/dt_Blk] 0~100V/s
2.7.13 Thermal Overload Protection
Base current setting range [49.Ib_Set] 0.04In~30In, 0.001In steps
Transformer thermal time constant [49.Tau] 0~100s, 0.001s steps
Thermal overload coefficient for trip [49.K_Trp] 1~3, 0.001 steps
Thermal overload coefficient for alarm [49.K_Alm] 1~3, 0.001 steps

Operating time
current between 1.2 and 20 multiples of pickup)
IEC hot time-current limit characteristic curve

(adopted curve in the relay)
2
I eq
t = τ ⋅ ln
2
Characteristic curve I eq − (k ⋅ I B ) 2
IEC hot cold-current limit characteristic curve
2
I eq − I 2p
t = τ ⋅ ln
2
I eq − (k ⋅ I B ) 2
2.7.14 Breaker Failure Initiation
Range of phase current setting [50BF.Ip_Set] 0.04In~30In, 0.001In steps
Range of residual current setting

0.04In~30In, 0.001In steps
[50BF.3I0_Set]
Range of negative sequence current setting

[50BF.I2_Set]
Current setting tolerance ≤2.5% of setting or 0.02×In, whichever is greater
Time setting range [50BF.tn_Op] n=1, 2 0.00~20s, 0.001s steps
Time setting tolerance ≤1% of Setting +30ms (at 2 times current setting)

Date: 2011-08-18
2 Technical Data
2.7.15 Pole Disagreement Protection
Range of residual current setting

[62PD.3I0_Set]
Range of negative sequence current setting

[62PD.I2_Set]
Current setting tolerance ≤2.5% of setting or 0.02×In, whichever is greater
Range of time setting [62PD.t_Op] 0.00~20s, 0.001s steps
Range of time setting [62PD.t_Alm] 0.00~20s, 0.001s steps
Time setting tolerance ≤1% of Setting +30ms (at 2 times current setting)
2.7.16 Phase Overcurrent Alarm Element
Current setting [50PAlmn.I_Set],n=1,2 0.04In~30In. 0.001A steps
Tolerance of current setting ≤2.5% of Setting or 0.02In, whichever is greater
50Hz: ≤25ms (at 2 times current setting)

Operating time without time delay
60Hz: ≤23ms (at 2 times current setting)
Time setting [50PAlmn.t_Op], n=1,2 0s ~ 3600s, 0.001s steps
Tolerance of time setting ≤1% of Setting +30ms (at 2 times current setting)

Date: 2011-08-18
3 Operation Theory
3 Operation Theory
Table of Contents
3.1 Overview........................................................................................................... 3-1

3.1 Transformer Current Differential Protection (87T) ........................................ 3-1
3.1.1 Application ..........................................................................................................................3-1
3.1.2 Function ..............................................................................................................................3-1
3.1.3 Protection Principle .............................................................................................................3-2
3.1.4 Logic .................................................................................................................................3-26
3.1.5 Inputs and Outputs ...........................................................................................................3-30
3.1.6 Setting ..............................................................................................................................3-32
3.2 Reactor Current Differential Protection (87R) ............................................. 3-34

3.2.1 Application ........................................................................................................................3-34
3.2.2 Function ............................................................................................................................3-34
3.2.3 Protection Principle ...........................................................................................................3-34
3.2.4 Logic .................................................................................................................................3-49
3.2.6 Setting ..............................................................................................................................3-53
3.3 Restricted Earth Fault Protection (64REF) .................................................. 3-54

3.3.1 Application ........................................................................................................................3-54
3.3.2 Function ............................................................................................................................3-54
3.3.4 Logic .................................................................................................................................3-61
3.3.6 Setting ..............................................................................................................................3-64
3.4 Winding Differential Protection (87W/87N) .................................................. 3-65

3.4.1 Application ........................................................................................................................3-65
3.4.2 Function ............................................................................................................................3-65

Date: 2011-10-19
3 Operation Theory
3.4.4 Logic .................................................................................................................................3-70
3.4.6 Setting ..............................................................................................................................3-73
3.5 Inter-Turn fault Protection (IntTurn) ............................................................. 3-74

3.5.1 Application ........................................................................................................................3-74
3.5.2 Functions ..........................................................................................................................3-74
3.5.4 Logic .................................................................................................................................3-79
3.5.6 Setting ..............................................................................................................................3-80
3.6 Overexcitation Protection (24) ...................................................................... 3-81

3.6.1 Application ........................................................................................................................3-81
3.6.2 Function ............................................................................................................................3-81
3.6.4 Logic .................................................................................................................................3-83
3.6.6 Settings.............................................................................................................................3-86
3.7 Frequency Protection (81) ............................................................................ 3-89

3.7.1 Application ........................................................................................................................3-89
3.7.2 Function ............................................................................................................................3-89
3.7.3 Fault Detector ...................................................................................................................3-90
3.7.5 Logic .................................................................................................................................3-92
3.7.7 Setting ..............................................................................................................................3-95
3.8 Mechanical Protection (MR).......................................................................... 3-98

3.8.1 Application ........................................................................................................................3-98
3.8.2 Function ............................................................................................................................3-98

Date: 2011-10-19
3 Operation Theory
3.8.4 Logic .................................................................................................................................3-98
3.8.6 Setting ............................................................................................................................3-100
3.9 Phase Overcurrent Protection (50/51P) ..................................................... 3-101

3.9.1 Application ......................................................................................................................3-101
3.9.2 Function ..........................................................................................................................3-101
3.9.3 Protection Principle .........................................................................................................3-102
3.9.4 Logic ...............................................................................................................................3-107
3.9.5 Inputs and Outputs .........................................................................................................3-109
3.9.6 Settings........................................................................................................................... 3-110
3.10 Ground Overcurrent Protection (50/51G) .................................................3-112

3.10.1 Application .................................................................................................................... 3-112
3.10.2 Function ........................................................................................................................ 3-113
3.10.3 Protection Principle ....................................................................................................... 3-113
3.10.4 Logic ............................................................................................................................. 3-118
3.10.5 Inputs and Outputs ....................................................................................................... 3-119
3.10.6 Settings.........................................................................................................................3-120
3.11 Phase Overvoltage Protection (59P) ........................................................ 3-122

3.11.1 Application ....................................................................................................................3-122
3.11.2 Function ........................................................................................................................3-122
3.11.3 Protection Principle .......................................................................................................3-123
3.11.4 Logic .............................................................................................................................3-125
3.11.5 Inputs and Outputs ........................................................................................................3-126
3.11.6 Settings .........................................................................................................................3-127
3.12 Residual Overvoltage Protection (59G) ................................................... 3-128

3.12.1 Application ....................................................................................................................3-128
3.12.2 Function ........................................................................................................................3-128
3.12.4 Logic .............................................................................................................................3-130
3.12.5 Inputs and Outputs .......................................................................................................3-131
PCS-978 Transformer Relay 3-c

Date: 2011-10-19
3 Operation Theory
3.12.6 Settings.........................................................................................................................3-132
3.13 Undervoltage Protection (27) .................................................................... 3-133

3.13.1 Application ....................................................................................................................3-133
3.13.2 Function ........................................................................................................................3-133
3.13.3 Operation Principle .......................................................................................................3-133
3.13.4 Logic .............................................................................................................................3-134
3.13.6 Settings.........................................................................................................................3-137
3.14 Thermal Overload Protection (49) ............................................................ 3-138

3.14.1 Application ....................................................................................................................3-138
3.14.2 Function ........................................................................................................................3-138
3.14.4 Logic .............................................................................................................................3-140
3.14.6 Settings.........................................................................................................................3-142
3.15 Breaker Failure Protection (50BF) ............................................................ 3-142

3.15.1 Application ....................................................................................................................3-142
3.15.3 Logic .............................................................................................................................3-144
3.15.4 Input and Output ...........................................................................................................3-145
3.15.5 Setting ..........................................................................................................................3-146
3.16 Pole Disagreement Protection (62PD) ..................................................... 3-147

3.16.1 Application ....................................................................................................................3-147
3.16.3 Logic .............................................................................................................................3-147
3.16.4 Input and Output ...........................................................................................................3-148
3.16.5 Setting ..........................................................................................................................3-149
3.17 Phase Overcurrent Alarm Element (50PAlm) .......................................... 3-149

3.17.1 Application ....................................................................................................................3-149
3.17.2 Function ........................................................................................................................3-150
3-d PCS-978 Transformer Relay

Date: 2011-10-19
3 Operation Theory
3.17.4 Logic .............................................................................................................................3-150
3.17.6 Settings.........................................................................................................................3-152
3.18 Three-Phase Current Element (Curr3P) ................................................... 3-152

3.18.1 Application ....................................................................................................................3-152
3.18.2 Function ........................................................................................................................3-152
3.18.3 Principle ........................................................................................................................3-152
3.18.4 Logic .............................................................................................................................3-153
3.18.6 Settings.........................................................................................................................3-155
3.19 Three-Phase Voltage Element (Volt3P) .................................................... 3-156

3.19.1 Application ....................................................................................................................3-156
3.19.2 Function ........................................................................................................................3-156
3.19.3 Principle ........................................................................................................................3-156
3.19.4 Logic .............................................................................................................................3-157
3.19.6 Settings.........................................................................................................................3-158
3.20 Residual Current Element (Curr1P).......................................................... 3-158

3.20.1 Application ....................................................................................................................3-158
3.20.2 Function ........................................................................................................................3-158
3.20.4 Settings.........................................................................................................................3-159
3.21 Residual Voltage Element (Volt1P) ........................................................... 3-159

3.21.1 Application ....................................................................................................................3-159
3.21.2 Function ........................................................................................................................3-159
3.21.4 Settings.........................................................................................................................3-160
3.22 Output Map (OutMap) ................................................................................ 3-160

3.22.1 Overview Description ....................................................................................................3-160
PCS-978 Transformer Relay 3-e

Date: 2011-10-19
3 Operation Theory
3.22.2 Output Map of Protection Element ................................................................................3-160
3.22.3 Programmable Tripping Output Element.......................................................................3-162
3.22.5 Setting ..........................................................................................................................3-163
3.23 Intermediate Variable Element .................................................................. 3-163

3.23.1 Principle ........................................................................................................................3-163
List of Figures
Figure 3.1-1 Current compensation calculation process .......................................................3-9
Figure 3.1-2 Operation characteristic curve of transformer sensitive biased differential

protection .................................................................................................................................3-12
Figure 3.1-3 Operation characteristic curve of transformer conventional biased differential

protection .................................................................................................................................3-13
Figure 3.1-4 Operation characteristic curve of biased and instant differential protections for
transformer ..............................................................................................................................3-14
Figure 3.1-5 Waveform of original current and DPFC current .............................................3-16
Figure 3.1-6 Operating characteristic curve of DPFC biased differential protection for
transformer ..............................................................................................................................3-19
Figure 3.1-7 Schematic of wave symmetry principle ............................................................3-21
Figure 3.1-8 Logic diagram of current differential protection..............................................3-27
Figure 3.1-9 Logic diagram of DPFC biased differential protection ....................................3-28
Figure 3.1-10 Logic diagram of CT circuit failure .................................................................3-29
Figure 3.1-11 87T function block ............................................................................................3-30
Figure 3.2-1 Current compensation calculation process .....................................................3-38
Figure 3.2-2 Operation characteristic curve of reactor sensitive biased differential

protection .................................................................................................................................3-41
Figure 3.2-3 Operation characteristic curve of reactor conventional biased differential

protection .................................................................................................................................3-42
Figure 3.2-4 Operation characteristic curve of biased and instant differential protections for
reactor ......................................................................................................................................3-43
Figure 3.2-5 Waveform of original current and DPFC current .............................................3-44
3-f PCS-978 Transformer Relay

Date: 2011-10-19
3 Operation Theory
Figure 3.2-6 Operating characteristic curve of reactor DPFC biased differential protection
..................................................................................................................................................3-47
Figure 3.2-7 Logic diagram of reactor current differential protection ................................3-49
Figure 3.2-8 Logic diagram of DPFC biased differential protection ....................................3-50
Figure 3.2-9 87R function block .............................................................................................3-51
Figure 3.3-1 REF application 1 for two-winding transformer with one CB at one side......3-55
Figure 3.3-2 REF application 2 for two-winding transformer with two CBs at one side ....3-55
Figure 3.3-3 REF typical application 3 for auto-transformer................................................3-56
Figure 3.3-4 Principle of restricted earth fault protection ....................................................3-58
Figure 3.3-5 Operating characteristic of REF protection .....................................................3-60
Figure 3.3-6 Logic diagram of winding differential protection ............................................3-62
Figure 3.3-7 64REF function block .........................................................................................3-63
Figure 3.4-1 Winding differential protection applied to auto-transformer ..........................3-66
Figure 3.4-2 Winding differential protection used as stub differential protection .............3-66
Figure 3.4-3 Operating characteristic curve of winding differential protection .................3-70
Figure 3.4-4 Logic diagram of winding differential protection of HV side ..........................3-71
Figure 3.4-5 87W function block.............................................................................................3-72
Figure 3.5-1 Wiring diagram of shunt reactors in power system ........................................3-76
Figure 3.5-2 Equivalent zero-sequence network for case 1 .................................................3-76
Figure 3.5-3 Vector relation for case 1 ...................................................................................3-77
Figure 3.5-4 Equivalent zero-sequence network for case 2 .................................................3-77
Figure 3.5-5 Vector relation for case 2 ...................................................................................3-77
Figure 3.5-6 Logic diagram of inter-turn fault protection .....................................................3-79
Figure 3.5-7 IntTurn Function block .......................................................................................3-80
Figure 3.6-1 Inverse-time characteristic of overexcitation protection ................................3-83
Figure 3.6-2 Logic diagram of stage 1 definite-time overexcitation protection .................3-83
Figure 3.6-3 Logic diagram of inverse-time overexcitation protection ...............................3-84
Figure 3.6-4 Function block of 24DT for trip .........................................................................3-84
Figure 3.6-5 Function block of 24DT for alarm ......................................................................3-85
Figure 3.6-6 Function block of 24IDMT ..................................................................................3-85
PCS-978 Transformer Relay 3-g

Date: 2011-10-19
3 Operation Theory
Figure 3.7-1 Logic diagram of underfrequency protection ..................................................3-92
Figure 3.7-2 Logic diagram of overfrequency protection.....................................................3-93
Figure 3.7-3 81U function block .............................................................................................3-94
Figure 3.7-4 81O function block .............................................................................................3-94
Figure 3.8-1 Logic Diagram of mechanical protection .........................................................3-98
Figure 3.8-2 Function block MR .............................................................................................3-99
Figure 3.9-1 Function diagram of phase overcurrent protection ......................................3-102
Figure 3.9-2 Connection of VT and CT of directional element ...........................................3-106
Figure 3.9-3 Directional characteristic of phase overcurrent protection ..........................3-106
Figure 3.9-4 Logic Diagram of phase overcurrent protection of x side (50/51Pn, n=1, 2, 3, 4)
................................................................................................................................................3-108
Figure 3.9-5 Logic Diagram of phase-to-phase VCE ........................................................3-108
Figure 3.9-6 Logic Diagram of negative-sequence VCE ..................................................3-108
Figure 3.9-7 Function block 50/51P (Each stage） .............................................................3-109
Figure 3.10-1 Function diagram of ground overcurrent protection ..................................3-114
Figure 3.10-2 Connection of VT and CT of directional element .........................................3-116
Figure 3.10-3 Directional characteristic of ground overcurrent protection ......................3-117
Figure 3.10-4 Logic Diagram of ground overcurrent protection of x side (50/51Gn, n=1,2,3,4)
................................................................................................................................................3-118
Figure 3.10-5 Function block 50/51G (each stage) .............................................................3-119
Figure 3.11-1 Logic diagram of residual overvoltage protection (59Pn, n=1,2) .............3-125
Figure 3.11-2 Function block 59G (Each stage) ..................................................................3-126
Figure 3.12-1 Logic diagram of residual overvoltage protection (59Pn, n=1,2) .............3-130
Figure 3.12-2 Function block 59G (Each stage) ..................................................................3-131
Figure 3.13-1 Logic diagram of undervoltage protection ................................................3-135
Figure 3.13-2 Function block 27 ...........................................................................................3-136
Figure 3.14-1 Characteristic curve of thermal overload protection ..................................3-139
Figure 3.14-2 Logic diagram of thermal overload protection of x side ..........................3-140
Figure 3.14-3 Function block 49 ...........................................................................................3-141
Figure 3.15-1 Logic diagram of breaker failure protection of x side .................................3-144
3-h PCS-978 Transformer Relay

Date: 2011-10-19
3 Operation Theory
Figure 3.15-2 Function block 50BF ......................................................................................3-145
Figure 3.16-1 Logical diagram of pole disagreement protection of x side .......................3-147
Figure 3.16-2 Function block 62PD ......................................................................................3-148
Figure 3.17-1 Logic diagram of phase overcurrent alarm (50PAlmn, n=1,2) .................3-150
Figure 3.17-2 Function block 50PAlm (each stage) ............................................................3-151
Figure 3.18-1 Current pre-processing logic diagram .........................................................3-153
Figure 3.18-2 Function block Curr3P ...................................................................................3-154
Figure 3.19-1 Voltage pre-processing logic diagram .........................................................3-157
Figure 3.19-2 Function block Volt3P ....................................................................................3-157
Figure 3.20-1 Function block Curr1P ...................................................................................3-158
Figure 3.21-1 Function block Volt1P ....................................................................................3-159
Figure 3.22-1 Output map of protection element ................................................................3-161
Figure 3.23-1 Programmed logic example ...........................................................................3-164
List of Tables
Table 3.1-1 Matrix of phase compensation..............................................................................3-6
Table 3.1-2 Comparison of different blocking modes ..........................................................3-22
Table 3.1-3 Input signals of 87T function block ....................................................................3-30
Table 3.1-4 Output signals of 87T function block .................................................................3-30
Table 3.1-5 Output signals of 87T: records ...........................................................................3-30
Table 3.1-6 Output signals of 87T: measurements ...............................................................3-31
Table 3.1-7 Setting list of 87T .................................................................................................3-32
Table 3.2-1 Input signals of 87R function block ....................................................................3-51
Table 3.2-2 Output signals of 87R function block .................................................................3-51
Table 3.2-3 Output signals of 87R: records ...........................................................................3-51
Table 3.2-4 Output signals of 87T: measurements ...............................................................3-52
Table 3.2-5 Setting list of 87R .................................................................................................3-53
Table 3.3-1 Input signals of 64REF function block ...............................................................3-63
Table 3.3-2 Output signals of 64REF function block ............................................................3-63
Table 3.3-3 Output signals of 64REF: report .........................................................................3-63
PCS-978 Transformer Relay 3-i

Date: 2011-10-19
3 Operation Theory
Table 3.3-4 Output signals of 64REF: measurements ..........................................................3-64
Table 3.3-5 Settings of 64REF of each side ...........................................................................3-64
Table 3.4-1 Input signals of 87W function block ...................................................................3-72
Table 3.4-2 Output signals of 87W function block ................................................................3-72
Table 3.4-3 Output signals of 87W: report .............................................................................3-72
Table 3.4-4 Output signals of 87W: measurements ..............................................................3-73
Table 3.4-5 Settings of 87W ....................................................................................................3-73
Table 3.5-1 Input signals of IntTurn function block ..............................................................3-80
Table 3.5-2 Output signals of IntTurn function block ...........................................................3-80
Table 3.5-3 Output signals of IntTurn: report ........................................................................3-80
Table 3.5-4 Settings of IntTurn ...............................................................................................3-80
Table 3.6-1 Input signals of function blocks (24DT and 24IDMT) ........................................3-85
Table 3.6-2 Output signals of function block 24DT1 for trip ................................................3-85
Table 3.6-3 Output signals of function block 24DT2 for alarm ............................................3-85
Table 3.6-4 Output signals of 24 .............................................................................................3-85
Table 3.6-5 Output signals of 24: report ................................................................................3-86
Table 3.6-6 Output signals of 24: measurements .................................................................3-86
Table 3.6-7 settings of 24 ........................................................................................................3-86
Table 3.6-8 Settings of 24DT1 (for trip) ..................................................................................3-87
Table 3.6-9 Settings of 24DT2 (for alarm) ..............................................................................3-87
Table 3.6-10 Settings of 24IDMT .............................................................................................3-87
Table 3.71 Input signals of 81U and 81O function block ......................................................3-94
Table 3.7-2 Output signals of 81U function block .................................................................3-94
Table 3.7-3 Output signals of 81O function block ................................................................3-94
Table 3.7-4 Output signals of frequency protection: report.................................................3-95
Table 3.7-5 Settings of frequency protection ........................................................................3-95
Table 3.8-1 Input signals of function block MR.....................................................................3-99
Table 3.8-2 Output signals of function block MR ..................................................................3-99
Table 3.8-3 Output signals of MR: report.............................................................................3-100
Table 3.8-4 Settings of MR ....................................................................................................3-100
3-j PCS-978 Transformer Relay

Date: 2011-10-19
3 Operation Theory
Table 3.9-1 Inverse-time curve parameters of stage 4 phase overcurrent protection ..3-103
Table 3.9-2 Voltage used for VCE.........................................................................................3-105
Table 3.9-3 Current and voltage used for directional element...........................................3-106
Table 3.9-4 Input signals of function block 50/51P (Each stage） ....................................3-109
Table 3.9-5 Output signals of function block 50/51P (Each stage） .................................3-109
Table 3.9-6 Output signals of 50/51P: report .......................................................................3-110
Table 3.9-7 Settings of control and blocking elements settings of 50/51P.......................3-110
Table 3.9-8 Settings of 50/51P Stage n (n=1,2,3) .................................................................3-111
Table 3.9-9 Settings of 50/51P Stage 4 ................................................................................3-111
Table 3.10-1 Inverse-time curve parameters of stage 4 ground overcurrent protection .3-115
Table 3.10-2 Input signals of function block 50/51G (each stage) .....................................3-119
Table 3.10-3 Output signals of function block50/51G (each stage) ...................................3-119
Table 3.10-4 Output signals of 50/51G: report ....................................................................3-119
Table 3.10-5 Settings of control and blocking elements of 50/51G ...................................3-120
Table 3.10-6 Settings of 50/51G Stage n (n=1,2,3) ..............................................................3-120
Table 3.10-7 Settings of 50/51G stage 4...............................................................................3-121
Table 3.11-1 Inverse-time curve parameters of stage 2 phase overvoltage protection ...3-124
Table 3.11-2 Input signals of function block 59G (Each stage) .........................................3-126
Table 3.11-3 Output signals of function block 59G（Each stage） ..................................3-126
Table 3.11-4 Output signals of 59G: report .........................................................................3-126
Table 3.11-5 Settings of 59P Stage 1 ...................................................................................3-127
Table 3.11-6 Settings of 59P Stage 2 ...................................................................................3-127
Table 3.12-1 Inverse-time curve parameters of stage 2 residual overvoltage protection3-130
Table 3.12-2 Input signals of 59G (Each stage)...................................................................3-131
Table 3.12-3 Output signals of 59G (Each stage) ................................................................3-131
Table 3.12-4 Output signals of 59G: report .........................................................................3-131
Table 3.12-5 Settings of 59G stage1 ....................................................................................3-132
Table 3.12-6 Settings of 59G stage 2 ...................................................................................3-132
Table 3.13-1 Input signals of function block 27 ..................................................................3-136
Table 3.13-2 Output signals of function block 27 ...............................................................3-136
PCS-978 Transformer Relay 3-k

Date: 2011-10-19
3 Operation Theory
Table 3.13-3 Output signals of 27: report ............................................................................3-136
Table 3.13-4 Settings of 27....................................................................................................3-137
Table 3.14-1 Input signals of function block 49 ..................................................................3-141
Table 3.14-2 Output signals of function block 49 ...............................................................3-141
Table 3.14-3 Output signals of 49: report ............................................................................3-141
Table 3.14-4 Output signals of 49: measurements .............................................................3-142
Table 3.14-5 Settings of 49....................................................................................................3-142
Table 3.15-1 Input signals of function block 50BF .............................................................3-145
Table 3.15-2 Output signals of function block 50BF ..........................................................3-145
Table 3.15-3 Output signals of 50BF: report .......................................................................3-145
Table 3.15-4 Settings of 50BF ...............................................................................................3-146
Table 3.16-1 Input signals of function block 62PD .............................................................3-148
Table 3.16-2 Output signals of function block 62PD ..........................................................3-148
Table 3.16-3 Output signals of 62PD: report .......................................................................3-149
Table 3.16-4 Settings of pole disagreement protection......................................................3-149
Table 3.17-1 Input signals of function block 50PAlm (each stage) ...................................3-151
Table 3.17-2 Output signals of function block 50PAlm (each stage) ................................3-151
Table 3.17-3 Output signals of 50PAlm: report ...................................................................3-152
Table 3.17-4 Settings of 50PAlm stage n (n=1,2) ................................................................3-152
Table 3.18-1 Input signals of function block Curr3P ..........................................................3-154
Table 3.18-2 Output signals of function block Curr3P .......................................................3-154
Table 3.18-3 Output signals of Curr3P: report ....................................................................3-154
Table 3.18-4 Output signals of Curr3P: measurements .....................................................3-155
Table 3.18-5 Settings of Curr3P............................................................................................3-155
Table 3.19-1 Input signals of function block Volt3P ...........................................................3-157
Table 3.19-2 Output signals of function block Volt3P ........................................................3-157
Table 3.19-3 Output signals of Volt3P: report .....................................................................3-158
Table 3.19-4 Settings of Volt3P ............................................................................................3-158
Table 3.20-1 Input signals of function block Curr1P ..........................................................3-159
Table 3.20-2 Output signals of function block Curr1P .......................................................3-159
3-l PCS-978 Transformer Relay

Date: 2011-10-19
3 Operation Theory
Table 3.20-3 Settings of Curr1P............................................................................................3-159
Table 3.21-1 Input signals of function block Volt1P ...........................................................3-159
Table 3.21-2 Output signals of function block Volt1P ........................................................3-160
Table 3.21-3 Settings of Volt1P ............................................................................................3-160
Table 3.22-1 Input signals of programmable tripping output element ..............................3-162
Table 3.22-2 Settings of programmable tripping output element ......................................3-163
Table 3.23-1 Input signals of intermediate variable element .............................................3-164
PCS-978 Transformer Relay 3-m

Date: 2011-10-19
3 Operation Theory
3.1 Overview
The equipment consists of current differential protection, restricted earth fault protection,
overexcitation protection, phase overcurrent protection, directional ground overcurrent protection,
phase overvoltage protection, undervoltage protection, ground overvoltage protection, thermal
overload protection, and ancillary functions of current transformer and voltage transformer
supervision.
The equipment has 2 plug-in modules (i.e. protection DSP module and fault detector DSP module)
for protection calculation. Protection DSP module is responsible for calculation of protection
elements, and fault detector DSP module is responsible for calculation of general fault detector
element to determine fault appearance on the protected power system. General fault detector
picks up to provide positive supply to output relays. The output relays can only operate when both
a protection element and the corresponding general fault detector operate simultaneously.
Otherwise, the output relays would not operate. An alarm message will be issued with blocking
output if a protection element operates while the corresponding general fault detector does not
operate.
The fault detector of fault detector DSP module consists of several independent fault detector
elements, which can monitor corresponding protection elements without influence to other
protection elements. For example, biased current differential protection will not release trip
command until both protection element of protection DSP module and the corresponding fault
detector of fault detector DSP module operate simultaneously. Furthermore, if there is a hardware
fault on one DSP module or the differential current is at the trip boundary, the inconsistent pickup
of fault detectors of biased current differential protection on two DSP modules will occur.
3.1 Transformer Current Differential Protection (87T)
3.1.1 Application
In power system, the power transformer is one of most valuable and expensive equipment. If a
fault occurs in the protection zone of a transformer, current differential protection operates quickly
to clear the fault to avoid the transformer from damages or reduce the maintenance cost as low as
possible.
3.1.2 Function
z Maximum 6 group CT inputs for differential protection.
z Protection for 2-winding, 3-winding transformer and auto-transformer.
z 24 vector groups available for two-winding transformer.
z 288 vector groups available for 3-winding transformer.
z Optional inrush current distinguished principles: harmonic criterion (second harmonic and
third harmonic) or waveform distortion.

Date: 2011-10-19
3 Operation Theory
z There are two optional modes for harmonic criterion: self-adaptive blocking mode and
phase-to-phase cross blocking mode. Self-adaptive blocking mode can enhance ability of
differential protection to avoid maloperation during transformer energization effectively and
ensure high speed of differential protection for faults under normal operation.
z Fifth harmonic or third harmonic criterion applied continuously to detect overexcitation

condition.
z Three slopes biased differential protection are settable by users.
z Unrestrained instantaneous differential protection is equipped.
z Distinct Method of Phase Compensation
△→Y and Y→△ transfer methods can be selected by user through settings, and △→Y
transfer method is recommended. During transformer energization, △→Y transfer method is
used to adjust phase angle of secondary current on each side of the transformer, and thus the
faulty and healthy phase can possess its characteristic. Therefore, restraint current and
differential current can be phase-segregated, which can distinguish the faulty phase from
phase only with inrush current characteristic when transformer is energized. Zero-sequence
current is always eliminated both at Y and Δ windings by adopting Δ→Y method.
small internal fault current within the transformer. Its performance against current transformer
conventional differential elements as well as independent CT saturation criterion.
be distinguished.
3.1.3 Protection Principle
3.1.3.1 Overview
Current differential protection includes biased differential protection, unrestrained differential

protection, DPFC biased differential protection. Biased differential protection is three-slope
differential protection with biased characteristic. Unrestrained differential protection is to
accelerate the operating speed for transformer’s severe internal faults without biased
characteristic and blocking elements. DPFC biased differential protection calculated by current
variation has high sensitivity to inter-turn faults and high impedance fault) under heavy load.
Above three differential protection elements work coordinately to form the high-speed current
differential protection with high sensitivity.

Date: 2011-10-19
3 Operation Theory
3.1.3.2 Fault Detector
z Fault Detector of Biased Differential Current
The pickup of this fault detector will enable the biased differential protection, and its operation
equation is as follows.
I d > [87T.I_Biased] Equation 3.1-1
Where：
I d is the differential current of any phase.
[87T.I_Biased] is the pickup current of biased differential protection.
z Fault Detector of Instantaneous Differential Protection
The pickup of this fault detector will enable the unrestrained instantaneous differential protection, ,
and its operation equation is as follows.
I d > 0.9x[87T.I_Instant] Equation 3.1-2
Where：
[87T.I_Instant] is the setting of the unrestrained instantaneous differential protection.
z Fault Detector of DPFC Differential Current
The pickup of this fault detector will enable the DPFC biased differential protection, and its
operation equation is as follows.
ΔI d > 1.25ΔI dt + I dth

Equation 3.1-3
ΔI = ΔI& + ΔI& + ... + ΔI&
d 1 2 m
Where:
ΔI dt is the floating threshold varied with the change of load current from time to time. The change
of load current is small and gradually under normal or even power swing condition, the adaptive
floating threshold ( ΔI dt ) is higher than the change of current under these conditions and hence
the element maintains stability.
I dth is fixed threshold in program. The sum value of ΔI dt and I dth is equal to 0.2pu.

Date: 2011-10-19
3 Operation Theory
ΔI&1 …. ΔI&m are the DPFC current of each side of transformer representatively.
ΔI d is the DPFC differential current.
This fault detector, regardless of direction of power flow and very sensitive, is used to guard DPFC
biased differential protection. The setting is fixed in factory and thus site setting is not required.
3.1.3.3 Amplitude Compensation
During the normal operation, the magnitudes of secondary current of each side of transformer are
different due to the mismatch between the CT ratios and the power transformer ratio. The current
value difference between each side shall be eliminated before calculation for current differential
protection by amplitude compensation.
z Calculate rated primary current at each side
Sn
I1bBrm = Equation 3.1-4
3U 1nBrm
Where:
Brm=Branch (side) “m”.
S n is the maximum rated capacity (i.e. the setting [Sn]).
U 1n is rated primary voltage.
U 1nBrm is rated primary voltage of branch m (i.e. the setting [Un_XXX])
I1bBrm is rated primary current of branch m.
z Calculate rated secondary current at each side
I
I 2bBrm = 1bBrm Equation 3.1-5
CTBrm
Where:
I 2bBrm is rated secondary current of branch m.
CTBrm is the CT ratio of branch m.

Date: 2011-10-19
3 Operation Theory
z Limitation of secondary current
For all differential protections, the secondary currents of each branch must follow below criterion.
Max{I 2bBr1 / I 2nBr1, I 2bBr 2 / I 2nBr 2 ,..., I 2bBrm / I 2nBrm )

<16 Equation 3.1-6
Min{I 2bBr1 / I 2 nBr1, I 2bBr 2 / I 2nBr 2 ,..., I 2bBrm / I 2nBrm )
For DPFC biased differential protection, the secondary currents of each branch must follow below
criteria in addition to the previous one.
Max{I 2bBr1 / I 2 nBr1, I 2bBr 2 / I 2 nBr 2 ,..., I 2bBrm / I 2 nBrm ) >0.4

Equation 3.1-7
Min{I 2bBr1 / I 2 nBr1, I 2bBr 2 / I 2 nBr 2 ,..., I 2bBrm / I 2 nBrm ) >0.1
Where:
I 2bBr1, I 2bBr 2 , I 2bBrm are rated secondary current of branch 1, branch 2 and branch m of
transformer.
I 2 nBr1, I 2 nBr 2 , I 2 nBrm are rated secondary current of CT at branch 1, branch 2 and branch m of
NOTE! If Equation 3.1-6 is not met, alarm signals [ProtBrd.Alm_Settings] and
[FDBrd.Alm_Settings] are issued and displayed on LCD and the protective equipment
being blocked at the same time.
NOTE: If Equation 3.1-7 is not met, DPFC biased differential protection must not be
enabled. Otherwise, alarm signals [ProtBrd.Alm_Settings] and [FDBrd.Alm_Settings] are

issued on LDC and the protective equipment being blocked at the same time.
When viewing settings and values of conventional current differential protection in the relay, user
will find the unit “pu” (per unit). The current in differential protection calculation is not actual
secondary value but per unit value which is got by actual secondary value of each branch of
transformer divided by transformer secondary rated current of each branch (i.e. I 2bBrm ).
3.1.3.4 Phase Compensation
z Phase Compensation Principle
False differential current is caused by phase shift between the power transformer primary and

Date: 2011-10-19
3 Operation Theory
secondary currents for delta/wye, so phases of each side secondary current must be
compensated by this phase compensation.
The following transforming method is based on the assumptions listed here:
1) Each side three-phase CT of transformer shall be connected in star type.
2) The positive polarity of each side three-phase CT shall be at busbar side.
The wiring connection of HV, MV and LV sides may be different, so it is needed to compensate
phase of each side current of transformer for calculation of current differential protection. There
are two transforming methods for phase compensation: Δ→Y and Y→Δ, and different transforming
methods will result in the difference.
Phase compensation is controlled by the following settings:
1) [Clk_MVS_WRT_HVS],[Clk_LVS_WRT_HVS]: the wiring o’clock of MV/LV side with respect to

HV side, is the parameter shown on transformer nameplate with the range of 0~11, and need
no further calculation.
2) [Opt_Clk_PhComp]: the target o’clock each side current will be shift to for phase
compensation.
3) [En_I0Elim_HVS], [En_I0Elim_MVS] and [En_I0Elim_LVS]: logic settings to enable

zero-sequence current elimination for phase compensation of each side of transformer. The
setting is recommended to be set to “1” in general condition, and only if one side of transformer,
without eathing transformer being connected to, is not grounded, the setting of corresponding
side is recommended to be set to “0”.
For example:
The vector group of a transformer is Y0/Δ11 and the target o’clock ([Clk_PhComp]) is set to “11”.
1) For HV side, with reference to the set target o'clock the o'clock of HV side is 1 (i.e. wiring
o’clock 12-target o’clock 11) clock, so the matrix of relative o’clock 1 is adopted to
compensate HV side current.
2) For LV side, with reference to the set target o'clock the o'clock of HV side is 0 (i.e. wiring
o’clock 11- target o’clock 11), so the matrix of relative o’clock 0 is adopted to compensate LV
side current.
If an earthing transformer is connected outide the protection zone of differential protection, the
setting [En_I0Elim_HVS(or LVS)] could be disabled, i.e. set to 0.
If an earthing transformer is connected within the protection zone of differential protection,

then zero-sequence current must be eliminated and otherwise differential protection may
operate unexpectively during an external fault. Therefore the setting [En_I0Elim_HVS(or LVS)]
must be enabled, i.e. set to 1.
Table 3.1-1 Matrix of phase compensation

Date: 2011-10-19
3 Operation Theory
Matrix
Matrix
Relative o’clock (without zero-sequence current
(with zero-sequence current elimination)
elimination)
⎡1 0 0⎤ ⎡ 2 −1 −1⎤
0 ⎢ ⎥ 1 ⎢ ⎥
⎢0 1 0⎥ ⋅ ⎢− 1 2 − 1⎥
(No phase shit) 3
⎢⎣0 0 1⎥⎦ ⎢⎣− 1 − 1 2 ⎥⎦
⎡ 1 −1 0 ⎤ ⎡ 1 −1 0 ⎤
1 1 ⎢ ⎥ 1 ⎢ ⎥
(Shift 30° leading) ⎢ 0 1 − 1⎥ ⎢ 0 1 − 1⎥
3⎢ 3⎢
⎣− 1 0 1 ⎥⎦ ⎣− 1 0 1 ⎥⎦
⎡ 0 − 1 0⎤ ⎡ 1 −2 1 ⎤
2 ⎢ 0 0 −1 ⎥ 1 ⎢ ⎥
⎢ ⎥ ⋅⎢ 1 1 − 2⎥
(shift 60° leading) 3
⎢⎣− 1 0 0⎥⎦ ⎢⎣− 2 1 1 ⎥⎦
⎡ 0 −1 1 ⎤ ⎡ 0 −1 1 ⎤
3 1 ⎢ ⎥ 1 ⎢ ⎥
(Shit 90° leading) ⎢ 1 0 − 1⎥ ⎢ 1 0 − 1⎥
3⎢ 3⎢
⎣− 1 1 0 ⎥⎦ ⎣− 1 1 0 ⎥⎦
⎡0 0 1⎤ ⎡ −1 −1 2 ⎤
4 ⎢ ⎥ 1 ⎢ ⎥
⎢1 0 0⎥ ⋅ ⎢ 2 − 1 − 1⎥
(Shit 120° leading) 3
⎢⎣0 1 0⎥⎦ ⎢⎣− 1 2 − 1⎥⎦
⎡ −1 0 1 ⎤ ⎡ −1 0 1 ⎤
5 1 ⎢ ⎥ 1 ⎢ ⎥
(Shift 150° leading) ⎢ 1 −1 0 ⎥ ⎢ 1 −1 0 ⎥
3⎢ 3⎢
⎣ 0 1 − 1⎥⎦ ⎣ 0 1 − 1⎥⎦
⎡− 1 0 0⎤ ⎡−2 1 1⎤
6 ⎢ 0 − 1 0⎥ 1 ⎢ ⎥
⎢ ⎥ ⋅⎢ 1 −2 1 ⎥
(Shift 180° leading) 3
⎢⎣ 0 0 − 1⎥⎦ ⎢⎣ 1 1 − 2⎥⎦
⎡ −1 1 1 ⎤
7 ⎡ −1 1 1 ⎤ 1 ⎢ ⎥
1 ⎢ ⎥ ⎢ 0 −1 1 ⎥
(Shift 150° lagging)
⎢ 0 −1 1 ⎥ 3⎢
3⎢ ⎣ 1 0 − 1⎥⎦
⎣ 1 0 − 1⎥⎦
⎡0 1 0⎤ ⎡ −1 2 − 1 ⎤
⎢ ⎥ 1 ⎢
⋅ ⎢ −1 − 1 2 ⎥⎥
8
(Shift 120° lagging) ⎢0 0 1⎥ 3
⎢⎣1 0 0⎥⎦ ⎢⎣ 2 − 1 − 1⎥⎦
⎡ 0 1 −1⎤ ⎡ 0 1 −1⎤
9 1 ⎢ ⎥ 1 ⎢ ⎥
(Shift 90° lagging) ⎢− 1 0 1 ⎥ ⎢− 1 0 1 ⎥
3⎢ 3⎢
⎣ 1 − 1 0 ⎥⎦ ⎣ 1 − 1 0 ⎥⎦

Date: 2011-10-19
3 Operation Theory
Matrix
Matrix
Relative o’clock (without zero-sequence current
(with zero-sequence current elimination)
elimination)
⎡ 0 0 −1⎤ ⎡1 1 −2 ⎤
10 ⎢ ⎥ 1 ⎢ ⎥
⎢− 1 0 0 ⎥ ⋅ ⎢− 2 1 1⎥
(Shift 60° lagging) 3
⎢⎣ 0 − 1 0 ⎥⎦ ⎢⎣ 1 − 2 1 ⎥⎦
⎡ 1 0 −1⎤ ⎡ 1 0 −1⎤
11 1 ⎢ ⎥ 1 ⎢ ⎥
(Shift 30° lagging) ⎢− 1 1 0 ⎥ ⎢− 1 1 0 ⎥
3⎢ 3⎢
⎣ 0 − 1 1 ⎥⎦ ⎣ 0 − 1 1 ⎥⎦
3.1.3.5 Calculations of Differential and Restraint Currents
⎡ I dA ⎤ ⎡ I A1⎤ ⎡ I A2 ⎤ ⎡ I A3⎤ ⎡ I A4 ⎤
⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢ dB ⎥ M 1 ⎢ I B1⎥ 2bBr1 M 2 ⎢ I B2 ⎥ 2bBr2 M 3 ⎢ I B3⎥ 2bBr3 M 4 ⎢ I B4 ⎥ / I 2bBr4 +
I = × / I + × / I + × / I + ×
⎢⎣ I dC ⎥⎦ ⎢ I C1⎥ ⎢ I C 2⎥ ⎢ I C 3⎥ ⎢I C 4 ⎥
144 ⎣42⎦444 3 144 ⎣ 42⎦4443 144 ⎣ 42⎦4443 144 ⎣ 42⎦4443
1 2 3 4
Equation 3.1-8
⎡ I A5 ⎤ ⎡ I A6 ⎤
⎢ ⎥ ⎢ ⎥
M 5 × ⎢ I B5 ⎥ / I 2bBr5 + M 6 × ⎢ I B6 ⎥ / I 2bBr6
⎢I C5 ⎥ ⎢I C6 ⎥
144 ⎣ 42⎦4443 144 ⎣ 42⎦4443
5 6
The above equation can be simplified to the following:
⎧ I dA = I ′ A1 + I ′ A2 + I ′ A3 + I ′A4 + I ′A5 + I ′A6

⎪
⎨ I dB = I ′ B1 + I ′B 2 + I ′B 3 + I B′ 4 + I B′ 5 + I B′ 6 Equation 3.1-9
⎪
⎩ I dC = I ′C1 + I ′C 2 + I ′C 3 + I C′ 4 + I C′ 5 + I C′ 6
Where:
I Am , I Bm , I Cm in the equation are vectors, the secondary current of branch (Br for abbreviation) m
(m=1, 2, 3, 4, 5, 6).
I ′ Am , I ′Bm , I ′Cm are corrected secondary current of branch m (m=1, 2, 3, 4, 5, 6).
I dA , I dB , I dC are differential currents.

M 1, M 2 , M 3 , M 4 , M 5 , M 6 are matrixes of phase shifting of each branch of transformer respectively. Its
value is decided according to the vector group of transformer and please refers to Section 3.1.3.3
for details.
I 2bBr1 , I 2bBr 2 , I 2bBr 3 , I 2bBr 4 , I 2bBr 5 , I 2bBr 6 are rated secondary values of each branch of transformer
respectively.
The equation of calculating restraint current is:

Date: 2011-10-19
3 Operation Theory
⎧ 1
( )
⎪ I rA = 2 I ′ A1 + I ′ A2 + I ′ A3 + I ′ A4 + I ′ A5 + I ′ A6
⎪
⎪
⎨ I rB =
1
2
(
I ′B1 + I ′B 2 + I ′B 3 + I ′B 4 + I ′B 5 + I ′B 6) Equation 3.1-10
⎪
⎪ 1
(
⎪ I rC = 2 I ′C1 + I ′C 2 + I ′C 3 + I ′C 4 + I ′C 5 + I ′C 6 )
⎩
Where:
I rA , I rB , I rC are restraint currents.
Current compensation process is shown in the flowing figure by taken 2-winding transformer with
three-phase CT inputs for an example. In an ideal situation, the differential current （ i.e.
I d = I ′ _ H + I ′ _ L ）should be zero during the normal operation of the transformer or an external
fault occurring.
I_H I_L
HV side LV side
I'_H I'_L
PCS-978
Phase shift/zero sequence Phase shift/zero sequence
current elimination (*M1) current elimination (*M2)
Magnitude compensation Magnitude compensation

(/I2bBr1) (/I2bBr2)
I''_H I''_L
Calculate differential current and restraint current
Figure 3.1-1 Current compensation calculation process
NOTE! The symbol * represents the polarity of CT. If current flowing into the polarity of CT,
the current direction is defined as positive direction.
In above figure:
I_H, I_L are primary currents of HV and LV sides respectively.
I’_H, I’_L are secondary currents of HV and LV sides respectively.
I’’_H, I’’_L are secondary corrected currents of HV and LV sides respectively.
M1, M2 are matrixes of phase shifting and zero sequence current elimination of HV and LV sides
respectively.

Date: 2011-10-19
3 Operation Theory
I 2bBr 1 , I 2bBr 2 are rated secondary currents at HV and MV sides respectively.
To clarify the situation, three important operation conditions with ideal and matched measurement
quantities are considered.
1. Through-flowing current under undisturbed conditions or external fault:
I’_H flows into the protected zone, I’_L leaves the protected zone, i.e. is negative according to
the definition of signs in above figure, therefore I’_H=–I’_L.
Moreover |I’_H|=|I’_L|
Id=|I’_H+I’_L|=|I’_H–I’_H|=0;
Ir=(|I’_H|+|I’_L|)/2=(|I’_H|+|I’_H|)/2=|I’_H|
No differential current (Id=0), restraint current (Ir) corresponds to double the through-flowing
current, and current differential protection does not operate.
2. Internal short-circuit. e.g. fed with equal currents each side:
The following applies I’_L=I’_H, moreover |I’_L|=|I’_H|
Id=|I’_H+I’_L|=|I’_H+I’_H|=2|I’_H|;
Ir=(|I’_H|+|I’_L|)/2=(|I’_H|+|I’_H|)/2=|I’_H|
Differential current (Id) are two times of restraint current (Ir) and corresponding to the total
fault, and current differential protection operates.
3. Internal short-circuit, fed from one side only:
The following applies I’_L=0
Id=|I’_H+I’_L|=|I’_H+0|=|I’_H|;
Ir=(|I’_H|+|I’_L|)/2=(|I’_H|+|0|)/2=|I’_H|/2
Differential current (Id) are two times of restraint current (Ir) and corresponding to single-sided
3.1.3.6 Sensitive Biased Differential Protection
The currents used in this section analysis and the following analysis have been corrected, that
means the currents for following calculation are the products of the actual secondary current of
each side multiplying its own correction coefficient
The sensitive biased differential protection with low pickup setting and restraint slope is much
more sensitive for a slight internal fault. Four blocking elements, CT saturation, inrush current, CT
circuit failure (optional) and overexcitation (optional) have also been included for the protection in
order to prevent it from the unwanted operation during an external fault

Date: 2011-10-19
3 Operation Theory
⎧I d > Slope1 × I r + I_Biased I r < I_Knee1

⎪
⎪I d > Slope2 × ( I r − I_Knee1) + Slope1 × I_Knee1 + I_Biased .I_Knee1 ≤ I r ≤ I_Knee 2
⎪I d > Slope3 × ( I r − I _ Knee 2) + Slope2 × ( I _ Knee 2 − I _ Knee1) + Slope1 × I _ Knee1 + I_Biased I r > I_Knee 2
⎪ m
∑ I&
⎪ 1
⎨I r = i
⎪ 2
⎪ i =1
⎪ m
⎪I d
⎪
= ∑ I&
i =1
i
⎩
Equation 3.1-11
Where:
I&i (i = 1 … m) are the phase currents of each branch (from 1 to m) of a transformer respectively.
I d is the differential current.
I r is the restraint current.
[I_Biased] is the pickup current of biased differential protection.
[I_Knee1] and [I_Knee2] are respectively current settings of knee point 1 and keen point 2.
[Slope1], [Slope2], [Slope3] are three slopes of biased differential protection. Recommended
values: [Slope1]=0.2, [Slope2]=0.5 and [Slope3]=0.75.
pu is the unit of differential current and restraint current.
NOTE! In the protection relay, setting items are added with a prefix “87T.”, such as
[87T.I_Biased], [87T.I_Knee1], etc.
Operation characteristic of sensitive biased differential protection is shown below.

Date: 2011-10-19
3 Operation Theory
Id(pu)
Differential
current
2
K=
[87T.I_Instant]
6
0. of .
K= ea Diff
ar d
3]
g se
pe
n
ti ia
lo
S
ra e B
7.
e
[8
p v
O siti
n
se
]
lo pe2
1.2 T.S
[87
e1]
.Slop
[87T
[87T.I_Biased]
0.8 restraint current
0 [87T.I_Knee1] [87T.I_Knee2] Ir(pu)
Figure 3.1-2 Operation characteristic curve of transformer sensitive biased differential protection
In above figure:
[87T.I_Instant] is the current setting of unrestrained instantaneously differential protection.
3.1.3.7 Conventional Biased Differential Protection
Conventional biased differential protection with higher setting and restraint coefficient comparing
with sensitive biased differential protection is blocked only by an inrush current detection.
Conventional biased differential protection provides faster operation for sever internal faults.
Operation criterion of this biased differential protection is:
⎧ I d > 1.2 pu I r ≤ 0.8 pu

⎨
⎩ I d > 0.6 × ( I r − 0.8 pu ) I r > 0.8 pu Equation 3.1-12
Where:
I d , I r and pu have same definitions as mentioned above.
NOTE! The slope and the keen point are fixed in program, values of which eliminate the
influence of CT saturation during an external fault and ensures reliable operation even if
CT is saturated during an internal fault by means of its biased characteristic. Therefore,

Date: 2011-10-19
3 Operation Theory
the slope and the keen point with constant values do not need to be set by user.
Operation characteristic of conventional biased differential protection is shown below.
2
K=
d f
.
iff
se o
ia rea
D
lb a
tia ing
en rat
nv pe
co O
6
0.
K=
Figure 3.1-3 Operation characteristic curve of transformer conventional biased differential protection
3.1.3.8 Unrestrained Instantaneous Differential Protection
Unrestrained instantaneous differential protection for transformer is to accelerate the operation

speed for transformer’s internal fault. The element has no blocking element but to guard that the
setting must be greater than the maximum inrush current.
Unrestrained differential element shall operate to clear the fault when any phase differential
current is higher than its setting. Its operation criterion is:
I d >[87T.I_Instant] Equation 3.1-13
Where:
I d is the maximum value of three phase differential currents.
[87T.I_Instant] is the setting of the unrestrained instantaneous differential protection.
3.1.3.9 Operation Characteristic of Biased and Instant Differential Protections
The characteristic of internal faults is a straight line with the slope 2 (63.4°) in the operation

Date: 2011-10-19
3 Operation Theory
diagram (dash-dotted line K=2)
Id (pu)
2
K=
F Tripping area of
instantaneous Diff.
[87T.I_Instant]
ff.
Di
se f
ia o
d
l b rea
6
na a
tio ing 0. o f f.
K= a Dif
e
en pp
ar d
]
e3
g ias e
nv Tri
op
n
pi B
Sl
7.
ip ve
[8
r
T i ti
co
E C ns
se
D
1.2 ]
e1] lo pe2
.Slop T.S
[87T
[87
[87T.I_Biased]
B restraint current
0 A KP1 0.8 KP2 Ir (pu)
Figure 3.1-4 Operation characteristic curve of biased and instant differential protections for transformer
In above figure:
KP1, KP2 are respectively X-axis values of keen point 1 and keen point 2, i.e. [87T.I_Knee1] and
[87T.I_Knee2].
A is the point shows normal operation of transformer.
B is the point shows CT saturation.
C, D, E, and F are points show internal faults or external fault of transformer.
1) Sensitive biased differential protection element will send tripping signal monitored by CT
saturation, overexcitation, inrush current and CT circuit failure (optional). It can ensure
sensitivity of protection and avoid the unwanted operation when CT is saturated during an
external fault. Its operation area is the tint shadow area in the figure above.
When a slight intern fault occurs, differential current rises not greatly and the operating point
moves from A to D into the tripping area of sensitive biased differential protection.
When an external fault occurs, the short-circuit current rise strongly, causing a correspondingly
high restraint current (2 times through-flowing current) with little differential current. After CT

Date: 2011-10-19
3 Operation Theory
reaches saturation (point B), a differential quantity is produced and the restraint quantity is
reduced. In consequence, the operating point may moves into the tripping area of sensitive
biased differential protection. Because CT saturation criterion is equipped, sensitive biased
differential protection will no maloperate even the fault point moves into the tripping area.
2) Conventional biased differential protection element will send tripping signal monitored by
inrush current only. It eliminates the influence of transient and steady saturations of CT during
an external fault and ensures reliable operation even if CT is in saturation condition during an
internal fault by means of its biased characteristic. Its operation area is the deeper shadow
area in the figure above.
When an internal fault occurs, differential current rises greatly and the operating point moves
to F in the tripping area of conventional biased differential protection.
NOTE! Only the second harmonic criterion is adapted to distinguishing inrush current for
blocking conventional biased differential protection.
3) Unrestrained instantaneous differential protection element will send tripping signal without any
blocking if differential current of any phase reaches its setting. Its operation area is over the
above two areas with the deepest dark shadow.
When a severe internal fault occurs, differential current rises sharply and the operating point
moves to E in the tripping area of instantaneous differential protection.
3.1.3.10 DPFC Biased Differential Protection Element
3.1.3.10.1 DPFC Concept
ΔI = I (k ) − I (k − 24)
DPFC (Deviation of Power Frequency Component) is the power frequency component of fault
component, which is the differential value between the sampling value at this time point and that at
a cycle before.
I (k ) is the sampling value at the time point.
I ( k − 24) is the sampling value at a cycle before, 24 is the sampling points in one cycle.

Date: 2011-10-19
3 Operation Theory
200
100
-100
-200
0 20 40 60 80 100 120
Original Current
100
50
-50
-100
0 20 40 60 80 100 120
DPFC current
Figure 3.1-5 Waveform of original current and DPFC current
From above figures, it is concluded that DPFC can reflect the sudden change of fault current at the
initial stage of a fault and has a perfect performance of fault detection.
3.1.3.10.2 Operation Criterion
DPFC (Deviation of Power Frequency Component) biased differential protection reflects variation
of load condition to perform a sensitive protection for the transformer. Lab tests show that it is
more sensitive than the biased differential relay under the heavy load condition.
The operation criteria of DPFC biased differential are as follows:
⎧ΔI d > 0.2 pu

⎪
⎪ΔI d > 1.25 × ΔI dt + I dth
⎨
⎪ΔI d > 0.6 × ΔI r ΔI r < 2 pu
⎪ΔI d > 0.75 × ΔI r − 0.3 × I e ΔI r > 2 pu
⎩
Equation 3.1-14
m m m
ΔI r = max{ ∑ ΔI& , ∑ ΔI& ,∑ ΔI&
k =1
ak
k =1
bk
k =1
ck }
ΔI d = ΔI&1 + ΔI&2 + .... + ΔI&m
Where:

Date: 2011-10-19
3 Operation Theory
I dth is fixed threshold and need not use to configure it. The sum value of ΔI dt and I dth is
equal to 0.2pu.
ΔI&a1 ， ΔI&b1 ， ΔI&c1 are DPFC current of branch 1 of power transformer.
ΔI&am ， ΔI&bm ， ΔI&cm are DPFC current of branch m of power transformer.
ΔI r is the DPFC restraint current, it is the maximum current among the restraint current of three
phases.
NOTE! Calculation of restraint current of DPFC biased differential protection is different to
the biased differential protection, it is difficult to test the characteristic at site, so we

recommend qualitative function test only at site.
Calculation of DPFC restraint current and differential current is phase-segregated. DPFC biased
differential protection is blocked by inrush current, overexcitation and CT circuit failure.
z Advantages of DPFC differential protection
DPFC biased differential protection has the higher anti-CT saturation characteristic, the
sensitivity of which to slight inter-turn fault is maintained during normal operation of transformer.
Floating threshold patent technology is adopted to prevent maloperation of DPFC differential
protection due to system frequency deviation, external faults and CB tripping process.
The sensitivity of current differential protection is improved greatly when DPFC differential
protection enabled, especially in the situation turn-to-turn fault during heavy load operation.
3.1.3.10.3 Fault Calculation Examples
DPFC differential protection can detect a slight inter-turn fault of transformer more sensitively than
biased current differential protection. During a slight inter-turn fault, fault current will flowing
through transformer whether transformer is fed from one side or from both sides. Therefore,
following two typical situations an external fault and a slight inter-turn fault are given to show
differential and restraint current calculation.
During normal operation, Ia_HVS=1A∠0°, Ib_LVS=1A∠180°

Date: 2011-10-19
3 Operation Theory
1) A slight inter-turn fault: I'a_HVS=1.3A∠0°, I'b_LVS=1.1A∠180°, other phase supposed zero
Biased differential protection for the fault:
Id=|I'a_HVS+I'b_LVS|=|1.3A∠0°+1.1A∠180°|=0.2A
Ir=0.5x(|I'a_HVS|+|I'b_LVS|)=0.5x(|1.3A∠0°|+|1.1A∠180°|)=1.2A
DPFC differential protection for the fault:
ΔId=|(I'a_HVS-Ia_HVS)+(I'b_LVS-Ib_LVS)|
=|(1.3A∠0°-1A∠0°)+(1.1A∠180°-1A∠180°)|=0.2A
ΔIr=Max(|I'a_HVS-Ia_HVS|, |I'b_LVS-Ib_LVS|)
=Max(|1.3A∠0°-1A∠0°|,|1.1A∠180°-1A∠180|)=0.3A
Conclusion: DPFC differential protection is more sensitive than biased differential protection
during an internal fault.
2) An external fault: I'a_HVS=2A∠0°, I'b_LVS=2A∠180°, other phase supposed zero
Id=|I'a_HVS+I'b_LVS|=|2A∠0°+2A∠180°|=0A
Ir=0.5x(|I'a_HVS|+|I'b_LVS|)=0.5x(|2A∠0°|+|2A∠180°|)=2A
ΔId=|(I'a_HVS-Ia_HVS)+(I'b_LVS-Ib_LVS)|
=|(2A∠0°-1A∠0°)+(2A∠180°-1A∠180°)|=0A
ΔIr=Max(|I'a_HVS-Ia_HVS|, |I'b-_LVS-Ib_LVS|)
=Max(|2A∠0°-1A∠0°|,|2A∠180°-1A∠180°|)=1A
Conclusion: DPFC differential protection does not operate during an external fault.
3.1.3.10.4 Operation Characteristic

Date: 2011-10-19
3 Operation Theory
△ Id
m
K= K=0.75
1.2pu
K=0.6
0.2pu
restraint current
2pu
0.333pu
△Ir
Figure 3.1-6 Operating characteristic curve of DPFC biased differential protection for transformer
In above figure:
The value of m is not greater than 1. For the phase with maximum restraint current, m is equal to 1,
and for other phases, m is less than 1.
3.1.3.11 Inrush Current Detection
In this protection equipment, the logic setting [Opt_Inrush_Ident] is provided for user to select the
restraint blocking principle. If the logic setting is set as “0”, discrimination by waveform distortion
is enabled, and if it is set as “1”, discrimination by harmonics is enabled.
3.1.3.11.1 Distinguishing by Harmonics
In PCS-978 series protection equipment, the second and third harmonics of differential current can
be used to distinguish inrush current. Its criteria are:
⎧⎪ I d _ 2nd > [87T.K_Hm2_Inrush] × I d _ 1st

⎨I Equation 3.1-15
⎪⎩ d _ 3rd > [87T.K_Hm3_Inrush] × I d _ 1st
Where:
I d _ 2 nd and I d _ 3rd are the second and third harmonics of phase differential current
respectively.
I d _ 1st is the fundamental component of the differential current of the corresponding phase.
[87T.K_Hm2_Inrush] and [87T.K_Hm3_Inrush] are the setting values of restraint coefficient of

Date: 2011-10-19
3 Operation Theory
second and third harmonics respectively, [87T.K_Hm2_Inrush]=0.15 and [87T.K_Hm3_Inrush]=0.2

is recommended.
When an internal fault occurs and CT goes to stable saturation, there are great third harmonic
component in secondary current of CT. If the third harmonic criterion is used to block conventional
biased differential protection element, the protection element will be blocked by the criterion.
Therefore, the third harmonic criterion is not used to block conventional differential protection
element. Because sensitive biased differential protection element has too high sensitivity, the third
harmonic criterion is selectable to block sensitive biased differential element to prevent it from
maloperation.
Users can select the second harmonic ciriterion or wave distortaion criterion (see following section)
to distinguish inrush current, can also enable the third harmonic criterion to detect inrush current.
When [87T.Opt_Inrush_Indent] is set to 1, the second harmonic criterion is used as inrush blocking
function for both conventional and sensitive biased differential elements. If [En_Hm3_Inrush] is set
to 1, then the third harmonic criterion is used as inrush blocking function only for sensitive biased
differential element at the same time.
3.1.3.11.2 Distinguishing by Wave Distortion
The differential current is basically the fundamental sinusoidal wave during a fault. When the
transformer is energized plentiful harmonics will appear, and the waveform will be distorted,
interrupted and unsymmetrical. Wave symmetry principle is used to distinguish inrush current .
Wave symmetry principle: CT saturation characteristics make waveform unsymmetrical between

the first half cycle and the second half cycle. During internal faults, current waveform is sinusoidal
wave, so two half cycles of wave are almost symmetrical after aperiodic component is eliminated
(calculate the differential of differential current in fact). Then use described method to analyse the
sampling points of differential current waveform.
In the following figure, arc ABC is a cycle of typical waveform of differential current with aperiodic
component. Flip the arc BC of second half cycle vertically to get the arc B'C', and then move it
forward half cycle to get the arc B”C”.
There are some symbols are defined:
X: arc AB,
Y: arc B”C”
S+: are of X-Y
S-: are of X+Y
S+
K sym = : degree of symmetry of current wave
S−

Date: 2011-10-19
3 Operation Theory
Figure 3.1-7 Schematic of wave symmetry principle
For a differential current waveform, the area of X is almost equal to that of Y and the value of Ksym
is almost 0. For an unsymmetrical waveform, thee area of X is not equal to that of Y, so the value
of Ksym is great. Therefore, waveform of inrush current can be distinguished from the waveform of
internal fault according to the value of Ksym.
Wave symmetry principle and second harmonic principle are both based on current distortion of
inrush current, and the only difference is the mathematical method. The second harmonic principle
is to calculate the percentage of second harmonic in differential current, but the wave symmetry
principle is to calculate the percentage of even harmonic to total differential current.
If wave distortion of one phase is detected, the biased differential protection of this phase and only
this phase will be blocked.
When [87T.Opt_Inrush_Indent] is set to 0, the waveform distortion criterion is used as inrush

blocking function for both conventional and sensitive biased differential elements. If
[En_Hm3_Inrush] is set to 1, then the third harmonic criterion is used as inrush blocking function
only for sensitive biased differential element at the same time.
3.1.3.11.3 Inrush Blocking Mode
Users can select the inrush blocking mode of harmonic by the logic setting
[87T.Opt_BlkMode_Inrush]. When it is set to 0, above described self-adaptive blocking mode is
adopted, and when set to 1, the phase-to-phase crossing blocking mode is adopted. The
self-adaptive blocking mode is recommended to be selected in the actual application.
z Self-adaptive Blocking Mode
The equipment has an energizing detection element by current criterion (without additional
breaker position signal) for checking whether transformer is in the process of energization. Once
transformer in the process of energization is detected, following self-adaptive measures are
adopted to improve the stability to avoid mal-operation caused by inrush current.
1) Protection equipment automatically decreases the restraint coefficient values of harmonics

during the initial stage of transformer energization, and with the passage of time automatically
increases those values which shall be not greater than corresponding values of settings
[87T.K_Hm2_Inrush] and [87T.K_Hm3_Inrush]. This feature ensures biased differential
protection fast operation for transformer energized on to a fault in addition to the inrush

Date: 2011-10-19
3 Operation Theory
current blocking.
2) Protection equipment can be self-adaptive to enable the phase-to-phase crossing block mode
according to the comprehensive characteristics of three-phase differential current. If inrush
current is distinguished, equipment enables phase-to-phase crossing block mode for short
time, and then switches to phase-segregated blocking mode after a period.
3) If the Second harmonic percent of differential current used as auxiliary criteria continues to
rise, then biased differential protection is kept being blocked
z Phase-to-phase Crossing Blocking Mode
Only if two phases current is distinguished not inrush current, then differential protection of
corresponding two phases is released to operate.
z Comparison Between Different Blocking modes
Convention blocking mode is phase blocking mode (mode 3), and a list is give below to compare
operation of differential protection in following situations.
It is supposed that three differential currents are Ida, Idb, and Idc
Table 3.1-2 Comparison of different blocking modes
Mode 2:
Mode 1: Mode 3:
Harmonic of each phase-to-phase
Situation self-adaptive blocking Phase blocking
phase current crossing block
mode Mode
mode
Ida（great harmonic）
1 Idb（great harmonic） Diff prot not operate Diff prot not operate Diff prot not operate
Idc（great harmonic）
Ida（little harmonic）
2 Idb（little harmonic） Diff prot operate Diff prot operate Diff prot operate
Idc（little harmonic）
Ida（great harmonic） Diff prot may operate or
Idb（great harmonic） not according to
3 Diff prot not operate Diff prot not operate
differential current
waveform
Ida（great harmonic）
4 Idb（little harmonic） Diff prot operate Diff prot operate Diff prot not operate
From above list, it can be concluded that:
1) The blocking level of three blocking modes is increased one by one.
2) The difference between blocking mode 2 and 3 is the operation of differential protection in
situation 4. Differential protection will operate in the situation that greater harmonic in one phase
differential current but little harmonic in other two phases if blocking mode 2 selected, but
differential protection will not operate in the situation if blocking mode 3 selected. Situation 4 is

Date: 2011-10-19
3 Operation Theory
usually an internal fault, so blocking mode 2 can ensure differential protection operate correctly if
there is an internal fault in situation 4.
3) The difference between blocking mode1 and 2 is the operation of differential protection in
situation 3. Situation 3 may be an internal fault or inrush current, blocking mode 1 can distinguish
through its perfect criteria (refer to manual for details). Therefore, we recommend user use
blocking mode 1 i.e. self-adaptive blocking mode.
Users can select blocking mode 1 or blocking mode 2 in PCS-978 according to their requirements.
3.1.3.12 CT Saturation Detection
There are two CT saturation conditions, i.e. transient CT saturation and stable CT saturation. If an
external fault or an inter fault occurs, primary current of CT increases greatly and secondary
current of CT consists of fundamental component, DC component and harmonic component. The
decaying DC component results in remanent magnetism in magnetic core, and with the
accumulation of remanent magnetism CT goes into CT saturation state called transient CT
saturation. With the time passed, the DC component decays to zero almost and CT is still
saturated caused by AC excitation, which is called stable CT saturation.
According to our lab tests, it is found that the second harmonic component is greater than the third
harmonic component at CT transient saturation stage and the third harmonic is greater than the
secondary harmonic at the CT stable saturation stage. Therefore, the second and third harmonics
both can be used to detection CT saturation.
In order to prevent an unwanted operation of sensitive biased differential protection caused by

transient or steady state saturation of CT during an external fault, the second and third harmonics
of secondary current of individual CTs are used for the protection equipment to discriminate
saturation of three-phase CT. If CT saturation is detected, then sensitive biased differential
element will be blocked.
⎧⎪I Φ _ 2 nd > K Φsat _ 2 xb × I Φ _ 1st

⎨ (Equation 3.1-16)
⎪⎩I Φ _ 3rd > K Φsat _ 3 xb × I Φ _ 1st
Where:
I Φ _ 1st is the fundamental component of one phase current of some side.
I Φ _ 2nd is the secondary harmonic of the same phase current.
I Φ _ 3rd is the third harmonic of the same phase current.
K Φsat _ 2 xb , K Φsat _ 3 xb are fixed coefficients of secondary and third harmonics respectively.
If any harmonic of one phase current meets the above equation, it will be considered that it is CT
saturation to cause this phase differential current and sensitive percent differential element will be

Date: 2011-10-19
3 Operation Theory
blocked.
Internal faults can be distinguished from external faults by differential protection through the
asynchronous method of differential and restraint, and it is needed that the saturation free time of
CT is no less than 4ms for internal faults to ensure differential protection operate correctly with the
added CT saturation criterion.
3.1.3.13 Overexcitation Detection
When a transformer is overexcited, the exciting current will increase sharply which may result in
an unwanted operation of differential protection. Therefore the overexcitation shall be
discriminated to block differential protection. The third or fifth harmonic of differential current can
be selected to determinate overexcitation.
I d _ 3rd / 5th > [87T .K _ Hm3 / Hm5 _ OvExc] × I d _ 1st Equation 3.1-17
Where:
I d _ 1st is the fundamental component of differential current.
I d _ 3rd / 5th is the third or fifth harmonic of differential current.
[87T.K_Hm3/Hm5_OvExc] is the coefficient of third or fifth harmonic overexcitation detection and

the recommended value is 0.25.
If the logic setting [87T.Opt_Hm3/Hm5_OvExc] is set to 0, the 3rd harmonic is selected for
calculation, and if set to 1, 5th harmonic is selected. Correspondingly, the setting
[87T.K_Hm3/Hm5_OvExc] is to set 3rd or 5th harmonic coefficient. 5th harmonic is recommended to
be selected for overexcitation calculation.
Degree of overexcitation can is evaluated as follows:
n = U* / f* Equation 3.1-18
Where:
U * and f * are per unit value of voltage and frequency respectively.
The base value for calculating per unit value of voltage is rated secondary voltage value (phase
voltage) of the voltage transformer, and the base value for calculating per unit value of frequency
is rated frequency. During normal operation, n = 1.
If overexcitation factor is less than 1.4, biased differential protection is blocked when the constant
of 5th or 3rd harmonics is greater than [87T.K_Hm3/Hm5_OvExc] and this condition is judged as
overexcitation condition without damages to transformer. If overexcitation factor is greater than 1.4,
biased differential protection is no longer being blocked by overexcitation because transformer is
damaged in this situation.

Date: 2011-10-19
3 Operation Theory
3.1.3.14 CT Supervision for Differential Protection
3.1.3.14.1 CT Circuit Abnormality of Differential Protection
If the differential current in any phase is greater than the alarm setting [87T.I_Alm] without fault
detector of differential protection pickup for over 10s, differential current abnormality alarm
[87T.Alm_Diff] will be issued without blocking the protection.
3.1.3.14.2 CT Circuit Failure of Differential Protection
z Criteria
The following two cases are considered as CT circuit failure, and the protection relay can
discriminate which side the CT circuit failure by the unbalanced currents.
Differential CT secondary circuit failure can be judged more accurately and reliably by adopting
combined method of voltage and current.
1) First case, if none of following four conditions is satisfied after the fault detector of biased
differential current, or biased residual differential current, or biased winding differential current
picks up, it will be judged as CT circuit failure and CT circuit failure alarm will be issued.
¾ Negative-sequence voltage at any side is greater than 2%Upp (Upp is the secondary
phase-to-phase rated voltage).
¾ Any phase current of any side increases after fault detector picks up.
¾ The maximum phase current is greater than 1.1pu after the fault detector picks up.
¾ DPFC element of any phase-to-phase voltage of any side picks up.
2) Second case, if CT circuit abnormality of differential protection alarm (i.e. [87T.Alm_Diff]) is

issued and negative-sequence current of one side is greater than 0.2 times maximum phase
current of the corresponding side, and then CT circuit failure will be judged.
z Influence of CT circuit failure on differential protections
User can configure the output of CT circuit failure alarm to block transformer sensitive biased
differential protection, reactor sensitive biased differential protection, biased REF protection and
biased winding differential protection via logic settings [87T.En_CTS_Blk], [87R.En_CTS_Blk],
[64REF.En_CTS_Blk], and [87W.En_CTS_Blk] respectively. The CT circuit failure alarm is latched
once issued, it can be reset only after the failure is cleared and equipment is reset (i.e. the binary
input [BI_RstTarg] is energized).
1) Transformer conventional biased differential protection and instantaneous differential

protection are always not blocked during CT circuit failure.
2) Transformer DPFC biased differential relay is always blocked during CT circuit failure.
3) Transformer sensitive biased differential protection can be blocked when CT circuit failure is
detected by configuring the logic setting [87T.En_CTS_Blk].
¾ If this logic setting is set as “0”, transformer sensitive biased differential protection is not

Date: 2011-10-19
3 Operation Theory
blocked.
¾ If this logic setting is set as “1”, transformer sensitive biased differential protection is
blocked.
4) Reacotr sensitive biased differential protection can be blocked when CT circuit failure is
detected by configuring the logic setting [87R.En_CTS_Blk].
¾ If this logic setting is set as “0”, reactor sensitive biased differential protection is not
blocked.
¾ If this logic setting is set as “1”, reactor sensitive biased differential protection is blocked.
5) Biased REF protection can be blocked when CT circuit failure is detected by configuring the
logic setting [64REF.En_CTS_Blk].
¾ If this logic setting is set as “0”, biased REF protection is not blocked.
¾ If this logic setting is set as “1”, biased REF protection is blocked.
6) Biased winding differential protection can be blocked when CT circuit failure is detected by
configuring the logic setting [87W.En_CTS_Blk].
¾ If this logic setting is set as “0”, biased winding differential protection is not blocked.
¾ If this logic setting is set as “1”, biased winding differential protection is blocked.
NOTE！The operation time of biased differential protection with CT circuit failure being
distinguished has 50ms delay than that of biased differential protection without CT
circuit failure.
3.1.4 Logic
For current differential protection, when following three conditions are met the stage protection is
enabled.
(1) Logic setting [87T.En] is set to “1”.
(2) Enabling inputs [87T.En1], [87T .En2] are both set to “1”
(3) Blocking input [87T.Blk] is set to “0”.
When the protective function block is disabled, [87T.St], [87T.Op] signals are both reset. Default
values of Inputs [87T.En1] and [87T.En2] are “1” and [87T.Blk] is “0” when those inputs are not
connected to external signals or setting.

Date: 2011-10-19
3 Operation Theory
3.1.4.1 Logic of Current Differential Protection
U * / f*
Figure 3.1-8 Logic diagram of current differential protection
Where:
Idmax is the maximum value of three phase differential currents.
U * / f * is the value indicating the degree of overexcitation of transformer.
Flg_ConvBiasDiff is the internal flag indicating that operation criteria of conventional biased
differential protection are satisfied.
Flg_SensBiasDiff is the internal flag indicating that operation criteria of sensitive biased differential
protection are satisfied.
Flg_CTS is the internal flag indicating CT circuit failure is distinguished.
Flg_CTSaturation is the internal flag indicating CT saturated.

Date: 2011-10-19
3 Operation Theory
Flg_Inrush_ConvBiasDiff is the internal flag indicating inrush current is distinguished for

conventional biased differential protection.
Flg_Inrush_SensBIasDIff is the internal flag indicating inrush current is distinguished for sensitive
biased differential protection.
Flg_OvExc_Hm5/Hm3 is the internal flag indicating overexcitation of power transformer is

distinguished by the third or fifth harmonic or third harmonic criterion.
FD_InstDiff is the signal indicating that the fault detector of instantaneous differential protection
picks up.
FD_BiasDiff is the signal indicating that the fault detector of biased differential protection picks up.
NOTE! Detailed descriptions of three flags of inrush current in logic figures are given
below.
Internal flag Related Criterion
Second harmonic or wave distoration (alternative)
Flg_Inrush_SensBiasDiff
Third harmonic (selectable)
Flg_Inrush_ConvBiasDiff Second harmonic or wave distoration (alternative)
Flg_Inrush_DPFC_Diff Second harmonic or wave distoration (alternative)
3.1.4.2 Logic of DPFC Biased differential Protection
EN [87T.En_DPFC]
SIG [87T.En1] &
SIG [87T.En2] &
SIG [87T.Op_DPFC]
[87T.Blk]
SIG Flg_DPFC_Diff
SIG Flg_Inrush_DPFC_Diff
SIG Flg_CTS &
SIG Flg_OvExc_Hm3/Hm5 &
SIG U * / f * >1.4
SIG FD_DPFC_Diff 0ms 500ms
Figure 3.1-9 Logic diagram of DPFC biased differential protection
Where:
U * / f* is the value indicating the degree of overexcitation of transformer.
Flg_DPFC_Diff is the internal flag indicating that operation criteria of DPFC differential protection
are satisfied.
FD_DPFC_Diff is the signal indicating the fault detector of DPFC biased differential protection

Date: 2011-10-19
3 Operation Theory
picks up.
Flg_Inrush_DPFC_Diff is the internal flag indicating inrush current is distinguished for DPFC
Flg_OvExc_Hm3/Hm5 is the internal flag indicating overexcitation of power transformer is

distinguished by the third or fifth harmonic criterion
3.1.4.3 Logic of CT Circuit Failure
SIG U2>2%Upp
≥1
SIG Flg_DPFCVolt ≥1
SIG Flg_CurrIncrease
&
&
T 0ms
Flg_CTS
SIG Ipmax>1.1pu
SIG FD_BiasDiff
SIG Flg_CTS &

[x.AlmH_CTS]
SIG I2>0.04Ipmax or I2>0.1In
&
[87T.Alm_CTS]
Figure 3.1-10 Logic diagram of CT circuit failure
Where:
Upp is the secondary phase-to-phase rated voltage.
Flg_DPFCVolt is the internal flag indicating that DPFC element of any phase-to-phase voltage of
any side picks up
Flg_CurrIncrease is the internal flag indicating that Any phase current of any side increases after
fault detector picks up.
Ipmax>1.1pu represents that the maximum phase current is greater than 1.1pu after the fault
detector picks up.
Flg_CTS is the internal flag indicating that CT circuit failure is distinguished.
[x.AlmH_CTS] is the alarm signal of CT circuit failure of x side of transformer.
[87T.Alm_CTS] is the alarm signal of CT circuit failure for current differential protection. If CT
circuit failure for REF protection or winding differential protection is detected, the corresponding
signal [64REF.Alm_CTS] or [87W.Alm_CTS] will be issued.

Date: 2011-10-19
3 Operation Theory
3.1.5 Inputs and Outputs
87T
I3P1 St
I3P2 Op
I3P3 Op_Instant
I3P4 Op_Biased
I3P5 Op_DPFC
I3P6 Alm_Diff
En1 Alm_CTS
En2
Blk
Figure 3.1-11 87T function block
Table 3.1-3 Input signals of 87T function block
No. Signal Description

1 I3P1 Three-phase current data input 1
7 En1 Function enabling input1 and input 2, it can be binary inputs or settings, such as
8 En2 function enabling binary inputs, logic links, etc.
Function blocking input, such as function blocking binary input.
9 Blk
When the input is 1, the protection is not reset.
Table 3.1-4 Output signals of 87T function block

1 St Current differential protection starts.
2 Op Transformer current differential protection operates.
3 Op_Instant Instantaneous differential protection operates.
4 Op_Biased Biased differential protection operates.
5 Op_DPFC DPFC differential protection operates.
6 Alm_Diff Alarm message indicating CT secondary circuit of differential protection abnormal.
7 Alm_CTS Alarm message indicating that CT secondary circuit of differential protection fails.
Above input signals and output signals can be used for programmable logic, and following output
signals are only for LCD display of equipment and oscillograph function.
Table 3.1-5 Output signals of 87T: records
No. Output Signal Description
1 87T.Op_Instant Instantaneous differential protection operates.
2 87T.Op_Biased Biased differential protection operates.

Date: 2011-10-19
3 Operation Theory
3 87T.Op_DPFC DPFC differential protection operates.
Tripping reports of protection element.
4 87.St Current differential protection starts.
Start signals of protection element.
5 87T.Alm_Diff CT secondary circuit for current differential protection is abnormal.
6 87T.Alm_CTS CT secondary circuit for differential protection of fails.
Alarm reports of equipment operation.
7 87T.TrigDFR_Instant Instantaneous differential protection picks up to trigger DFR function.
8 87T.TrigDFR_Biased Biased differential protection picks up to trigger DFR function.
9 87T.TrigDFR_DPFC DPFC differential protection picks up to trigger DFR function.
Signals of protection element triggering DFR function recorded as IO events.
NOTE! DFR is disturbance and fault recording, also called oscillograph function.
Table 3.1-6 Output signals of 87T: measurements
No. Output Signal Description Unit
87T.Ida
1 87T.Idb Three phase differential current. pu
87T. Idc
87T.Ithra
2 87T.Ithrb Threshold f three phase restraint current. pu
87T.Ithrc
87T.Ida_Hm2_Pct
3 87T.Idb_Hm2_Pct Second harmonic percentage of total differential current. %
87T.Idc_Hm2_Pct
87T.Ida_Hm3_Pct
4 87T.Ida_Hm3_Pct Third harmonic percentage of total differential current. %
87T.Ida_Hm3_Pct
87T.Ida_Hm5_Pct
5 87T.Idb_Hm5_Pct Fifth harmonic percentage of total differential current. %
87T.Idc_Hm5_Pct
87T.Ia_Corr_Brm
Corrected values of three phase currents of branch (Br for
6 87T.Ib_Corr_Brm pu
abbreviation) m (m= 2, 3, 4, 5, 6) used for differential protection.
87T.Ic_Corr_Brm
87T.Ang(Ia)_Br1-Brm
Phase angles of corrected currents between branch 1 and branch m
7 87T.Ang(Ib)_Br1-Brm deg
(m= 2, 3, 4, 5, 6)
87T.Ang(Ic)_Br1-Brm

Date: 2011-10-19
3 Operation Theory
Rated primary/secondary current of branch m (m=1, 2, 3, 4, 5, 6) of

8 87T.Ib_Brn A
power transformer used for differential protection.
Path:
Main menu -> Measurements -> Measurements1-> Diff Measurements
3.1.6 Setting
Table 3.1-7 Setting list of 87T
No. Setting Item Range Step Unit Description
Current setting of knee point 1 of biased

1 87T.I_Knee1 0.1~1 0.001 pu
Current setting of knee point 2 of biased

2 87T.I_Knee2 4~8 0.001 pu
3 87T.I_Biased 0.05~5 0.001 pu Pickup setting of biased differential protection.
Current setting of unrestrained instantaneous

4 87T.I_Instant 0.05~20 0.001 pu
differential protection
5 87T.Slope1 0.1~0.9 0.001 Slope 1 of biased differential protection.
Coefficient of 2nd harmonics for inrush current

8 87T.K_Hm2_Inrush 0.05~0.3 0.001
detection.
Coefficient of 3rd harmonics for inrush current

9 87T.K_Hm3_Inrush 0.05~0.3 0.001
detection.
10 87T.I_Alm 0.05~1.5 0.001 pu Setting of differential current abnormality alarm.
Coefficient of 3rd or 5th harmonic for

11 87T.K_Hm3/Hm5_OvExc 0.05~0.3 0.001
overexcitation detection
0: disable Logic setting of enabling/disabling unrestrained

12 87T.En_Instant 1
1: enable instantaneous differential protection.
0: disable Logic setting of enabling/disabling conventional

13 87T.En_Biased 1
1: enable biased differential protection.
0: disable Logic setting of enabling/disabling DPFC current

14 87T.En_DPFC 1
1: enable differential protection.
Logic setting of selecting the method of

distinguishing inrush current:
15 87T.Opt_Inrush_Ident 0, 1 1
0: Waveform distortion principle
1: Harmonics principle
Logic setting of selecting blocking mode of

16 87T.Opt_BlkMode_Inrush 0, 1 1
inrush current

Date: 2011-10-19
3 Operation Theory
0: Self-adaptive blocking mode

1: Phase-to-phase crossing blocking mode
Logic setting of enabling/disabling the third

0: disable harmonic blocking function, i.e. enable/disable
17 87T.En_Hm3_Blk 1
1: enable the third harmonic criteria to distinguish inrush
current.
Logic setting of enabling/disabling blocking

0: disable
18 87T.En_CTS_Blk 1 biased differential protecting during CT circuit
1: enable
failure.
Logic setting of selecting 3rd or 5th harmonic for

87T.Opt_Hm3/Hm5_
19 0,1 1 overexcitation criterion.
OvExc
0: 3rd harmonic; 1: 5th harmonic
0000~ Tripping logic setting of current differential

20 87T.OutMap
FFFF protection.
[87T.OutMap]
The tripping logic setting is used to specify which breakers will be tripped when current differential
protection operates. This logic setting comprises 16 binary bits as follows and is expressed by a
hexadecimal number of 4 digits from 0000H to FFFFH. The tripping logic setting of the equipment
is specified as follows:
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TrpOutput16
TrpOutput15
TrpOutput14
TrpOutput13
TrpOutput12
TrpOutput11
TrpOutput10
TrpOutput09
TrpOutput08
TrpOutput07
TrpOutput06
TrpOutput05
TrpOutput04
TrpOutput03
TrpOutput02
TrpOutput01
Function
NOTE！“TrpOutput01” just means to drive 1st group of tripping output contacts to pickup
and please refer to Chapter “Hardware”. The tripping outputs are recorded as “T01~T16”
by the protection equipment when they operate, and “Txx” (xx=01, 02, …, 16) represents
“Tripoutputxx” (xx=01, 02, …, 16).
The bit corresponding to the breaker to be tripped shall be set as“1” and other bits shall be “0”.
For example, if differential protection operates to make “TrpOutput01”, “TrpOutput02”,
“TrpOutput03” contacts pickup, the bit “1” and bit “2” and bit “3” positions shall be filled with “1”
and other bit positions shall be filled with “0”. Then a hexadecimal number 0007H is formed as
the tripping output logic setting.
Tripping output logic settings of the equipment should be set on basis of application-specific
drawings.
NOTE! The logic setting [87T.OutMap] is shared by the unrestrained instantaneous

Date: 2011-10-19
3 Operation Theory
differential protection, biased differential protection and DPFC current differential

protection.
3.2 Reactor Current Differential Protection (87R)
3.2.1 Application
If an earth fault or phase-to-phase fault of reactor occurs, current differential protection can
operates quickly to clear the fault to avoid the reactor from damages or reduce the maintenance
cost as low as possible. Different to transformer current differential protection based on
electromagnetic balance, reactor current differential protection is based on Kirchhoff's law, so it is
needed to develop current differential protection according to the actual application of reactor not
only to use transformer current differential protection to protect reactors.
3.2.2 Function
z Reliable CT transient characteristic distinguishing method
During reactor energization, inrush current similar to that of transformer occurs. There is great
decaying DC component in inrush current, which may result in the difference of transient
transfer characteristics between CTs at two ends of reactor, and therefore differential current
occurs. Inrush current can be distinguished to avoid maloperation of current differential
protection by detecting harmonic of differential current and measured current and adopting
asynchronous method for recognition of CT saturation.
small internal fault current within the reactor. Its performance against current transformer
conventional differential elements as well as independent CT saturation criterion and
harmonic blocking.
be distinguished.
3.2.3.1 Overview
Reactor current differential protection consists of biased differential protection, unrestrained

instantaneous differential protection and DPFC biased differential protection. Biased differential
protection is two-slope differential protection with biased characteristic. Unrestrained differential
protection is to accelerate the operating speed for reactor’s severe internal faults without biased

Date: 2011-10-19
3 Operation Theory
characteristic and blocking elements. DPFC biased differential protection calculated by current
variation has high sensitivity to earth faults at ground end of reactor. Above three differential
protection elements work coordinately to form the high-speed current differential protection with
high sensitivity.
z Fault Detector of Biased Differential Current
The pickup of this fault detector will enable the biased differential protection, and its operation
equation is as follows.
I d > [87R.I_Biased] Equation 3.2-1
Where：
[87R.I_Biased] is the pickup current of biased differential protection.
z Fault Detector of Instantaneous Differential Protection
The pickup of this fault detector will enable the unrestrained instantaneous differential protection,
and its operation equation is as follows.
I d > 0.9x[87R.I_Instant] Equation 3.2-2
Where：
[87R.I_Instant] is the setting of the unrestrained instantaneous differential protection.
z Fault Detector of DPFC Differential Current
The pickup of this fault detector will enable the DPFC biased differential protection, and its
operation equation is as follows.

Equation 3.2-3
ΔI = ΔI& + ΔI&
d 1 2
Where:

Date: 2011-10-19
3 Operation Theory
I dth is fixed threshold in program. The sum value of ΔI dt and I dth is equal to 0.2pu.
ΔI&1 , ΔI&2 are the DPFC current of two ends of reactor representatively.
This fault detector, regardless of direction of power flow and very sensitive, is used to guard DPFC
biased differential protection. The setting is fixed in factory and thus site setting is not required.
During the normal operation, the magnitudes of secondary current of both ends of ractor are
different due to the mismatch between the CT ratios. The current value difference shall be
eliminated before calculation for current differential protection by amplitude compensation.
z Calculate rated primary current at each side
Sn
I1b = Equation 3.2-4
3U n
Where:
S n is the rated capacity of reactor (i.e. the setting [Sn] in “Systeme_Settings” menu).
U n is rated voltage of reactor. (i.e. the setting [Un] in “Systeme_Settings” menu).
I1b is rated primary current of reactor.
z Calculate rated secondary current at each end
I1b I
I 2b1 = , I 2b 2 = 1b Equation 3.2-5
CTLine CTNeu
Where:
I 2b1 , I 2b 2 are rated secondary current of two ends of reactor.
CTLine is the ratio of CT at the line side of reactor (also called CT1 hereinafter).
CTNeu is the ratio of CT at the neutral side of reactor (also called CT2 hereinafter).

Date: 2011-10-19
3 Operation Theory
z Correction Coefficients
Kph1=1
Kph2=(I1n_CT2)/(I2n_CT1) Equation 3.2-6
Kph2≤4
Where:
I1n_CT1 is the primary current of CT at the line side of reactor.
I1n_CT2 is the primary current of CT at the neutral side of reactor.
Kph1 is the correction coefficient of CT at the line side of reactor.
Kph2 is the correction coefficient of CT at the neutral side of reactor.
Line side of reactor is taken as reference side, so the correction coefficient of line side is 1 and that
of neutral side is equal to the ratio of primary current of CT2 to primary current of CT1. The
maximum ratio of two sides is 4. If the ratio is out of the limit, the relay will be blocked and an alarm
message [Alm_Setting] is issued.
When viewing settings and values of conventional current differential protection in the relay, user
will find the unit “pu” (per unit). The current in differential protection calculation is not actual
secondary value but per unit value which is got by actual secondary value of each side of reactor
divided by reactor secondary rated current of each branch (i.e. I 2b1, I 2b 2 ).
3.2.3.4 Calculations of Differential and Restraint Currents
⎡ I dA ⎤ ⎡ I A1⎤ ⎡ I A2 ⎤
⎢ ⎥ ⎢ ⎥ ⎢ ⎥
I
⎢ dB ⎥ = K × I
ph1 ⎢ B1⎥ 2b1/ I + K ×
ph2 ⎢ I B2 ⎥ / I 2b2
Equation 3.2-7
⎢⎣ I dC ⎥⎦ ⎢ I C1⎥ ⎢ I C 2⎥
1444 ⎣24⎦44 3 1444 ⎣24⎦443
1 2
⎧I dA = I ′ A1 + I ′ A2
⎪
⎨I dB = I ′ B1 + I ′ B 2 Equation 3.2-8
⎪
⎩I dC = I ′C1 + I ′C 2
Where:
I A1, I B1 , I C1 is the equation are vectors, the secondary current of line side of reactor.
I A2 , I B 2 , I C 2 is the equation are vectors, the secondary current of neutral side of reactor.
I ′ A1 , I ′ B1 , I ′ C1 is the corrected secondary current of line side of reactor.
I ′ A2 , I ′ B 2 , I ′ C 2 is the corrected secondary current of neutral side of reactor.
I dA , I dB , I dC are differential currents.

Date: 2011-10-19
3 Operation Theory
K ph1 , K ph 2 are corrected coefficients of line and neutral sides of reactor respectively.
I 2b11 , I 2b 2 are rated secondary values of CT at line side and CT at neutral side of reactor
respectively.
⎧ I rA = I ′ A2
⎪⎪
⎨ I rB = I ′B 2 Equation 3.2-9
⎪
⎪⎩ I rC = I ′C 2
Where:
I rA , I rB , I rC are restraint currents.
Current compensation process is shown in the flowing figure by taken 2-winding transformer with
three-phase CT inputs for an example. In an ideal situation, the differential current (i.e.
Id=I'_Line+I'_Neu) should be zero during the normal operation of the transformer or an external
fault occurring.
Figure 3.2-1 Current compensation calculation process
Where:
I_Line, I_Neu are primary currents of line and neutral sides of reactor respectively.
I'_Line, I'_Neu are secondary currents of line and neutral sides of reactor respectively.
I''_Line, I''_Neu are secondary corrected currents of line and neutral sides of reactor respectively.

Date: 2011-10-19
3 Operation Theory
CT1, CT2 are respectively current transformer at line side and that at neutral side.
K ph1 , K ph 2 are corrected coefficients of line and neutral sides of reactor respectively.
I 2b1 , I 2b2 are rated secondary values of CT at line side and CT at neutral side of reactor
respectively.
To clarify the situation, three important operation conditions with ideal and matched measurement
quantities are considered.
I’_Line flows into the protected zone, I’_Neu leaves the protected zone, i.e. is negative
according to the definition of signs in above figure, therefore I’_Line=–I’_Neu.
Moreover |I’_Line|=|I’_Neu|
Id=|I’_Line+I’_Neu|=|I’_Line–I’_Neu|=0;
Ir=|I’_Neu|)=|I’_Line|
No differential current (Id=0), restraint current (Ir) corresponds to double the through-flowing
current, and current differential protection does not operate.
2. Internal short-circuit，|I’_Line|<|I’_Neu|
The following applies I’_Neu=0.5xI’_Line
Id=|I’_Line+I’_Neu|=|I’_Line+0.5xI’_Line|=1.5x|I’_Line|;
Ir=|I’_Neu|=0.5x|I’_Line|
Differential current (Id) are three times of restraint current (Ir) and corresponding to the total
3.2.3.5 Sensitive Biased Differential Protection
The currents used in this section analysis and the following analysis have been corrected, that
means the currents for following calculation are the products of the actual secondary current of
each side multiplying its own correction coefficient
The sensitive biased differential protection with low pickup setting and restraint slope is much
more sensitive for a slight internal fault. Three blocking elements, CT saturation, CT circuit failure
(optional) have also been included for the protection in order to prevent it from the unwanted
operation during an external fault.

Date: 2011-10-19
3 Operation Theory
⎧I d > [87 R.I_Biased]

⎪
⎪I d > [87 R.Slope] × I r
⎪⎪ I r = I&2
⎨ Equation 3.2-10
⎪ 2
⎪I d
⎪
⎪⎩
= ∑ I&
i =1
i
Where:
I&1, I&2 are phase currents of line and neutral sides of reactor respectively.
I d is the differential current.
I r is the restraint current. In order to improve the sensitivity of differential protection, current of
neutral side is taken as restraint current. When an internal fault occurs, current partly flows into
ground through the short circuit point, so current at neutral side will decrease and therefore the
sensitivity of differential protection is improved.
[87R.I_Biased] is the pickup current of biased differential protection.
[87R.Slope] is the slope of biased differential protection. Recommended values: 0.2≤[87R.Slope]

≤0.75,
Operation characteristic of sensitive biased differential protection is shown below.

Date: 2011-10-19
3 Operation Theory
Id
[87R.I_Instant]
6
0.
K=
lo pe]
R.S
[8 7
1.2pu
[87R.I_Biased]
Restraint current
0 KP Ir
0.8pu
Figure 3.2-2 Operation characteristic curve of reactor sensitive biased differential protection
In above figure:
[87R.I_Instant] is the current setting of unrestrained instantaneously differential protection.
3.2.3.6 Conventional Biased Differential Protection
Conventional biased differential protection with higher setting and restraint coefficient comparing
with sensitive biased differential protection is blocked only by an inrush current detection.
Conventional biased differential protection provides fast operation for sever internal faults.
Operation criterion of this biased differential protection is:
⎧ I d > 1.2 pu I r ≤ 0.8 pu

⎨
⎩ I d > 0.6 × ( I r − 0.8 pu ) + 1.2 pu I r > 0.8 pu Equation 3.2-11
Where:
I d and I r have same definitions as mentioned above.
NOTE! Parameters of this protection have been fixed in the program and do not need to
be configured by user.
Operation characteristic of conventional biased differential protection is shown below.

Date: 2011-10-19
3 Operation Theory
Differential
current
d f
.
i ff
se o
ia rea
D
lb a
tia ing
en rat
nv pe
co O
Figure 3.2-3 Operation characteristic curve of reactor conventional biased differential protection
3.2.3.7 Unrestrained Instantaneous Differential Protection
Unrestrained instantaneous differential protection for reactor is to accelerate the operation speed
for reactor’s internal fault. The element has no blocking element but to guard that the setting must
be greater than the maximum unbalanced current caused by inrush current.
Unrestrained differential element shall operate to clear the fault when any phase differential
current is higher than its setting. Its operation criterion is:
I d >[87R.I_Instant] Equation 3.2-12
Where:
I d is the maximum value of three phase differential currents.
[87R.I_Instant] is the setting of the unrestrained instantaneous differential protection.
Please refer to Figure 3.1-6 for operation characteristic of instant differential protection.

Date: 2011-10-19
3 Operation Theory
3.2.3.8 Operation Characteristic Curve of Biased and Instant differential Protection
Figure 3.2-4 Operation characteristic curve of biased and instant differential protections for reactor
Where:
The value of K is not more than 1.
KP is keen point, and the value of it can be calculated by user after the slope setting is set.
A is the point shows normal operation of transformer.
D, E, and F are points show internal faults of transformer.
1) Sensitive biased differential protection element will send tripping signal monitored by criteria of
CT transient characteristic difference, and CT circuit failure (optional). It can ensure sensitivity
of protection and avoid the unwanted operation when CT is saturated during an external fault
or caused by inrush current. Its operation area is the tint shadow area in the figure above.
When a slight intern fault occurs, differential current rises not greatly and the operating point
moves from A to D into the tripping area of sensitive biased differential protection.
2) Conventional biased differential protection element will send tripping signal without blocking
criteria. It eliminates the influence of transient and steady saturations of CT during an external
fault and ensures reliable operation even if CT is in saturation condition during an internal fault
by means of its biased characteristic. Its operation area is the deeper shadow area in the
figure above.
When an internal fault occurs, differential current rises greatly and the operating point moves

Date: 2011-10-19
3 Operation Theory
to F in the tripping area of conventional biased differential protection.
3) Unrestrained instantaneous differential protection element will send tripping signal without any
blocking if differential current of any phase reaches its setting. Its operation area is over the
above two areas with the deepest dark shadow.
When a severe internal fault occurs, differential current rises sharply and the operating point
moves to F in the tripping area of instantaneous differential protection.
3.2.3.9 DPFC Biased Differential Protection Element
3.2.3.9.1 DPFC Concept
ΔI = I (k ) − I (k − 24)
DPFC (Deviation of Power Frequency Component) is the power frequency component of fault
component, which is the differential value between the sampling value at this time point and that at
a cycle before.
I ( k ) is the sampling value at the time point.
I (k − 24) is the sampling value at a cycle before, 24 is the sampling points in one cycle.
200
100
-100
-200
0 20 40 60 80 100 120
Original Current
100
50
-50
-100
0 20 40 60 80 100 120
DPFC current
Figure 3.2-5 Waveform of original current and DPFC current

Date: 2011-10-19
3 Operation Theory
From above figures, it is concluded that DPFC can reflect the sudden change of fault current at the
initial stage of a fault and has a perfect performance of fault detection.
DPFC (Deviation of Power Frequency Component) biased differential protection reflects variation
of load condition to perform a sensitive protection for the reactor. Lab tests show that it is more
sensitive than the biased differential relay under the heavy load condition.
The operation criteria of DPFC biased differential are as follows:
⎧ΔI d > 0.2 pu

⎪
⎪ΔI d > 1.25 × ΔI dt + I dth
⎨
⎪ΔI d > 0.6 × ΔI r ΔI r < 2 pu
⎪ΔI d > 0.75 × ΔI r − 0.3 pu ΔI r > 2 pu
⎩
Equation 3.2-13
2 2 2
ΔI r = max{ ∑k =1
ΔI&ak , ∑
k =1
ΔI&bk , ∑ ΔI&
k =1
ck }
ΔI d = ΔI&1 + ΔI&2
Where:
I dth is fixed threshold and need not use to configure it. The sum value of ΔI dt and I dth is
equal to 0.2pu.
ΔI&a1 ， ΔI&b1 ， ΔI&c1 is the DPFC current of line side of reactor.
ΔI&a 2 ， ΔI&b 2 ， ΔI&c 2 is the DPFC current of neutral side of reactor.
ΔI r is the DPFC restraint current, it is the maximum current among the restraint current of three
phases.

Date: 2011-10-19
3 Operation Theory
NOTE! Calculation of restraint current of DPFC biased differential protection is different to
the biased differential protection, it is difficult to test the characteristic at site, so we

recommend qualitative function test only at site.
Calculation of DPFC restraint current and differential current is phase-segregated. DPFC biased
differential protection is blocked by inrush current and CT circuit failure.
DPFC biased differential protection has the higher anti-CT saturation characteristic, the sensitivity
of which to slight inter-turn fault is maintained during normal operation of reactor.
z Advantages of DPFC differential protection
DPFC biased differential protection has the higher anti-CT saturation characteristic, the
sensitivity of which to faults with fault resistance and fault and faults close to neutral side is
maintained during normal operation of reactor. Floating threshold patent technology is adopted
to prevent maloperation of DPFC differential protection due to system frequency deviation,
external faults and CB tripping process.
The sensitivity of current differential protection is improved greatly when DPFC differential
protection enabled, especially in the situation faults with fault resistance and fault and faults
close to neutral side.
3.2.3.9.3 Fault Calculation Examples
During normal operation, Ia_Line=0.5A∠180°, Ib_Neu=0.5A∠180°
1) An external fault: I'a_Line’=2A∠180°, I'b_Neu=2A∠180°, other phase supposed zero
Id=|I'a_Line+I'b_Neu|=|2A∠180°+2A∠180°|=0A
Ir=|I'b_Neu|=|2A∠180°|=2A
ΔId=|(I'a_Line-Ia_Line)+(I'b_Neu-Ib_Neu)|
=|(2A∠0°-0.5A∠0°)+(2A∠180°-0.5A∠180°)|=0A
ΔIr=Max(|I'a_Line-Ia_Line|, |I'b_Neu-Ib_Neu|)
=Max(|2A∠0°-0.5A∠0°|,| 2A∠180°-0.5A∠180°|)=1.5A
Conclusion: DPFC differential protection does not operate during an external fault.
2) A sight turn-to-ground fault: I'a_Line=1.1A∠0°, I'b_Neu=0.7A∠180°, other phase supposed

zero
Id=|I'a_Line+I'b_Neu|=|1.1A∠0°+0.7A∠180°|=0.3A

Date: 2011-10-19
3 Operation Theory
Ir=|I'b_Neu|=0.7A
ΔId=|(I'a_Line-Ia_Line)+(I'b_Line-Ib_Neu)|
=|(1.1A∠0°-0.5A∠0°)+(0.7A∠180°-0.5A∠180°)|=0.4A
ΔIr= Max(|I'a_Line-Ia_Line|, |I'b_Neu-Ib_Neu|)
=Max(|1.1A(∠0°-0.5A∠0°|,|0.7A∠180°-0.5A∠180°|)=0.6A
Conclusion: DPFC differential protection is more sensitive than biased differential protection
during an internal fault.
3.2.3.9.4 Operation Characteristic

m
K=
Figure 3.2-6 Operating characteristic curve of reactor DPFC biased differential protection
In above figure:
The value of m is not greater than 1. For the phase with maximum restraint current, m is equal to 1,
and for other phases, m is less than 1.
During reactor energization or a system disturbance, decaying DC component is caused because

magnetic flux of reactor can not change suddenly. The decaying DC component will result in
transient CT saturation and differential current occurs correspondingly. CT saturation should be
detected and block reactor differential protection to prevent it from from maloperation during this
situation.
There are two methods adopted to distinguish CT saturation: harmonic criterion and asynchronous

Date: 2011-10-19
3 Operation Theory
method for the recognition of current transformer saturation. If any phase differential current is
caused by CT saturation, the sensitive biased differential element will be blocked. Once an internal
fault is distinguished by asynchronous method, harmonic criterion is not used to judge CT
saturation any more.
3.2.3.10.1 Asynchronous Method for the Recognition of CT saturation
Decaying DC current caused by a fault or a system disturbance will result in CT saturation, and
there is a period before CT goes to saturation. At the initial stage, CT can transmit current correctly,
after a while, CT goes to saturation state. Therefore:
1) When an external fault occurs, at the initial stage CT not statured, the differential current is
almost zero and the restraint current increases greatly. After a while, CT goes to saturation and
the differential current begins to increase.
2) When an internal fault occurs, at the initial stage CT not saturated, the differential current and
the restraint current both increases greatly
It is concluded that the internal fault can be distinguished from external faults at the initial stage of
the fault according to the sequential relationship of differential current and restraint current
increasing. This is the basic principle of asynchronous method.
3.2.3.10.2 Harmonic Criterion
If the following criterion is satisfied, then sensitive biased differential element will be blocked.
If any harmonic of one phase current meets the following equation, it will be considered that the
phase differential current is caused by the difference between CT transient characteristics, and
sensitive percent differential element will be blocked.
⎧⎪ I Φ _ 2nd > [87R.K_Hm2] × I Φ _ 1st

⎨I Equation 3.2-14
⎪⎩ Φ _ 3rd > [87R.K_Hm3] × I Φ _ 1st
Where:
I Φ _ 1st is the fundamental component of one phase current of one side.
I Φ _ 2nd is the secondary harmonic of the same phase current.
I Φ _ 3rd is the third harmonic of the same phase current.
[87R.K_Hm2], [87R.K_Hm3] are coefficients of secondary and third harmonics respectively, and
generally [87R.K_Hm2]=0.15, [87R.K_Hm3]=0.2.
3.2.3.11 CT Supervision for Differential Protection
3.2.3.11.1 CT Circuit Abnormality of Differential Protection
If the differential current in any phase is greater than the alarm setting [87R.I_Alm] without fault

Date: 2011-10-19
3 Operation Theory
[87R.Alm_Diff] will be issued without blocking the protection.
3.2.3.11.2 CT Circuit Failure for Differential Protection
Please refer to Section 3.1.3.14.2 for details.
3.2.4 Logic
For current differential protection, when following three conditions are met the protection is
enabled.
(1) Logic setting [87R.En] is set to “1”.
(2) Enabling inputs [87R.En1], [87T .En2] are both set to “1”
(3) Blocking input [87R.Blk] is set to “0”.
When the protective function block is disabled, [87R.St], [87R.Op] signals are both reset. Default
values of Inputs [87R.En1] and [87R.En2] are “1” and [87R.Blk] is “0” when those inputs are not
3.2.4.1 Logic of Current Differential Protection
EN [87R.En_Instant]
SIG [87R.En1] &
&
SIG [87R.En2]
[87R.Op_Instant]
SIG [87R.Blk]
SIG Idmax>[87R.I_Instant]
0ms 500ms
SIG FD_InstDiff
EN [87R.En_Biased]
SIG [87R.En1] &
SIG &
[87R.En2]
SIG [87R.Blk]
SIG Flg_ConvBiasDiff
0ms 500ms
SIG FD_BiasDiff
≥1
[87R.Op_Biased]
EN [87R.En_Biased]
SIG [87R.En1] &
SIG [87R.En2]
SIG [87R.Blk]
&
SIG Flg_SensBiasDiff
SIG Flg_CT_Sat &
SIG Flg_CTS &
SET [87R.En_CTS_Blk]
SIG FD_BiasDiff 0ms 500ms
Figure 3.2-7 Logic diagram of reactor current differential protection

Date: 2011-10-19
3 Operation Theory
Where：
Idmax is the maximum value of three phase differential currents.
Flg_ConvBiasDiff is the internal flag indicating that operation criteria of conventional biased
differential protection are satisfied.
Flg_SensBiasDiff is the internal flag indicating that operation criteria of sensitive biased differential
protection are satisfied.
Flg_CT_Satu is the internal flag indicating CT saturation is detected.
FD_InstDiff is the signal indicating that the fault detector of instantaneous differential protection
picks up.
3.2.4.2 Logic of DPFC Biased differential Protection
Figure 3.2-8 Logic diagram of DPFC biased differential protection
Where:
Flg _DPFC_Diff is the internal flag indicating that operation criteria of DPFC differential protection
are satisfied.
FD_DPFC_Diff is the signal indicating the fault detector of DPFC biased differential protection
picks up.
Flg_Hm2&Hm3 is the internal flag indicating harmonic criteria is met.
Flg_Asynchr_CTSat the internal flag indicating asynchronous method detects CT saturation.

Date: 2011-10-19
3 Operation Theory
Figure 3.2-9 87R function block
Table 3.2-1 Input signals of 87R function block

3 En1 Function enabling input1 and input 2, it can be binary inputs or settings, such
4 En2 as function enabling binary inputs, logic links, etc.
5 Blk
Table 3.2-2 Output signals of 87R function block

1 St Current differential protection starts.
Alarm message indicating that CT secondary circuit of differential protection
2 Alm_CTS
fails.
Alarm message indicating CT secondary circuit of differential protection
3 Alm_Diff
abnormal.
4 Op_Instant Instantaneous differential protection operates.
5 Op_Biased Biased differential protection operates.
6 Op_DPFC DPFC differential protection operates.
Table 3.2-3 Output signals of 87R: records
1 87R.Op_Instant Instantaneous differential protection operates.
2 87R.Op_Biased Biased differential protection operates.
3 87R.Op_DPFC DPFC differential protection operates.

Date: 2011-10-19
3 Operation Theory
4 87R.St Current differential protection starts.
5 87R.Alm_Diff CT secondary circuit for current differential protection is abnormal.
6 87T.Alm_CTS CT secondary circuit for differential protection of fails.
7 87R.TrigDFR_Instant Instantaneous differential protection picks up to trigger DFR function.
8 87R.TrigDFR_Biased Biased differential protection picks up to trigger DFR function.
9 87R.TrigDFR_DPFC DPFC differential protection picks up to trigger DFR function.
NOTE! DFR is disturbance and fault recording, also called oscillograph function.
Table 3.2-4 Output signals of 87T: measurements
Ia_Corr_L pu
Corrected values of three phase currents of CT at line side
Ib_Corr_L pu
1 used for differential protection.
Ic_Corr_L pu
I0_Corr_L Corrected values of calculated residual current at Line side
2 Ia_Corr_N pu
Corrected values of three phase currents of CT at neutral side
3 Ib_Corr_N pu
used for differential protection.
4 Ic_Corr_N pu
5 I0_Corr_N Corrected values of calculated residual current at neutral side
Rated secondary current of CT at line side used for differential

6 I2b_ Diff_L A
protection.
Rated secondary current of CT at neutral side used for

7 I2b_ Diff_N
8 Ang(Ia)_L-N
9 Ang(Ib)_ L-N Phase angles of corrected currents between CT at line side deg
10 Ang(Ic)_ L-N and CT at neutral side.
11 Ang(I0)_ L-N
12 Ida, Idb, Idc,Id0 Three-phase differential current value. pu
Ithra, Ithrb, Ithrc,

13 Threshold value of restraint current. pu
Ithr0
Ida_Hm2_Pct
14 Second harmonic percentage of total differential current. %
Idb_Hm2_Pct

Date: 2011-10-19
3 Operation Theory
Idc_Hm2_Pct
Ida_Hm3_Pct
15 Ida_Hm3_Pct Third harmonic percentage of total differential current. %
Ida_Hm3_Pct
Path:
3.2.6 Setting
Table 3.2-5 Setting list of 87R
1 87R.I_Biased 0.05~5 0.001 pu Pickup setting of biased differential protection.
Current setting of unrestrained instantaneous

2 87R.I_Instant 0.05~20 0.001 pu
3 87R.Slope 0.1~0.9 0.001 Slope of biase differential protection.
Coefficient of 2nd harmonics for CT

4 87R.K_Hm2 0.05~0.3 0.001
saturation detection.
Coefficient of 3rd harmonics for CT

5 87R.K_Hm3 0.05~0.3 0.001
saturation detection.
Setting of differential current abnormality

6 87R.I_Alm 0.1~1.5 0.001 pu
alarm.
Logic setting of enabling/disabling

0: disable
7 87R.En_Instant 1 unrestrained instantaneous differential
1: enable
protection.
0: disable Logic setting of enabling/disabling

8 87R.En_Biased 1
1: enable conventional biased differential protection.
0: disable Logic setting of enabling/disabling DPFC

9 87R.En_DPFC 1
1: enable current differential protection.
Logic setting of enabling/disabling blocking

0: disable
10 87R.En_CTS_Blk 1 biased differential protecting during CT
1: enable
circuit failure.
Tripping logic setting of current differential

11 87R.OutMap 0000~FFFF
protection.
NOTE! The logic setting [87R.OutMap] is shared by the unrestrained instantaneous
differential protection, biased differential protection and DPFC current differential

protection.

Date: 2011-10-19
3 Operation Theory
3.3 Restricted Earth Fault Protection (64REF)
3.3.1 Application
The Restricted Earth Fault (REF) protection is meant to protect a single winding of a power
transformer. The winding which should be protected must be earthed. In the case of delta windings,
the winding must be earthed by an earthing transformer, which must be electrically placed
between the winding and the current transformers.
REF protection is a kind of differential protection, so it calculates differential current and bias
current. The differential current is a vectorial difference of the neutral current (i.e. current flowing in
the neutral conductor) and the residual current from the lines. For internal faults, this difference is
equal to the total earth fault current. REF protection operates on the fault current only, and is not
dependent on eventual load currents. This makes REF protection a very sensitive protection.
REF protection can be applied to protection of two-winding transformer, three-winding transformer
or auto-transformer.
3.3.2 Function
z Maximum 4 group CT and 1 neutral CT inputs for REF protection, and the maximum current
inputs applied for an auto-transformer with two circuit breakers at HV and MV sides
respectively.
z Maximum 3 REF protections for each side of a three-winding transformer
z Inrush current has no effect on REF protection.
z RFE protection has high sensitivity to internal earth faults because there is no load current in
the restraint current.
z The tap of transformer has no effect on REF protection.
adopted to eliminate the influence of difference of transient characteristic to REF protection.
maloperation of REF protection during an external fault.
3.3.3.1 Overview
The difference between current differential protection and restricted earth fault protection is that
the first one is based on adjusted phase current balance and the later is based on balance of
calculated residual current and residual current from neutral CT.
Three phase currents and neutral current are the inputs to the restricted earth fault protection of a
three-phase winding. Polarity of three-phase CT is at busbar side, and that of neutral CT is at
transformer side as shown in the following figure.

Date: 2011-10-19
3 Operation Theory
DANGER! Before REF protection of a side is put into operation on site, polarity of neutral
CT must have been checked by a primary injection test. Otherwise a maloperation may
occur during an external earth fault.
* * *
Figure 3.3-1 REF application 1 for two-winding transformer with one CB at one side
Figure 3.3-2 REF application 2 for two-winding transformer with two CBs at one side

Date: 2011-10-19
3 Operation Theory
HV side
* * *
I_H
I_M
* * *
MV side
3I0Cal'_H
CW side
3I0Cal'_M
*
Magnitude I_CW
compensation HV side REF LV
Protection side
Magnitude
compensation
Magnitude I'_CW
compensation
Figure 3.3-3 REF typical application 3 for auto-transformer
In above figures：
I_H, I_H1, I_H2 and I_M are primary values of each side of transformer.
I_HNP is primary value of neutral current of HV side.
I_CW is primary value of common winding neutral CT.
I'_HNP and I'_CW are respectively secondary value of neutral current of HV side and common
winding neutral CT.
3I0Cal'_H, 3I0Cal'_H1, 3I0Cal'_H2, 3I0Cal’_M are respectively secondary values of calculated

residual current from three-phase current of each side of transformer.
The criterion of fault detector of restricted earth fault protection is as follows. The pickup of this
fault detector will enable restricted earth fault protection of the corresponding side.
I 0 d >[64REF.I_Biased] Equation 3.3-1
Where:
I 0 d is the residual differential current of some side.
[64REF.I_Biased] is the setting threshold of REF protection of the corresponding side.

Date: 2011-10-19
3 Operation Theory
If CTs used for REF have different primary rated values, the equipment will automatically adjust
the currents with respective correction ratio shown as below.
I1n I1n _ max

K lph = × K lb and K lb = min( ,4) Equation 3.3-2
I1n _ max I1n _ min
Where:
K lph is the correction coefficient of the calculated side.
I1n is the primary value of CT at calculated side.
I1n _ min is the minimum value among primary values of all CTs for REF protection.
I1n _ max is the maximum value among primary values of all CTs for REF protection.
This calculation method is to take the minimum CT primary rating of all calculated sides as the
reference side. If the multiple of the maximum CT primary ratio to the minimum CT primary rating
is greater than 4, then reference side shall be taken as 4 and other sides shall be calculated
proportionally. Otherwise, the reference side shall be taken as 1, and other sides will be calculated
proportionally.
The currents used in the following analysis have been corrected, that means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient ( K lph ).
3.3.3.4 Calculations of Differential and Restraint Current
The equation of calculating residual differential current is as follows.
I0d = Klph1× I01/ I2n _ CT1 + Klph2 × I02 / I2n _ CT2 + Klph3× I03/ I2n _ CT3 + Klph4 × I04 / I2n _ CT4 − KlphNP× INP/ I2n _ CTNP
144424443 1444 424444 3 1444 424444 3 1444 424444 3 14444244443
1 2 3 4 5
Equation 3.3-3
′ + I 02
I 0d = I 01 ′ + I 04
′ + I 03 ′ − I ′NP Equation 3.3-4
Where:
I 0d is the residual differential current.
I 01 , I 02 , I 03 , I 04 are secondary values of calculated residual current of each branch.

Date: 2011-10-19
3 Operation Theory
I NP is secondary current of neutral CT.
′ are secondary values of corrected calculated residual current of each branch.

I ′01 , I ′02 , I ′03 , I 04
I ′ NP is the secondary corrected current from neutral CT.
Klph1, Klph 2 , Klph3 , Klph 4 are corrected coefficients of each branch of amplitude compensation
respectively.
K lphNP is corrected coefficient of neutral CT.
I 2 n _ CT 1, I 2 n _ CT 2 , I 2 n _ CT 3 , I 2 n _ CT 4 are rated secondary values of CTs of each branch.
I 2 n _ CTNP is the rated secondary value of neutral CT.
NOTE! Because the polarity of neutral CT is at transformer side, current from neutral CT is
subtracted in the differential current calculation.
The equation of calculating residual restraint current is:
′ , I 02
I 0 r = max{ I 01 ′ , I 04
′ , I 03 ′ , I 0′ NP } Equation 3.3-5
Where:
I 0r is the residual restraint current.
The earth fault differential protection compares the fundamental wave of the current flowing in the
starpoint connection, which is designated as I’_NP in the following, with fundamental wave of the
sum of the phase currents, which should be designated as 3I0Cal’ shown in the following figure.
Ia
A
Ib
B
Ic
C
I_NP
3I0Cal' =I'c+I'b+I'a
PCS-978 REF
I'_NP
Figure 3.3-4 Principle of restricted earth fault protection

Date: 2011-10-19
3 Operation Theory
I_NP’ flows into the protected zone from ground, 3I0Cal’ leaves the protected zone, i.e. is
positive according to the definition of signs in above figure, therefore I_NP’= 3I0Cal’.
I0d=|3I0Cal’–I_NP’|= |3I0Cal’– 3I0Cal’|=0;
I0r=Max(|3I0Cal’|,|I_NP’|)=Max(|3I0Cal’|+|3I0Cal’|)=|3I0Cal’|
No differential current (I0d=0), restraint current (I0r) corresponds to double the

through-flowing current, and restricted earth fault protection does not operate.
2. Internal short-circuit:
The following applies I_NP’=–3I0Cal’, moreover | I_NP’|=|3I0Cal’|
I0d=|3I0Cal’- I_NP’|=|3I0Cal’ –(–3I0Cal’)|=2x|3I0Cal’|;
I0r=Max(|3I0Cal’|,|I_HNP)=Max(|3I0Cal’|,|3I0Cal’|)=|3I0Cal’|
Differential current (0Id) are two times of restraint current (I0r) and corresponding to the total
fault, and restricted earth fault protection operates.
3.3.3.5 Operation Criterion
The operation criteria of REF protection are as follows:
⎧ I 0d > [64REF.I_Biased] I 0r ≤ [64 REF .I _ Knee]

⎪
I
⎪ 0d > [64REF.Slop e ] × (I 0r − [ 64 REF . I _ Knee ]) + [64REF.I_Biased ]
⎨ I = max{ I , I , I , I , I
⎪ 0r 01 02 03 04 0 NP }
⎪ I 0d = I&01 + I&02 + I&03 + I&04 + I&0 NP
⎩
Equation 3.3-6
Where:
I 0d is the REF differential current of one side.
I 0r is the residual restraint current of the corresponding side.
I 01 , I 02 , I 03 , I 04 are the calculated residual currents of the corresponding side.
I 0 NP is the current from neutral CT.
[64REF.I_Biased] is the pickup value of biased REF protection.
[64REF.I_Knee] is the setting of knee point of biased REF protection, and 0.5In is recommended.
[64REF.Slope_Biased] is the percent restraint coefficient of biased REF protection and 0.5 is
recommended.

Date: 2011-10-19
3 Operation Theory
3.3.3.6 Operation Characteristic Curve
Operation characteristic of restricted earth fault protection is showed in the following figure.
I0d
diiferential current
m
K=
[64REF.Slope]
[64REF.I_Biased]
restraint current I0r
[64REF.I_Knee]
Figure 3.3-5 Operating characteristic of REF protection
Where:
The value of m is defined by the branch number for REF protection calculation. For example, there
are two branches at HV side (wye winding with neutral point earthed), so there are three branches
constitute the REF protection of HV side and m is equal to 3.
3.3.3.7 Detection of CT Transient Characteristic Difference
Non-identical CT characteristics can cause unbalance current. During phase-to-phase faults and
three-phase faults, the unbalance of three-phase CTs results in residual current which may lead
to maloperation of RFE protection. Therefore, positive sequence current restraint blocking criterion
is adopted to prevent maloperation of REF protection in above mentioned conditions.
When the residual current of each side REF protection is greater than β0 times positive sequence
current, it is decided that zero-sequence current is caused by a fault and release REF protection.
Positive sequence current restraint blocking criterion is showed below.
I 0 > β0 × I1 Equation 3.3-7
Where:
I 0 is the zero-sequence current at a side.
I 1 is its corresponding positive sequence current.

Date: 2011-10-19
3 Operation Theory
β 0 is a proportional constant and the value is 0.6
The CT saturation detection principle of REF protection is the same to that of current differential
protection, and please refer to Section 3.1.3.12 for details.
3.3.3.9 CT Supervision for REF Protection
The CT supervision for REF protection is divided into two kinds: REF differential CT circuit
abnormality without the pickup of the fault detector of REF protection and differential CT circuit
failure with the pickup of the fault detector pickup.
3.3.3.9.1 CT Circuit Abnormality of REF Protection
If the following operation formula is met for 10s, CT circuit abnormality alarm of REF protection will
be issued without blocking the protection.
The operation formula is as follows:
I 0d > Max(0.2 × [64REF.I_B iased],0.1I n ) Equation 3.3-8
Where:
I 0d , I n and [64REF.I_Biased] have same definitions as mentioned above.
3.3.3.9.2 CT Circuit Failure of REF Protection
3.3.4 Logic
The logic diagram of REF protection of HV side is taken as example to show below.

Date: 2011-10-19
3 Operation Theory
EN HVS.[64REF.En]
SIG HVS.[64REF.En1] &
SIG HVS.[64REF.En2]
SIG HVS.[64REF.Blk]
SIG Flg_REF_HVS
SIG Flg_I1_Restraint
SIG Flg_CTSaturation & &

[64REF.t_Op] 0ms
[HVS.64REF.Op]
SIG Flg_CTS &
SIG HVS.[64REF.En_CTS_Blk]
SIG 3I0Ext_H>0.04In ≥1
SET [HVS.64REF.En_NeuCurr
0ms 500ms
SIG FD_REF_HVS
Figure 3.3-6 Logic diagram of winding differential protection
Where:
Flg_REF_HVS is the internal flag indicating that operation criterion of REF protection of HV side
is satisfied.
Flg_I1_Restraint is the internal flag indicating that difference of CT transient characteristic is

detected.
3I0Ext_H is the measured residual current of HV side.
FD_REF_HVS is the signal indicating that the fault detector of REF protection of HV side picks up.
For restricted earth fault protection, when following three conditions are met the stage protection is
enabled.
(1) Logic setting [x.64REF.En] is set to “1”.
(2) Enabling inputs [x.64REF.En1], [x.64REF.En2] are both set to “1”
(3) Blocking input [x.64REF.Blk] is set to “0”.
When the protective function block is disabled, [x.64REF.St], [x.64REF.Op] signals are both reset.
Default values of Inputs [x.64REF.En1] and [x.64REF.En2] are “1” and [x.64REF.Blk] is “0” when
those inputs are not connected to external signals or setting.

Date: 2011-10-19
3 Operation Theory
64REF
I3P1 St
I3P2 Op
I3P3 Alm_Diff
I3P4 Alm_CTS
I1P
En1
En2
Blk
Figure 3.3-7 64REF function block
Table 3.3-1 Input signals of 64REF function block

5 I1P Residual current data input
6 En1 Function enabling input1 and input 2, it can be binary inputs or settings, such as function
7 En2 enabling binary inputs, logic links, etc.
8 Blk
When the input is 1, the protection is not reset and time delay is cleared.
Table 3.3-2 Output signals of 64REF function block

1 St Restricted earth fault protection starts.
2 Op Restricted earth fault protection operates.
Alarm message indicating CT secondary circuit of restricted earth fault protection
3 Alm_Diff
abnormal
4 Alm_CTS Alarm message indicating that CT secondary circuit of differential protection fails
NOTE! Symbol ”x” represents some side of transformer defined by user through
PCS-PC software, which may be “H”, “HV” “HVS”, “HVS1”,” HVS2”, etc. If only one
protection element is equipped, the prefix “x.” may disappear.
Table 3.3-3 Output signals of 64REF: report

Date: 2011-10-19
3 Operation Theory
1 x.64REF.Op Restricted earth fault protection of x side operates.
2 x.64REF.St Restricted earth fault protection of x side starts.
3 x.64REF.Alm_Diff CT secondary circuit for restricted earth fault protection of x side is abnormal.
4 x.64REF.Alm_CTS CT secondary circuit for restricted earth fault protection of x side fails.
5 x.64REF.TrigDFR DPFC differential protection of x side picks up to trigger DFR function..
Table 3.3-4 Output signals of 64REF: measurements
1 x.64REF.I0d Residual differential current of x side REF protection. In
2 x.64REF.I0thr Residual threshold current of x side REF protection. In
Corrected value of calculated residual current of x side branch m In

3 x.64REF.I0_Corr_Brm
(m=1, 2, 3, 4,).
4 x.64REF.I0_Corr_Neu Corrected value of current from neutral CT of x side. In
Angle of calculated residual current between x side branch 1 and deg

5 x.64REF.Ang(3I0)_Br1-Brm
branch m(m=2, 3, 4,).
Angle between calculated residual current of HV side branch 1 and deg

6 x.64REF.Ang(3I0)_Br1-Neu
current from neutral CT of x side.
Corrected coefficient of current of HV side branch m (m=1, 2, 3, 4)

7 x.64REF.K_Brm
for REF protection of x side.
Corrected coefficient of current from neutral CT for REF protection of

8 x. 64REF.K_Neu
x side.
Path:
Main menu -> Measurements -> Measurements1-> REF Measurements
Main menu -> Measurements -> Measurements2-> REF Measurements
3.3.6 Setting
Table 3.3-5 Settings of 64REF of each side
1 x.64REF.I_Knee 0.1~4 0.001 In Knee point setting of biased REF protection.
2 x.64REF.I_Biased 0.05~5 0.001 In Pickup setting of biased REF protection
Percentage restraint coefficient of biased REF

3 x.64REF.Slope 0.2~0.75 0.001
protection
4 x.64REF.t_Op 0~20s 0.001 s Time delay for REF protection. Recommended value

Date: 2011-10-19
3 Operation Theory
is zero.
0: disable Logic setting of enabling/disabling blocking REF

5 x.64REF.En_CTS_Blk 1
1: enable protection during CT circuit failure
0: disable Logic setting of enabling/disabling neutral current

6 x.64REF.En_NeuCurr 1
1: enable criterion.
0: disable
7 x.64REF.En 1 Logic setting of enabling/disabling REF protection.
1: enable
8 x.64REF.OutMap 0000~FFFF Tripping logic setting of REF protection
3.4 Winding Differential Protection (87W/87N)
3.4.1 Application
When each side and common winding of auto-transformer are installed with three phase CTs,
winding differential protection can be equipped. Winding differential protection is based on
Kirchhoff's law, so inrush current has no effect on it. Winding differential protection consists of
phase winding differential protection and residual winding differential protection. Residual winding
differential protection adopts the calculated residual current of each side and common winding for
the protection calculation and three-phase CT polarity is easy to be checked. The operation
principle of which is similar to that of REF protection, but compared to REF protection, winding
differential protection can operate not only during internal earth faults but also during
phase-to-phase faults.
3.4.2 Function
z Maximum 5 group CT inputs applied for an auto-transformer with two circuit breakers at HV
and MV sides respectively.
z Maximum 3 winding differential protections for each side of a three-winding transformer
z Inrush current has no effect on winding differential protection.
z Winding differential protection has high sensitivity to internal earth faults because there is no
load current in the restraint current.
z The tap of transformer has no effect on winding differential protection.
adopted to eliminate the influence of difference of transient characteristic to winding
maloperation of winding differential protection during an external fault.

Date: 2011-10-19
3 Operation Theory

3.4.3.1 Overview
Winding differential protection is based on Kirchhoff's first law and calculates differential currents
of electrical connection circuits including phase A, phase B phase C and residual differential
currents. Normally, winding differential protection is applied in following two situations.
HV side
* * *
I_H
I_M
MV side
* * *
I'_H
CW side
I'_M
Magnitude Winding I_C

compensation LV
differential * * *
Magnitude protection side
compensation
Magnitude I'_CW
compensation
Figure 3.4-1 Winding differential protection applied to auto-transformer

* * *
Figure 3.4-2 Winding differential protection used as stub differential protection
In above figures:
I_H, I_H1, I_H2 and I_M are primary values of current of each side of transformer respectively.
I_CW is primary value of common winding three-phase CT
I_HBush is primary value of current of HV side bushing CT
I'_H, I'_H1, I'_H2 and I'_M are primary values of current of each side of transformer respectively.

Date: 2011-10-19
3 Operation Theory
I'_CW is secondary value of common winding three-phase CT
I'_HBush is secondary value of current of HV side bushing CT
DANGER! When winding differential protection is used as stub differential protection, the
polarity of CT must be checked. If polarities of the circuit breaker CT and the bushing CT
of some side of a transformer are both at busbar side, either of them must be reversed by
PCS-PC software.
The criterion of fault detector of winding differential protection is as follows. The pickup of this fault
detector will enable winding differential protection of the corresponding side.
I wd > [87W.I_Biased] Equation 3.4-1
Where:
I wd is winding differential current.
[87W.I_Biased] is the pickup setting of winding differential protection.
If CTs used for winding differential protection have differential primary rated value, then the current
compensation is carried out in the program automatically with parameters input. Following gives
the criteria of calculating correction coefficient.
I1n I1n _ max

K wph = × K wb and K wb = min( ,4) Equation 3.4-2
I1n _ max I 1n _ min
Where:
K wph is the correction coefficient of the calculated CT input.
I1n is the primary value of CT at calculated CT input.
I1n _ min is the minimum value among primary values of all CTs for winding differential protection.
I1n _ max is the maximum value among primary values of all CTs for winding differential protection.
This calculation method is to take the minimum CT primary rating of all calculated CT inputs as the
reference. If the multiple of the maximum CT primary ratio to the minimum CT primary rating is
greater than 2.95, then reference shall be taken as 2.95 and others shall be calculated
proportionally. Otherwise, the reference shall be taken as 1, and others will be calculated
proportionally.

Date: 2011-10-19
3 Operation Theory
The currents used in the following analysis have been corrected, that means the currents for
following calculation are the products of the actual secondary current of each side multiplying its
own correction coefficient ( K wph ).
3.4.3.4 Calculations of Differential and Restraint Current
The equation of calculating winding differential current is as follows.
⎡ I wdA ⎤ ⎡ I A1⎤ ⎡ I A2 ⎤ ⎡ I A3 ⎤
⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢ I wdB ⎥ = K I B1
× ⎢ ⎥ / I 2n _ CT1 + K wph2 × ⎢
I B2 ⎥ I
/ I 2n _ CT 2 + K wph3 × ⎢ B3 ⎥ / I 2n _ CT 3 +
⎢ I wdC ⎥ wph1 ⎢ IC1⎥ ⎢ IC 2 ⎥ ⎢ IC 3 ⎥
⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥
⎢⎣ I wd 0 ⎥⎦ ⎢ I ⎥⎦ ⎢ I ⎥⎦ ⎢ I ⎥⎦
1444⎣401 244443 1444⎣402 244443 1444⎣403 244443
1 2 3
Equation 3.4-3
⎡ I A4 ⎤ ⎢ I A5 ⎥
⎢ ⎥ ⎢ ⎥
I I
K wph4 × ⎢⎢
B4 ⎥
/ I 2n _ CT 4 + K wph5 × ⎢ B5 ⎥ / I 2n _ CT 5
IC 4 ⎥ ⎢ IC 5 ⎥
⎢ ⎥ ⎢ ⎥
⎢ I ⎦⎥ 4443 1444⎣⎢4 I05 ⎦⎥
1444⎣404 24 244443
4 5
⎧ I wdA = I ′A1 + I ′A2 + I ′A3 + I ′A4 + I ′A5

⎪ ′ 1 + IB′ 2 + IB′ 3 + IB′ 4 + IB′5
⎪ I wdB = I B
⎨ Equation 3.4-4
′ 1 + IC
⎪ I wC = I C ′ 2 + IC′ 3 + IC′ 4 + IC′5
⎪ I wd 0 = I 01′ ′ ′ ′ ′
+ I 02 + I 03 + I 04 + I 05
⎩
Where:
I wdA I wdB I wdC I wd 0 are respectively three phase and residual winding differential currents.
I An , I Bn , I Cn , I 0n are respectively secondary values of three phase currents and calculated neutral
current of branch m (m=1, 2, 3, 4 ,5).
I ′An , I Bn ′ , I 0′ n are respectively secondary values of corrected three phase currents and calculated
′ , I Cn
residual current of branch m (m=1, 2, 3, 4 ,5）
K wph1, K wph 2 , K wph3 , K wph 4 , K wph5 are corrected coefficients of each side for magnitude compensation
respectively.
I 2 n _ CT 1, I 2 n _ CT 2 , I 2 n _ CT 3 , I 2 n _ CT 4 , I 2 n _ CT 5 are respectively rated secondary values of CTs of each
branch.

Date: 2011-10-19
3 Operation Theory
{
⎧ I wrA = max I ′A1 + I ′A2 + I ′A3 + I ′A4 + I ′A5}
⎪
{
⎪ I wrB = max I B′ 1 + IB′2 + IB ′ 3 + IB′ 4 + IB′5}
⎨
{
′ 1 + IC
⎪ I wrC = max I C ′2 + IC ′ 3 + IC′ 4 + IC′5 } Equation 3.4-5
⎩ {
⎪ I wr 0 = max I 01
′ + I 02
′ ′ + I 04
+ I 03 ′ + I 05
′ }
Where:
I wrA , I wrB , I wrC , I wr 0 are secondary values of three phase restraint currents and neutral
restraint current respectively.
The operation criteria of winding differential protection are as follows, and maximum 5 branches
are supported for the calculation.
⎧ I wd > [ 87T .I_Biased] I wr ≤ [87W .I _ Knee]

⎪
⎪ I wd > [87W .Slope] × (I wr − [87W .I _ Knee]) + [87T .I_Biased ]
⎨I = max{ I w1 , I w2 , I w3 , I w4 , I w5 } Equation 3.4-6
⎪ wr
⎪ I wd = I&w1 + I&w2 + I&w3 + I&w4 + I&w5
⎩
Where:
I w1 … I w5 are currents of five branches respectively.
I wr is winding restraint current.
[87W.I_Biased] is the pick up value of biased winding differential protection.
[87W.I_Knee] is the setting of knee point of biased winding differential protection, and 0.5In is
recommended.
[87W.Slope] is the restraint coefficient of biased winding differential protection and 0.5 is
recommended.
NOTE! For protecting an autotransformer, a winding differential protection is composed of
three-phase currents of HV side, LV side and common winding.
NOTE! When calculated residual currents of each branch are used for the calculation, the
winding differential protection (87W) becomes neutral differential protection (87N) also
called residual differential protection in the following description.
3.4.3.6 Operation Characteristic Curve
Operation characteristic of winding differential protection is shown in the following figure.

Date: 2011-10-19
3 Operation Theory
K=m
Figure 3.4-3 Operating characteristic curve of winding differential protection
Where:
The value of m is defined by the branch number for winding differential protection. For example,
the protection is applied for protecting an autotransformer including HV side, MV side and
common winding and m is equal to 3.
The CT saturation detection principle of winding differential protection is the same as that of
current differential protection, and please refer to Section 3.1.3.12 for details.
3.4.3.8 CT Supervision for Winding Differential Protection
3.4.3.8.1 CT Circuit Abnormality of Winding Differential Protection
If the following operation formula is met for 10s, CT circuit abnormality alarm of winding differential
protection will be issued without blocking the protection.
The operation criterion is as follows:
I wd > Max(0.2 × [87W .I _ Biased ] ,0.1I n ) Equation 3.4-7
Where:
I n is the rated secondary voltage of CT.
3.4.3.8.2 CT Circuit Failure of Winding Differential Protection
3.4.4 Logic
The logic diagram of winding differential protection of HV side is taken as example to show below.

Date: 2011-10-19
3 Operation Theory
Figure 3.4-4 Logic diagram of winding differential protection of HV side
Where:
Flg_WdgDiff_HVS is the internal flag indicating that operation criterion of winding differential
protection of HV side is satisfied.
FD_WdgDiff_HVS is the signal indicating that the fault detector of winding differential protection of
HV side picks up.
For winding differential protection, when all following three conditions are met the protection is
enabled.
(1) Logic setting [x.87W.En] is set to “1”.
(2) Enabling inputs [x.87W.En1], [x.87W.En2] are both set to “1”
(3) Blocking input [x.87W.Blk] is set to “0”.
When the protective function block is disabled, [x.87W.St], [x.87W.Op] signals are both reset.
Default values of Inputs [x.87W.En1] and [x.87W.En2] are “1” and [x.87W.Blk] is “0” when those
inputs are not connected to external signals or setting.

Date: 2011-10-19
3 Operation Theory
87W
I3P1 St
I3P2 Op_Phase
I3P3 Op_Residual
I3P4 Alm_Diff
I3P5 Alm_CTS
En1
En2
Blk
Figure 3.4-5 87W function block
Table 3.4-1 Input signals of 87W function block

8 Blk
Table 3.4-2 Output signals of 87W function block

5 St Winding differential protection starts.
6 Op_Phase Phase winding differential protection operates.
7 Op_Residual Residual differential protection operates.
Alarm message indicating CT secondary circuit of winding differential protection
8 Alm_Diff
abnormal.
9 Alm_CTS Alarm message indicating that CT secondary circuit of differential protection fails.
Table 3.4-3 Output signals of 87W: report
6 87W.Op_Phase Phase winding differential protection of x side operates.
7 87W.Op_Residual Residual differential protection of x side operates.

Date: 2011-10-19
3 Operation Theory
8 87W.St Winding differential protection of x side starts.
9 87W.Alm_WD CT secondary circuit for winding differential protection of x side is abnormal.
10 87W.Alm_CTS CT secondary circuit for Winding differential protection of x sided fails.
11 87W.TrigDFR Winding differential protection of x side picks up to trigger DFR function.
Table 3.4-4 Output signals of 87W: measurements
87W.Ida
1 87W.Idb Three phase differential current of winding differential protection. In
87W.Idc
2 87W.I0d Residual differential current of winding differential protection. In
87W.Ithra
Thereshold of three phase restraint current of winding differential
3 87W.Ithrb In
protection
87W.Ithrc
4 87W.Ithr0 Thereshold of residual restraint current of residual differential protection. In
87W.Ia_Corr_Brm
Corrected values of three phase current of winding differential protection
5 87W.Ib_Corr_Brm In
of branch m (n=1, 2, 3, 4, 5).
87W.Ic_Corr_Brm
Corrected value of residual differenital current of winding differential

6 87W.I0_Corr_Brm In
protection.
87W.Ang(Ia)_Br1-Brm
Three phase angles between the current of branch 1 and the current of
7 87W.Ang(Ib)_Br1-Brm deg
branch m (m=2, 3, 4, 5).
87W.Ang(Ic)_Br1-Brm
Angle between residual current of branch 1 and residual current of branch

8 87W.Ang(3I0)_Br1-Brm deg
m (m=2, 3, 4, 5).
Corrected coefficient of branch m (n=1, 2, 3, 4, 5) for winding differential

9 87W.K_Brm
protection.
Path:
Main menu -> Measurements -> Measurements1-> WDIF Measurements
Main menu -> Measurements -> Measurements2-> WDIF Measurements
3.4.6 Setting
Table 3.4-5 Settings of 87W

Date: 2011-10-19
3 Operation Theory
Knee point setting of biased winding differential

1 87W.I_Knee 0.1~4 0.001 In
protection.
2 87W.I_Biased 005~5 0.001 In Pickup setting of biased winding differential protection
Percentage restraint coefficient of biased winding

3 87W.Slope 0.1~0.9 0.001
0: disable Logic setting of enabling/disabling blocking winding

4 87W.En_CTS_Blk 1
1: enable differential protection during CT circuit failure
0: disable Logic setting of enabling/disabling phase winding

5 87W.En_Phase 1
1: enable differential protection.
0: disable Logic setting of enabling/disabling residual differential

6 87W.En_Residual 1
1: enable protection.
7 87W.OutMap 0000~FFFF Tripping logic setting of winding differential protection
3.5 Inter-Turn fault Protection (IntTurn)
3.5.1 Application
Shunt reactors as the key equipment are widely applied in extra-high voltage and ultra-high
voltage level power system, which has a dominate effect on safe operation of the power system.
The inter-turn fault is a common internal fault occurred in reactor, but current differential protection
cannot operate during inter-turn faults. Considering ground overcurrent protection cannot be taken
as the fast protection for inter-turn faults, a dedicated protection for inter-turn protection of reactor
is needed to be equipped.
Inter-turn faults in reactors present a formidable challenge to the protection engineer. The current
and voltage changes encountered during an inter-turn fault can be of similar magnitude as load
variation, and therefore, sensitive, reliable protection schemes should be considered.
3.5.2 Functions
z Current of CT at line side of reactor is adopted for the protection calculation.
z Inter-turn protection consists of zero-sequence power directional element and zero-sequence

impedance element with high reliability.
z The amplitude of residual voltage is compensated to ensure zero-sequence power directional

element can distinguish direction correctly when system impedance is too low.
z Inter-turn protection being blocked by CT and VT circuit failure.
3.5.3.1 Overview
Inter-turn fault protection consists of three parts: self-adjusted zero-sequence power directional

Date: 2011-10-19
3 Operation Theory
element, zero-sequence impedance element and DPFC inter-turn fault detector element. Three
elements can improve relay sensitivity and ensure relay against maloperation during external
faults, transient process (such as series compensated lines, LC resonance, power swing etc.) or
abnormal conditions (such as pole disagreement, CT secondary circuit failure, etc.)
In order to avoid maloperation of inter-turn fault protection during some transient conditions, such
as pole disagreement operation of lines (or compensated lines), reclosing of auto-recloser after
earth faults, pole disagreement of circuit breaker，reactor energization with line (or compensated
line), LC resonance due to circuit breakers at line both sides being tripped, external faults and pole
disagreement with power swing, etc., Residual power directional element and zero-sequence
impedance element are adopted to consist inter-turn fault protection of reactor.
The pickup of this fault detector (DPFC inter-turn fault detector) will enable the inter-turn fault
differential protection, and its operation equation is as follows.

Equation 3.5-1
ΔI = ΔI& + ΔI&
d 1 2
Where:
of load current is small and gradually under normal or even power swing condition, and the
adaptive floating threshold ( ΔI dt ) is higher than the change of current under these conditions and
hence the element maintains stability.
ΔI&1 , ΔI&2 are the DPFC current of two ends of reactor representatively.
I dth is the fixed threshold and the value is 0.2pu.
3.5.3.3 Residual Power Directional Element
3.5.3.3.1 Analysis of Inter-Turn Fault of Reactor
The wiring diagram of shunt reactors in power system is shown as following figure.

Date: 2011-10-19
3 Operation Theory
AC1 Zs1 ZL Zs2 AC2

F1
Zr1 Zr2 F2
Shunt reactor 1 Shunt reactor 2
Figure 3.5-1 Wiring diagram of shunt reactors in power system
Where:
AC1, AC2 : equivalent voltage source.
Zs1, Zs2: equivalent system impedance.
Zr1, Zr2 : impedance of shunt reactor.
ZL: line impedance.
F1: fault point 1
F2: fault point 2
1) Case 1: External single-phase earth fault of line (close-up external earth fault at F1)
The fault point is zero sequence source, the equivalent zero-sequence network is shown below.
Figure 3.5-2 Equivalent zero-sequence network for case 1
Where：
Zs＇: equivalent system impedance, Zs＇=(Zr1//Zs1+ ZL)//Zs2
U0: relay detected zero sequence voltage
I0: relay detected zero sequence current
FaultPS: fault power source
It is an external earth fault, so viewing from reactor relay location, zero-sequence current flows to
reactor from reactor grounding point and via transmission line back to the ground at the earth fault
point. Therefore, the equation between U0 and I0 at the relay location is:
U0=I0xZr2
Vector relation between U0 and I0 is:

Date: 2011-10-19
3 Operation Theory
Figure 3.5-3 Vector relation for case 1
2) Case 2: Internal inter-turn fault (fault at F2)
Because of the fault point in reactor, the equivalent zero-sequence network is shown below.
Figure 3.5-4 Equivalent zero-sequence network for case 2
Where：
Zs＇: equivalent system impedance, Zs＇=(Zr1//Zs1+ ZL)//Zs2
Zr1-1: impedance of Zr1 part 1
Zr1-2: impedance of Zr1 part 2
U0: relay detected zero sequence voltage
I0: relay detected zero sequence current
FaultPS: fault power source
It is an internal inter-turn fault, so viewing from reactor relay location, zero-sequence current flows
from reactor to ground through system reactance. Therefore, the equation between U0 and I0 at
the relay location is:
U0=-I0x Zs＇
Vector relation between U0 and I0 is
I0
U0
Figure 3.5-5 Vector relation for case 2

Date: 2011-10-19
3 Operation Theory
The phase angle of residual current leading residual voltage is nearly 90 degree if an inter-turn
fault of reactor winding occurs. The residual current phase leads the residual voltage phase if an
internal single-phase earth fault occurs; and the residual current phase lags the residual voltage
phase if an external single-phase earth fault occurs. Therefore, the phase angle between residual
current and residual voltage can be used to distinguish internal faults from external faults. The
zero-sequence impedance of system very small compared to that of reactor, so the residual
voltage detected by the relay will not be sensitive to operate and need to be compensated.
The operation criterion of this residual power directional protection is:
• •
o (3U 0 + kZb ⋅ 3 I 0 )
− 180 < Arg < 0o Equation 3.5-2
•
3I0
Where:
• •
3U 0 、
3 I 0 are respectively calculated residual voltage and calculated residual current from VT and
CT1 (i.e. CT at the line side of reactor).
Z b is the zero-sequence impedance of reactor including neutral earthing reactor, i.e.[ IntTurn.Z0].
K is the floating coefficient adaptive to variation of zero-sequence voltage and current from 0 to
0.8.
3.5.3.4 Zero-sequence Impedance Element
Zero-sequence impedance of reactor is usually thousands of ohms which is greater than that of
system. When an inter-turn fault or internal single-phase earth fault of reactor occurs, the
impedance detected by the relay is exactly the zero-sequence impedance of system. If an external
single-phase fault of reactor occurs, the impedance detected by the relay is the zero-sequence
impedance of reactor. According to different values of measured impedances, inter-turn faults (or
internal fault) and external earth faults can be distinguished.
Operation criterion:
Zm<0.25xZ0 Equation 3.5-3
Where:
Zm is measured zero-sequence impedance.
Z0 is zero-sequence impedance of reactor.
NOTE:
Influence of VT abnormality

Date: 2011-10-19
3 Operation Theory
When VT abnormality (including star line of VT is not connected) is detected, zero-sequence

power directional element and zero-sequence impedance element are not satisfied, which
implies that inter-turn fault protection inter-turn fault protection is out of service.
Influence of CT abnormality
When CT abnormality at line side is detected, zero-sequence power directional element and
zero-sequence impedance element operation criteria are not satisfied, which implies that
inter-turn fault protection is out of service.
3.5.4 Logic
Figure 3.5-6 Logic diagram of inter-turn fault protection
Where:
Flg_ZSImpedance is the internal flag indicating that zero-sequence impedance element operates.
Flg_ResidPwrDir is the internal flag indicating that residual power directional element operates.
FD_DPFC_IntTurn is the internal flag indicating that DPFC inter-turn fault detector operates.
[Alm_CTS] is the alarm signal indicating CT circuit abnormality is distinguished.
[Alm_VTS] is the alarm signal indicating VT circuit abnormality is distinguished.
For inter-turn fault protection, when following three conditions are met the protection is enabled.
(1) Logic setting [IntTurn.En] is set to “1”.
(2) Enabling inputs [IntTurn.En1], [IntTurn.En2] are both set to “1”
(3) Blocking input [IntTurn.Blk] is set to “0”.
When the protective function block is disabled, [IntTurn.St], [IntTurn.Op] signals are both reset.
Default values of Inputs [IntTurn.En1] and [IntTurn.En2] are “1” and [IntTurn.Blk] is “0” when those

Date: 2011-10-19
3 Operation Theory
Figure 3.5-7 IntTurn Function block
Table 3.5-1 Input signals of IntTurn function block

1 I3P Three-phase current data input 1
2 U3P Three-phase voltage data input 2
5 Blk
Table 3.5-2 Output signals of IntTurn function block

1 St Inter-turn fault protection starts.
2 Op Inter-turn fault protection operates.
Table 3.5-3 Output signals of IntTurn: report
1 IntTurn.Op Inter-turn fault protection operates.
2 IntTurn.St Inter-turn fault protection starts.
3 x.IntTurn.TrigDFR Inter-turn fault protection picks up to trigger DFR function..
3.5.6 Setting
Table 3.5-4 Settings of IntTurn
1 IntTurn.En 0: disable 1 Logic setting of enabling/disabling inter-turn fault

Date: 2011-10-19
3 Operation Theory
2 IntTurn.OutMap 0000~FFFF Tripping logic setting of inter-turn fault protection.
3.6 Overexcitation Protection (24)
3.6.1 Application
Overexcitation results from excessive applied voltage, possibly in combination with below-normal
frequency. Such condition may occur when a unit is on load, but are more likely to arise when it is
on open circuit, or at a loss of load occurrence. Transformers directly connected to generators are
in particular danger to experience overexcitation condition.
During overexcitation, field current of transformer rises greatly to cause excessive heating and
severe damage. The transformer, working magnetic flux density near the keen point, is subject to
overexcitation. Frequency range for normal operation is 45~55Hz for 50Hz working frequency of
power system and 55~65Hz for 60Hz working frequency of power system.
Overexcitation protection can be configured at any side of transformer through PCS-PC, and it is
recommended to be equipped at the side without OLTC tap.
3.6.2 Function
Overexcitation protection has following functions:
z Voltage for protection calculation is RMS of three phase voltages and not affected by
frequency fluctuation.
z Overexcitation multiple is calculated by voltage and frequency.
z Two-stage definite-time overexcitation protection and one-stage definite-time overexcitation

alarm element are equipped.
z One-stage inverse-time overexcitation protection including tripping and alarm functions is

equipped.
z Overexcitation inverse-time curve is sectional linear curve, which has high adaptivity.

Overexitation protection consists of definite-time protection and inverse-time protection.
z Calculate overexcitation degree:
Degree of overexcitation can be evaluated by following overexcitation multiple:
n = U* / f* Equation 3.6-1
Where:

Date: 2011-10-19
3 Operation Theory
U * and f * are per unit value of voltage and frequency respectively.
The base value for calculating per unit value of voltage is secondary voltage corresponding to
primary voltage of one side of transformer, and the base value for calculating per unit value of
frequency is rated frequency. During normal operation, n = 1.
For example, overexcitation protection is equipped at HV side, primary voltage of HV side is 525kV
(i.e. [Un_HVS]=525kV) and voltage transformer ratio is 500kV/100V (i.e. [U1n_VT_HVS] =500kV,
[U2n_VT_HVS]=100V). The base value for calculating per unit value of voltage is equatl to:
[Un _ HVS ]x[U 2n _ VT _ HVS ] 525 × 100

= = 60.62V
3 × [U 1n _ VT _ HVS ] 3 × 500
This base voltage calculation is carried out in the relay and users need not calculate the ratio of VT
when configure settings.
z Definite-time operation criterion:
U * / f * >[24DTn.k_Set] Equation 3.6-2
Where:
U * / f * is overexcitation multiple.
[24DTn.k_Set] is multiplier setting of stage n (n=1, 2) definite-time overexcitation protection. Stage

1 is for tripping and stage 2 for alarming.
Inverse-time overexcitation protection realizes inverse-time characteristic by linear processing on

given inverse-time operation characteristic, obtaining multiple of overexcitation by calculation, and
getting the corresponding operation delay by sectional linear insertion. It reflects the heat
accumulation and radiation.
Several groups of setting point with independent settings can be configured for simulating the
inverse-time operation characteristics curve and this protection can satisfy overexcitation
requirements of various transformers.
Following figure shows inverse-time characteristic of overexcitation protection.

Date: 2011-10-19
3 Operation Theory
U * / f*
Figure 3.6-1 Inverse-time characteristic of overexcitation protection
The main harm of overexcitation to transformer is overheat, so accumulation method is adopted

and accumulate the time delay according to curve time corresponding to calculated overexcitation
multiple. When accumulated time delay is greater than the operating time delay, inverse-time
overexcitation protection operates. Dissipating process is also simulated, when overexcitation
multiple is less than the minimum overexcitation multiple setting, the accumulated value
decreases to 0 gradually. If overexcitation protection operates and overexcitation condition
disappears, thermal accumulation value decreases to zero in 10s.
Overexcitation multiple comprises overexcitation information at current instant and also

overexcitation information integrated over various time intervals from its beginning.
Inverse-time characteristic curve can be specified by several overexcitation multiple settings, and
the relation between various settings of n and t are:
n0≥n1 ≥ n2 ≥ n3 ≥ n4 ≥ n5 ≥ n6 ≥ n7 ≥ n8 ≥ n9
t0 ≤t1 ≤ t2 ≤ t3 ≤ t4 ≤ t5 ≤ t6 ≤ t7≤ t8 ≤ t9
3.6.4 Logic
Two-stage definite-time overexcitation protection with independent current and time delay settings.
Stage 1 and stage 2 has identical logic diagrams but stage 1 for trip and stage 2 for alarm.
On-stage inverse-time overexcitation operates to trip and issued the alarm signal.
SIG [24DT1.En1]
&
SIG [24DT1.En2]
&
SIG [24DT1.Blk] [24DT1.t_Op] 0ms
[24DT1.Op]
EN [24DT1.En]
SIG U * / f * >[24DT1.K_Set]
Figure 3.6-2 Logic diagram of stage 1 definite-time overexcitation protection
Where:

Date: 2011-10-19
3 Operation Theory
For definite-time overexcitation protection, when following three conditions are met the protection
is enabled.
(1) Logic setting [24DTx.En] (x=1 or 2) is set to “1”.
(2) Enabling inputs [24DTx.En1], [24DTx.En2] are both set to “1”
(3) Blocking input [24DTx.Blk] is set to “0”.
When the stage protective function block is disabled, [24DTx.St], [24DTx.Op] signals are both
reset. Default values of Inputs [24DTx.En1] and [24DTx.En2] are “1” and [24DTx.Blk] is “0” when
SIG [24IDMT.En1]
&
SIG [24IDMT.En2]
&
SIG [24IDMT.Blk] IDMT [24IDMT.Op]
EN [24IDMT.En]
IDMT [24IDMT.Alm]
SIG U * / f *>[24IDMT.Kn_Set]
Figure 3.6-3 Logic diagram of inverse-time overexcitation protection
Where:
[24IDMT.Kn_Set] (n=0,1,2,…,9) is the multiple setting of inverse-time overexcitation.
For inverse-time overexcitation protection, when following three conditions are met the protection
is enabled.
(1) Logic setting [24IDMT.En] is set to “1”.
(2) Enabling inputs [24IDMT.En1], [24IDMT.En2] are both set to “1”
(3) Blocking input [24IDMT.Blk] is set to “0”.
When the protective function block is disabled, [24IDMT.St], [24IDMT.Op] signals are both reset.
Default values of Inputs [24IDMT.En1] and [24IDMT.En2] are “1” and [24IDMT.Blk] is “0” when
24DT1
OvExc St
En1 Op
En2
Blk
Figure 3.6-4 Function block of 24DT for trip

Date: 2011-10-19
3 Operation Theory
24DT2
OvExc Alm
En1
En2
Blk
Figure 3.6-5 Function block of 24DT for alarm
Figure 3.6-6 Function block of 24IDMT
Table 3.6-1 Input signals of function blocks (24DT and 24IDMT)

1 OvExc Overexcitation data, including frequency and voltage signals.
4 Blk
Table 3.6-2 Output signals of function block 24DT1 for trip

1 St Protection starts.
2 Op Protection operates to trip.
Table 3.6-3 Output signals of function block 24DT2 for alarm

1 St Alarm element starts
2 Alm Alarm element operates
Table 3.6-4 Output signals of 24

Date: 2011-10-19
3 Operation Theory

1 St Protection starts
2 Op Protection operates.
3 Alm Protection issues alarm signal.
Table 3.6-5 Output signals of 24: report
1 24DT1.Op Definite-time overexcitation tripping element operates.
2 24IDMT.Op Inverse-time overexcitation tripping element operates.
3 24DT2.Op Definite-time overexcitation alarm element operates.
4 24IDMT.Alm Inverse-time overexcitation alarm element operates.
Alarm reports of protection element.
5 24DT1.St Definite-time overexcitation tripping element starts.
6 24DT2.St Definite-time overexcitation alarm element starts.
7 24IDMT.St Inverse-time overexcitation protection starts.
8 24DT1.TrigDFR Definite-time overexcitation protection picks up to trigger DFR function.
9 24DTIDMT.TrigDFR Inverse-time overexcitation protection picks up to trigger DFR function.
Table 3.6-6 Output signals of 24: measurements
1 f Measured system frequency Hz
2 U/f_24DT Overexcitation multiple of definite-time overexcitation protection.
Thermal state of inverse-time overexcitation protection. When the %

3 24IDMT.ThermState
value is “1”, inverse-time overexcitation protection operates.
Path:
Main menu -> Measurements -> Measurements1-> OvExc Measurements
Main menu -> Measurements -> Measurements2-> OvExc Measurements
3.6.6 Settings
Table 3.6-7 settings of 24

Logic setting of selecting phase voltage or
1 24.Opt_Up/Upp 0~1
phase-to-phase voltage for calculation of

Date: 2011-10-19
3 Operation Theory

overexcitation protection.
0: phase voltage; 1: phase-to-phase voltage.
Table 3.6-8 Settings of 24DT1 (for trip)

Multiple setting of definite-time overexcitation
1 24DT1.K_Set 1.0~1.7 0.001
protection
Time delay setting of definite-time overexcitation
2 24DT1.t_Op 0.1~9999 0.001 s
alarm protection
0: disable Logic settings of enabling definite-time overexcitation
3 24DT1.En 1
1: enable alarm protection
Tripping logic settings of definite-time overexcitation
4 24DT1.OutMap 0000~FFFF
alarm protection
Table 3.6-9 Settings of 24DT2 (for alarm)

Multiple setting of definite-time overexcitation alarm
1 24DT2.K_Set 1.0~1.7 0.001
element
Time delay setting of definite-time overexcitation
2 24DT2.t_Op 0.1~9999 0.001 s
alarm element
0: disable Logic settings of enabling definite-time overexcitation
3 24DT2.En 1
1: enable alarm element
Table 3.6-10 Settings of 24IDMT

Highest-limit multiple setting of Inverse-time
1 24IDMT.K0_Set 1.0~1.7 0.001
overexcitation protection: n0
Time delay setting corresponding to highest-limit
2 24IDMT.t0_Op 0.1~9999 0.001 s
setting: t0
Multiple setting 1 of inverse-time overexcitation
3 24IDMT.K 1_Set 1.0~1.7 0.001
protection: n1
Time delay setting corresponding to multiple setting 1:
4 24IDMT.t1_Op 0.1~9999 0.001 s
t1
5 24IDMT.K2_Set 1.0~1.7 0.001
protection: n2
6 24IDMT.t2_Op 0.1-9999 0.001 s
t2
7 24IDMT.K3_Set 1.0~1.7 0.001
protection: n3
8 24IDMT.t3_Op 0.1~9999 0.001 s
t3
9 24IDMT.K4_Set 1.0~1.7 0.001 Multiple setting 4 of inverse-time overexcitation

Date: 2011-10-19
3 Operation Theory

protection: n4
10 24IDMT.t4_Op 0.1~9999 0.001 s
t4
11 24IDMT.K5_Set 1.0~1.7 0.001
protection: n5
12 24IDMT.t5_Op 0.1~9999 0.001 s
t5
13 24IDMT.K6_Set 1.0~1.7 0.001
protection: n6
14 24IDMT.t6_Op 0.1~9999 0.001 s
t6
15 24IDMT.K7_Set 1.0~1.7 0.001
protection: n7
16 24IDMT.t7_Op 0.1~9999 0.001 s
t7
17 24IDMT.K 8_Set 1.0~1.7 0.001
protection: n8
18 24IDMT.t8_Op 0.1~9999 0.001 s
t8
Lowest-limit multiple setting of inverse-time
19 24IDMT.K9_Set 1.0~1.7 0.001
overexcitation: n9.
Time delay setting corresponding to lowest-limit
20 24IDMT.t9_Op 0.1~9999 0.001 s
multiple setting: n9.
Multiple setting of inverse-time overexcitation
21 24IDMT.K _Alm 0.5~0.99 0.001
protection for alarming.
0: disable Logic setting of enabling inverse-time overexcitation
22 24IDMT.En_Alm 0
1: enable protection for alarm
23 24IDMT.t_Cooling 0.1~9999 0.001 s Cooling time of inverse-time overexcitation protection.
0: disable Logic setting of enabling inverse-time overexcitation
24 24IDMT.En_Trp 0
1: enable protection for trip
Tripping logic setting of inverse-time overexcitation
25 24IDMT.OutMap 0~FFFF 1
protection
NOTE! Please input the corresponding values of selected 10 points of overexcitation
curve of transformer to the protection device and the values of 10 points are distributed averagely.
NOTE! Inverse-time curve is based on the actual operation voltage, so users need not
calculate the ratio of VT when configure settings.
NOTE! I Inverse-time overexcitation protection is set with reference to the curve given by
the transformer manufactory. The relation between all settings of inverse-time overexcitation

Date: 2011-10-19
3 Operation Theory
protection is:
[24IDMT.K9_Op]<[24IDMT.K8_ Op]<…<[24IDMT.K1_ Op]<[24IDMT.K0_ Op]
[24IDMT.t0_Op]<[ 24IDMT.t1_ Op]<…<[24IDMT.k8_ Op] <[24IDMT.t9_ Op]
3.7 Frequency Protection (81)
3.7.1 Application
In case of frequency decline due to lack of active power in the power system, underfrequency
protection operates to shed part of the load according to the declined value of frequency to
re-balance the power supply and the load. On the contrary, if the power frequency of regional rises
due to the active power excess demand, overfrequency protection operates to perform generator
rejection to shed part of the generators automatically according to the rising frequency so that
power supply and the load are re-balanced.
3.7.2 Function
z Underfrequency Protection
In order to prevent possible maloperation of underfrequency protection in conditions of high

harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:
a) Blocking in undervoltage condition
If the positive voltage U＜0.15Un, the calculation of protection is not carried out and the output
relay will be blocked.
b) df/dt blocking element
If －df/dt≥[81U.df/dt_Blk], the calculation of protection is not carried out and the output relay will
be blocked. The blocking element will not be released automatically until the system frequency
recovers to be less than the setting [81U.f_Pkp].
c) frequency over-range blocking element
If the system frequency is less than the setting [f_low_FreqAlm] or greater than the setting
[f_High_FreqAlm], frequency measurement is decided to be abnormal and output relays are
blocked.
z Overfrequency Protection
In order to prevent possible maloperation of overfreqency protection in conditions of high

harmonics, voltage circuit failures and so on, such blocking measures are carried out as follows:
a) Blocking in undervoltage condition
If the positive voltage U＜0.15Un, the calculation of protection is not carried out and the output
relay will be blocked.
b) frequency over-range blocking element

Date: 2011-10-19
3 Operation Theory
If the system frequency is less than the setting [f_low_FreqAlm] or greater than the setting
[f_High_FreqAlm], frequency measurement is decided to be abnormal and output relays are
blocked.
3.7.3 Fault Detector

z Fault detector of underfrequency protection
The pickup of this fault detector will enable underfrequency protection, which operation criterion is
as follows.
f <[81U.f_Pkp] Equation 3.7-1
Where:
f is the measured system frequency.
[81U.f_Pkp] is the frequency pickup settings of underfrequency protection.
z Fault detector of overfrequency protection
The pickup of this fault detector will enable overfrequency protection which operation criterion is as
follows.
f <[81O.f_Pkp] Equation 3.7-2
Where:
f is the measured system frequency.
[81O.f_Pkp] is the frequency pickup settings of overfrequency protection.

Operation criteria of underfrequency protection and overfrequency protection are shown in the
following two equations respectively, and the corresponding protection operates when one
operation criterion is met. Undervoltage blocking element is equipped to block overfrequency and
underfrequency protections when positive-sequence voltage is less than 30V.
z Operation criterion of underfrequency protection
f <[81U.UFx.f_Set] Equation 3.7-3
Where:
f is system frequency.
[81U.UFx.f_Set] is the frequency settings of stage x (x=1, 2, 3 or 4) of underfrequency protection.

Date: 2011-10-19
3 Operation Theory
The equation of df/dt blocking function is as follows.
−df / dt ≥ [81U.df/dt_Blk] Equation 3.7-4
Where:
df / dt is the frequency slip speed and the time step (i.e. dt ) for the calucation is equal to 5
cycle.
[81U.df/dt_UF] is the setting of df/dt blocking underfrequency protection.
Underfrequency protection can be blocked by the frequency slip speed (df/dt). If the logic setting
[81U.UFx.En_df/dt_Blk] (x=1, 2, 3 or 4) is set as “1”, when Equation 3.7-3 and Equation 3.7-4 are
met, it is decided that a fault occurred and the corresponding stage underfrequency protection is
blocked at the same time for the purpose of waiting for operation of other related protection. The
blocking signal will not reset until the system frequency recovers, i.e. the system frequency is
greater than the setting [81U.f_Pkp]. If the logic setting is set as “0”, when Equation 3.7-3
and Equation 3.7-4 are met, the stage underfrequency protection will be released to operate.
z Operation criterion of overfrequency protection
f >[81O.OFx.f_Set] Equation 3.7-5
Where:
f is system frequency.
[81O.OFx.f_Set] is the frequency setting of stage x (x=1, 2, 3, or 4) of overfrequency protection.

Date: 2011-10-19
3 Operation Theory
3.7.5 Logic
3.7.5.1 Logic of Underfrequency Protection
SIG [81U.En1] &

SIG [81U.En2] Flg_En81U
SIG [81U.Blk]
OTH U1<0.15Un
SIG f＜fmin or f＞fmax ≥1

Flg_Blk81U
SIG [x.In_VT]
SET -df/dt>[81U.df/dt_Blk]
SIG Flg_En81U &
SIG Flg_Blk81U &
OTH f<[81U.f_Pkp] 50ms 0ms &

[81U.UF1.t_Op] 0ms
[81U.UF1.Op]
SET f<[81U.UF1.f_Set]
EN [81U.UF1.En]
&
[81U.UF2.t_Op] 0ms
SET f<[81U.UF2.f_Set] [81U.UF2.Op]
EN [81U.UF2.En]
&
[81U.UF3.t_Op] 0ms
EN [81U.UF3.En]
&
[81U.UF4.t_Op] 0ms
EN [81U.UF4.En]
Figure 3.7-1 Logic diagram of underfrequency protection
Where:
fmin and fmax are respectively settings [f_Low_FreqAlm] and [f_High_FreqAlm].
[x.In_VT] is the input signal indicating that VT of x side in service. (x represent some side, such as
HVS, MVS, etc.). The signal can be configured as a binary input according to user requirements,
and if the binary input is not configured, the default value of the signal is 1.
Flg_En81U is the internal signal to enable underrequency protection.
Flg_Blk81U is the internal signal to block underfrequency protection.
For underfrequency protection, when following three conditions are met the protection is enabled.
(1) Logic setting [81U.En] is set to “1”.
(2) Enabling inputs [81U.En1], [81U.En2] are both set to “1”
(3) Blocking input [81U.Blk] is set to “0”.

Date: 2011-10-19
3 Operation Theory
When the protective function block is disabled, [81U.St], [81U.Op] signals are both reset. Default
values of Inputs [81U.En1] and [81U.En2] are “1” and [81U.Blk] is “0” when those inputs are not
3.7.5.2 Logic of Overfrequency Protection
SIG [81O.En1] &

SIG [81O.En2] Flg_En81O
SIG [81O.Blk]
OTH U1<0.15Un ≥1
SIG f＜fmin or f＞fmax Flg_Blk81O
SIG [x.In_VT]
SIG Flg_En81O &
SIG Flg_Blk81O &
OTH f>[81O.f_Pkp] 50ms 0ms &

[81O.OF1.t_Op] 0ms
[81O.OF1.Op]
SET f>[81O.OF1.f_Set]
EN [81O.OF1.En]
&
[81O.OF2.t_Op] 0ms
SET f>[81O.OF2.f_Set] [81O.OF2.Op]
EN [81O.OF2.En]
&
[81O.OF3.t_Op] 0ms
EN [81O.OF3.En]
&
[81O.OF4.t_Op] 0ms
EN [81O.OF4.En]
Figure 3.7-2 Logic diagram of overfrequency protection
Where:
Flg_En81O is the internal signal to enable overfrequency protection.
Flg_Blk81O is the internal signal to block overfrequency protection.
For overfrequency protection, when following three conditions are met the protection is enabled.
(1) Logic setting [81O.En] is set to “1”.
(2) Enabling inputs [81O.En1], [81O.En2] are both set to “1”
(3) Blocking input [81O.Blk] is set to “0”.
When the protective function block is disabled, [81O.St], [81O.Op] signals are both reset. Default
values of Inputs [81O.En1] and [81O.En2] are “1” and [81O.Blk] is “0” when those inputs are not

Date: 2011-10-19
3 Operation Theory
Figure 3.7-3 81U function block
Figure 3.7-4 81O function block
Table 3.71 Input signals of 81U and 81O function block

1 U3P Three-phase voltage data input.
2 Freq Measured freqeuency data input.
5 Blk
Table 3.7-2 Output signals of 81U function block

1 St Overfrequency protection starts.
2 UF1.Op Overfrequency protection stage 1 operates.
Table 3.7-3 Output signals of 81O function block

6 St Overfrequency protection starts.
7 OF1.Op Overfrequency protection stage 1 operates.

Date: 2011-10-19
3 Operation Theory

Table 3.7-4 Output signals of frequency protection: report
1 81U.UF1.Op Underfrequency protection stage 1 operates.
5 81U.OF1.Op Overfrequency protection stage 1 operates.
9 81U.St Underfrequency protection starts.
10 81O.St Overfrequency protection starts.
11 81U.TrigDFR Underfrequency protection picks up to trigger DFR function.
12 81O.TrigDFR Overfrequency protection picks up to trigger DFR function.
3.7.7 Setting
Table 3.7-5 Settings of frequency protection
Pickup setting of overfrequency

1 81O.f_Pkp 50~65 0.01 Hz
protection.
Frequency setting of stage 1 of

2 81O.OF1.f_Set 50~65 0.01 Hz
overfrequency protection.

3 81O.OF1.f_Set 50-65 0.01 Hz
Time delay of stage 1 of overfrequency

4 81O.OF1.t_Set 0.1~6000 0.001 s
protection.
0:disable Logic setting of enabling/disabling stage 1

5 81O.OF1.En
1:enable of overfrequency protection.
6 81O.OF1.OutMap. 0000~FF Tripping logic setting of stage 1 of

Date: 2011-10-19
3 Operation Theory
FF overfrequency protection.

7 81O.OF2.f_Set 50~65 0.01 Hz
8 81O.OF2.t_Set 0.1~6000 0.001 s Time delay of OF stage 2.

9 81O.OF2.En
0000~FF Tripping logic setting of stage 2 of

10 81O.OF2.OutMap.

11 81O.OF3.f_Set 50~65 0.01 Hz
Time delay of stage 3 of overfrequency

12 81O.OF3.t_Set 0.1~6000 0.001 s
protection.

13 81O.OF3.En

14 81O.OF3.OutMap.

15 81O.OF4.f_Set 50~65 0.01 Hz
16 81O.OF4.t_Set 0.1~6000 0.001 s Time delay of OF stage 4.

17 81O.OF4.En

18 81O.OF4.OutMap.
Pickup setting of underfrequency

19 81U.f_Pkp 40~60Hz 0.01 Hz
protection.
Setting of df/dt blocking underfrequency

20 81U.df/dt_Blk 0.05~20 0.01 Hz/s
protection.

21 81U.UF1.f_Set 45~60 0.01 Hz
underfrequency protection.
Time delay of stage 1 of underfrequency

22 81U.UF1.t_Set 0.1~6000 0.001 s
protection.
0:disable Logic setting of enabling/disabling stage

23 81U.UF1.En 1
1:enable 1 of underfrequency protection.
Logic setting of enabling/disabling df/dt

0:disable
24 81U.UF1.En_df/dt_Blk 1 blocking function for stage 1 of
1:enable

25 81U.UF1.OutMap
FF underfrequency protection.

Date: 2011-10-19
3 Operation Theory

26 81U.UF2.f_Set 45~60 0.01 Hz
0.1~6000 Time delay of stage 2 of underfrequency

27 81U.UF2.t_Set 0.001 s
s protection.

28 81U.UF2.En
1:enable of underfrequency protection.

0:disable
29 81U.UF2.En_df/dt_Blk blocking function for stage 2 of
1:enable

30 81U.UF2.OutMap

31 81U.UF3.f_Set 45~60 0.01 Hz

32 81U.UF3.t_Set 0.1~600s 0.001 s
protection.

33 81U.UF3.En
1:enable of underfrequency protection.

0:disable
1:enable

35 81U.UF3.OutMap

36 81U.UF4.f_Set 45~60 0.01 Hz

37 81U.UF4.t_Set 0.1~6000 0.001 s
protection.

38 81U.UF4.En
1:enable of underfrequency.

0:disable
1:enable

40 81U.UF4.OutMap

Date: 2011-10-19
3 Operation Theory
3.8 Mechanical Protection (MR)
3.8.1 Application
If there is a fault in transformer body, winding temperature relay, oil temperature relay and
buchholz relay (or called gas relay) integrated in transformer will operate to send signals to
transformer relay. Mechanical protection of transformer relay will repeat these signals to send
alarm signals, or send tripping command directly or send tripping command with time delay to
prevent transformer from damage. Inputs of mechanical protection are operation signals of
transformer integrated relay, and it is generally required to repeat those signals through
high-power relays to improve the anti-inference ability of the protection.
3.8.2 Function
Mechanical protection has following functions:
z High-power relays are adopted to improve the anti-inference ability of mechanical protection.
z Mechanical protection does not maloperate if 110Vac (or 220Vac) voltage is connected to the
terminal of mechanical relay signal input by mistake.
z Provide 4 mechanical signal input channels for tripping directly or with time delay.

Transformer relay repeats external signal through high-power relays and send them to CPU
through opto-coupler circuits. After CPU receives those signals, transformer relay will record them
as events and send tripping command with settable time delays. Because the drop out time of
mechanical input signals is usually too long, the setting [MR.t_PW_n] (n=1, 2, 3, and 4) can be set
to avoid the relay sending long-time tripping command.
3.8.4 Logic
EN [MR.En_n]
SIG [MR.En1] &
SIG [MR.En2] &

[MR.t_PW_n]
[MR.Opn]
SIG [MR.Blk]
SIG [MR.Inputn]
Figure 3.8-1 Logic Diagram of mechanical protection
z Function Enable/Disable
For mechanical protection, when following three conditions are met the stage protection is
enabled.
(1) Logic setting [MR.En_n] (n=1, 2, 3 or 4) is set to “1”.

Date: 2011-10-19
3 Operation Theory
(2) Enabling inputs [MR.En1], [50/51Pn.En2] are both set to “1”
(3) Blocking input [MR.Blk] is set to “0”.
When the protective function block is disabled, [MR.Op1], [MR.Op2], [MR.Op3] and [MR.Op4]
signals are both reset. Default values of Inputs [MR.En1], [MR.En2] are “1” and [MR.Blk] is 0 when
those inputs are not connected to external signals or settings.
Figure 3.8-2 Function block MR
Table 3.8-1 Input signals of function block MR

1 Input1 Mechanical relay (MR) signal input 1
7 Blk
Table 3.8-2 Output signals of function block MR

1 Sig1 Output signal of repeating MR signal input 1.
5 Op1 MR1 mechanical protection operates.

Date: 2011-10-19
3 Operation Theory
Table 3.8-3 Output signals of MR: report
1 MR.Op1 MR1 mechanical protection operates.
5 MR.Sig1 Output signal of repeating MR signal input 1
IO events of the protection.
3.8.6 Setting
Table 3.8-4 Settings of MR

Delay pickup time of tripping command of MR1
1 MR.t_DPU_1 0~3600 0.001 s
mechanical protection.
Pulse width of tripping command of MR1 mechanical
2 MR.t_PW_1 0~10 0.001 s
protection
0: disable
3 MR.En_1 Logic setting of enabling MR1 mechanical protection.
1: enable
Tripping logic setting of enabling MR1 mechanical
4 MR.OutMap_1 0000~FFFF
protection.
5 MR.t_DPU_2 0~3600 0.001 s
6 MR.t_PW_2 0~10 0.001 s
protection
0: disable
1: enable
protection.
9 MR.t_DPU_3 0~3600 0.001 s
10 MR.t_PW_3 0~10 0.001 s
protection
11 MR.En_3 0: disable Logic setting of enabling MR2 mechanical protection.

Date: 2011-10-19
3 Operation Theory

1: enable
protection.
13 MR.t_DPU_4 0~3600 0.001 s
14 MR.t_PW_4 0~10 0.001 s
protection
0: disable
1: enable
protection.
3.9 Phase Overcurrent Protection (50/51P)
3.9.1 Application
When a fault occurs in power system, the current increases and phase overcurrent protection
operates to avoid damages to protected equipment. Voltage control element can be selected to
improve the sensitivity of phase overcurrent protection and directional element can be selected to
improve the selectivity of the protection. In case that phase overcurrent protection operates
unexpectedly, harmonic blocking element can be selected to block the protection.
An external fault will result in transformer overload, and phase overcurrent protection operates to
trip circuit breakers of transformer to its avoid physical damage. To small transformers, phase
overcurrent protection can protect transformer from internal faults as main protection, to
large-scale transformers, no-directional protection is applied as the backup protection of
transformer differential protection.
3.9.2 Function
Phase overcurrent protection has following functions:
z Four-stage phase overcurrent protection with independent logic, current and time delay
settings.
inverse-time curve.
z Voltage control element can be selected to control each stage phase overcurrent protection.
z Directional element can be selected to control each stage phase overcurrent protection with
z Second harmonic can be selected to block each stage phase overcurrent protection.

Date: 2011-10-19
3 Operation Theory
3.9.3.1 Overview
Phase overcurrent protection consists of following four elements:
z Phase overcurrent element: each stage equipped with one independent ground overcurrent
element.
z Voltage control element: one voltage control element shared by all phase overcurrent
elements.
z Directional element: one directional element shared by all phase overcurrent elements, and
each stage protection can select protection direction.
z Harmonic blocking element: one harmonic blocking element shared by all phase overcurrent
elements.
Figure 3.9-1 Function diagram of phase overcurrent protection
The operation criterion of each stage ground overcurrent protection is:
I p > [x.50/51Pn.I_Set] Equation 3.9-1
Where:
I p is measured phase current.
[x.50/51Pn.I_Set] is the current setting of stage n (n=1, 2, 3, or 4) of phase overcurrent protection

Date: 2011-10-19
3 Operation Theory
of x side.
If any phase current is greater than the setting of any stage enabled phase overcurrent protection,
the stage phase overcurrent protection will operate after time delay if voltage control element
operates (or voltage control element not enabled), directional element operates (or directional
element not enabled), and the stage protection will drops off instantaneously after fault current
disappears.
3.9.3.3 Time Curve
Phase overcurrent protection stage 1, stage 2 and stage 3 are definite-time characteristic and
each stage can perform instantaneous operation with the corresponding time delay setting at zero.
Stage 4 can be selected as definite-time or inverse-time characteristic, and inverse-time operating
time curve is as follows.
⎛ ⎞
⎜ ⎟
K
t(I) = ⎜⎜ + C ⎟⎟ × TP Equation 3.9-2
I α
⎜⎜ ( I ) −1 ⎟⎟
⎝ set ⎠
Where:
I set is current setting [x.51P4.I_Set].
T p is time multiplier setting [x.51P4.TMS].
K , C is constants.
α is a constant.
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [x.50/51P4.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.
Table 3.9-1 Inverse-time curve parameters of stage 4 phase overcurrent protection
x.51P4.Opt_Curve Time Characteristic K α C
0 Definite time
1 IEC Normal inverse 0.14 0.02 0
2 IEC Very inverse 13.5 1.0 0
3 IEC Extremely inverse 80.0 2.0 0
4 IEC Short-time inverse 0.05 0.04 0
5 IEC Long-time inverse 120.0 1.0 0
6 ANSI Extremely inverse 28.2 2.0 0.1217

Date: 2011-10-19
3 Operation Theory
7 ANSI Very inverse 19.61 2.0 0.491
8 ANSI Inverse 0.0086 0.02 0.0185
9 ANSI Moderately inverse 0.0515 0.02 0.114
10 ANSI Long-time extremely inverse 64.07 2.0 0.25
11 ANSI Long-time very inverse 28.55 2.0 0.712
12 ANSI Long-time inverse 0.086 0.02 0.185
13 Programmable user-defined
If all available curves do not comply with user application, user may select [x.50/51P4.Opt_Curve]
at“13” to customize the inverse-time curve characteristic, and setting constants K , α and C .
Define-time or inverse-time phase overcurrent protection drops off instantaneously.
3.9.3.4 Voltage Control Element
Phase overcurrent protection is equipped as the backup protection of transformer and adjacent
power equipment, and voltage is usually used to control phase overcurrent protection to improve
sensitivity of the protection. Unsymmetrical faults result in unsymmetrical sequence voltages and
symmetrical faults lead to low three phase voltages at relay location, so phase overcurrent
protection can operate if the sequence voltage greater than a setting or phase voltage lower than a
setting. Therefore, current settings of phase overcurrent protection can be set lower with high
sensitivity.
z Operation criterion of VCE
The voltage control element picks up if phase-to-phase voltage is lower than its setting or
negative-sequence voltage is greater than its setting.
Criteria:
U ΦΦ < [x.50/51P.Upp_VCE] or U 2 > [x.50/51P.U2_VCE] Equation 3.2-3
Where:
U ΦΦ is the phase-to-phase voltage of x side.
U 2 is the negative-sequence voltage of x side.
[x.50/51P.Upp_VCE] is the phase-to-phase undervoltage setting of x side.
[x.50/51P.U2_VCE] is the negative-sequence overvoltage setting of x side.
Voltage of any side can be used as the input of voltage control element, and there are logic
settings used to select which side voltage control element to control OC protection of some side.

Date: 2011-10-19
3 Operation Theory
Table 3.9-2 Voltage used for VCE
Overcurrent Element Voltage for Controlling

Ia> Uab< or Uca< or U2>
Ib> Ubc< or Uab< or U2>
Ic> Uca< or Ubc< or U2>
In above table, Uab, Ubc and Uca are phase-to-phase voltage, and U2 is negative-sequence
voltage.
z Effect of VT Circuit
When VT circuit fails (i.e. message [x.Alm_VTS] being issued) or VT is not put into service (i.e.
[x.In_VT] is “0”), then voltage control element resets instantaneously and voltage controlled phase
overcurrent protection is blocked, and if the setting is set to”0” then voltage control element picks
up automatically and voltage controlled phase overcurrent protection becomes non-directional
phase overcurrent protection.
3.9.3.5 Directional Element
Directional element can be selected to control phase overcurrent protection to coordinate with
other protections of power grid. If the element is selected for phase overcurrent protection, then
the protection becomes directional overcurrent protection.
Positive-sequence voltage (U1) is adopted as polarizing voltage, and memory voltage is used
during close-up faults to ensure the directional element working properly. Phase current (Ip) is
adopted for calculation of directional element, and if current is less than current threshold, neither
of forward and reverse directions is met.
&
When a fault occurs at forward direction, the angle between polarizing voltage U ref and fault
current I&dir is:
U&
ϕ k = arg & ref Equation 3.9-3
I dir
When a fault occurs at reverse direction, the angle is:
U&
ϕ ′k = arg & ref = 180° + ϕ k Equation 3.9-4
I dir
Relay characteristic angle ϕ sen (setting [x.50/51P.RCA]), i.e. the angle polarizing voltage leading
fault current, is given as the directional setting, and the forward operating range is:
U ref <
ϕ sen − 90° < arg ϕ sen + 90° Equation 3.9-5
I dir

Date: 2011-10-19
3 Operation Theory
Table 3.9-3 Current and voltage used for directional element
Phase Current Polarizing voltage

A Ia U1
B Ib U1
C Ic U1
In above table, U1 is positive-sequence voltage.
If VT and CT are connected as Figure 3.9-2 shown, i.e. polarity of CT is at busbar side, and
forward direction is to protected object, then forward and reverse operating regions are shown
in Figure 3.9-3.
Figure 3.9-2 Connection of VT and CT of directional element
NOTE! Symbol ” ” represents the polarity of current transformer.
Reverse
Uref(U1)
Φsen
Φsen+180°
Idir(Ip)
Forward
Figure 3.9-3 Directional characteristic of phase overcurrent protection
When VT circuit fails (i.e. message [x.Alm_VTS] being issued) or VT is not put into service (i.e.
[x.In_VT] is “0”), if setting [x.50/51Pn.En_VTS_Blk] is set to “1”, then directional element resets
instantaneously and directional phase overcurrent is blocked, and if the setting is set to”0” then

Date: 2011-10-19
3 Operation Theory
directional element picks up automatically and directional phase overcurrent becomes

non-directional ground overcurrent protection.
3.9.3.6 Harmonic Blocking Element
When phase overcurrent protection is set to protect transformer during transformer energization,
in order to prevent inrush current leading to maloperation of phase overcurrent protection,
harmonic blocking function can be selected for every stage of this relay.
Blocking mode is selectable between phase segregated blocking mode or phase crossing blocking
mode through the setting [x.50/51P.Opt_Hm_Blk], “0” for phase segregated blocking mode and “1”
for phase crossing blocking mode. If any phase harmonic meets the following criterion, harmonic
blocking condition is satisfied. But when any phase current is greater than the setting
[50/51P.I_Rls_HmBlk], phase overcurrent protection dose not be blocked by harmonic even if
blocking condition is satisfied.
I p _ 2nd > [ x.50 / 51P.K _ Hm2] × I p Equation 3.9-6
Where:
I p _ 2 nd is second harmonic of phase current
Ip is fundamental component of phase current.
[x.50/51P.K_Hm2] is harmonic blocking coefficient and recommended value is 0.15.
If fundamental component of any phase current is lower than the minimum operating current
（0.04In）, then harmonic calculation is not carried out and harmonic blocking element does not
operate.
3.9.4 Logic
Logic diagram of phase overcurrent is shown in the following figure, including phase overcurrent
element, voltage control element and directional element, harmonic blocking element and
enabling and blocking logic of the protection.
Logic schemes of phase overcurrent protection of each stage are same except that stage 4 can be
selected as inverse-time characteristic, and that stage 4 is taken as an example to show the logic.

Date: 2011-10-19
3 Operation Theory
EN [50/51Pn.En]
SIG [50/51Pn.En1] &
SIG [50/51Pn.En2]
SIG [50/51Pn.Blk]
SIG [50/51P.I3P]
SET [x.50/51Pn.I_Set]
Direction
&
SIG [U3P] Check
≥1
Fwd/Rev
Non-Dir
SET [x.50/51Pn.Opt_Dir] & &
[x.50/51Pn.St]
SIG [x.Alm_VTS] &

Timer
t
SET [x.50/51P.En_VTS_Blk] [x.50/51Pn.Op]
t
& Inverse for OC4 only
SIG Sig_U2 or Sig_Upp
SIG I3P 2nd Hm Detect &
SET [50/51Pn.En_Hm2_Blk]
Figure 3.9-4 Logic Diagram of phase overcurrent protection of x side (50/51Pn, n=1, 2, 3, 4)
UΦΦ
Figure 3.9-5 Logic Diagram of phase-to-phase VCE
U2
Figure 3.9-6 Logic Diagram of negative-sequence VCE

Date: 2011-10-19
3 Operation Theory
Where:
U ΦΦ is the phase-to-phase voltage of one side.
U 2 is the negative-sequence voltage of one side.
Sig_Upp is the internal operation signal of phase-to-phase undervoltage element.
Sig_U2 is the internal operation signal of negative-sequence voltage element.
z Function Enable/Disable
For any stage phase overcurrent protection, when following three conditions are met the stage
protection is enabled.
(1) Logic setting [50/51Pn.En] is set to “1”.
(2) Enabling inputs [50/51Pn.En1], [50/51Pn.En2] are both set to “1”
(3) Blocking input [50/51Pn.Blk] is set to “0”.
When the protective function block is disabled, [50/51Pn.St], [50/51Pn. Op] signals are both reset.
Default values of Inputs [50/51Pn.En1], [50/51Pn.En2] are “1” and [50/51Pn.Blk] is 0 when those
inputs are not connected to external signals or settings.
50/51P
I3P St
U3P Op
En1
En2
Blk
Figure 3.9-7 Function block 50/51P (Each stage）
Table 3.9-4 Input signals of function block 50/51P (Each stage）

1 I3P Three phase current data, including calculated residual current.
2 U3P Three phase voltage data, including calculated residual voltage.
5 Blk
Table 3.9-5 Output signals of function block 50/51P (Each stage）


Date: 2011-10-19
3 Operation Theory

signals are only for LCD display of equipment.
Table 3.9-6 Output signals of 50/51P: report
No. Input Signal Description
1 x.50/51P1.Op Phase overcurrent protection stage 1 of x side operates.
2 x.50 /51P2.Op Phase overcurrent protection stage 2 of x side operates.
3 x.50/51 P3.Op Phase overcurrent protection stage 3 of x side operates.
4 x.50/51P4.Op Phase overcurrent protection stage 4 of x side operates.
5 x.50/51P1.St Phase overcurrent protection stage 1 of x side starts.
Phase overcurrent protection stage 1 of x side picks up to trigger DFR

9 x.50/51P1.TrigDFR
function.

10 x.50/51P2. TrigDFR
function.

function.

function.
3.9.6 Settings
Table 3.9-7 Settings of control and blocking elements settings of 50/51P
1 x.50/51P.Upp_VCE 2~200 0.001 V Phase-to-phase undervoltage setting.
2 x.50/51P.U2_VCE 2~200 0.001 V Negative-sequence overvoltage setting.
Relay characteristic angle of phase overcurrent
3 x.50/51P.RCA 0~360 1 deg
protection.
4 x.50/51P.K_Hm2 0.05~1.0 0.001 Harmonic blocking coefficient of ground overcurrent

Date: 2011-10-19
3 Operation Theory

protection.
Current setting of releasing harmonic blocking
5 x.50/51P.I_Rls_HmBlk 0.04~150 0.001 A
function of phase overcurrent protection.
Logic setting of selecting blocking mode of
harmonic.
6 x.50/51P.Opt_Hm_Blk 0~1 1
“0”: phase segerated blocking mode;
“1”: phase crossing blocking mode.
Logic setting of enabling voltage controlled phase
0: disable
7 x.50/51P.En_VTS_Blk 1 overcurrent protection being blocked during VT
1: enable
circuit failure.
Table 3.9-8 Settings of 50/51P Stage n (n=1,2,3)

Current setting of stage n of phase overcurrent
1 x.50/51Pn.I_Set 0.04A~30In 0.001 A
protection.
Time delay of stage n of phase overcurrent
2 x.50/51Pn.t_Op 0~3600 0.001 s
protection.
0: disable Logic setting of enabling voltage control element
3 x.50/51Pn.En_VCE
1: enable for phase overcurrent protection.
Logic setting of selecting control mode of
directional element to stage n of phase overcurrent
protection.
4 x.50/51Pn.Opt_Dir 0~2 1
0: no direction;
1: forward direction;
2: reverse direction
Logic setting of enabling harmonic blocking stage
0: disable
5 x.50/51Pn.En_Hm2_Blk 1 n of phase overcurrent protection.
1: enable
0: disable; 1: enable
Logic setting of enabling stage n of phase
0: disable
6 x.50/51Pn.En 1 overcurrent protection.
1: enable
Tripping logic setting of stage n of phase
7 x.50/51Pn.OutMap 0000~FFFF
overcurrent protection.
Table 3.9-9 Settings of 50/51P Stage 4

Pickup setting of stage 4 of phase overcurrent
1 x.50/51P4.I_Set 0.04A~30In 0.001 A
protection.
Multiple of the maximum operating current to the
2 x.50/51P4.K_Iset 10~40 0.001 pickup setting of stage 4 of phase overcurrent
protection.
Time delay of stage 4 of phase overcurrent
3 x.50/51P4.t_Op 0~3600 0.001 s
protection.

Date: 2011-10-19
3 Operation Theory

Time multiplier setting of stage 4 of phase
4 x.50/51P4.TMS 0.05~3.2 0.001
Minimum delay of stage 4 of phase overcurrent
5 x.50/51P4.tmin 0~20 0.001 s
protection.
The constant K of stage 4 of phase overcurrent
6 x.50/51P4.K 0~120 0.001
protection.
The constant C stage 4 of phase overcurrent
7 x.50/51P4.C 0~20 0.001 s
protection.
The exponent alpha stage 4 of phase overcurrent
8 x.50/51P4.Alpha 0.02~5 0.001
protection.
Logic setting for selecting operating characteristic
9 x.50/51P4.Opt_Curve 0~13 1 curve of stage 4 of phase overcurrent protection.
Please refer to Section 3.9.3.3 for details.
0: disable Logic setting of enabling voltage control element
10 x.50/51P4.En_VCE 1
1: enable for phase overcurrent protection.
Logic setting of selecting control mode of
directional element to stage 4 of phase overcurrent
protection.
11 x.50/51P4.Opt_Dir 0~2 1
0: no direction;
1: forward direction;
0: disable
12 x.50/51P4.En_Hm2_Blk 1 4 of phase overcurrent protection.
1: enable
Logic setting of enabling stage 4 of phase
0: disable
13 x.50/51P4.En 1 overcurrent protection.
1: enable
Tripping logic setting of stage 4 of phase
14 x.51P4.OutMap 0000~FFFF
NOTE! If the minimum operating time [x.51P4.tmin] is set to “0”, the maximum operating
current is valid. That means the multiple of current the operating time of IDMT become
flat [x.51P4.K_Iset] can be set according to requirements and when the current is
greater than [x.51P4.K_Iset]x[x.51P4.I_Set], the operating time of IDMT becomes flat. If
[x.51P4.tmin] is not set to “0”, then maximum operating current is not valid and use only
can set the setting [x.51P4.tmin].
3.10 Ground Overcurrent Protection (50/51G)
3.10.1 Application
During normal operation of power system, there is trace residual current whereas a fault current

Date: 2011-10-19
3 Operation Theory
flows to earth will result in greater residual current. Therefore residual current is adopted for the
calculation of ground overcurrent protection.
In order to improve the selectivity of ground overcurrent protection in power grid with multiple
power sources, directional element can be selected to control ground overcurrent protection. For
application on transformer circuits, second harmonic also can be selected to block ground
overcurrent protection to avoid the effect of sympathetic current on the protection.
3.10.2 Function
Ground overcurrent protection has following functions:
z Four-stage ground overcurrent protection with independent logic, current and time delay
settings.
inverse-time curve.
z Directional element can be selected to control each stage ground overcurrent protection with
z Second harmonic can be selected to block each stage ground overcurrent protection.
z Measured neutral current or calculated residual current can be selected for the calculation of
ground overcurrent protection.
3.10.3.1 Overview
Ground overcurrent protection consists of following three elements:
z Ground overcurrent element: each stage equipped with one independent ground overcurrent
element.
z Directional element: one directional element equipped shared by all ground overcurrent
elements, and each stage protection can select protection direction.
z Harmonic blocking element: one harmonic blocking element shared by all ground
overcurrent elements.

Date: 2011-10-19
3 Operation Theory
Stage1
St
Ground
Op
Overcurrent
Element
3U0 from I3P

Stage2
Direction Direction signal St
Element Ground
[Alm_VTS] Op
Overcurrent
Element
3I0 from I3P

or IN from I0P Stage3
St
Ground
Op
Overcurrent
Harmonic
Hm blocking signal Element
Blocking
Element
Stage4
St
Ground
Op
Overcurrent
Element
Figure 3.10-1 Function diagram of ground overcurrent protection
The operation criterion of each stage ground overcurrent protection is:
3 I 0 >[x.50/51Gn.3I0_Set]
Equation 3.10-1
Or 3 I 0 >[ x.50/51Gn.3I0_Set]
Where:
3I 0 is measured neutral current or calculated residual current, which is selected by user through
the setting [x.50/51Gn.Opt_3I0], n (n=1, 2 or 3) or [x.50/51G4.Opt_3I0].
[x.50/51Gn.3I0_Set] is the current setting of stage n (n=1, 2 or 3) of ground overcurrent protection

of x side.
If ground current is greater than the setting of any stage enabled ground overcurrent protection,
the stage ground overcurrent protection will operate after time delay if directional element operates
(or directional element not enabled) and no harmonic detected (or harmonic blocking not enabled),
and the stage protection will drops off instantaneously after fault current disappears.
3.10.3.3 Time Curve
Ground overcurrent protection stage 1, stage 2 and stage 3 are definite-time characteristic and
each stage can perform instantaneous operation with the corresponding time delay setting at zero.
Stage 4 can be selected as definite-time or inverse-time characteristic, and inverse-time operating
time curve is as follows.

Date: 2011-10-19
3 Operation Theory
⎛ ⎞
⎜ ⎟
K
t(I) = ⎜⎜ + C ⎟⎟ × TP Equation 3.10-2
I α
⎜⎜ ( ) −1 ⎟⎟
⎝ I set ⎠
Where:
I set is residual current setting [x.50/51G4.3I0_Set].
T p is time multiplier setting [x.50/51G4.TMS].
K , C is constants.
α is a constant.
I is actual value of measured current from the neutral CT or calculated residual current.
setting [x.50/51G4.Opt_Curve], and parameters of available characteristics for selection are
shown in the following table.
Table 3.10-1 Inverse-time curve parameters of stage 4 ground overcurrent protection
x.50/51G4.Opt_Curve Time Characteristic K α C
0 Definite time
8 ANSI Inverse 0.0086 0.02 0.0185
13 Programmable User-defined
If all available curves do not comply with user application, user may setting [x.50/51G4.Opt_Curve]

Date: 2011-10-19
3 Operation Theory
at“13”to customize the inverse-time curve characteristic, and constants K , α and C with
configuration tool software.
Define-time or inverse-time phase overcurrent protection drops off instantaneously.
3.10.3.4 Residual Direction Element
Calculated residual voltage (3U0) is adopted as polarizing quantity (i.e. polarizing voltage) of
residual directional element. When the neutral current (IN) is selected for the calculation of ground
overcurrent, it is the operating quantity (i.e. fault current), and when calculated residual current
(3I0) is selected, it is the operating quantity.
&
When a fault occurs at forward direction, the angle polarizing voltage U ref leading fault current
I&dir is:
U&
ϕ k = arg & ref Equation 3.10-3
I dir
When a fault occurs at reverse direction, the angle is:
U&
ϕ ′k = arg & ref = 180° + ϕ k Equation 3.10-4
I dir
Relay characteristic angle ϕ sen (setting [x.50/51G.RCA]), i.e. the angle polarizing voltage leading
fault current, is given as the directional setting, and the forward operating range is:
U ref <
ϕ sen − 90° < arg ϕ sen + 90° Equation 3.10-5
I dir
If VT and CT are connected as Figure 3.10-2 shown, i.e. polarity of CT is at busbar side, and
forward direction is to protected object, then forward and reverse operating regions are shown in
following Figure 3.10-3.
Figure 3.10-2 Connection of VT and CT of directional element

Date: 2011-10-19
3 Operation Theory
NOTE! Symbol ” ” represents the polarity of current transformer.
Figure 3.10-3 Directional characteristic of ground overcurrent protection
When VT circuit fails (i.e. message [x.Alm_VTS] being issue) or VT is not put into service (i.e.
[x.In_VT] is “0”), if setting [x.50/51Gn.En_VTS_Blk] is set to “1”, then residual directional element
resets instantaneously and directional ground overcurrent is blocked, and if the setting is set to”0”
then residual directional element picks up automatically and directional ground overcurrent
becomes non-directional ground overcurrent protection.
3.10.3.5 Harmonic Blocking Element
In order to prevent effects of sympathetic inrush current on ground overcurrent relay, harmonics
blocking function can be selected for every stage of this relay.
When the percent of second harmonic to fundamental component of zero sequence current is
greater than setting [x.50/51G.K_Hm2], harmonic blocking element operates to block ground
overcurrent protection if logic setting [x.50/51Gn.En_Hm2_Blk] (n=1, 2, 3 or 4) enabled
When residual current is greater than the setting [x.50/51G.3I0_Rls_HmBlk], ground overcurrent
protection dose not be blocked by harmonic even if following blocking criterion is satisfied.
I 0 _ 2nd > [ x.50 / 51G.K _ Hm2] × I 0 Equation 3.10-6
Where:
I 0 _ 2nd is second harmonic of zero sequence current
I 0 is fundamental component of zero sequence current.
[x.51/51G.K_Hm2] is harmonic blocking coefficient.

Date: 2011-10-19
3 Operation Theory
If fundamental component of zero sequence current is lower than the minimum operating current
(0.4In) then harmonic calculation is not carried out and harmonic blocking element does not
operate.
3.10.4 Logic
Logic diagram of ground overcurrent is shown in the following figure, including phase overcurrent
element, directional element, voltage control element, harmonic blocking element and enabling
and blocking logic of the protection.
Logic schemes of ground overcurrent protection of each stage are same except that stage 4 can
be selected as inverse-time characteristic, and that stage 4 is taken as an example to show the
logic.
Figure 3.10-4 Logic Diagram of ground overcurrent protection of x side (50/51Gn, n=1,2,3,4)
Where:
3I0 is calculated residual current.
IN is measured neutral current.
For any stage ground overcurrent protection, when following three conditions are met the stage
(1) Logic setting [50/51Gn.En] is set to “1”.
(2) Enabling inputs [50/51Gn.En1], [50/51Gn.En2] are both set to “1”.

Date: 2011-10-19
3 Operation Theory
(3) Blocking input [50/51Gn.Blk] is set to “0”.
When the protective function block is disabled, [50/51Gn.St], [50/51Gn.Op] signals are both reset.
Default values of Inputs [50/51Gn.En1] and [50/51Gn.En2] are “1” and [50/51Gn.Blk] is “0” when

Each stage ground overcurrent protection has the identical function block shown as follows.
Figure 3.10-5 Function block 50/51G (each stage)
Table 3.10-2 Input signals of function block 50/51G (each stage)

2 I1P Measured neutral current data.
6 Blk
Table 3.10-3 Output signals of function block50/51G (each stage)

Table 3.10-4 Output signals of 50/51G: report

Date: 2011-10-19
3 Operation Theory
1 x.50/51G1.Op Ground overcurrent protection stage 1 of x side operates.
5 x.50/51G1.St Ground overcurrent protection stage 1 of x side starts.
9 x.50/51G1. TrigDFR Ground overcurrent protection stage 4 of x side picks up to trigger DFR function.
3.10.6 Settings
Table 3.10-5 Settings of control and blocking elements of 50/51G

Relay characteristic angle of ground overcurrent
1 x.50/51G.RCA 0~360 1 deg
protection
Harmonic blocking coefficient of ground overcurrent
2 x.50/51G.K_Hm2 0.05~1.0 0.001
protection
Current setting of releasing harmonic blocking
3 x.50/51G.3I0_Rls_HmBlk 0.04~150 0.001 A
function of ground overcurrent protection.
0: disable Logic setting of enabling ground overcurrent
4 x.50/51G.En_VTS_Blk 1
1: enable protection being blocked during VT circuit failure
Table 3.10-6 Settings of 50/51G Stage n (n=1,2,3)

Current setting of stage n of ground overcurrent
1 x.50/51Gn.3I0_Set 0.04A~30In 0.001 A
protection
Time delay of stage n of ground overcurrent
2 x.50/51Gn.t_Op 0~3600 0.001 s
protection
Logic setting of selecting control mode of residual
3 x.50/51Gn.Opt_Dir 0~2 1 directional element to stage n of ground

Date: 2011-10-19
3 Operation Theory

0: no direction
1: forward direction
Logic setting of selecting residual current for the
calculation of stage n of ground overcurrent
4 x.50/51Gn.Opt_3I0 0~1 1 protection:
0: Measured residual current
1: Calculated residual current
0: disable
5 x.50/51Gn.En_Hm2_Blk 1 n of ground overcurrent protection.
1: enable
Logic setting of enabling stage n of ground
0: disable
6 x.50/51Gn.En 1 overcurrent protection.
1: enable
Tripping logic setting of stage n of ground
7 x.50/51Gn.OutMap 0000~FFFF
overcurrent protection
Table 3.10-7 Settings of 50/51G stage 4

Pickup setting of stage 4 of ground overcurrent
1 x.50/51G4.3I0_Set 0.04A~30In 0.001 A
protection
Multiplier of the maximum operating residual
2 x.50/51G4.K_3I0set 10~40 0.001 current to the pickup setting of stage 4 of ground
Time delay of stage 4 of ground overcurrent
3 x.50/51G4.t_Op 0~3600 0.001 s
protection.
Time multiplier setting of stage 4 of ground
4 x.50/51G4.TMS 0.05~3.2 0.001
Minimum delay of stage 4 of ground overcurrent
5 x.50/51G4.tmin 0~20 0.001 s
protection.
The constant K of stage 4 of ground overcurrent
6 x.50/51G4.K 0~120 0.001
protection.
The constant C stage 4 of ground overcurrent
7 x.50/51G4.C 0~20 0.001 s
protection.
The exponent alpha stage 4 of ground overcurrent
8 x.50/51G4.Alpha 0.02~5 0.001
protection.
curve of stage 4 of ground overcurrent protection.
9 x.50/51G4.Opt_Curve 0~13 1
Please refer to Please refer to Section 3.10.3.3 for
details.
Logic setting of selecting control mode of residual
10 x.50/51G4.Opt_Dir 0~2 1
directional element to stage 4 of ground

Date: 2011-10-19
3 Operation Theory

0: no direction
1: forward direction
Logic setting of selecting residual current for the
calculation of stage 4 of ground overcurrent
11 x.50/51G4.Opt_3I0 0~1 1 protection:
0: Measured residual current
1: Calculated residual current
0: disable
12 x.50/51G4.En_Hm2_Blk 1 4 of ground overcurrent protection.
1: enable
Logic setting of enabling stage 4 of ground
0: disable
13 x.50/51G4.En 1 overcurrent protection.
1: enable
Tripping logic setting of stage 4 of ground
14 x.50/51G4.OutMap 0000~FFFF
overcurrent protection
NOTE! If the minimum operating time [x.51G4.tmin] is set to “0”, the maximum operating
current is valid. That means the multiple of current the operating time of IDMT become
flat [x.51G4.K_Iset] can be set according to requirements and when the current is
greater than [x.51G4.K_Iset]x[x.51P4.I_Set], the operating time of IDMT becomes flat. If
[x.51G4.tmin] is not set to “0”, then maximum operating current is not valid and use only
3.11 Phase Overvoltage Protection (59P)
3.11.1 Application
In the power system, when users operating circuit breakers or a fault occurring, system
parameters will change, which can cause the power system electromagnetic energy converting
and transferring and overvoltage will appears in the system. Overvoltage protection is equipped for
the protection of electric equipment and its insulation.
3.11.2 Function
Phase overvoltage protection has following functions:
z Two-stage phase overvoltage protection with independent logic, voltage and time delay
settings.
z Stage 1 and stage 2 definite-time characteristic, stage 2 can be selected as definite-time or

Date: 2011-10-19
3 Operation Theory
z Phase voltage or phase-to-phase voltage can be selected for protection calculation.
z “1 out of 3” or “3 out of 3” logic can be selected for protection criterion.
Users can select phase voltage or phase-to-phase voltage for the protection calculation. If setting
[x.59Pn.En_Vpp] is set to “0”, phase voltage criterion is selected and if [x.59Pn_En_Vpp] is set to
“1”, phase-to-phase voltage criterion is selected.
When phase voltage or phase-to-phase voltage is greater than one stage voltage setting,
corresponding stage protection picks up and operate after delay, which will drop off
instantaneously when fault voltage disappears.
z Phase voltage criterion
Two operation criteria of definite-time overvoltage protection are as follows, which of them is
selected depending on the logic setting [x.59Pn.Opt_1P/3P].
U Φ _ max > [ x.59Pn.U_Set] Equation 3.11-1
⎧ U a > [x.59Pn.U_Set]
⎪
⎨ U b > [x.59Pn.U_Set] Equation 3.11-2
⎪ U > [x.59Pn.U_Set]
⎩ c
Where:
U Φ _ max is the maximum value of three phase-voltage.
U a,U b,U c are three phase voltages..
[x.59Pn.U_Set] is the setting of stage n (n=1 or 2) overvoltage protection of the corresponding

side.
When [x.59Pn.Opt_1P/3P] is set as “0” “1 out of 3” logic (i.e. Equation 3.11-1) is selected as
operation criterion, and when set as “1”, “3 out of 3” logic (i.e. Equation 3.11-2) is selected.
z Phase-to-phase voltage criterion

Two operation criteria of definite-time overvoltage protection are as follows, which of them is
selected depending on the logic setting [x.59Pn.Opt_1P/3P].
U ΦΦ _ max > [x.59Pn.U_Set] Equation 3.11-3

Date: 2011-10-19
3 Operation Theory
⎧ U ab > [x.59Pn.U_Set]
⎪
⎨ U bc > [x.59Pn.U_Set] Equation 3.11-4
⎪ U > [x.59Pn.U_Set]
⎩ ca
Where:
U ΦΦ _ max is the maximum value of phase-to-phase value of one side.
U ab , U bc U ca are phase-to-phase voltages of one side.
[x.59Pn.U_Set] is the setting of stage n (n=1 or 2) overvoltage protection of the corresponding

side.
When [x.59Pn.Opt_1P/3P] is set as “0” “1 out of 3” logic (Equation 3.11-3) is selected as operation
criterion, and when set as “1”, “3 out of 3” logic (Equation 3.11-4) is selected.
3.11.3.2 Time Curve
Phase overvoltage protection stage 1 is definite-time characteristic and can perform instantaneous
operation with the corresponding time delay setting at zero. Stage 2 can be selected as
definite-time or inverse-time characteristic, and inverse-time operating time curve is as follows.
⎛ ⎞
⎜ ⎟
⎜ K
t(I) = + C ⎟ × TP Equation 3.11-5
⎜ U α ⎟
⎜ ( U ) −1 ⎟
⎝ set ⎠
Where:
U set is voltage setting [x.59P2.U_Set].
T p is time multiplier setting [x.59P2.TMS].
K , C is constants.
α is a constant.
U is actual measured phase voltage (or phase-to-phase voltage) value.
setting [x.59P2.Opt_Curve], and parameters of available characteristics for selection are shown in
the following table.
Table 3.11-1 Inverse-time curve parameters of stage 2 phase overvoltage protection

Date: 2011-10-19
3 Operation Theory
0 Definite time
8 ANSI Inverse 0.0086 0.02 0.0185
If all available curves do not comply with user application, user may setting [x.59P2.Opt_Curve] at
“13” to customize the inverse-time curve characteristic, and constants K , α and C with
Define-time or inverse-time phase overvoltage protection drops off instantaneously.
3.11.4 Logic
EN [59Pn.En]
SIG [59Pn.En1] &
SIG [59Pn.En2]
SIG [59Pn.Blk]
&
SIG [x.59Pn.U3P] [x.59Pn.St]
SET [x.59Pn.U_Set] Timer

t
[x.59Pn.Op]
t
Inverse for OV2 only
Figure 3.11-1 Logic diagram of residual overvoltage protection (59Pn, n=1,2)
For any stage phase overvoltage protection, when following three conditions are met the stage

Date: 2011-10-19
3 Operation Theory
(1) Logic setting [59Pn.En] is set to “1”.
(2) Enabling inputs [59Pn.En1], [59Pn.En2] are both set to “1”
(3) Blocking input [59Pn.Blk] is set to “0”.
When the protective function block is disabled, [59Pn.St], [59Pn.Op] signals are both reset. Default
values of Inputs [59Pn.En1], [59Pn.En2] are “1” and [59Pn.Blk] is “0” when those inputs are not
59P
I3P St
U3P Op
En1
En2
Blk
Figure 3.11-2 Function block 59G (Each stage)
Table 3.11-2 Input signals of function block 59G (Each stage)

4 Blk
Table 3.11-3 Output signals of function block 59G（Each stage）

1 St Protection start
2 Op Protection operate
Table 3.11-4 Output signals of 59G: report
1 x.59P1.Op Phase overvoltage protection stage 1 of x side operates.

Date: 2011-10-19
3 Operation Theory
2 x.59P2.Op Phase overvoltage protection stage 2 of x side operates.
3 x.59P1.St Phase overvoltage protection stage 1 of x side starts.
4 x.59P2.St Phase overvoltage protection stage 2 of x side starts.
Phase overvoltage protection stage 1 of x side picks up to trigger DFR

5 x.59P1.TrigDFR
function.
Phase overvoltage protection stage 2 of x side picks up to trigger DFR

6 x.59P2.TrigDFR
function.
3.11.6 Settings
Table 3.11-5 Settings of 59P Stage 1

Voltage setting of stage 1 of phase overvoltage
1 x.59P1.U_Set 2~200 0.001 V
protection.
Time delay of stage 1 of phase overvoltage
2 x.59P1.t_Op 0~3600 0.001 s
protection.
3 x.59P1.Opt_Up/Upp 0/1 1 phase-to-phase voltage for protection of stage 1 of
phase overvoltage protection.
Logic setting of selecting “1 out of 3” or “3 out of 3”
4 x.59P1.Opt_1P/3P 0/1 1 logic for operation criterion of stage 1 of phase
overvoltage protection.
0: disable Logic setting of enabling stage 1 of phase
5 x.59P1.En 1
1: enable overvoltage protection.
Table 3.11-6 Settings of 59P Stage 2

Pickup setting of stage 2 of phase overvoltage
1 x.59P2.U_Set 2~200 0.001 V
protection.
Multiplier of the maximum operating voltage to the
2 x.59P2.K_Uset 1~10 0.001 pickup setting of stage 2 of phase overvoltage
protection.
Time delay of stage 2 of phase overvoltage
3 x.59P2.t_Op 0~3600 0.001 s
protection.
4 x.59P2.Opt_Vp/Vpp 0~1 1
phase-to-phase voltage for protection of stage 2 of

Date: 2011-10-19
3 Operation Theory

phase overvoltage protection.
Logic setting of selecting “1 out of 3” or “3 out of 3”
5 x.59P2.Opt_1P/3P 0~1 1 logic for operation criterion of stage 2 of phase
Time multiplier setting of stage 2 of phase
6 x.59P2.TMS 0.05~3.2 0.001
Minimum delay of stage 2 of phase overvoltage
7 x.59P2.tmin 0~20s 0.001 s
protection.
The constant K of stage 2 of phase overvoltage
8 x.59P2.K 0~120 0.001
protection.
The constant C stage 2 of phase overvoltage
9 x.59P2.C 0~20 0.001 s
protection.
The exponent alpha stage 2 of phase overvoltage
10 x.59P2.Alpha 0.02~5 0.001
protection.
11 x.59P2.Opt_Curve 0~13 1 curve for stage 2 of phase overcurrent protection.
Logic setting of enabling stage 2 of phase
0: disable
12 x.59P2.En 1 overvoltage protection.
1: enable
NOTE! If the minimum operating time [x.51P2.tmin] is set to “0”, the maximum operating
voltage is valid. That means the multiple of voltage the operating time of IDMT become
flat [x.51P2.K_Iset] can be set according to requirements and when the voltage is
greater than [x.51P2.K_Iset]x[x.51P4.I_Set], the operating time of IDMT becomes flat. If
[x.51P2.tmin] is not set to “0”, then maximum operating voltage is not valid and use only
3.12 Residual Overvoltage Protection (59G)
3.12.1 Application
A single phase earth fault in ungrounded system or Peterson coil grounded system will result in
residual overvoltage, so residual overvoltage protection is equipped to prevent protected
equipment being damaged by residual overvoltage in this condition.
3.12.2 Function
Residual overvoltage protection has following functions
z Two-stage residual overvoltage protection with independent logic, voltage and time delay
settings.

Date: 2011-10-19
3 Operation Theory
z Stage 1 is definite-time characteristic, stage 2 can be selected as definite-time or

3U 0 > [x.59Gn.3U0_Set] （公式 3.12-1）
Where:
3U 0 is measured residual voltage.
[x.59Gn.3U0_Set] is the voltage setting of stage n (n=1 or 2) of residual overvoltage protection.
If residual current is greater than the setting of any stage enabled residual overvoltage protection,
the stage residual overvoltage protection will operate after time delay and the stage protection will
drops off instantaneously after fault voltage disappears..
3.12.3.2 Time Curve
Residual overvoltage protection stage 1 is definite-time characteristic and can perform

instantaneous operation with the corresponding time delay setting at zero. Stage 2 can be
selected as definite-time or inverse-time characteristic, and inverse-time operating time curve is as
follows.
⎛ ⎞
⎜ ⎟
K
⎜
t(I) = ⎜ + C ⎟⎟ × TP Equation 3.12-1
U α
⎜⎜ ( ) −1 ⎟⎟
⎝ U set ⎠
Where:
U set is residual voltage setting [x.59G2.3U0_Set].
T p is time setting [x.59G2.TMS].
K and C are constants.
α is a constant
U is actual measured residual voltage.
setting [x.59G2.Opt_Curve], and parameters of available characteristics for selection are shown in
the following table.

Date: 2011-10-19
3 Operation Theory
Table 3.12-1 Inverse-time curve parameters of stage 2 residual overvoltage protection
x.59G2.Opt_Curve Time Characteristic K α C
0 Definite time
8 ANSI Inverse 0.0086 0.02 0.0185
If all available curves do not comply with user application, user may setting [x.59G2.Opt_Curve] at
“13” to customize the inverse-time curve characteristic, and constants K , α and C with
Define-time or inverse-time residual overvoltage protection drops off instantaneously.
3.12.4 Logic
EN [59Gn.En]
SIG [59Gn.En1] &
SIG [59Gn.En2]
SIG [59Gn.Blk]
&
SIG [x.59Gn.U3P] [x.59Gn.St]
SET [x.59Gn.U_Set] Timer

t
[x.59Gn.Op]
t
Inverse for ROV2 only
Figure 3.12-1 Logic diagram of residual overvoltage protection (59Pn, n=1,2)
For any stage residual overvoltage protection, when following three conditions are met the stage

Date: 2011-10-19
3 Operation Theory
(1) Logic setting [59Gn.En] is set to “1”.
(2) Enabling inputs [59Gn.En1], [59Gn.En2] are both set to “1”
(3) Blocking input [59Gn.Blk] is set to “0”.
When the protective function block is disabled, [59Gn.St], [59Gn.Op] signals are both reset.
Default values of Inputs [59Gn.En1], [59Gn.En2] are “1” and [59Gn.Blk] is “0” when those inputs
are not connected to external signals or setting.
59G
U3P St
U1P Op
En1
En2
Blk
Figure 3.12-2 Function block 59G (Each stage)
Table 3.12-2 Input signals of 59G (Each stage)

2 U1P Measured residual voltage data
5 Blk
Table 3.12-3 Output signals of 59G (Each stage)

1 St Protection start
2 Op Protection operate
Table 3.12-4 Output signals of 59G: report

Date: 2011-10-19
3 Operation Theory
1 x.59G.Op Residual overvoltage protection stage 1 of x side operates.
2 x.59G2.Op Residual overvoltage protection stage 2 of x side operates.
3 x.59G1.St Residual overvoltage protection stage 1 of x side starts.
4 x.59G2.St Residual overvoltage protection stage 2 of x side starts.
5 x.59G1. TrigDFR Residual overvoltage protection stage 1 of x side picks up to trigger DFR function.
6 x.59G2. TrigDFR Residual overvoltage protection stage 2 of x side picks up to trigger DFR function.
3.12.6 Settings
Table 3.12-5 Settings of 59G stage1

Voltage setting of stage 1 of residual overvoltage
1 x.59G1.3U0_Set 2~200 0.001 V
protection.
Time delay of stage 1 of residual overvoltage
2 x.59G1.t_Op 0~3600 0.001 s
protection.
0: disable Logic setting of enabling stage 1 of residual
3 x.59G1.En 1
1: enable overvoltage protection.
Tripping logic setting of stage 1 of residual
4 x.59G1.OutMap 0000~FFFF
Table 3.12-6 Settings of 59G stage 2

Voltage setting of stage 2 of residual overvoltage
5 x.59G2.3U0_Set 2~200 0.001 V
protection.
Multiplier of the maximum operating residual voltage
6 x.59G2.K_3U0set 1~2 0.001 to the pickup setting of stage 2 of residual overvoltage
protection.
Time delay of stage 2 of residual overvoltage
7 x.59G2.t_Op 0~3600 0.001 s
protection.
Minimum delay of stage 2 of residual overvoltage
8 x.59G2.tmin 0~20s 0.001 s
protection.
Time multiplier setting of stage 2 of residual
9 x.59G2.TMS 0.05~3.2 0.001
The constant K of stage 2 of residual overvoltage
10 x.59G2.K 0.0~120 0.001
protection.
The constant C stage 2 of residual overvoltage
11 x.59G2.C 0.0~20 0.001 s
protection.

Date: 2011-10-19
3 Operation Theory

The exponent alpha stage 2 of residual overvoltage
12 x.59G2.Alpha 0.02~5 0.001
protection.
13 x.59G2.Opt_Curve 0~13 1 curve of stage 2 of esidual overvoltage protection.
Logic setting of enabling stage 2 of residual
0: disable
14 x.59G2.En 1 overvoltage protection.
1: enable
Tripping logic setting of stage 2 of residual
15 x.59G2.OutMap 0000~FFFF
NOTE! If the minimum operating time [x.51G2.tmin] is set to “0”, the maximum operating
voltage is valid. That means the multiple of voltage the operating time of IDMT become
flat [x.51G2.K_Iset] can be set according to requirements and when the voltage is
greater than [x.51G2.K_Iset]x[x.51P4.I_Set], the operating time of IDMT becomes flat. If
[x.51G2.tmin] is not set to “0”, then maximum operating voltage is not valid and use only
can set the setting [51G2.tmin].
3.13 Undervoltage Protection (27)
3.13.1 Application
The increase of reactive power load leads to voltage decreasing, and voltage quality cannot be
satisfied only through AVR and OLTC voltage regulation. In this situation, undervoltage protection
should operate to shed part of loads to make voltage recovery to the normal level.
3.13.2 Function
Undervoltage protection has following functions:
z Four-stage definite-time undervoltage protection with independent voltage and time delay
settings.
z The rate of change of voltage blocking function is equipped.
3.13.3 Operation Principle

Three-phase undervoltage caused by the lack of system reactive power is almost symmetrical and
does not change suddenly, so the undervoltage protection adopts the positive-sequence voltage
for the protection calculation. If negative-sequence voltage is greater than 0.15Un or
positive-sequence voltage changes suddenly, the undervoltage protection is blocked.
Undervoltage load shedding protection has the unique capability of fault distinguishing, and its
operating time does not need to coordinate with that of other protections, so undervoltage
protection can operate quickly when system voltage is low.

Date: 2011-10-19
3 Operation Theory
When a short circuit occurs in the power system, bus voltage will decreases suddenly and
therefore undervoltage protection should be blocked simultaneously. After other protections
operate to clear the fault, the voltage at the relay location recovers quickly. If the voltage cannot
recover to the normal operation value, but greater than the value of setting [x.27.U_Recov],
blocking of undervoltage protection should be released at once, and the protection can operate to
shed corresponding loads to make voltage recovery (When system voltage collapses, disappears
or decreases, voltage recovery is the progress the system voltage recover to rated voltage.). A
time delay setting [x.27.t_Recov] should be set, which should be greater than the operating time of
backup protection generally. For example, if the longest operating time of backup protection is 4s,
the setting [x.27.t_Recov] can be set to “4.5s~5s”. If the voltage does not recover to the value
greater than the setting [x.27.U_Recov] after the time delay [x.27.t_Recov], alarm signal
[x.27.Alm_Unrecov] will be issued.
When system voltage is lower than stage 1 voltage setting, stage 1 operates after corresponding
time delay to shed part of loads. If system voltage continues to decrease lower than stage 2
voltage setting, stage 2 operates after corresponding time delay, and so on.
In order to prevent the maloperation of undervoltage caused by abnormality contestations such as

load back feed, higher harmonics, circuit connection etc., following blocking criteria are equipped.
（1） Undervoltage blocking
If positive-sequence voltage is lower than 0.15Un, undervoltage protection is blocked.
（2） Negative-sequence blocking
If negative-sequence voltage is greater than 0.15Un, undervoltage is blocked.
（3） Rate of change of voltage blocking
If the rate of change of voltage (du/dt) is greater than the setting [27.du/dt_Blk], undervoltage is
blocked and the blocking is not released until the system voltage greater than the recovery voltage
and above (setting [27.U_Recov])
When any one criterion is met, undervoltage protection is blocked.
3.13.4 Logic
Logic diagram of undervoltage protection is shown in the following figure.

Date: 2011-10-19
3 Operation Theory
SIG [27.En1]
&
SIG [27.En2] Flg_En27
SIG [27.Blk]
SIG [x.Alm_VTS]
≥1
OTH U1<0.15Un
OTH U2>0.15Un
≥1
Flg_Blk27
SET -du/dt>[x.27.du/dt_Blk] &
EN [x.27.En_du/dt_Blk]
SIG [x.In_VT]
SIG Flg_En27 &
SIG Flg_Blk27
&
SET U1<[x.27.UV1.U_Set] [x.27.St]
[x.27.UV1.t_Op] 0ms
[x.27.UV1.Op]
EN [x.27.UV1.En]
&
[x.27.UV2.t_Op] 0ms
EN [x.27.UV2.En] [x.27.UV2.Op]
&
[x.27.UV3.t_Op] 0ms
&
[x.27.UV4.t_Op] 0ms
Figure 3.13-1 Logic diagram of undervoltage protection
Where:
U1 is the positive sequence voltage.
[x.In_VT] is the input signal indicating that VT of x side in service. (x represent some side, such as
HVS, MVS, etc.). The signal can be configured as a binary input according to user requirements,
and if the binary input is not configured, the default value of the signal is 1.
Flg_En27 is the internal signal to enable undervoltage protection.
Flg_Blk27 is the internal signal to block undervoltage protection.

Date: 2011-10-19
3 Operation Theory
Figure 3.13-2 Function block 27
Table 3.13-1 Input signals of function block 27

1 U3P Three phase voltage data.
4 Blk
Table 3.13-2 Output signals of function block 27

1 St Undervoltage protection starts.
2 UV1.Op Stage 1 undervoltage protection operates.
6 Alm_Unrecov Alarm signal indicating that the voltage does not recovery to normal level.
1 x.27.UV1.Op Undervoltage protection stage 1 of x side operates to issue trip command.
5 x.27.Alm_Unrecov Alarm signal indicating that the voltage of x side does not recovery to normal level.
6 x.27. TrigDFR Undervoltage protection stage 1 of x side picks up to trigger DFR function.

Date: 2011-10-19
3 Operation Theory
3.13.6 Settings
Table 3.13-4 Settings of 27

1 x.27.du/dt_Blk 0~100 0.001 V/s Setting of du/dt blocking undervoltage protection.
2 x.27.U_Recov 10~100 0.001 V Lowest voltage threshold of fault recovery.
3 x.27.t_Recov 0~20， 0.001 s Time setting of fault recovery.
Voltage setting of stage 1 of undervoltage
4 x.27.UV1.U_Set 10~100 0.001 V
protection.
5 x.27.UV1.t_Op 0.05~100 0.001 s Time delay of stage 1 of undervoltage protection.
0: disable Logic setting of enabling du/dt blocking function for
6 x.27.UV1.En_du/dt_Blk 1
1: enable stage 1 of undervoltage protection.
0: disable Logic setting of enabling stage 1 of undervoltage
7 x.27.UV1.En 1
Tripping logic setting of stage 1 of undervoltage
8 x.27.UV1.OutMap 0000~FFFF 1
protection.
9 x.27.UV2.U_Set 0~100 0.001 V
protection.
12 x.27.UV2.En 1
protection.
14 x.27.UV3.U_Set 0~100 0.001 V
protection.
17 x.27.UV3.En 1
protection.
19 x.27.UV4.U_Set 0~100 0.001 V
protection.
21 x.27.UV4.En 1
22 x.27.UV4.En_du/dt_Blk 0: disable 1 Logic setting of enabling du/dt blocking function for

Date: 2011-10-19
3 Operation Theory

protection.
3.14 Thermal Overload Protection (49)
3.14.1 Application
During overload operation of a power transformer, great current results in greater heat to lead
temperature of transformer increase and if the temperature reaches too high values the equipment
might be damaged. The insulation within the transformer will have forced ageing. As a
consequence of this the risk of internal phase to phase or phase to earth faults will increase. High
temperature will degrade the quality of the transformer oil.
The thermal overload protection estimates the internal heat content of the transformer
(temperature) continuously. This estimation is made by using a thermal model of the transformer
with two time constants, which is based on current measurement.
Two stages are available. When the temperature increases to the alarm value, the protection
issues alarm signal to remind the operator for attention, and if the temperature continues to
increase to the trip value, the protection sends trip command of the protected transformer.
There are maximum three thermal overload protection elements equipped at each side of
transformer, and it is recommended to be equipped at the side without OLTC tap.
3.14.2 Function
Thermal overload protection has following functions:
z Thermal time characteristic of IEC 60255-8 is adopted.
z One stage for alarm and one stage for trip.
z Fundamental current or 1st to 7th harmonic current is used for protection calculation.
NOTE! Users must declare current value calculation for thermal overload protection,
fundamental current or 1st to 7th harmonic current before making an order.

Thermal overload module of IEC60255-8 is adopted, which is shown as follows.

Date: 2011-10-19
3 Operation Theory
Figure 3.14-1 Characteristic curve of thermal overload protection
There are two types of thermal time characteristic cold time-current limit characteristic and hot
start characteristic.
The cold time-current limit characteristic is given by the following equation.
2
I eq
t = τ ⋅ ln Equation 3.14-1
2
I eq − (k ⋅ I B ) 2
The hot time-current limit characteristic is given by the following equation.
2
I eq − I 2p
t = τ ⋅ ln Equation 3.14-2
2
I eq − (k ⋅ I B ) 2
Where:
t is the theoretical operate time, following application of the overload current.

τ is the heating thermal time constant of the protected equipment, i.e. [x.49.Tau].
I eq is the equivalent heating current, i.e. actual measured current.
I p is the steady-state load current prior to the overload for a duration which would result in
constant thermal level (duration is greater than several time constant τ ), which is memory
current. For cold time-current limit characteristic I p is zero,
ln is natural logarithm.

Date: 2011-10-19
3 Operation Theory
I B is the base current , i.e. [x.49.Ib_Set].
k is thermal overload coefficient, i.e. [x.49.K_Alm] or [x.49.K_Trp].

The hot time-current limit characteristic is adopted in the protection relay. The calculation is carried
out at zero of Ip, so users need not to set the value of Ip.
Tripping outputs of the protection is controlled by current, even if the thermal accumulation value is
greater than the setting for tripping, the protection drops off instantaneously when current
disappears. Alarm outputs of the protection is not controlled by current, and only if the thermal
accumulation value is greater than the setting for alarm, alarm output contacts, which can be
connected to block the auto-recloser of a circuit breaker, will operate.
3.14.4 Logic
Figure 3.14-2 Logic diagram of thermal overload protection of x side
For thermal overload protection, when following three conditions are met the stage protection is
enabled.
(1) Logic setting [49.En] is set to “1”.
(2) Enabling inputs [49.En1],[49. En2] are both set to “1”.
(3) Blocking input [49.Blk] is set to “0”.
When the protective function block is disabled, [49.St], [49.Alm] and [49.Op] signals are both reset.
Default values of Inputs [49.En1] and [49. En2] are “1” and [49.Blk] is “0” when those inputs are not

Date: 2011-10-19
3 Operation Theory
Figure 3.14-3 Function block 49
Table 3.14-1 Input signals of function block 49

6 Clr Clear command of thermal accumulation value.
9 Blk
Table 3.14-2 Output signals of function block 49

1 x.49.Op Thermal overload protection of x side operates to issue trip command.
2 x.49.Alm Thermal overload protection of x side operates to issue alarm command.
3 x.49.St Thermal overload protection of x side starts.

Date: 2011-10-19
3 Operation Theory
4 x.49.TrigDFR Thermal overload protection of x side picks up to trigger DFR function.
Table 3.14-4 Output signals of 49: measurements
Phase A thermal state of thermal overload protection. When the value is

1 ThermState_PhA
“1”, thermal overload protection operates.
Phase B thermal state of thermal overload protection. When the value is

2 ThermState_PhB
Phase C thermal state of thermal overload protection. When the value is

3 ThermState_PhC
3.14.6 Settings
Table 3.14-5 Settings of 49

1 x.49.K_Trp 1~3 0.001 Setting of thermal capacity for tripping.
2 x.49.K_Alm 1~3 0.001 Setting of thermal capacity for alarming.
3 x.49.Ib_Set 0.04A~30In 0.001 A Base current setting.
4 x.49.Tau 0.1~100 0.001 min Thermal time constant
0: disable
5 x.49.En_Trp 1 Logic setting of enabling tripping function.
1: enable
0: disable
6 x.49.En_Alm 1 Logic setting of enabling alarming function.
1: enable
7 x.49.OutMap 0000~FFFF Tripping logic setting of thermal overload protection.
3.15 Breaker Failure Protection (50BF)
3.15.1 Application
Breaker failure protection is applied for intertripping each side of transformer when trip signals of
breaker failure protection of busbar or other device are received. When the binary input of external
tripping is energized and current element picks up, a trip command will be issued after a delay to
trip circuit breakers at each side of transformer.

When the binary input of external tripping is energized and current element picks up, a trip
command will be issued after a delay to trip circuit breakers at each side of transformer.
Current criteria include phase current criterion, zero-sequence current criterion,

negative-sequence current criterion and DPFC current criterion. If any current criterion is satisfied
and current flowing through the protective equipment is detected, current element of breaker

Date: 2011-10-19
3 Operation Theory
failure protection picks up.
1) Phase current criterion：
I Φ _ max >[x.50BF.I_Set] Equation 3.15-1
Where:
I Φ _ max is the maximum value of three phase-current of some side.

[x.50BF.I_Set] is the current setting of breaker failure protection of the corresponding side.
2) Zero-sequence current criterion：
3I0 >[x.50BF.3I0_Set] Equation 3.15-2
Where:
3I0 is three times calculated zero-sequence current of some side.
[x.50BF.3I0_Set] is zero-sequence current of breaker failure protection of the corresponding side.
3) Negative-sequence current criterion：
I2> [x.50BF.I2_Set] Equation 3.15-3
Where:
I2 is negative-sequence current of some side.
[x.50BF.I2_Set] is negative-sequence current of breaker failure protection of the corresponding

side.
4) DPFC current criteria：
There is no setting for user to configure in the criteria.
ΔI > 1.25 * ΔI t + I th Equation 3.15-4
Where:
ΔI t is the floating threshold value which will arise automatically and gradually according to
increasing of the output of deviation component. In order to ensure the threshold voltage is slightly
greater than the unbalance voltage, multiple 1.25 of the deviation component is reasonable.
ΔI is the half-wave calculated of phase-to-phase current.
I th is the fixed threshold of 0.1pu and does not need to be set on site.

Date: 2011-10-19
3 Operation Theory
3.15.3 Logic
Logics of breaker failure protection of delay 1 and delay 2 are similar with independent settings,
and the lgoic of delay 1 is taken as an example to show below.
SIG I Φ _ max >0.06In
SET [x.50BF.En_Ip] &
SIG I Φ _ max >[x.50BF.Ip_Set]
SET [x.50BF.En_3I0] &

&
SIG 3I0>[x.50BF.3I0_Set] ≥1
SET [x.50BF.En_I2] &
SIG I2>[x.50BF.I2_Set]
&
SET [x.50BF.En_DPFC] &
[x.50BF.St]
SIG ΔI > 1.25 * ΔI t + I th

[x.50BF.t1_Op] 0ms
[x.50BF.Op_t1]
EN [50BF.En_t1]
SIG [50BF.En1] &
SIG [50BF.En2]
SIG [50BF.Blk]
SIG [50BF.Init]
SIG FD_BFP_x
Figure 3.15-1 Logic diagram of breaker failure protection of x side
Where:
“x” reprents some side of transformer, may be HVS, MVS or LVS.
In is rated secondary current of CT.
I Φ _ max is the maximum value of three phase-current of x side.

3I0 is calculated residual current of x side.
I2 is negative-sequence current of xside.
FD_BFP_x is the operation flag of the fault detector of breaker failure protection of x side.
Please refer to above section for descriptions of other symbols.
For breaker failure protection, when following three conditions are met the stage protection is
enabled.
(1) Logic setting [50BF.En] is set to “1”.
(2) Enabling inputs [50BF.En1],[ 50BF. En2] are both set to “1”.
(3) Blocking input [50BF.Blk] is set to “0”.
When the protective function block is disabled, [50BF.St], and [50BF.Op] signals are both reset.
Default values of Inputs [50BF.En1] and [50BF. En2] are “1” and [50BF.Blk] is “0” when those

Date: 2011-10-19
3 Operation Theory
3.15.4 Input and Output
Figure 3.15-2 Function block 50BF
Table 3.15-1 Input signals of function block 50BF

2 Init Input signal of initiating breaker failure protection.
5 Blk
Table 3.15-2 Output signals of function block 50BF

4 St Breaker failure protection starts.
5 Op_t1 Delya 1 of breaker failure protection operates.
6 Op_t2 Delya 2 of breaker failure protection operates.
Alarm message indicating the duration of receiving input signal of initating breaker
7 Alm_Init
failure protection is over 3s.
Alarm message indicating the duration of receiving current signal for breaker failure
8 Alm_Curr
protection is over 3s.
Table 3.15-3 Output signals of 50BF: report
5 x.50BF.Op_t1 Delay 1 of breaker failure protection of x side operates to issue trip command.

Date: 2011-10-19
3 Operation Theory
6 x.50BF.Op_t2 Delay 2 of breaker failure protection of x side operates to issue trip command.
Alarm message indicating the duration of receiving input signal of initating breaker
7 x.50BF.Alm_Init
failure protection of x side is over 3s.
Alarm message indicating the duration of receiving current signal for breaker failure
8 x.50BF.Alm_Curr
protection of x side is over 3s.
9 x.50BF.St Breaker failure protection of x side starts.
10 x.50BF.TrigDFR Breaker failure protection of x side picks up to trigger DFR function.
3.15.5 Setting
Table 3.15-4 Settings of 50BF

8 x.50BF.Ip_Set 0.04A~30In 0.001 A Current setting of phase current criterion.
9 x.50BF.3I0_Set 0.04A~30In 0.001 A Current setting of residual current criterion.
Current setting of negative-sequence current
10 x.50BF.I2_Set 0.04A~30In 0.001 A
criterion.
0: disable Logic setting of enabling/disabling phase current
11 x.50BF.En_Ip 1
1: enable criterion to control breaker failure protection.
0: disable
12 x.50BF.En_I2 1 negative-sequence current criterion to control
1: enable
breaker failure protection.
0: disable Logic setting of enabling/disabling DPFC current
13 x.50BF.En_DPFC 1
1: enable criterion to control breaker failure protection.
0: disable
14 x.50BF.En_3I0 1 residual-sequence current criterion to control
1: enable
15 x.50BF.t1_Op 0~20 0.001 s Time delay 1 of breaker failure protection.
0: disable Logic setting of enabling/disabling time delay 1 of
16 x.50BF.En_t1 1
1: enable breaker failure protection.
Tripping logic setting of time delay 1 of breaker
17 x.50BF.OutMap_t1 0000~FFFF
failure protection.
18 x.50BF.t2_Op 0~20 0.001 s Time delay 2 of breaker failure protection.
0: disable Logic setting of enabling/disabling time delay 2 of
19 x.50BF.En_t2 1
1: enable breaker failure protection.
Tripping logic setting of time delay 2 of breaker
20 x.50BF.OutMap_t2 0000~FFFF
failure protection.

Date: 2011-10-19
3 Operation Theory
3.16 Pole Disagreement Protection (62PD)
3.16.1 Application
With voltage level involved, the switching equipment usually consists of single pole devices that
are not mechanically linked, with each pole having an independent operating mechanism. With
such an arrangement, the possibility exists that one pole may not operate coincidentally with the
other poles, thus creating an undesirable imbalance in system voltages or, in case the switching
equipment were called upon to clear a fault, might fail to remove the faulted source from service.
So that if a pole disagreement fault is detected, after a certain delay, the transformer relay will
initiate a trip command to trip all poles of the switching equipment.

z Initiate signal
Input signal of pole disagreement position, [62PD.In_PD_CB], is used to initiate pole

disagreement protection..
z Current control element
There are two current control elements for pole disagreement protection: residual current element
and negative sequence current element which are configurable by logic settings and are “OR”
relation to release pole disagreement protection.
3.16.3 Logic
Logical diagram of pole disagreement protection is presented in Figure 3.16-1.
BI [62PD.In_PD_CB]
SIG 3I0>[x.62PD.3I0_Set] &
EN [x.62PD.En_3I0]
≥1 ≥1 &
SIG [x.62PD.St]
EN I2>[x.62PD.I2_Set] & [x.62PD.t_Op] 0ms SIG [x.62PD.Op]
SIG [x.62PD.En_I2]
SIG [62PD.Blk]
SIG [62PD.En2] &

SIG [62PD.En2]
EN [62PD.En]
[x.62PD.t_Alm] 0ms
BI [62PD.In_PD_CB] SIG [x.62PD.Alm]
Figure 3.16-1 Logical diagram of pole disagreement protection of x side
Where:
3I0 is calculated reasidual current.
I2 is negative sequence current.

Date: 2011-10-19
3 Operation Theory
For pole disagreement protection, when following three conditions are met the stage protection is
enabled.
(1) Logic setting [62PD.En] is set to “1”.
(2) Enabling inputs [62PD.En1],[62PD. En2] are both set to “1”.
(3) Blocking input [62PD.Blk] is set to “0”.
When the protective function block is disabled, [62PD.St], and [62PD.Op] signals are both reset.
Default values of Inputs [62PD.En1] and [62PD. En2] are “1” and [62PD.Blk] is “0” when those
3.16.4 Input and Output
Figure 3.16-2 Function block 62PD
Table 3.16-1 Input signals of function block 62PD

2 In_PD_CB Input signal of indicating pole disagreement state of a circuit breaker
5 Blk
Table 3.16-2 Output signals of function block 62PD


Date: 2011-10-19
3 Operation Theory
Table 3.16-3 Output signals of 62PD: report
1 x.62PD.Op Pole disagreement protection of x side operates to issue trip command.
2 x.62PD.Alm Pole disagreement protection of x side operates to issue alarm command.
3 x.62PD.St Pole disagreement protection of x side starts.
4 x.62PD.TrigDFR Pole disagreement protection of x side picks up to trigger DFR function.
3.16.5 Setting
Table 3.16-4 Settings of pole disagreement protection

1 x.62PD.3I0_Set 0.04A~30In 0.001 A Current setting of residual current criterion.
Current setting of negative-sequence current
2 x.62PD.I2_Set 0.04A~30In 0.001 A
criterion.
Time delay of pole disagreement protection for
3 x.62PD.t_Op 0~20 0.001 s
tripping
4 x.62PD.t_Alm 0~20 0.001 s Time delay of breaker failure protection. for alarming
0: disable Logic setting of enabling/disabling residual current
5 x.62PD.En_3I0 1
1: enable criterion to control pole disagreement protection.
0: disable
6 x.62PD.En_I2 1 negative-sequence current criterion to control
1: enable
0: disable Logic setting of enabling/disabling pole
7 x.62PD.En_PD 1
1: enable disagreement protection..
Tripping logic setting of pole disagreement
8 x.62PD.OutMap 0000~FFFF
protection.
3.17 Phase Overcurrent Alarm Element (50PAlm)
3.17.1 Application
During overload operation of a power transformer, great current results in greater heat to lead
temperature of transformer increase and if the temperature reaches too high values the equipment
might be damaged. The insulation within the transformer will have forced ageing.
The phase overcurrent alarm element is equipped to monitor the load of transformer winding, and
when load current exceeds the transformer limit load current, phase overcurrent alarm element
can be applied to issuing alarm signals to remind field operators.

Date: 2011-10-19
3 Operation Theory
Besides, during overload of transformer, it is needed to initiate cooling system (such as cooling fan)
and blocking OLTC function of the tap of transformer. Therefore phase overcurrent alarm element
can also be applied to the initiation of cooling system and the blocking of OLTC function.
3.17.2 Function
Phase overcurrent alarm element has following functions:
z Two-stage definite-time phase overcurrent alarm element with independent logic, current and
time delay settings.
z Outputs of phase overcurrent alarm element only applied for alarm signals.
z Fundamental current or 1st to 7th harmonic current is used for protection calculation.
z Drop off coefficient of phase overcurrent alarm element is settable.
NOTE! Users must declare current value calculation for thermal overload protection,
fundamental current or 1st to 7th harmonic current before making an order.

I p > [50PAlmn.I_Set] Equation 3.17-1
Where:
I p is three phase current.
[51Almn.I_Set] is the current setting of stage n stage n (n=1, or 2) phase overcurrent alarm
element..
If any phase current is greater than the setting of any stage enabled phase overcurrent alarm
element, the stage phase overcurrent alarm element will operate after time delay and the stage
protection will drop off after the overload current disappear.
3.17.4 Logic
EN [50PAlmn.En]
SIG [50PAlmn.En1] &
SIG [50PAlmn.En1] &
SIG [50PAlmn.Blk] [x.50PAlmn.St]
SIG [x.50PAlmn.I3P]
[x.50PAlmn.t_Op] 0ms
[x.50PAlmn.Alm]
SET [x.50PAlmn.I_Set]
Figure 3.17-1 Logic diagram of phase overcurrent alarm (50PAlmn, n=1,2)

Date: 2011-10-19
3 Operation Theory
For any stage phase overcurrent alarm element, when following three conditions are met the stage
(1) Logic setting [50PAlmn.En] is set to “1”.
(2) Enabling inputs [50PAlmn.En1], [50PAlm. En2] are both set to “1”.
(3) Blocking input [50PAlmn.Blk] is set to “0”.
When the protective function block is disabled, [x.59Almn.St], [x.59Almn.Alm] and [x.59Almn.Op]
signals are both reset. Default values of Inputs [x.59Almn.En1] and [x.59Almn.En2] are “1” and
[x.59Almn.Blk] is “0” when those inputs are not connected to external signals or setting.
50PAlm
I3P St
En1 Alm
En2
Blk
Figure 3.17-2 Function block 50PAlm (each stage)
Table 3.17-1 Input signals of function block 50PAlm (each stage)

1 I3P Three phase current data.
4 Blk
When the input is 1, ground overcurrent protection is not reset and time delay is cleared.
Table 3.17-2 Output signals of function block 50PAlm (each stage)


Date: 2011-10-19
3 Operation Theory
Table 3.17-3 Output signals of 50PAlm: report
1 x.50PAlm1.Alm Phase overcurrent alarm stage 1 of x side operates to issue alarm command.
2 x.50PAlm2.Alm Phase overcurrent alarm stage 2 of x side operates to issue alarm command.
3 x.50PAlm1.St Phase overcurrent alarm stage 1 of x side starts
4 x.50PAlm2.St Phase overcurrent alarm stage 2 of x side starts
3.17.6 Settings
Table 3.17-4 Settings of 50PAlm stage n (n=1,2)

Current setting of stage n of phase overcurrent alarm
1 x.50PAlmn.I_Set 0.04A~30In 0.001 A
element.
Time delay of stage n of phase overcurrent alarm
2 x.50PAlmn.t_Op 0~3600 0.001 s
element.
Drop off ratio of stage n of phase overcurrent alarm
3 x.50PAlmn.K_DOP 0.7~1.0 0.95
element
0: disable Logic setting of enabling stage n of phase
4 x.50PAlmn.En 1
1: enable overcurrent alarm element.
3.18 Three-Phase Current Element (Curr3P)
3.18.1 Application
Three-phase current element is responsible for pre-processing three phase currents and
calculating sequence components, amplitudes and phases of three phase currents, etc. All
calculated information of three-phase current element is for the protection logic calculation.
3.18.2 Function
Three-phase current element has following functions:
z Pre-process three phase currents.
z Calculate information related to three-phase current.
z Monitor the secondary circuit of current including CT circuit abnormality and CT circuit failure.
3.18.3 Principle
z CT circuit abnormality supervision
If any one of the following two criteria is met, the corresponding alarm signal [x.AlmL_CTS] will be
issued after 10s, and it will be reset after 10s if equipment returns to normal condition..

Date: 2011-10-19
3 Operation Theory
1) Calculated residual current is greater than 0.06In or greater than 0.2 times maximum phase
current.
2) Negative-sequence current is greater than 0.1In or greater than 0.4 times maximum phase
current.
z CT circuit failure supervision
When current of the element is engaged in the calculation of transformer differential protection,
restricted earth fault protection or winding differential protection, the CT circuit failure supervision
function of each protection is carried out in the corresponding protection element and please refer
to corresponding sections for details.
z Current detection
When any phase current is greater than 0.04In, inputted current signals are decided valid and the
valid signal is outputted for programmable logic application.
3.18.4 Logic
SIG 3I0>0.06In ≥1
10s 10s
[AlmL_CTS]
SIG I2>0.1In
SIG Ia>0.04In
≥1
SIG Ib>0.04In [OnLoad]
SIG Ic>0.04In
Figure 3.18-1 Current pre-processing logic diagram
Where:
Ia, Ib, and Ic are sampled three phase current values.
I2 is the negative-sequence current.

Date: 2011-10-19
3 Operation Theory
Figure 3.18-2 Function block Curr3P
Table 3.18-1 Input signals of function block Curr3P

1 ia Sampled value of phase A current
2 ib Sampled value of phase B current
3 ic Sampled value of phase C current
Table 3.18-2 Output signals of function block Curr3P

1 I3P A current data set
2 Ang(Ia) Phase angle of phase A current
3 Ang(Ib) Phase angle of phase B current
4 Ang(Ic) Phase angle of phase C current
5 AlmL_CTS Alarm message of CT secondary circuit abnormality
6 AlmH_CTS Alarm message of CT secondary circuit failure
7 OnLoad A flag indicating there is load current detected
Table 3.18-3 Output signals of Curr3P: report
1 x.AlmL_CTS Current transformer circuit of x side is abnormal.
2 x.AlmH_CTS Current transformer circuit of x side fails.
Alarm reports of equipment during operation.

Date: 2011-10-19
3 Operation Theory
Table 3.18-4 Output signals of Curr3P: measurements
1 x.Ua
2 x.Ub Three-phase voltage values of x side.
3 x.Uc
4 x.3U0Cal Calculated residual voltage value of x side.
5 x.U1 Positive-sequence voltage value of x side.
6 x.U2 Negative-sequence voltage value of x side.
7 x.Ang(Ua-Ub) Angle between phase A and phase B voltages of x side.

8 x.Ang(Ub-Uc) Angle between phase B and phase C voltages of x side.
9 x.Ang(Uc-Ua) Angle between phase C and phase A voltages of x side.
10 x.3U0Ext Measured residual voltage value of x side.
11 x.Ia
12 x.Ib Three-phase current values of x side.
13 x.Ic
14 x.Ang(Ia-Ib) Angle between phase A and phase B currents of x side.
15 x.Ang(Ia-Ic) Angle between phase B and phase C currents of x side
16 x.3I0Cal Calculated residual current value of x side.
17 x.I1 Positive-sequence current value of x side.
18 x.I2 Negative-sequence current value of x side.
19 x.Ia_Brn
20 x.Ib_Brn Three-phase current of x side branch n (n=1, 2).
21 x.Ic_Brn
22 x.Ang(Ia-Ib)_Brn Angle between phase A and phase B currents of x side branch n (n=1, 2).
23 x.Ang(Ia-Ic)_Brn Angle between phase B and phase C currents of x side branch n (n=1, 2).
24 x.3I0Ext Current value from neutral CT at neutral point of x side.
25 x.Ang(Ua-Ia) Angle between phase A voltage and current of x side.
26 x.Ang(Ub-Ib) Angle between phase B voltage and current of x side
27 x.Ang(Uc-Ic) Angle between phase C voltage and current of x side
Path:
Main menu -> Measurements -> Measurements1-> x Measurements
Main menu -> Measurements -> Measurements2-> x Measurements
3.18.6 Settings
Table 3.18-5 Settings of Curr3P

Date: 2011-10-19
3 Operation Theory

1 x.I1n 0~60000 1 A Primary current value, default value: 1000A
2 x.I2n 1 or 5 A Secondary current value, default value: 1A
3.19 Three-Phase Voltage Element (Volt3P)
3.19.1 Application
Three-phase voltage element is responsible for pre-processing three phase voltages and
calculating sequence components, amplitudes and phases of three phase currents, etc. All
calculated information of three-phase voltage element is for the protection logic calculation
3.19.2 Function
z Pre-process three phase voltages.
z Calculate information related to three phase voltages.
z Monitor the secondary circuit of voltage including VT circuit abnormality.
3.19.3 Principle
z VT circuit abnormality supervision
If one of following two criteria is met and there is no operation of any fault detectors VT circuit
abnormality alarm will be issued after 10s. The abnormality alarm will be reset after 10s if
equipment returns to normal condition.
When the secondary phase-to-phase voltage of VT is equal to 100V:
1) Positive sequence voltage is less than 30 V and any phase current is greater than 0.04 In.
2) Positive sequence voltage is less than 30 V and the breaker is in closed position.
3) The negative sequence voltage is greater than 8 V.
4) The 3rd harmonic magnitude of phase voltage is greater than 10V.
If the secondary phase-to-phase rated voltage is set to 110V, all corresponding operating voltage
will be adjusted in the same ratio.

Date: 2011-10-19
3 Operation Theory
3.19.4 Logic
Figure 3.19-1 Voltage pre-processing logic diagram
Where:
Up_3rd is the 3rd harmonic value of phase voltage.
U2 and U1 are respectively negative sequence voltage value and positive sequence current value.
Figure 3.19-2 Function block Volt3P
Table 3.19-1 Input signals of function block Volt3P

8 ua Sampled value of Phase A voltage
9 ub Sampled value of Phase B voltage
10 uc Sampled value of Phase C voltage
11 52b Binary input of auxiliary normally closed contact of a circuit breaker
12 In_VT Input signal of indicating VT in service.
13 OnLoad A flag indicating sampled current valid
Table 3.19-2 Output signals of function block Volt3P

1 U3P A voltage data set
2 Ang(Ua) Phase angle of phase A voltage

Date: 2011-10-19
3 Operation Theory

3 Ang(Ub) Phase angle of phase B voltage
4 Ang(Uc) Phase angle of phase C voltage
5 Alm_VTS Alarm message of VT secondary circuit abnormality
Table 3.19-3 Output signals of Volt3P: report
3 x.Alm_VTS Voltage transformer circuit of HV side is abnormal.
Alarm reports of equipment during operation.
3.19.6 Settings
Table 3.19-4 Settings of Volt3P

3 U1n 1~2000 0.001 kV Primary current value, default value: 1000kV
4 U2n 100~130 0.001 V Secondary current value, default value: 100V
3.20 Residual Current Element (Curr1P)
3.20.1 Application
Residual current element is responsible for pre-processing measured residual current and
calculating the magnitude and the phase angle of residual current, etc. All calculated information
of three-phase current element is for the protection logic calculation
3.20.2 Function
z Pre-process measured residual current.
z Calculate information related to residual current.
Figure 3.20-1 Function block Curr1P

Date: 2011-10-19
3 Operation Theory
Table 3.20-1 Input signals of function block Curr1P

1 3i0 Measured residual current
Table 3.20-2 Output signals of function block Curr1P

1 I1P A current data set
2 Ange(3I0) Phase angle of residual current
3.20.4 Settings
Table 3.20-3 Settings of Curr1P

Primary current value of neutral CT, default value:
1 I1n_Neu 0~60000 1 A
1000A
2 I2n_Neu 1 or 5 A Secondary current value of neutral, default value: 1A
3.21 Residual Voltage Element (Volt1P)
3.21.1 Application
Residual voltage element is responsible for pre-processing residual voltage and calculating the
magnitude and the phase angle of residual voltage, etc. All calculated information of three-phase
voltage element is for the protection logic calculation
3.21.2 Function
z Pre-process measured residual voltage.
z Calculate information related to voltage current.
Figure 3.21-1 Function block Volt1P
Table 3.21-1 Input signals of function block Volt1P

2 3u0 Measured residual voltage

Date: 2011-10-19
3 Operation Theory
Table 3.21-2 Output signals of function block Volt1P

3 U1P A voltage data set
4 Ang(3U0) Phase angle of residual voltage
3.21.4 Settings
Table 3.21-3 Settings of Volt1P

Primary current value of broken-delta VT , default
1 U1n_Delt 1~2000 1000 kV
value: 1000kV
Secondary current value of broken-delta VT, default
2 U2n_Delt 10~200 100 V
value: 100V
3.22 Output Map (OutMap)
3.22.1 Overview Description

Tripping output element consists of tripping outputs of protection element and programmable
tripping output element. Each protection element has its corresponding tripping logic setting used
to configure tripping output contacts of each element, and 10 programmable tripping output
elements are equipped for visualization programming of user level.
The tripping output contacts are with 120ms (fixed in program) dwell time to ensure sufficient time
of tripping command for CB opening.
3.22.2 Output Map of Protection Element

Each protection element has its corresponding tripping logic setting used to configure tripping
output contacts of each element, and total 10 groups of tripping output contacts can be controlled
by tripping logic settings. Therefore, user can configure the tripping output contacts of each
protection element individually though the corresponding tripping logic setting, and following figure
shows the tripping map of protection element.

Date: 2011-10-19
3 Operation Theory
10 Groups of Tripping Output Contacts
1 2 3 4 5 6 7 8 9 10
[87T.OutMap]
[HVS.64REF.OutMap]
[MVS.64REF.OutMap]
[LVS.64REF.OutMap]
[24DT1.OutMap]
[24DT2.OutMap]
[HVS.50/51P1.OutMap]
[HVS.50/51G1.OutMap]
Figure 3.22-1 Output map of protection element
z Tripping output contacts
10 groups of independent tripping output contacts can be defined to trip HV side, MV side, and
LVS side etc. Each group of tripping contacts can correspond to certain amount of contacts on
binary output plug-in modules.
z Tripping logic settings
Tripping logic settings are used to specify which breakers will be tripped when some protection
element operates. This logic setting comprises 16 binary bits as follows and is expressed by a
hexadecimal number of 4 digits from 0000H to FFFFH. The tripping logic setting of the equipment
is specified as follows:
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TrpOutput15
TrpOutput14
TrpOutput13
TrpOutput12
TrpOutput11
TrpOutput10
TrpOutput09
TrpOutput08
TrpOutput07
TrpOutput06
TrpOutput05
TrpOutput04
TrpOutput03
TrpOutput02
TrpOutput01
Function
N/A
NOTE！ “TrpOutput01” just means to drive 1st group of tripping output contacts to pickup
and please refer to Chapter “Hardware” for details. The tripping outputs are recorded as
“T01~T15” by the protection equipment when they operate, and “Txx” (xx=01, 02, …, 15)
represents “Tripoutputxx” (xx=01, 02, …, 15).
The bit corresponding to the breaker to be tripped shall be set as“1” and other bits shall be “0”.

Date: 2011-10-19
3 Operation Theory
For example, if differential protection operates to make “TrpOutput1”, “TrpOutput2”, “TrpOutput3”

contacts pickup, the bit “1” and bit “2” and bit “3” positions shall be filled with “1” and other bit
positions shall be filled with “0”. Then a hexadecimal number 0007H is formed as the tripping
output logic setting, i.e. [87T.OutMap] shall be set as “0007H”.
3.22.3 Programmable Tripping Output Element

10 programmable tripping output elements with inputs, outputs and settings are provided for
visualization programming of user level.
Users can program output of function elements in the device by visualization programming
software if tripping map of protection element provided by protective equipment cannot meet
application requirements completely.
For example, if user need stage 1 of overcurrent protection of HV side operate to issue trip
command after its operation criterion is satisfied “AND” receiving a binary input which can be a
blocking signal from other protection equipment, users can complete the function configuration as
following steps.
1) Set tripping logic setting of stage 1 of overcurrent protection of HV side as “0”, i.e.
[87T.OutMap]=0000H.
2) Finish required logic programming by visualization programming tool.
3) Connect final logic programming output to input of programming tripping output element.
4) Set corresponding programmable tripping logic setting to complete the function configuration.

Table 3.22-1 Input signals of programmable tripping output element
1 Sig_ProgTrp01 Input signal of programmable tripping output element 1.
Input signals of programmable tripping output element.

Date: 2011-10-19
3 Operation Theory
Figure 3.23-1 Programmed logic example
Where:
[HVS. 50/51P1.Op] is the operation flag of stage 1 of overcurrent protection of HV side.
[LVS. 50/51P1.Op] is the operation flag of stage 1 of overcurrent protection of MV side.
[Sig_Spare1] is the signal of intermediate variable 1 for logic programming.
LED10 is the programmable LED10.

Table 3.23-1 Input signals of intermediate variable element
1 Sig_Spare01 Signal of intermediate variable 1 for logic programming.
Input signals of programmable logic.

Date: 2011-10-19
3 Operation Theory

Date: 2011-10-19
4 Supervision
4 Supervision
Table of Contents
4.1 Overview........................................................................................................... 4-1

4.2 Relay Self-supervision .................................................................................... 4-1
4.2.1 Relay Hardware Supervision ..............................................................................................4-1
4.2.2 Output Tripping Circuit Supervision ....................................................................................4-1
4.2.3 Setting Checking ................................................................................................................4-1
4.2.4 Memory Checking ...............................................................................................................4-1
4.2.5 Opto-coupler Power Supervision ........................................................................................4-2
4.2.6 Fault Detector Element Supervision ...................................................................................4-2
4.2.7 Test Mode Supervision .......................................................................................................4-2
4.2.8 Hardware Configuration Supervision ..................................................................................4-2
4.3 Equipment Operation Supervision ................................................................. 4-2

4.3.1 Current Transformer Supervison (CTS) ..............................................................................4-2
4.3.2 Voltage Transformer Supervison (VTS) ..............................................................................4-6
4.3.3 Frequency Supervison ........................................................................................................4-7
4.4 Failure and Abnormality Alarms ..................................................................... 4-7

4.4.1 Hardware Self-supervision Alarms ......................................................................................4-8
4.4.2 Equipment Operation Alarms ............................................................................................ 4-11
List of Tables
Table 4.4-1 Equipment self-check alarm list ...........................................................................4-8
Table 4.4-2 Equipment operation alarm list...........................................................................4-11

Date: 2011-10-20
4 Supervision

Date: 2011-10-20
4 Supervision
4.1 Overview
Though the protection system is in non-operating state under normal conditions, it is waiting for a
power system fault to occur at any time and must operate for the fault without fail. When
equipment is in energizing process before the LED “HEALTHY” is on, the equipment needs to be
checked to ensure no errors. Therefore, the automatic supervision function, which checks the
health of the protection system when startup and during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a fatal fault is detected during automatic supervision, the equipment will be blocked. It
means that relay is out of service. Before you must re-energize the relays or reset CPU module
and MON module to make relay back into service, please find out the cause and inform the
factory.
When a failure is detected by the automatic supervision, it is followed with an LCD message, LED
indication and alarm contact outputs. At the same time event recording will record the failure alarm
which can be viewed in event recording report and be printed.
4.2 Relay Self-supervision
4.2.1 Relay Hardware Supervision

All chips on each module are monitored to ensure whether they are damaged or have errors. If
any one of them is detected damaged or having error, the corresponding alarm signal
[ProtBrd.Fail_DSP] or [FDBrd.Fail_DSP] is issued with equipment being blocked.
AC current and voltage samplings of protection DSP module and fault detector DSP module are
monitored and if the samples are detected to be wrong or inconsistent, an alarm
[ProtBrd.Fail_Sampel] or [FDBrd.Fail_Sample] will be issued and the relay will be blocked.
4.2.2 Output Tripping Circuit Supervision

State of binary outputs on each BO module at slot Bx (Bx is the slot number) is continuously
monitored. If any abnormality is detected on the module, the corresponding alarm signal
[Bx.Fail_Output] will be issued with equipment being blocked.
4.2.3 Setting Checking

This relay has 10 setting groups, while only one is active at the same time. The settings of active
setting group are checked to ensure they are reasonable. If settings are checked to be
unreasonable or out of setting scopes, a corresponding alarm signal will be issued, and the
protective device is also blocked.
4.2.4 Memory Checking

Data in non-volatile memory, which are not changed after device energized, are always checked

Date: 2011-10-20
4 Supervision
during device normal operation, such as settings, pointers, etc. If these data changed abnormally,
the corresponding alarm [ProtBrd.Memory] or [FDBrd.Memory] will be issued.
4.2.5 Opto-coupler Power Supervision

Positive power supply of opto-coupler on each BI module at slot x (Bx is the slot number) is
continuously monitored, and if a failure or damage on the module is detected, then the alarm
signal [Bx.Alm_OptoDC] will be issued.
4.2.6 Fault Detector Element Supervision

If any fault detector picks up to trigger oscillograph function, the corresponding binary input
changing report will be recorded in “IO_Events” menu with tripping report [TrigDFR] being issued.
If a fault detector on protection or fault detector DSP module keeps picking up for 10s, the
corresponding alarm signal [ProtBrd.Alm_Pkp] or [FDBrd.Alm_Pkp] will be issued without
equipment being blocked.
4.2.7 Test Mode Supervision

When protection equipment is in communication test mode the alarm signal [Alm_CommTest] is
issued without blocking equipment.
4.2.8 Hardware Configuration Supervision

Module configuration is checked automatically during equipment initialization, if plug-in module
configuration is not consistent to the design drawing of an applied-specific, the alarm signal
[Fail_BoardConfig] is issued with the equipment being blocked.
4.3 Equipment Operation Supervision
4.3.1 Current Transformer Supervison (CTS)

The CTS function will be always processed all the time, which includes following two aspects
The CTS logic in the relay is designed to detect the CT secondary circuit to ensure that current
measurement is the actual value of power system. The main purpose of the CTS function is to
ensure the integrity of the CT circuits maintaining the performance of protective equipment.
4.3.1.1 CT Circuit Abnormality of Differenital Protection
z For transformer current differential protection
If the differential current in any phase is greater than the alarm setting [87T.I_Alm] without fault
[87T.Alm_Diff] will be issued without blocking the protection.
z For reactor current differential protection
If the differential current in any phase is greater than the alarm setting [87R.I_Alm] without fault

Date: 2011-10-20
4 Supervision
[87R.Alm_Diff] will be issued without blocking the protection.
z For restricted earth fault protection
If the following operation formula is met for 10s, CT circuit abnormality alarm of REF protection will
be issued without blocking the protection.
The operation formula is as follows:
I 0d > Max(0.2 × [64REF.I_Biased] ,0.1I n ) Equation 4.3-1
Where:
I 0d is the REF differential current of one side.
[64REF.I_Biased] is the pickup value of biased REF protection.
I n is the rated secondary current of CT.
z For transformer winding differential protection
If the following operation formula is met for 10s, CT circuit abnormality alarm of winding differential
protection will be issued without blocking the protection.
The operation criterion is as follows:
I wd > Max(0.2 × [87W .I _ Biased ] ,0.1I n ) Equation 4.3-2
Where:
[87W.I_Biased] is the pick up value of biased winding differential protection.
I n is the rated secondary current of CT.
4.3.1.2 CT Crcuit Abnormality of CT
If any one of the following two criteria is met, the corresponding alarm signal [x.AlmL_CTS] will be
issued after 10s, and it will be reset after 10s if equipment returns to normal condition.
1) Calculated residual current is greater than 0.06In or greater than 0.2 times maximum phase
current.
2) Negative-sequence current is greater than 0.1In or greater than 0.4 times maximum phase
current.

Date: 2011-10-20
4 Supervision
SIG 3I0>0.06In ≥1
10s 10s
[AlmL_CTS]
SIG I2>0.1In
SIG Ia>0.04In
≥1
SIG Ib>0.04In [OnLoad]
SIG Ic>0.04In
Figure 4.3-1 Current pre-processing logic diagram
Where:
Ia, Ib, and Ic are sampled three phase current values.
I2 is the negative-sequence current.
In is the rated secondary current of CT.
[AlmL_CTS] is alarm message of CT secondary circuit abnormality.
[Onload] is a flag indicating there is load current detected.
4.3.1.3 CT Circuit Failure of Differential Protection
z Criteria
The following two cases are considered as CT circuit failure, and the protection relay can
discriminate which side the CT circuit failure by the unbalanced currents.
Differential CT secondary circuit failure can be judged more accurately and reliably by adopting
combined method of voltage and current.
1) First case, if none of following four conditions is satisfied after the fault detector of biased
differential current, or biased residual differential current, or biased winding differential current
picks up, it will be judged as CT circuit failure and the CT circuit failure alarm ([87T.Alm_CTS],
[87R.Alm_CTS], [64REF.Alm_CTS], [87W.Alm_CTS] or [x.AlmH_CTS], x represents some
side of transformer) will be issued.
¾ Negative-sequence voltage at any side is greater than 2%xUpp (Upp is the secondary
phase-to-phase rated voltage).
¾ Any phase current of any side increases after fault detector picks up.
¾ The maximum phase current is greater than 1.1pu after the fault detector picks up.
¾ DPFC element of any phase-to-phase voltage of any side picks up.
2) Second case, if CT circuit abnormality of differential protection alarm (i.e. [87T.Alm_Diff]) is

issued and negative-sequence current of one side is greater than 0.2 times maximum phase
current of the corresponding side, and then CT circuit failure will be judged.

Date: 2011-10-20
4 Supervision
z Influence of CT circuit failure on differential protections
User can configure the output of CT circuit failure alarm to block the sensitive biased differential
protection, biased REF protection and biased winding differential protection via logic settings
[87T.En_CTS_Blk], [87R.En_CTS_Blk], [64REF.En_CTS_Blk], and [87W.En_CTS_Blk]
respectively. The CT circuit failure alarm is latched once issued, it can be reset only after the
failure is cleared and equipment is reset (i.e. the binary input [BI_RstTarg] is energized).
1) Transformer conventional biased differential protection and instantaneous differential

protection are always not blocked during CT circuit failure.
2) Transformer DPFC biased differential relay is always blocked during CT circuit failure.
3) Transformer sensitive biased differential protection can be blocked when CT circuit failure is
detected by configuring the logic setting [87T.En_CTS_Blk].
¾ If this logic setting is set as “0”, transformer sensitive biased differential protection is not
blocked.
¾ If this logic setting is set as “1”, transformer sensitive biased differential protection is
blocked.
4) Reacotr sensitive biased differential protection can be blocked when CT circuit failure is
detected by configuring the logic setting [87R.En_CTS_Blk].
¾ If this logic setting is set as “0”, reactor sensitive biased differential protection is not
blocked.
¾ If this logic setting is set as “1”, reactor sensitive biased differential protection is blocked.
5) Biased REF protection can be blocked when CT circuit failure is detected by configuring the
logic setting [64REF.En_CTS_Blk].
¾ If this logic setting is set as “0”, biased REF protection is not blocked.
¾ If this logic setting is set as “1”, biased REF protection is blocked.
6) Biased winding differential protection can be blocked when CT circuit failure is detected by
configuring the logic setting [87W.En_CTS_Blk].
¾ If this logic setting is set as “0”, biased winding differential protection is not blocked.
¾ If this logic setting is set as “1”, biased winding differential protection is blocked.
NOTE！The operation time of biased differential protection with CT circuit failure being
distinguished has 50ms delay than that of biased differential protection without CT
circuit failure.
z Logic of CT Circuit Failure
The CT circuit failure logic of transformer current differential protection is taken as an example to
shown below.

Date: 2011-10-20
4 Supervision
SIG U2>2%Upp
≥1
SIG Flg_DPFCVolt ≥1
SIG Flg_CurrIncrease
&
&
T 0ms
Flg_CTS
SIG Ipmax>1.1pu
SIG FD_BiasDiff
SIG Flg_CTS &

[x.AlmH_CTS]
SIG I2>0.04Ipmax or I2>0.1In
&
[87T.Alm_CTS]
Figure 4.3-2 Logic diagram of CT circuit failure of transformer current differential protection
Where:
Upp is the secondary phase-to-phase rated voltage.
Flg_DPFCVolt is the internal flag indicating that DPFC element of any phase-to-phase voltage of
any side picks up
Flg_CurrIncrease is the internal flag indicating that Any phase current of any side increases after
fault detector picks up.
Ipmax>1.1pu represents that the maximum phase current is greater than 1.1pu after the fault
detector picks up.
Flg_CTS is the internal flag indicating that CT circuit failure is distinguished.
[x.AlmH_CTS] is the alarm signal of CT circuit failure of x side of transformer.
[87T.Alm_CTS] is the alarm signal of CT circuit failure for current differential protection. If CT
circuit failure for REF protection or winding differential protection is detected, the corresponding
signal [64REF.Alm_CTS] or [87W.Alm_CTS] will be issued.
4.3.2 Voltage Transformer Supervison (VTS)

The VTS logic in the relay is designed to detect the VT secondary circuit to ensure that voltage
measurement is the actual value of power system. When VT failure is detected, equipment can
automatically adjust the configuration of protective elements of which the stability would be
affected and might lead to mal-operation.
z VT circuit abnormality supervision
If one of following four criteria is met and there is no operation of any fault detectors VT circuit
abnormality alarm will be issued after 10s. The abnormality alarm will be reset after 10s if

Date: 2011-10-20
4 Supervision
equipment returns to normal condition.
When the secondary phase-to-phase voltage of VT is equal to 100V:
1) Positive sequence voltage is less than 30 V and any phase current is greater than 0.04 In.
2) Positive sequence voltage is less than 30 V and the breaker is in closed position.
3) The negative sequence voltage is greater than 8 V.
4) The 3rd harmonic magnitude of phase voltage is greater than 10V.
If the secondary phase-to-phase rated voltage is set to 110V, all corresponding operating voltage
will be adjusted in the same ratio.
z Logic
Figure 4.3-3 Voltage pre-processing logic diagram
Where:
Up_3rd is the 3rd harmonic value of phase voltage.
U2 and U1 are respectively negative sequence voltage value and positive sequence current value.
[52b] is the binary input of auxiliary normally closed contact of a circuit breaker.
[Onload] is a flag indicating there is load current detected.
[In_VT] is the input signal of indicating VT in service.
[Alm_VTS] is the alarm message of VT secondary circuit abnormality.
4.3.3 Frequency Supervison

If system frequency detected is too high or low, transformer relay will send alarm signal [Alm_Freq]
instantly tor reminde users for attention. Users can configure two settings [f_High_FreqAlm] and
[f_Low_FreqAlm] in “System Settings” menu.
4.4 Failure and Abnormality Alarms
NOTE! Following alarm messages and corresponding LED indicators are fixed in
equipment software. Besides, there are other programmable LED indicators configured

Date: 2011-10-20
4 Supervision
according to user requirement.
4.4.1 Hardware Self-supervision Alarms

Equipment hardware circuits and software working conditions are always monitored by the relay. If
any abnormality occurs, the corresponding alarm message will be issued on the LCD of the
equipment.
When some light failures are detected, part of protection functions probably be disabled and
others can still work. Some servere failures of hardware or software will result in the equipment
being blocked and the contacts of equipment failure will operate at same time. During that
condition, the protection relay has to be out of service for maintenance.
NOTE! If alarm signal is issued with equipment being blocked, please try to make a fault
diagnosis by referring the issued alarm messages but not simply reboot or re-power the
relay. If user cannot find the failure reason on site, please inform the manufacturer or the
agent for maintenance.
Table 4.4-1 Equipment self-check alarm list
No. Alarm Message Meaning Description
1 Alm_Device The device is abnormal.
2 Alm_CommTest The device is in the communication test mode.
3 Alm_TimeSync Time synchronization abnormality alarm.
The error is found during checking the version of software

4 Alm_Version
downloaded to the device.
The error is found during MON module checking settings of

5 Alm_Settings_MON
device.
6 BI_Maintenance The device is in maintenance state.
The active group set by settingsin device and that set by binary
7 Alm_BI_SettingGrp
input are not matched
8 Bx.Alm_OptoDC The power supply of BXX binary input module is abnormal.
Duration of pickup of any fault detector on protection module is

9 ProtBrd.Alm_Pkp
in excess of 10s.
Duration of pickup of any fault detector on fault detector

10 FDBrd.Alm_Pkp
module is in excess of 10s.
When No.1~No.15 messages are issued on the LCD of the relay, the LED “HEALTHY” is steady green and
the protection equipment is not blocked with the LED “ALARM” being lit.
11 Fail_Device The device fails.
12 Fail_Setting_OvRange Setting values are out of range.
Mismatch between the configuration of plug-in boards and the

13 Fail_BoardConfig
designing drawing of an applied-specific project.

Date: 2011-10-20
4 Supervision
After config file is updated, settings of the file and settings

14 Fail_SettingItem_Chgd
saved on the device are not matched.
15 ProtBrd.Fail_Settings Error is found during checking settings on protection module.
Error is found during checking settings on fault detector

16 FDBrd.Fail_Settings
module.
Error is found during checking the memory data on protection

17 ProtBrd.Fail_Memory
module.
Error is found during checking the memory data on fault

18 FDBrd.Fail_Memory
detector module.
19 ProtBrd.Fail_Sample Sample values on protection module are abnormal.
20 FDBrd.Fail_Sample Sample values on fault detector module are abnormal.
Software configuation on protection module is found

21 ProtBrd.Fail_Config
incorrectly.
Software configuation on fault detector module is found

22 FDBrd.Fail_Config
incorrectly.
23 ProtBrd.Fail_DSP DSP chip on protection module is damaged.
24 FDBrd.Fail_DSP DSP chip on fault detector module is damaged.
The quality factor of sample values on protection module is

25 ProtBrd.Fail_QF_SV
abnormal.
The quality factor of sample values on fault detector module is

26 FDBrd.Fail_QF_SV
abnormal.
Driving circuits of binary output relays on the BXX module are

27 Bx.Fail_Output
damaged.
When No.8~No.24messages are issued on the LCD, the LED “HEALTHY” is extinguished, and the
protection equipment is blocked at the same time, but the LED “ALARM” is not lit.
Handling suggestion:
1. No.1, No.11: The signal is issued with other specific alarm signals, and please refer to the
handling suggestion other specific alarm signals.
2. No.2: No special treatment is needed. Just wait the completion of communication test., or exit
the test.
3. No.3: Step1: check whether the selected clock synchronization mode matches the clock
synchronization source;
Step 2: check whether the wiring connection between the equipment and the clock
synchronization source is correct
Step 3: check whether the setting for selecting clock synchronization (i.e. [Opt_TimeSync]) is
set correctly. If there is no clock synchronization, please set the setting [Opt_TimeSync] as
“No TimeSync”.

Date: 2011-10-20
4 Supervision
After the abnormality is removed, the “ALARM” LED will be extinguished and the
corresponding alarm message will disappear and the equipment will restore to normal
operation state.
4. No.4: Users may pay no attention to the alarm signal in the project commissioning stage, but it
is needed to download the latest package file (including correct version checksum file)
provided by R&D engineer to make the alarm signal disappear. Then users get the correct
software version. It is not allowed that the alarm signal is issued on the device already has
been put into service. the devices having being put into service so that the alarm signal
disappears
5. No.6: After maintenance is finished, please de-energized the binary input [BI_Maintenance]
and then the alarm will disappear and the equipment restore to normal operation state.
6. No.7: Please check the value of setting [Active_Grp] and binary input of indiating active group,
and make them matched. Then the “ALARM” LED will be extinguished and the corresponding
alarm message will disappear and the equipment will restore to normal operation state.
7. No. 8: Step 1: check whether the binary input module is connected to the power supply.
Step 2: check whether the voltage of power supply is in the required range.
After the voltage for binary input module restores to normal range, the “ALARM” LED will be
extinguished and the corresponding alarm message will disappear and the equipment will
restore to normal operation state.
8. No.9~No.10: Please check secondary values and protection settings. If settings are not set
reasonable to make fault detectors pick up, please reset settings, and then the alarm
message will disappear and the equipment will restore to normal operation state.
NOTE! Tripping out contacts are blocked in 1s after a transformer relay is energized with
“HEALTHY” LED indicatior being lit. This situation is decided as a relay fault, and the alarm
signal [ProtBrd.Alm_Pkp] and [FDBrd.Alm_Pkp] will be issued after tripping output contacts
keeps on picking up over10s.
9. No.12: Please reset setting values according to the range described in the instruction manual,
then re-power or reboot the equipment and the alarm message will disappear and the
equipment will restore to normal operation state.
10. No.13: Step 1: Go to the menu “Information”->”Borad Info”, check the abnormality
information.
Step 2: For the abnormality board, if the board is not used, then remove, and if the board is
used, then check whether the board is installed properly and work normally.
After the abnormality is removed, re-power or reboot the equipment and the equipment will
restore to normal operation state.
11. No.14: Please check the settings mentioned in the prompt message on the LCD, and go to
the menu “Settings” and select “Confirm_Settings” item to comfirm settings. Then, the

Date: 2011-10-20
4 Supervision
equipemtn will restore to normal operation stage.
12. No.15, No.16: Step 1: Check CT ratio settings of each side of transformer to be set in proper
range, and if need, please reset those settings and reboot or re-power the equipment.
Step 2: Check overexcitation settings to be set reasonable, and if need, please reset those
settings and reboot or re-power the equipment.
Step 3: After above two steps, abnormality may disappear. Otherwise, a hardware failue
probably occurs and please inform the manufacture or the agent.
13. No.5, No.17, No.18: Please inform the manufacture or the agent for maintenance.
14. No.19 No.20: Step 1: Please make the equipment out of service.
Step 2: Then check if the analog input modules and wiring connectors connected to those
modules are installed at the position.
Step 3: Re-power the equipment and the equipment will restore to normal operation state.
15. No.21, No.22: Please inform configuration engineers to check and confirm visualization
functions of the device
16. No.23, No.24: Chips are damaged and please inform the manufacture or the agent replacing
the module.
17. No.25, No.26: Thess alarms may be issued for electric transformer applied projects. If alarms
are issued, please check working state of merging units and the connection between merging
units and the protection device.
18. No.27: Please re-insert the corresponding binary output module and re-power the equipment
after the completion of insertion, and the equipment will restore to normal operation state.
NOTE! If the equipment still cannot restore to normal operation state after suggested
procedures, please inform the manufacture or the agent for maintenance.
4.4.2 Equipment Operation Alarms

During the equipment normal operation, VT and CT circuit and some binary input circuits are
always monitored by the relay. If any abnormality of them occurs or any alarm element operates,
the corresponding alarm message will be issued on the LCD of the equipment without blocking
equipment.
When this kind of alarm messages are issued, user need to find the abnormality reason, and then
take corresponding measures to eliminate the alarm message to make the equipment return to the
normal operation state.
Table 4.4-2 Equipment operation alarm list
1 87T.Alm_CTS Secondary circuit failure of CT used in all differential protections.

Date: 2011-10-20
4 Supervision
2 x.AlmH_CTS CT secondary circuit at x side fails.
When No.1~No.2 messages are issued on LCD, conventional differential protection can be blocked by configuring
the corresponding logic setting.
CT secondary circuit failure for restricted earth fault protection of x

3 x.64REF.Alm_CTS
side fails.
When No.5~No.7 messages are issued on LCD, restricted earth fault protection of the corresponding side can be
blocked by configuring the corresponding logic setting.
Differential current of current differential protection is in excess of

4 87T.Alm_Diff
normally endurable level.
Differential current for restricted earth fault protection of x side is

5 x.64REF.Alm_Diff
abnormal.
6 x.Alm_VTS VT secondary circuit at x side is abnormal.
7 x.AlmL_CTS CT secondary circuit at x side is abnormal.
8 x.49.Alm Thermal overload protection operates to issue alarm signal.
9 24DT2.Alm Definite-time overexciation alarm element operates.
10 24IDMT.Alm Inverse-time overexciation alarm element operates.
11 x.50Alm1.Alm Stage 1 overload alarm element of x side operates.
12 x.50Alm2.Alm Stage 2 overload alarm element of x side operates.
13 Alm_Freq System frequency abnormality alarm signals.
PCS-Explore software, which may be “H”, “HV” “HVS”, “HVS1”,” HVS2”, etc. If only one
protection element is equipped, the prefix “x.” will disappear.
Handing suggestion:
1. No.1~No.3: Please check the corresponding CT secondary circuit. After the abnormality is
eliminated, equipment can return to normal operation state by energizing the binary input
[BI_RstTarg].
2. No.4~No.5 Please check the corresponding sampling values and VT/ CT secondary circuit to
find out the reason resulting in the abnormality. If sample values of the equipment are not
correct, please inform the manufacturer or agent for maintenance, and if it is caused by the
failure of the VT/CT secondary circuit or primary system, please finish troubleshooting
according to the operating instructions of protection relay.
3. No.6~No.7: Please check the corresponding CT secondary circuit. After the abnormality is
eliminated, “ALARM” LED will go off automatically and equipment returns to normal operation
state.
4. No.9~No.12: Please treat according to the specific application requirements.
5. No.13: Please check device measured frequence with system acutual frequence. If device

Date: 2011-10-20
4 Supervision
measured frquencey is not consistent with the system acutual frequence, please check the
device. If they are consistent, users please take measure according requrirments.

Date: 2011-10-20
4 Supervision

Date: 2011-10-20
5 Measurement and Recording
Table of Contents
5.1 General Description......................................................................................... 5-1

5.2 Measurement ................................................................................................... 5-1
5.3 Event & fault Records ..................................................................................... 5-3
5.3.1 Introduction .........................................................................................................................5-3
5.3.2 Event Recording .................................................................................................................5-3
5.3.3 Disturbance and Fault Recording .......................................................................................5-3
5.3.4 Present Recording ..............................................................................................................5-4
PCS-978 Transformer Protection 5-a

Date: 2011-11-08

Date: 2011-11-08
5.1 General Description
The relay also provides some auxiliary functions, such as on-line data metering, binary input
status, event and disturbance recording, etc. All these make the relay meet the demands of the
modern power grid requirements.
5.2 Measurement
The equipment performs continuous measurement of the analogue input quantities. The
measurement data shown below is displayed on the LCD of the relay front panel or on the local or
remote PC.
Equipment samples 24 points per cycle. Calculate the RMS value in each interval and LCD will be
updated every 0.5 second.
Fourier algorithm is adpted to calculate fundamental current amplitude, fundamental voltage

amplitude, 2nd-5th harmonic amplitudes and RMS value of 1st-7th harmonics in the equipemtn. For
thermal overload protection and overload alarm elements, RMS value of 1st -7th harmonics is used
for the protection calculation. The calculation of otherprotection elements of the device is based on
fundermental current or voltage amplitude, and harmonic blocking function is selectable for some
protections (refer to Chapter 3 Operation Theory ) for details.
1. RMS Value
1) Access path: Press key “▲” to enter main menu firstly.
2) Select the item “Measurements “ and press key “ENT” to enter.
3) Select submenu “Measurements1” (from protection DSP) or “Measurements2” (from fault

detector DSP).
4) Press key “ENT” to display corresponding measurement values as below on the LCD.
Directly measured value
z Phase currents and phase voltages of each side
z Broken-delta voltages of each side
z Neutral currents of each side
Calculated value
z Calculated residual voltages and negative-sequence voltages of each side
z Calculated residual currents of each side
z Corrected currents of each side
z Differential current and restraint threshold for conventional current differential protection
z Residual differential currents and restraint thresholds for each REF protection

Date: 2011-11-08
z Differential currents and restraint thresholds for each winding differenital protection
z Secondary rated currents of each side
z Corrected coefficients for REF protection and winding differential protection
z Corrected coefficients for winding differential protection and winding differential protection
z the percentage of second and third harmonics to differential current respectably
2. Phase angle
Access path:
1) Press key “▲” to enter main menu firstly.
2) Select the item “Measurements “ and press key “ENT” to enter, and then
3) Select submenu “Measurements1” (from protection DSP) or “Measurements2” (from fault

detector DSP).
z Angle between currents of each side
z Angle between voltages of each side
z Angle between voltage and current of each side
z Angle between corrected currents of each side for conventional current differential protection
z Angle between corrected currents of each REF protection
Please refer to each protection element in the Chapter “of Operation Theory” for detailed sample
value and phase angle,
3. Measurement of the primary value
Access path:
1) Press key “▲” to enter main menu firstly.
2) Select the item “Measurements “ and press key “ENT” to enter, and then
3) Select submenu “Measurements3”.
No. Symbol Definition Unit
20 x.P The primary value of active power (P) MW
21 x.Q The primary value of reactive power (Q) MVar
22 x.S The primary value of apparent power (S) MVA
23 x.Cos The value of power factor (Cos) -

Date: 2011-11-08
5.3 Event & fault Records
5.3.1 Introduction
The protection equipment provides the following recording functions:
z Event recording
z Fault and disturbance recording
z Present recording
All the recording information except waveform can be viewed on local LCD or by printing.
Waveform must be printed or be extracted using PCS-PC software and a waveform software.
5.3.2 Event Recording

The equipment can store 1024 abnormality alarm reports, 1024 binary input stage changing
reports respectively. All the records are stored in non-volatile memory, and when the available
space is exhausted, the oldest report is automatically overwritten by the latest one
z Abnormality alarm reports
An abnormality alarm being detected during relay self-check supervision or an alarm of secondary
circuit abnormality or protection alarm element will also be logged as individual events.
z Binary input status changing reports
When binary input status changes, the change information will be displayed on LCD and logged as
binary input change report at the same time.
5.3.3 Disturbance and Fault Recording
5.3.3.1 Application
Use the disturbance recorder to achieve a better understanding of the behavior of the power
network and related primary and secondary equipment during and after a disturbance. An analysis
of the recorded data provides valuable information that can be used to improve existing equipment.
This information can also be used when planning for new installations.
5.3.3.2 Design
Disturbance recorder is consisted of tripping report and fault waveform. Disturbance recorder is
triggered by fault detectors. The equipment can store 64 pieces of trip reports and waveforms in
non-volatile memory.
When protection operates, the operating information will be displayed on LCD and logged as trip

Date: 2011-11-08
record at same time, which can be viewed in trip report. Here fault recording includes two kinds of
cases:
1) Only the fault detector element operates.
2) The fault detector element operates associated with the operation of protective elements.
1. Trip record capacity and information
The equipment can store 64 pieces of trip reports in non-volatile memory. If a new fault occurs
when 64 faults have been stored, the oldest will be overwritten by the latest one..
The following items are recorded for one fault:
1) Sequence number
Each operation will be recorded with a sequence number in the report and displayed on LCD
screen.
2) Date and time of fault occurrence
The time resolution is 1 ms using the relay internal clock. Initiating date and time is when a fault
detector picks up. Relative time is the time when protection element operates to send tripping
signal after fault detector picks up.
3) Faulty phase
The faulty phase detected by the operating element is showed in the record report.
4) Trip mode
This shows the protection element that issues the tripping command. If no protection operates to
trip but only equipment fault detector picks up, fault report will record the title of fault detector.
2. Fault waveform record capacity and information
MON module of the relay can store 64 pieces of fault waveform oscillogram in non-volatile memory.
If a new fault occurs when 64 fault waveform recorders have been stored, the oldest will be
overwritten by the latest one.
Each fault record consists of all analog and digital quantities related to protection, such as original
current and voltage, differential current, alarm elements, and binary inputs and etc.
Each time recording includes 2-cycle pre-fault waveform and most 250 cycles can be recorded.
5.3.4 Present Recording

Present recording is used to record a piece of waveform of present operation equipment which
can be trigger manually on LCD of equipment or remotely through PCS-PC software. Recording
content of present recording is same to that of disturbance recording.
Each time recording includes 2-cycle waveform before triggering, and most 250 cycles can be
recorded.

Date: 2011-11-08
6 Hardware Description
Table of Contents
6.1 Overview........................................................................................................... 6-1

6.2 Typical Wiring .................................................................................................. 6-3
6.2.1 Plug-in Module Arrangement Scheme ................................................................................6-3
6.2.2 Conventional CT/VT Wiring ................................................................................................6-4
6.2.3 ECT/EVT Wiring .................................................................................................................6-6
6.3 Plug-in Module Terminal Definition ................................................................ 6-8

6.3.1 PWR Module (Power Supply) .............................................................................................6-8
6.3.2 MON Module (Manangement) ..........................................................................................6-10
6.3.3 DSP Module 1 (Protection Calculation) ............................................................................6-13
6.3.4 DSP Module 2 (Fault Detector Calculation) ......................................................................6-13
6.3.5 BI Module (Binary Input) ...................................................................................................6-14
6.3.6 BO Module (Binary Output) ..............................................................................................6-19
6.3.7 Mechanical Relay Modules (Optional) ..............................................................................6-22
6.3.8 AI Module (Analoge Input) ................................................................................................6-24
6.3.9 NET-DSP module (Optional) .............................................................................................6-49
6.3.10 HMI Module ....................................................................................................................6-49
6.4 Tripping Output Group .................................................................................. 6-49

6.5 Output Contact............................................................................................... 6-51
6.5.1 Tripping Output Contact ....................................................................................................6-51
6.5.2 Signal Output Contact.......................................................................................................6-51
List of Figures
Figure 6.1-1 Hardware diagram ................................................................................................6-1
Figure 6.1-2 Front view of PCS-978 .......................................................................................6-3
Figure 6.1-3 Typical rear view of PCS-978 ...............................................................................6-3
Figure 6.2-1 Rear view of fixed module position of 4U equipment .......................................6-4

Date: 2011-11-02
Figure 6.2-2 Typical wiring of PCS-978 (conventional CT/VT) ...............................................6-5
Figure 6.2-3 Typical wiring of PCS-978 (ECT/EVT) .................................................................6-7
Figure 6.3-1 Pin definition of DC power supply module NR1301A ........................................6-9
Figure 6.3-2 Rear view of MON modules ...............................................................................6-10
Figure 6.3-3 Wiring of communication interface ...................................................................6-13
Figure 6.3-4 Rear view of DSP modules ................................................................................6-14
Figure 6.3-5 Pin definition of tripping output module ..........................................................6-20
Figure 6.3-6 Pin definition of signal output module .............................................................6-21
Figure 6.3-7 Pin definition of mechanical relay IO module ..................................................6-23
Figure 6.3-8 Pin definition of AC analog output module ......................................................6-25
Figure 6.3-9 CT/VT connection for typical application 1 ......................................................6-26
Figure 6.3-10 CT/VT connection for typical application 2 ....................................................6-28
Figure 6.3-16 CT/VT connection for tyipical application 8 ...................................................6-43
Figure 6.3-17 Pin definition of DC analog output module ....................................................6-48
Figure 6.3-18 Typical connection of the module with external transducer ........................6-48
Figure 6.3-19 View of the NET-DSP module ..........................................................................6-49
List of Tables
Table 6.1-1 PCS-978 module configuration .............................................................................6-2

Date: 2011-11-02
6.1 Overview
Output Relay
Binary Input
External
Protection
Conventional CT/VT A/D Calculation
DSP
ECVT
Fault
A/D Detector Pickup
DSP Relay
ECVT
ETHERNET
LCD +E
GPS
Power
Uaux LED CPU
Supply
RJ45
Keypad
PRINT
Figure 6.1-1 Hardware diagram
The PCS-978 adopts 64-bit microchip processor CPU produced by FREESCALE as control core
for logic calculation and management function, meanwhile, adopts high-speed digital signal
processor DSP to be in charge of all the protection calculation. 24 points are sampled in every
cycle and parallel processing of sampled data can be realized in each sampling interval to ensure
ultra-high reliability and safety of protection equipment.
The working process of the device is as follows: firstly, the current and voltage is converted into
small voltage signal and sent to DSP module after being filtered and converted by AD for
protection calculation and fault detector respectively. When DSP module completes all the
protection calculation, the result will be sent to 64-bit CPU on MON module to be recorded. DSP
module 1 carries out protection logic calculation, tripping output, and MON module completes
SOE (sequence of event) record, waveform recording, printing, communication between
protection and SAS and communication between HMI and CPU. The work process of fault
detector DSP module is similar to that of protection DSP module, and the only difference is, when
fault detector DSP module decides a fault detector picks up, only positive power supply of output
relay is switched on.
The PCS-978 is comprised of intelligent modules, except that few particular modules’ position
cannot be changed in the whole device (please refer to Figure 6.2-1 for details), the others like AI
(analog input) module such as AC current, AC voltage, DC current, and etc., and IO (input and
output) module such as binary input, tripping output, signal output, and etc can be flexibly
configured according to the remained slot positions.

Date: 2011-11-02
Table 6.1-1 PCS-978 module configuration

No. Module description
1 Management module (MON module)
2 Protection calculation module (DSP module 1)
3 Fault detector calculation module (DSP module 2)
4 Analog input module ( AI module )
5 DC analog input module (DC AI module)
6 Binary input module (BI module)
7 Tripping output module (BO trip module )
8 Signal output module (BO signal module )
9 Power supply module (PWR module)
10 Human machine interface module (HMI module)
11 NET-DSP module (optional)
z MON module provides functions like management function, completed event record, setting
management, and etc.
z DSP modules are totally the same, to carry out filtering, sampling and protection calculation
and fault detector calculation respectively.
z AI module converts AC current and voltage to low voltage signals with current transformers
and voltage transformers respectively.
z BI module provides binary input, and the binary is inputted via 24V/36V/110V/125V/
220V/250V opto-coupler (configurable).
z BO trip module provides all tripping outputs.
z BO signal module provides all kinds of signal output contact, including annunciation signal,
remote signal, fault and disturbance signal, operation abnormal signal and etc.
z PWR module converts DC 250/220/125/110V into different DC voltage levels for various
modules of the equipment
z HMI module is comprised of LCD, keypad, LED indicator and test serial ports, and it is
convenient for user to perform human-machine interaction with equipment.
z NET-DSP module (optional) is applied for realization of GOOSE level interlocking, and for
connection to ECVT with supporting IEC61850-9-1and IEC61850-9-2 protocols.
Following figures show front and rear views of PCS-978 respectively. Programmable LED
indicators (No.4-No.20) can be defined by users trough PCS-PC software.

Date: 2011-11-02
P
GR C
ES
Figure 6.1-2 Front view of PCS-978
NR1102D NR1156A NR1156A NR1401 NR1401 NR1504 NR1521A NR1521A NR1523B NR1301
1 2 3 1 2 3 5V OK ALM
4 5 6 4 5 6 BO_ALM BO_FAIL
ON
OFF
DANGER DANGER
1 BO_COM1
2 BO_FAIL
3 BO_ALM
4 BO_COM2
5 BO_FAIL
6 BO_ALM
7 OPTO+
8 OPTO-
9
10 PWR+
11 PWR-
12 GND
Figure 6.1-3 Typical rear view of PCS-978
6.2 Typical Wiring
6.2.1 Plug-in Module Arrangement Scheme

4U chassis of PCS-978 has 16 slots, and the irremovable modules are power supply module,
MON module and DSP module.

Date: 2011-11-02
DSP module 2
DSP module 1
MON module
PWR module
Figure 6.2-1 Rear view of fixed module position of 4U equipment
Besides the fixed four modules are shown in above figure, there are twelve slots can be flexibly
configured.
z AI module, BI module and BO module can be configured at position between slot B04 to slot
07.
z The AC AI module can be configured up to 4 pieces, and each AC AI module occupying 2

slots can provide 12 analog inputs.
z The DC current input module (also called DC AI module) can be configured at any slot
between slot B04 and slot B11, which can provide 6 DC current inputs.
z If the slots from slot B04 to slot B11 are not used up, the BI module and BO module can be
configured at the rest slots.
z BI module and BO module can be configured at any slot between slot B12 and slot B15.
6.2.2 Conventional CT/VT Wiring

Typical configuration of PCS-978 connected to conventional CT/VT configuration is give as below
for reference.
NR1102 NR1156A NR1156A NR1401 NR1401 NR1504 NR1521A NR1521A NR1523B NR1301
BO module for signal
BO module 1 for trip

AC AI module 1
AC AI module 2
DSP module 1
DSP module 2
MON module
PWR module
BI module
Slot No.
B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 P1
The following typical wiring is given based on above hardware configuration

Date: 2011-11-02
1201 Power supply supervision 1301

1302 BO_Trp_1-1
1202 + BI_TimeSyn
1303 PCS-978 HV side MV side
1304 BO_Trp_1-2
C B A C B A
1203 + BI_Print 1305 AI module 1
*BI module can be independent common terminal

1306 BO_Trp_1-3 CB1 CB2
0401
Three-phase current
*
1307 Ia
1204 + BI_Maintenance 0402
1308 BO_Trp_2-1
0403
*
1309 Ib 0404

1205 + BI_RstTarg 1310 BO_Trp_2-2
*
0405
1311 Ic 0406
1312 BO_Trp_3-1
1206 + BI_05
1313 0407
*
Three-phase current
BO_Trp_3-2 Ia 0408
1314
*
1207 + BI_06 1315 0409
1316 BO_Trp_4-1 Ib 0410
1208
*
Not used
1317 0411
1209 + BI_07 1318 BO_Trp_4-2 Ic 0412
1319
BO_Trp_5-1
…
1320 0413
Three-phase voltage
1321 Ua 0414
1214 + BI_12
BO_Trp_5-2 0415
1322
1215 Ub 0416
Not used
0417
1216 + BI_13 1401 Uc 0418
1402 BO_Trp_6-1
…
1403
0419
Three-phase voltage
1404 BO_Trp_6-2
1221 + BI_18 Ua 0420
1405
1222 BO_Trp_6-3 0421
1406
Ub 0422
1407
1408 BO_Trp_7-1 0423
Uc 0424
1409
1410 BO_Trp_7-2
PWR+ P110
External DC power Power 1411 AI module 2
supply
PWR- P111 Supply
1412 BO_Trp_8-1 *
0607
OPTO+ P107 1413 3I0
Power supply for 0608
BO_Trp_8-2
Neutral current
opto-coupler (24V) P108 1414

OPTO- 0609
1415
PWR module
3I0 0610
P101 BO_FAIL 1416 BO_Trp_9-1
P102 BO_ALM 1417 0611
3I0
P103 COM 1418 BO_Trp_9-2 0612 *
P104 BO_FAIL 1419
P105 1420 BO_Trp_10-1
BO_ALM
P106 COM 1421 0613
Three-phase voltage
P112 BO_Trp_10-2 Ua
1422 0614
Grounding
Screw 0615
Ub 0616
Grounding
Bus 1501 0617
1502 BO_Signal_1-1 Uc 0618
Ethernet A
1503
Ethernet B 1504 BO_Signal_1-2
0601
Three-phase current
Electrical
Ethernet to 1505 Ia 0602
Optional
SCADA Ethernet C BO_Signal_2-1

1506 0603
Ethernet D 1507 Ib 0604 *
BO_Signal_2-2
*
1508 0605
Optical
Optional
Ethernet C 1509 Ic
Ethernet to 0606
SCADA
*
1510 BO_Signal_3-1
Ethernet D
MON module
1511 0619
Reserved voltage
COM(optonal)
485-1A 0101 1512 BO_Signal_3-2 0620

cable with single point earthing
To the screen of other coaxial
485-1B 0102 1513 0621

input
SGND 0103 BO_Signal_4 0622

1514 CB3
0104 0623
1515 LV side
BO_Signal_5 0624
SYN+ 0101 1516 C B A
Clock SYN
SYN- 0102 1517

SGND 0103 1518 BO_Signal_6
0104 1519
1520 BO_Signal_7
RTS 0105 Multiplex
PRINT
1521 RJ45 (Front)

TXD 0106
1522 BO_Prot
SGND 0107
Figure 6.2-2 Typical wiring of PCS-978 (conventional CT/VT)

Date: 2011-11-02
6.2.3 ECT/EVT Wiring

Typical configuration of PCS-978 connected to conventional ECT/EVT configuration is give as
below for reference.
NR1102 NR1151A NR1151A NR1136A NR1136A NR1504 NR1521A NR1521A NR1523B NR1301
Slot No.
B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 P1
The following typical wiring is given based on above hardware configuration

Date: 2011-11-02
TX Power supply supervision 1201

Ch1
FO interface for SV channel

RX
BI_TimeSyn + 1202
NET-DSP module 1
TX
Ch2
(LC Type)
RX PCS-978
BI_Print + 1203
…
BI_Maintenance + 1204
SV from TX
ECT/EVT at Ch8
each side Phase A RX RX 1301
*BI module can be independent common terminal

transformer BO_Trp_1-1 1302 BI_RstTarg + 1205
MU
Phase B
1303
BO_Trp_1-2 1304
Phase C TX TX
Ch1 BI_05 + 1206
FO interface for SV channel

RX 1305
BO_Trp_1-3
NET-DSP module 2
1306
Up to 8 (LC Type)
TX
Ch2 1307 BI_06 + 1207
RX BO_Trp_2-1 1308
Not used 1208
1309

…
BO_Trp_2-2 1310 BI_07 + 1209

TX 1311
Ch8 BO_Trp_3-1
…
RX 1312
1313
BI_12 + 1214
BO_Trp_3-2 1314
RX IRIG-B 1315 1215
(optional) Not used
BO_Trp_4-1 1316
BI_13 + 1216
1317
P110 BO_Trp_4-2 1318
PWR+
…
External DC power Power
1319
supply P111 Supply
PWR- BO_Trp_5-1 1320 BI_18 + 1221
OPTO+ P107
Power supply for 1321
BO_Trp_5-2 1222
opto-coupler (24V) P108 1322
OPTO-
PWR module
P101 BO_FAIL
P102 BO_ALM
P103 1501
COM 1401
BO_Signal_1-1 1502
P104 BO_FAIL BO_Trp_6-1 1402
P105 BO_ALM 1503
1403
P106 BO_Trp_6-2 BO_Signal_1-2 1504
COM 1404
P112 1505
1405
Grounding BO_Signal_2-1
BO_Trp_6-3 1406 1506
Screw
1407 1507
Grounding BO_Trp_7-1 BO_Signal_2-2
1408 1508
Bus
1409 1509
Ethernet A BO_Signal_3-1 1510

BO_Trp_7-2 1410
Ethernet B 1511
1411
Electrical BO_Signal_3-2 1512
BO_Trp_8-1 1412
Etherneto
Optional
SCADA Ethernet C 1513

1413
BO_Trp_8-2 BO_Signal_4 1514
Ethernet D 1414
1415 1515
Optional
Optical Ethernet C BO_Trp_9-1 1416 BO_Signal_5 1516

Ethernet to
SCADA Ethernet D 1417 1517
MON module
BO_Trp_9-2 1418 BO_Signal_6 1518

COM(optonal)
485-1A 0101 1419 1519

cable with single point earthing
To the screen of other coaxial
485-1B 0102 BO_Trp_10-1 1420

BO_Signal_7 1520
SGND 0103 1421 1521
0104 BO_Trp_10-2
1422 BO_Prot 1522
SYN+ 0101
Clock SYN
SYN- 0102
SGND 0103
0104
Multiplex
RTS 0105 RJ45 (Front)
PRINT
TXD 0106
SGND 0107
Figure 6.2-3 Typical wiring of PCS-978 (ECT/EVT)

Date: 2011-11-02
In the protection system adopting electronic current and voltage transformer (ECT/EVT), the
merging unit will merge the sample data from ECT/EVT, and then send it to the device through
multi-mode optical fibre. Two DSP modules respectively receive the data from merging unit
through the optical-fibre interface to complete the protection calculation and fault detector.
The difference between the hardware platform based on ECT/EVT and the hardware platform
based on conventional CT/VT lies in the receiving module of sampled values only, and the device
receives the sampled value from merging unit through multi-mode optical fibre.
6.3 Plug-in Module Terminal Definition
Equipment consists of power supply module, MON module, DSP module, Analog input module,
opto-coupler input module, tripping output module, signal output module, input and output signal
for mechanical relay. The definition and application of each module and its terminal is introduced
as follows:
6.3.1 PWR Module (Power Supply)

The power supply module (NR1301) is a DC/DC or AC/DC converter with electrical insulation
between input and output. The power supply module has an input voltage range as described in
Chapter “Technical Data”. The standardized output voltages are +3.3V, +5V, ±12V and +24V DC.
The tolerances of the output voltages are continuously monitored.
The +3.3V DC output provides power supply for the microchip processors, and the +5V DC output
provides power supply for all the electrical elements that need +5V DC power supply in this device.
The ±12V DC output provides power supply for A/D conversion circuits in this device, and the
+24V DC output provides power supply for the static relays of this device.
The use of an external miniature circuit breaker is recommended. The miniature circuit breaker
must be in the on position when the device is in operation and in the off position when the device is
in cold reserve.
A 12-pin connector is fixed on the front of the power supply module. The pin definition of the
connector is described as below.

Date: 2011-11-02
NR1301A
5V OK ALM
BO_ALM BO_FAIL
1 BO_COM1 01
BO_FAIL
2 BO_FAIL 02
BO_ALM
3 BO_ALM 03
4 BO_COM2 04
BO_FAIL
5 BO_FAIL 05
BO_ALM
6 BO_ALM 06
7 OPTO+
8 OPTO-
9
10 PWR+
11 PWR-
12 GND
Figure 6.3-1 Pin definition of DC power supply module NR1301A
Pin No. Symbol Description
01 BO_COM1 Common terminal 1
02 BO_FAIL Device failure output 1 (01-02, NC)
03 BO_ALM Device abnormality alarm output 1 (01-03, NO)
04 BO_COM2 Common terminal 2
05 BO_FAIL Device failure output 2 (04-05, NC)
06 BO_ALM Device abnormality alarm output 2 (04-06, NO)
07 OPTO+ Positive pole of power supply for Low-voltage BI module (24V)
08 OPTO- Negative pole of power supply for Low-voltage BI module (24V)
09 Not used
10 PWR+ Positive pole of power supply for the device (250/220V/125/110V)
11 PWR- Negative pole of power supply for the device (250/220V/125/110V)
12 GND Grounded connection of the device
NOTE! The rated voltage of DC power supply module is self-adaptive to 220Vdc and
110Vdc, but the power supply in other DC voltage level or power supply of AC voltage
need to be specially ordered, and check if the rated voltage of power supply module is
the same as the voltage of external control power supply before equipment being put into

Date: 2011-11-02
service.
NOTE! The DC power supply module provides pin 12 and earth connector for
grounding of equipment. The pin 12 shall be connected to earth connector and the
connected to the earth copper bar of panel via dedicated grounding wire.
NOTE! Effective grounding is the most important measure for equipment to prevent
EMI, so effective grounding must be ensured before the device is put into operation.
6.3.2 MON Module (Manangement)

The terminals of MON module (NR1102) and its wiring method are shown in the following figure.
The MON module consists of high-performance built-in processor, FLASH, SRAM, SDRAM,
Ethernet controller and other peripherals. Its functions include management of the complete
device, human machine interface, communication and waveform recording etc.
The MON module uses the internal bus to receive the data from other modules of the device. It
communicates with the LCD module by RS-485 bus. This module is provided with 100BaseT
Ethernet interfaces, RS-485 communication interfaces, PPS/IRIG-B differential time
synchronization interface and RS-232 printing interface.
Figure 6.3-2 Rear view of MON modules
Module ID Memory Interface Terminal No. Usage Physical Layer

NR1102A 64M DDR 2 RJ45 Ethernet To SCADA Twisted pair wire

Date: 2011-11-02

01 SYN+
02 SYN- To clock
RS-485
03 SGND synchronization
04
05 RXD
RS-232 06 TXD To printer
07 SGND
4 RJ45 Ethernet To SCADA
01 SYN+
02 SYN- To clock
RS-485
NR1102B 64M DDR Twisted pair wire
04
05 RXD
07 SGND
01 SYN+
02 SYN- To clock
RS-485
NR1102C 128M DDR Twisted pair wire
04
05 RXD
07 SGND
01 SYN+
02 SYN- To clock
RS-485
NR1102D 128M DDR Twisted pair wire
04
05 RXD
07 SGND
2 RJ45 Ethernet To SCADA Twisted pair wire
2 FO Ethernet To SCADA Optical fibre SC
01 SYN+
02 SYN- To clock
RS-485
NR1102H 128M DDR 03 SGND synchronization
04 Twisted pair wire
05 RXD
07 SGND
2 RJ45 Ethernet To SCADA Twisted pair wire
NR1102I 128M DDR
2 FO Ethernet To SCADA Optical fibre ST

Date: 2011-11-02

01 SYN+
02 SYN- To clock
RS-485
04 Twisted pair wire
05 RXD
07 SGND
01 485-1A To SCADA
02 485-1B
RS-485
03 SGND
04
05 485-1A
06 485-1B
RS-485 To SCADA
07 SGND
NR1101E 128M DDR 08 Twisted pair wire
09 SYN+
10 SYN- To clock
RS-485
12
13 RXD
15 SGND
16 FGND To earth
The correct method of connection is shown in Figure 6.3-3. Generally, the shielded cables with two
pairs of twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to
connect the “+” and “–” terminals of difference signal; the other pair of twisted pairs are used to
connect the signal ground of the interface, i.e. connect the signal groundings of all the devices
connected with the bus to the twisted pair. The module reserves a free terminal for all the
communication ports; the blank terminal does not need to be connected.

Date: 2011-11-02
Twisted pair wire

485-1A 01
485-1B 02
SGND 03
04
Twisted pair wire

SYN+ 01
SYN- 02
SGND 03
04
Twisted pair wire

RTS 05
TXD 06
SGND 07
Figure 6.3-3 Wiring of communication interface
6.3.3 DSP Module 1 (Protection Calculation)

The module consists of high-performance digital signal processor, optical-fibre interface, 16-digit
high-accuracy ADC that can perform synchronous sampling and other peripherals. The functions
of this module include analog data acquisition, sample data exchanging with the opposite side,
calculation of protection logic and tripping output etc.
When the module is connected to conventional CT/VT, it can perform the synchronous data
acquisition through the AC input board; when the module is connected to ECVT, it can receive the
real-time synchronous sample data from merging unit through the multi-mode optical-fibre
interface.
6.3.4 DSP Module 2 (Fault Detector Calculation)

The module consists of high-performance digital signal processor, optical-fibre interface, 16-digit
high-accuracy ADC that can perform synchronous sampling and other peripherals. The functions
of this module include analog data acquisition, calculation of fault detector elements and providing
positive power supply to output relay.
When the module is connected to conventional CT/VT, it can perform the synchronous data
acquisition through the AC input board; when the module is connected to ECVT, it can receive the
real-time synchronous sample data from merging unit through the multi-mode optical-fibre
interface.
DSP module 1 and DSP module 2 have same hardware configuration. The following figure shows
rear views and terminal definitions for different type of DSP modules; the corresponding module
shall be adopted in accordance with concrete situation.

Date: 2011-11-02
NR1156A NR1151D NR1152A
1 2 3 1 2 3 1 2 3
4 5 6 4 5 6 4 5 6
TX1
TX1 Multi-mode optical
fibre, used to ECVT
TX2
TX2
TX3
TX4
RX1
RX2
RX3
RX4
Figure 6.3-4 Rear view of DSP modules
Module ID Description
NR1156A 36 analog sampling channels, applied for conventional CT/VT.
NR1151D No analog sampling channel, applied for ECVT to receive signal from motherboard bus
NR1152A It is used to ECVT, 8 receiving channels, applied for ECVT to receive signal directly.
6.3.5 BI Module (Binary Input)

There are two kinds of BI modules available, NR1503 and NR1504. Up to 2 BI modules can be
equipped with on device. The input voltage can be selected to be 24V/48V (NR1503D or
NR1504D) or 110V/220V/125V/250V (NR1503A or Nr1504A). This module provides the
monitoring circuit of opto-coupler power supply.
Each BI module is with a 22-pin connector for 11 binary inputs (NR1503) or 18 binary inputs
(NR1504).

Date: 2011-11-02
For NR1503, each binary input has independent negative power input of opto-coupler, and can be
configurable. The terminal definition of the connector of BI module is described as below. [BI_n]
(n=01,02,…,10,11 can be configured as a specified binary input by PCS-PC software.)
Figure 6.3-4 Pin definition of BI module (NR1503)

Date: 2011-11-02
For NR1504, all binary inputs share one common negative power input, and can be configurable.
The terminal definition of the connector is described as below. [BI_n] (n=01,02,…,14 can be
configured as a specified binary input by PCS-PC software.)
Figure 6.3-4 Pin definition of BI module (NR1504)
Pin description for NR 1503 and NR1504 are shown as follows respectively.
1. NR1503

01 BI_TimeSyn Binary input of time synchronization pulse
02 Opto01- Negative pole of first binary input
03 BI_Print Binary input of triggering printing
04 Opto02- Negative pole of second binary input
05 BI_Maintenance Binary input of indicating the protection device is under maintenance state
06 Opto03- Negative pole of third binary input
07 BI_RstTarg Binary input of resetting signal of protective equipment
08 Opto04- Negative pole of 4th binary input
09 BI_05 Configurable binary input 5

Date: 2011-11-02

2. NR1504

01 Opto+ Positive pole of power supply of the module
08 Blank Not used
15 Blank Not used
22 COM- Common terminal of negative pole of power supply of the module
NOTE! If one BI module is configured, first four binary signals (BI_01, BI_02, BI_03,
BI_04) in the module are are [BI_TimeSyn], [BI_Print], [BI_Maintenance] and [BI_RstTarg]
respectively.

Date: 2011-11-02
NOTE! If more than one BI module is configured, first four binary inputs (BI_01, BI_02,
BI_03, BI_04) in the first BI module (i.e. the BI module at the left-most side slot from rear
view) are fixed, they are [BI_TimeSyn], [BI_Print], [BI_Maintenance] and [BI_RstTarg]
respectively.
1. Binary input: [BI_Pulse_GPS]
It is used to receive clock synchronism signal from GPS or other device, the binary input
[BI_Pulse_GPS] will change from “0” to “1” once GPS is received. When setting [Opt_TimeSyn] is
select as “PPM(DIN) “ , the device receives pulse per minute (PMS) via the binary input
[BI_Pulse_GPS].,.
2. Binary input: [BI_Print]
It is used to manually trigger printing latest report when the equipment is configured as manual
printing mode by logic setting [En_AutoPrint]=0. The printer button is located on the panel usually.
If the equipment is configured as automatic printing mode ([En_AutoPrint]=1), report will be printed
automatically as soon as it is formed.
3. Binary input: [BI_Maintenance]
It is used to block communication export when the BI is energized. During equipment maintenance
or testing, the BI is then energized not to send reports via communication port, local display and
printing still work as usual. The BI should be de-energized when the equipment is restored back to
normal.
4. Binary input: [BI_RstTarg]
It is used to reset latching signal relay and LCD displaying. The reset is done by pressing a button
on the panel.
NOTE! The rated voltage of binary input is optional: 24V, 48V, 110V, 125V, 220V or 250V,
which must be specified when placed order. It is necessary to check whether the rated
voltage of BI module complies with site DC supply rating before put the relay in service.
The application of the binary input [BI_Maintenance] for digital substation communication adopting
IEC61850 protocol is given as follows.
1) Processing mechanism for MMS (Manufacturing Message Specification) message
a) The protection device should send the state of this binary input to client.
b) When this binary input is energized, the bit “Test” of quality (Q) in the message sent
change “1”.
c) When this binary input is energized, the client cannot control the isolator link and circuit
breaker, modify settings and switch setting group remotely.
d) According to the value of the bit “Test” of quality (Q) in the message sent, the client

Date: 2011-11-02
discriminate whether this message is maintenance message, and then deal with it
correspondingly. If the message is the maintenance message, the content of the message
will not be displayed on real-time message window, audio alarm not issued, but the picture
is refreshed so as to ensure that the state of the picture is in step with the actual state. The
maintenance message will be stored, and can be inquired, in independent window.
2) Processing mechanism for GOOSE message
a) When this binary input is energized, the bit “Test” in the GOOSE message sent by the
protection device changes “1”.
b) For the receiving end of GOOSE message, it will compare the value of the bit “Test” in the
GOOSE message received by it with the state of its own binary input (i..e
[BI_Maintenance]), the message will be thought as invalid unless they are conformable.
3) Processing mechanism for SV (Sampling Value) message
a) When this binary input of merging unit is energized, the bit “Test” of quality (Q) of sampling
data in the SV message sent change “1”.
b) For the receiving end of SV message, if the value of bit “Test” of quality (Q) of sampling
data in the SV message received by it is “1”, the relevant protection functions will be
disabled, but under maintenance state, the protection device should calculate and display
the magnitude of sampling data.
c) For duplicated protection function configurations, all merging units of control module
configured to receive sampling should be also duplicated. Both dual protection devices
and dual merging units should be fully independent each other, and one of them is in
maintenance state will not affect the normal operation of the other.
6.3.6 BO Module (Binary Output)
6.3.6.1 Tripping Output Module (NR1521A)
NR1521A is a standard binary output module, which can provide 11 tripping output contacts and
output contacts can be controlled separately by positive power supply of fault detector. The
contacts provide by NR1521A are all normally open (NO) contacts.
[BO_Trp_n] (n=1,2,…,11) and [BO_Signal_n] (n=1,2,…,11) can be configured as a specified

tripping output contact and a signal output contact respectively only by PCS-PC software
according to user requirement.
A 22-pin connector is fixed on the front of this module. The pin definition of the connector is
described as below.

Date: 2011-11-02
Figure 6.3-5 Pin definition of tripping output module
6.3.6.2 Signal Output Module (NR1523B)
The NR1523B module is a standard binary output module for signal, which can provide 11 signal
output contacts without control by fault detector. Among those contacts, contacts [BO_Signal_n]
(n=1,2,…,7, 10) are normally open (NO) contacts and [BO_Signal_8] and [BO_Siganl_9] are
normally closed (NC) contacts. All contacts can be configured as specified signal output contacts
of some protection by PCS-PC software according to user requirement. Besides, the contact
[BO_Prot] is a magnetic latched NO contact defined as protection tripping signal fixedly.
described as below.

Date: 2011-11-02
Figure 6.3-6 Pin definition of signal output module
NOTE! If more magnetic latched contacts or normally closed (NC) contacts are required,
please specific when placing order.
Default pin definitions of the signal output module are shown below.
Original New-defined
Pin No. Description
Symbol Symbol
01 BO_Signal_1+ BO_Signal_1-1+
The NO contact 1 of 1st group of signal output.
02 BO_Signal_1- BO_Signal_1-1-
The NO contact 2 of 1st group of signal output.
The NO contact 1 of 2nd group of signal output.
The NO contact 2 of 2nd group of signal output.
The NO contact 1 of 3rd group of output.

Date: 2011-11-02
Pin No. Description
Symbol Symbol
The NO contact 2 of 3rd group of output.
13 BO_Signal_7+ BO_Signal_4+
The NO contact of 4th group of output.
14 BO_Signal_7- BO_Signal_4-
The NC contact of 5th group of output.
The NC contact of 6th group of output.
The NO contact of 7th group of output.
21 BO_Signal_11+ BO_Prot_+ The NO magnetic latched contact for indicating protection
22 BO_Signal_11- BO_Prot_- operation.
6.3.7 Mechanical Relay Modules (Optional)

NR1536A (220Vdc) and NR1536B(110Vdc/125V) are input and output modules (IO module) for
mechanical protection, and this module is used to output various signals, issue trip commands and
accept reset command.
described as below.

Date: 2011-11-02
NR1536A NR1536B
NR1536A/B (MR IO Module)
01 Reset Signal ResetInput
02 BI_MR1
High Voltage
Binary Input
03 Signals of BI_MR2
Mechanical BI_MR3
04
protection
05 BO_MR4
06 BO_MR1_1
07 BO_MR2_1
08 BO_MR3_1
09 BO_MR4_1
10 Common1
11 BO_MR1_2
12 BO_MR2_2
13 BO_MR3_2
14 BO_MR4_2
15 Common2
16 BO_MR1_3
17 BO_MR2_3
18 BO_MR3_3
19 BO_MR4_3
20 Common3
21 Pwr+
Module Power Input
22 Pwr -
Figure 6.3-7 Pin definition of mechanical relay IO module

Reset input, when a reset signal arrives, the corresponding magnetic lateched
01 ResetInput
contacts of mechanical signals are reset.
Mechanical signal inputs
02 BI_MR1 Mechancia relay (MR) signal input 1
st
1 group output contacts (magnetic latched contact)
10,02 BO_MR1_1 NO contact, is closed when binary input [BI_MR1] is energized.

Date: 2011-11-02

nd
2 group output contacts
rd
3 group output contacts
Power supply input of module
20 Pwr+ Positive pole of power of the board connected to DC power supply
21 Pwr- Negative pole of power of the board connected to DC power supply
6.3.8 AI Module (Analoge Input)
6.3.8.1 AC Analog Input Module (NR1401)
The protection device which supports ECVT should not be equipped with this module. The analog
input module can transform these high AC input values to relevant low AC output value for the
DSP module. The transformers are used both to step-down the currents and voltages to levels
appropriate to the electronic circuitry of this device and to provide effective isolation between this
device and the power system. A low pass filter circuit is connected to each transformer (CT or VT)
secondary circuit for reducing the noise of each analog AC input signal.
NOTE! The rated value of the input current transformer is optional: 1A or 5A. The rated
value of the CT must be definitely declared in the technical scheme and the contract.
NOTE! Because the rated value of the input current transformer is optional, it is
necessary to check whether the rated values of the current transformer inputs are
accordant to the demand of the engineering before putting the device into operation.
The NR1401 module has 12 input transformers, and each channel can be configured as a
specified current or voltage channel by PCS-PC software according to user requirements. There
are three kinds of typical application module as follwing shows.
z Type A: 6I and 6U, 6 current channels and 6 voltage channels.
z Type B: 9I and 3U, 9 current channels and 3 voltage channels
z Type C: 12I, 12 current channels.
The rated values of current inputs are selected at order.

Date: 2011-11-02
described as below.
NR1401
NR1401 NR1401 NR1401
I1 01 I1n 02 I1 01 I1n 02 I1 01 I1n 02
I2 03 I2n 04 I2 03 I2n 04 I2 03 I2n 04
I3 05 I3n 06 I3 05 I3n 06 I3 05 I3n 06
I4 07 I4n 08 I4 07 I4n 08 I4 07 I4n 08
I5 09 I5n 10 I5 09 I5n 10 I5 09 I5n 10
I6 11 I6n 12 I6 11 I6n 12 I6 11 I6n 12
U1 13 U1n 14 I7 13 I7n 14 I7 13 I7n 14
U2 15 U2n 16 I8 15 I8n 16 I8 15 I8n 16
U3 17 U3n 18 I9 17 I9n 18 I9 17 I9n 18
U4 19 U4n 20 U1 19 U1n 20 I10 19 I10n 20
U5 21 U5n 22 U2 21 U2n 22 I11 21 I11n 22
U6 23 U6n 24 U3 23 U3n 24 I12 23 I12n 24
Figure 6.3-8 Pin definition of AC analog output module
NOTE! In above figure, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12 and U1, U2, U3, U4,
U5, U6 are polarity terminals of corresponding relevant voltage and current inputs
respectively.
NOTE! If user needs other analog input configuration, please declare in the technical
scheme and the contract.
6.3.8.2 CT/VT Connection for Tyipcal Application
1. Two-winding transformer application 1
In this application, there are one branch at HV side and two branches at LV side without voltage
input.
AI Module Configuration:
Slot No. Module ID Type

B04 NR1401 12 current channels

Date: 2011-11-02
The CT/VT wiring diagram for the application is shown below.
LV side 2
A
HV side LV side 1
A A
B B
C
C
0420 0419 0422 0421
0401 0407
0402 0408
0403 0409
0404 0410
0405 0411
0406 0412
PCS-978
0413
0414
0415
0416
0417
0418
Figure 6.3-9 CT/VT connection for typical application 1
The following table lists the pin definition of AI module.
Pin No. Description
Symbol Symbol
0401 I1 Ia_H The phase A current input of HV side (polarity).
0402 I1n Ian_H The phase A current input of HV side.
0403 I2 Ib_H The phase B current input of HV side (polarity).
0404 I2n Ibn_H The phase B current input of HV side.
0405 I3 Ic_H The phase C current input of HV side (polarity).
0406 I3n Icn_H The phase C current input of HV side.
0407 I4 Ia_L1 The phase A current input of LV side 1 (polarity).
0408 I4n Ian_L1 The phase A current input of LV side 1.
0409 I5 Ib_L1 The phase B current input of LV side 1 (polarity).
0410 I5n Ibn_L1 The phase B current input of LV side 1.
0411 I6 Ic_L1 The phase C current input of LV side 1 (polarity).

Date: 2011-11-02
Pin No. Description
Symbol Symbol
0412 I6n Icn_L1 The phase C current input of LV side 1.
0419 I10 3I0_H The neutral current input of HV side (polarity).
0420 I10n 3I0n_H The neutral current input of HV side.
0421 I11 3I0_L The neutral current input of LV side (polarity).
0422 I11n 3I0n_L The neutral current input of LV side.
0423 I12 Reserved
0424 I12n Reserved
In this application, there is one branch at HV and LV side respectively with voltage input.

B04 NR1401 9 current channels and 3voltage channels

Date: 2011-11-02
*
*
*
*
*
Pin No. Description
Symbol Symbol
0407 I4 Ia_L The phase A current input of LV side (polarity).
0408 I4n Ian_L The phase A current input of LV side.
0409 I5 Ib_L The phase B current input of LV side (polarity).
0410 I5n Ibn_L The phase B current input of LV side.
0411 I6 Ic_L The phase C current input of LV side (polarity).
0412 I6n Icn_L The phase C current input of LV side.

Date: 2011-11-02
Pin No. Description
Symbol Symbol
0417 I9 Reserved
0418 I9n Reserved
0419 U1 Ua_H The phase A voltage input of HV side (polarity).
0420 U1n Uan_H The phase A voltage input of HV side.
0421 U2 Ub_H The phase B voltage input of HV side (polarity).
0422 U2n Ubn_H The phase B voltage input of HV side.
0423 U3 Uc_H The phase C voltage input of HV side (polarity).
0424 U3n Ucn_H The phase C voltage input of HV side.

B04 NR1401 9 current inputs and 3voltage inputs

Date: 2011-11-02
HV side
*
*
A
*
*
B
*
*
C
0416 0415
0401 0407
0402 0408
0403 0409
0404 0410
0405 0411
0406 0412
PCS-978
0419
0420
0421
0422
0423
0424
Pin No. Description
Symbol Symbol

Date: 2011-11-02
Pin No. Description
Symbol Symbol
0413 I7 Reserved
0414 I7n Reserved
0417 I9 Reserved
0418 I9n Reserved

B04 NR1401 6 current inputs and 6 voltage inputs

Date: 2011-11-02
HV side LV side
*
A A
*
*
B B
*
*
C C
*
0608 0607 0612 0611
0401 0601
0402 0602
0403 0603
0404 0604
0405 0605
0406 0606
0619 0623
0620
PCS-978 0624
0413 0613
0414 0614
0421 0615
0415 0616
0416 0617
0417 0618
Pin No. Description
Symbol Symbol
0407 I4 Reserved
0408 I4n Reserved
0409 I5 Reserved
0410 I5n Reserved
0411 I6 Reserved
0412 I6n Reserved

Date: 2011-11-02
Pin No. Description
Symbol Symbol
0419 U4 Reserved
0420 U4n Reserved
0421 U5 Reserved
0422 U5n Reserved
0423 U6 Reserved
0424 U6n Reserved
Pin No. Description
Symbol Symbol
0609 I5 Reserved
0610 I5n Reserved
0613 U1 Ua_L The phase A voltage input of LV side (polarity).
0614 U1n Uan_L The phase A voltage input of LV side.
0615 U2 Ub_L The phase B voltage input of LV side (polarity).
0616 U2n Ubn_L The phase B voltage input of LV side.
0617 U3 Uc_L The phase C voltage input of LV side (polarity).
0618 U3n Ucn_L The phase C voltage input of LV side.
0619 U4 3U0_H The residual current input of HV side (polarity).
0620 U4n 3U0n_H The residual current input of HV side.
0621 U5 Reserved

Date: 2011-11-02
Pin No. Description
Symbol Symbol
0622 U5n Reserved
0623 U6 3U0_L The residual current input of LV side (polarity).
0624 U6n 3U0n_L The residual current input of LV side.

*
*
*
*
*
*
Pin No. Description
Symbol Symbol

Date: 2011-11-02
Pin No. Description
Symbol Symbol
0407 I4 Reserved
0408 I4n Reserved
0409 I5 Reserved
0410 I5n Reserved
0411 I6 Reserved
0412 I6n Reserved
0419 U4 Reserved
0420 U4n Reserved
0421 U5 Reserved
0422 U5n Reserved
0423 U6 Reserved
0424 U6n Reserved
Pin No. Description
Symbol Symbol
0607 I4 Reserved

Date: 2011-11-02
Pin No. Description
Symbol Symbol
0608 I4n Reserved
0609 I5 Reserved
0610 I5n Reserved
0621 U5 Reserved
0622 U5n Reserved
6. Three-winding Transformer application 2
In this application, there is one branch at each side of transformer respectively with voltage input.


Date: 2011-11-02
LV side
*
A
*
B
HV side
*
A C
*
B
*
C MV side
*
A
*
B
*
C
*
0608 0607 0610 0609
0401
0402
0407
0403 0408
0404
0409
0405 0410
0406
0411
0412
0619
0620 0621
0622
0413
0414
0419
0415
0420
0416
0421
0417
0422
0418
PCS-978 0423
0424
0601
0602
0603
0604
0605
0606
0623
0624
0613
0614
0615
0616
0617
0618
The following tables list the pin definition of AI module.
Pin No. Description
Symbol Symbol
0407 I4 Ia_M The phase A current input of MV side (polarity).
0408 I4n Ian_M The phase A current input of MV side.
0409 I5 Ib_M The phase B current input of MV side (polarity).
0410 I5n Ibn_M The phase B current input of MV side.

Date: 2011-11-02
Pin No. Description
Symbol Symbol
0411 I6 Ic_M The phase C current input of MV side (polarity).
0412 I6n Icn_M The phase C current input of MV side.
0419 U4 Ua_M The phase A voltage input of MV side (polarity).
0420 U4n Uan_M The phase A voltage input of MV side.
0421 U5 Ub_M The phase B voltage input of MV side (polarity).
0422 U5n Ubn_M The phase B voltage input of MV side.
0423 U6 Uc_M The phase C voltage input of MV side (polarity).
0424 U6n Ucn_M The phase C voltage input of MV side.
Pin No. Description
Symbol Symbol
0609 I5 3I0_M The neutral current input of MV side (polarity).
0610 I5n 3I0n_M The neutral current input of MV side.
0611 I6 Reserved
0612 I6n Reserved

Date: 2011-11-02
Pin No. Description
Symbol Symbol
0621 U5 3U0_M The residual current input of MV side (polarity).
0622 U5n 3U0n_M The residual current input of MV side.
7. Three-winding Transformer application 2
In this application, PCS-978 supports 4 CT groups, two neutral CT and 3 three-phase VTs.


Date: 2011-11-02
*
*
*
*
*
*
*
*
*
*
*
*
*
Pin No. Description
Symbol Symbol
0401 I1 Ia_H1 The phase A current input of HV side 1 (polarity).
0402 I1n Ian_H1 The phase A current input of HV side 1.
0403 I2 Ib_H1 The phase B current input of HV side 1 (polarity).
0404 I2n Ibn_H1 The phase B current input of HV side 1.
0405 I3 Ic_H1 The phase C current input of HV side 1 (polarity).
0406 I3n Icn_H1 The phase C current input of HV side 1.

Date: 2011-11-02
Pin No. Description
Symbol Symbol
Pin No. Description
Symbol Symbol
0601 I1 Ia_M The phase A current input of MV side (polarity).
0602 I1n Ian_M The phase A current input of MV side.
0603 I2 Ib_M The phase B current input of MV side (polarity).
0604 I2n Ibn_M The phase B current input of MV side.
0605 I3 Ic_M The phase C current input of MV side (polarity).
0606 I3n Icn_M The phase C current input of MV side.
0615 I8 3I0_M The neutral current input of MV side (polarity).
0616 I8n 3I0n_M The neutral current input of MV side.
0617 I9 Reserved
0618 I9n Reserved

Date: 2011-11-02
Pin No. Description
Symbol Symbol
8. Auto-transformer/three-winding application
In this application, PCS-978 supports 6 CT groups, 3 neutral CTs and 3 three-phase VTs with
broken-delta voltage input. For auto-transformer or three-winding transformer application, users
can wiring PCS-978 according to the following wiring diagram.

B08 NR1401 12 current inputs

Date: 2011-11-02
LV side 2
*
A
*
B
*
C
LV side 1
*
A
*
B
*
C
0801
0802
Portion of
0803
PCS-978 0804
0805
0623 0806
0624
0613 0807
0614 0808
0615 0809
0616 0810
0617 0811
HV side 2 0618 0812
*
A
MV side 2
*
A
*
*
B
*
*
C
HV side 1
*
*
A MV side 1
*
A
*
*
*
B
*
*
*
C
*
0820 0819
0813
0814
01815
0816
0817
0818
0621
0619 0622
0620
0419
0413 0420
0414 0421
0415 0422
0416 0423
0417 0424
0418
PCS-978
0601
0401 0602
0402 0603
0403 0604
0404 0605
0405 0606
0406
0607
0407 0608
408 0609
0409 0610
0410 0611
0411 0612
0412
Figure 6.3-16 CT/VT connection for tyipical application 8
Pin No. Description
Symbol Symbol
0406 I3n Icn_H1 The phase C current input of HV side1.

Date: 2011-11-02
Pin No. Description
Symbol Symbol
Pin No. Description
Symbol Symbol
0601 I1 Ia_M1 The phase A current input of MV side 1 (polarity).
0602 I1n Ian_M1 The phase A current input of MV side 1.
0603 I2 Ib_M1 The phase B current input of MV side 1 (polarity).
0604 I2n Ibn_M1 The phase B current input of MV side 1.
0605 I3 Ic_M1 The phase C current input of MV side 1 (polarity).
0606 I3n Icn_M1 The phase C current input of MV side1.
0607 I4 Ia_M2 The phase A current input of MV side 2 (polarity).
0608 I4n Ian_M2 The phase A current input of MV side 2.
0609 I5 Ib_M2 The phase B current input of MV side 2 (polarity).
0610 I5n Ibn_M2 The phase B current input of MV side 2.
0611 I6 Ic_M2 The phase C current input of MV side 2 (polarity).
0612 I6n Icn_M2 The phase C current input of MV side 2.

Date: 2011-11-02
Pin No. Description
Symbol Symbol
0621 U5 3U0_M The residual current input of MV side (polarity).
0622 U5n 3U0n_M The residual current input of MV side.
Pin No. Description
Symbol Symbol
0806 I3n Icn_L1 The phase C current input of LV side1.
0813 I7 Ia_CW The phase A voltage input of common winding (polarity).
0814 I7n Ian_CW The phase A voltage input of common winding.
0815 I8 Ib_CW The phase B voltage input of common winding (polarity).
0816 I8n Ibn_CW The phase B voltage input of common winding.
0817 I9 Ic_CW The phase C voltage input of common winding (polarity).

Date: 2011-11-02
Pin No. Description
Symbol Symbol
0818 I9n Icn_CW The phase C voltage input of common winding.
0819 I10 3I0_CW Neutral current input of common winding (polarity).
0820 I10n 3I0n_CW Neutral current input of common winding.
0821 I11 Reserved
0822 I11n Reserved
0823 I12 Reserved
0824 I12n Reserved
6.3.8.3 CT Rquirement
-Rated primary current Ipn:
According to the rated current or maximum load current of primary apparatus.
-Rated continuous thermal current Icth:
According to the maximum load current.
-Rated short-time thermal current Ith and rated dynamic current Idyn:
According to the maximum fault current.
-Rated secondary current Isn
-Accuracy limit factor Kalf:
Ipn Rated primary current (amps)

Icth Rated continuous thermal current (amps)
Ith Rated short-time thermal current (amps)
Idyn Rated dynamic current (amps)
Isn Rated secondary current (amps)
Kalf Accuracy limit factor
Kalf=Ipal/Ipn
IPal Rated accuracy limit primary current (amps)
Performance verification
Esl > Esl’
Esl Rated secondary limiting e.m.f (volts)

Esl = kalf*Isn*(Rct+Rbn)
Kalf Accuracy limit factor
Kalf=Ipal/Ipn
IPal Rated accuracy limit primary current (amps)

Date: 2011-11-02

Rct Current transformer secondary winding resistance. (ohms)
Rbn Rated resistance burden(ohms)
Rbn=Sbn/Isn2
Sbn Rated burden (VAs)
Esl’ Required secondary limiting e.m.f (volts)

Esl’ = k*Ipcf *Isn*(Rct+Rb)/Ipn
k stability factor = 2
Ipcf Protective checking factor current (amps)
Same as the maximum prospective fault current
Rct Current transformer secondary winding resistance. (ohms)
Rb Real resistance burden (ohms)
Rb=Rr+2*RL+Rc
Rc Contact resistance, 0.05-0.1 ohm(ohms)
RL Resistance of a single lead from relay to current
transformer(ohms)
Rr Impedance of relay phase current input (ohms)
For example，Kalf=30, Isn=5A, Rct=1ohm, Sbn=60VA
Esl = kalf*Isn*(Rct+Rbn) = kalf*Isn*(Rct+ Sbn/Isn2)= 30*5*(1+60/52)=510V
Ipcf=40000A, RL=0.5ohm, Rr=0.1ohm, Rc=0.1ohm, Ipn=2000A
Esl’ = 2*Ipcf *Isn*(Rct+Rb)/Ipn= 2*Ipcf *Isn*(Rct+(Rr+2*RL+Rc))/Ipn
= 2*40000*5*(1+(0.1+2*0.5+0.1))/2000=440V
Esl > Esl’
6.3.8.4 DC Analog Input Module (NR1410B)
Transducer input module NR1410B can receive six input signals which can be 4~20mA current or
0~5V voltage from external transducer. The hardware and the software of the protection
equipment are provided to receive these signals from the external transducers and convert these
signals into a digital format for use as required. There are four pins 13, 16, 19 and 22 on the
module are ground terminals of the equipment.
described as below.

Date: 2011-11-02
NR1410B
01
02
Input_1+ 03
Input_1- 04
05
06
Input_2+ 07
Input_2- 08
09
10
Input_3+ 11
Input_3- 12
GND 13
Input_4+ 14
Input_4- 15
GND 16
Input_5+ 17
Input_5- 18
GND 19
Input_6+ 20
Input_6- 21
GND 22
Figure 6.3-17 Pin definition of DC analog output module
Typical connection of the module with external transducers is shown in the figure below, and there
is a jumper between pin S1 and pin S6 on module NR1401B to control the input signal type of the
module.
Figure 6.3-18 Typical connection of the module with external transducer
S1~S6 (OFF) 4-20mA shunt disabled and return paths interconnected and 0~5V measure provided.

Date: 2011-11-02
S1~S6 (ON) Input resistance with 4-20mA shunt enabled and 4~20mA measure provided.
6.3.9 NET-DSP module (Optional)

This module consists of high-performance DSP (digital signal processor), two 100Mbit/s
optical-fibre interface and two 100Mbit/s RJ-45 ethernet and other peripherals. It supports GOOSE
and SV by IEC 61850-9-2 protocols. It can receive and send GOOSE command to intelligent
control device, and receive SV from MU (merging unit).
This module supports IEEE1588 network time protocol, E2E and P2P defined in IEEE1588
protocol can be selected.This module supports Ethernet IEEE802.3 time adjustment message
format, UDP time adjustment message format and GMRP.
The view of the network DSP module is shown as below.
Figure 6.3-19 View of the NET-DSP module
6.3.10 HMI Module

The display panel consists of liquid crystal display module, keyboard, LED and ARM processor.
The functions of ARM processor include display control of the liquid crystal display module,
keyboard processing, and exchanging data with the CPU through serial port etc. The liquid crystal
display module is a high-performance grand liquid crystal panel with soft back lighting, which has a
user-friendly interface and an extensive display range.
6.4 Tripping Output Group
The PCS-978 provides output contacts which are controlled by tripping logic settings. Tripping

Date: 2011-11-02
logic settings of each protection element can be configured by users as per their requirements.
The tripping logic setting in form of [x.OutMap] is comprised of 16-bit binary number, but that
displayed on the LCD is 4-bit hexadecimal number. Each binary bit controls a set of tripping output
contacts. When the protection element operates, if the corresponding bit is set as “1”, the relevant
output contacts will pick up; if the bit is set as “0”, the relevant output relays will not pick up.
For typical configuration of PCS-978, two NR1521A modules are equipped with being installed
adjacently in slot S13 and slot S14, and then tripping output contacts controlled by logic setting are
list in the following table.
Table 6.4-1 Output contact groups of typical configuration
Contact
Bit Tripping output group Controlled contacts
amount
1301-1302, 1303-1304,
0 TrpOutp1: the 1st group of tripping output contacts 3
1305-1306
1 TrpOutp2: the 2nd group of tripping output contacts 1307-2808, 1309-1310 2
2 TrpOutp3: the 3rd group of tripping output contacts 1311-1312, 1313-1314 2
3 TrpOutp4: the 4th group of tripping output contacts 1315-1316, 1317-1318 2
1401-1402, 2903-1404
5 TrpOutp6: the 6th group of tripping output contacts 3
1405-1406,
6 TrpOutp7: the 7th group of tripping output contacts 2907-2908 2909-2910, 2
1419-1420
9 TrpOutp10: the 10th group of tripping output contacts 2
1421-1422
10 No definition
11 No definition
12 No definition
13 No definition
14 No definition
15 No definition
NOTE! Controlled contacts are represents with its slot position and pin number. For
example, contact 1301-1302 means terminal 01-02 of the module at the slot B13, i.e. 13
represents the slot position of module, 01(02) represents the pin number on the module.

Date: 2011-11-02
6.5 Output Contact
There are two types of output contact tripping output contact and signal output contact.
6.5.1 Tripping Output Contact

The protection equipment provides tripping contacts for tripping breaker generally. These contacts
are fixed on the tripping output modules. The number of tripping contacts can be flexibly
configured according to user requirement.
6.5.2 Signal Output Contact

The signal output contacts are classified into two types based on the sources: tripping output
contact and abnormal signal output contact. The tripping output contact picks up when protective
equipment operates and the abnormal signal output contact picks up when protective equipment is
in abnormal operation. Signals are divided into three types based on their applications:
annunciation signal, remote signal and fault&disturbance record (FDR) signal. The annunciation
signal is sent to local control panel the remote signal is sent to substation automation system, the
FDR signal is provided to independent fault recorder device. The annunciation output contact is
generally magnetic latched, so it needs manual reset and then the output contact can drop off.
The number of signal output contacts can be flexibly configured according t user requirement.
z Tripping output Contact
When the protection element operates, the equipment sends tripping command to drive the
tripping output contact and signal contact simultaneously. For example, when differential
protection operates, in addition to the pickup of tripping output contact controlled by the tripping
logic setting, the signal contacts are closed simultaneously, producing annunciation signal, remote
signal and FDR signal respectively. These contacts are assigned to contacts on signal output
module by PCS-PC software as user requirement.
z Abnormal Signal Output Contact
When some abnormal operation conditions are detected by protection equipment, the equipment
will send abnormal message to be displayed on the LCD and generate abnormal alarm signal.
These signals, such as equipment failure signal, CT circuit failure and so on, are used to produce
annunciation signal, remote signal and FDR signal. Please refer to power supply module for
detailed abnormal signal output contact.
z Abnormal Operation Contact
The abnormal operation contacts include initiating cooler, blocking on-load tap changing (OLTC)
function and etc. These contacts are assigned to contacts on signal output module by PCS-PC
software as user requirement.

Date: 2011-11-02

Date: 2011-11-02
7 Settings
7 Settings
Table of Contents
7.1 Overview........................................................................................................... 7-1

7.2 Device Settings ................................................................................................ 7-1
7.3 Communication Settings ................................................................................ 7-2
7.4 System Settings ............................................................................................... 7-6
List of Tables
Table 7.2-1 Device settings....................................................................................................... 7-1
Table 7.3-1 Communication settings ....................................................................................... 7-2
Table 7.4-1 System settings ..................................................................................................... 7-6
Table 7.4-2 Matrix of phase compensation ............................................................................. 7-8

Date: 2011-08-26
7 Settings

Date: 2011-08-26
7 Settings
7.1 Overview
Settings are classified to two kinds, protection settings and common settings. Each protection
element has its independent setting menu to configure which are given detailed description in
“Operation Theory”. Common settings consist of device settings, communication settings and
system settings,
The equipment has 10 setting groups for protection to coordinate with the mode of power system
operation, one of which is assigned to be active. However, common settings are shared by all
protection setting groups, and settings of protection element are set according to secondary
values.
7.2 Device Settings
z Setting list
Table 7.2-1 Device settings
No. Setting Item Range Description
Select encoding format of header (HDR) file

1 HDR_EncodeMode GB18030, UTF-8 COMTRADE recording file. Default value is
“UTF-8”.
Select the caption language sent to SAS via

2 Opt_Caption_103 0~1 IEC103 protocol. Default value is 0.
0: Local language; 1: Chinese
3 Un_BinaryInput 110V, 220V Voltage level of binary input
z Setting explanation
1. [HDR_EncodeMode], [Opt_Caption_103]
Two logic settings to select encoding format of header file and caption language of IEC103
protocol.
Default value of [HDR_EncodeMode] is 1((i.e. UTF-8 code) and please set it to 0 (i.e. GB18030)
according to the special requirement.
Default value of [Opt_Caption_103] is 0 (i.e. local language), and please set it to 1 (i.e. Chinese)
if the SAS is supplied by China Manufacturer.
2. [Un_BinaryInput]
The setting is used to set the voltage level of binary input module, and 110V or 220V can be
selected according to the actual requirement.
z Setting path
Access path in menu is:

Date: 2011-08-26
7 Settings
Main menu -> Settings -> Device Setup -> Device Settings
7.3 Communication Settings
z Setting list
Table 7.3-1 Communication settings
No. Settings item Range Description
000.000.000.000~
1 IP_LAN1 IP address of Ethernet port 1.
255.255.255.255
000.000.000.000~
2 Mask_LAN1 Subnet mask of Ethernet port1.
255.255.255.255
000.000.000.000~
3 IP_LAN2 IP address of Ethernet port 2.
255.255.255.255
000.000.000.000~
4 Mask_LAN2 Subnet mask of Ethernet port 2.
255.255.255.255
5 En_LAN2 0: disable, 1: enable Enable/disable the IP address of port 2.
6 IP_LAN3 0: disable, 1: enable IP address of Ethernet port 3.
000.000.000.000~
255.255.255.255
9 IP_LAN4 0: disable, 1: enable IP address of Ethernet port 4.
000.000.000.000~
255.255.255.255
000.000.000.000~
12 Gateway Gateway of router
255.255.255.255
Enable/disable sending message in broadcast

13 En_Broadcast 0: disable, 1: enable
mode via network. (IEC103).
Communication address between the protective

14 Addr_RS485A 0～255 device with the SCADA or RTU via RS-485 serial
port 1.
4800,9600,19200,
15 Baud_RS485A Baud rate of rear RS-485 serial port 1.
38400,57600,115200 bps
Communication protocol of rear RS-485 serial port

16 Protocol_RS485A 0～9
1.
Communication address between the protective

17 Addr_RS485B 0～255 device with the SCADA or RTU via RS-485 serial
port 2.

Date: 2011-08-26
7 Settings
No. Settings item Range Description
4800,9600,19200,
18 Baud_RS485B Baud rate of rear RS-485 serial port 2.
38400,57600,115200 bps
Communication protocol of rear RS-485 serial port

19 Protocol_RS485B 0～2
2.
Threshold value of sending measurement values to

20 Threshold_Measmt 0~100% SCADA through IEC103 or IEC61850 protocol.
Default value: “1%”.
The time period when the equipment sends

measurement data to SCADA through IEC103
21 Period_Measmt 0~65535s
protocol.
Default value:“60”.
Select the format of measurement data sent to

22 Format_Measmt 0, 1
SCADA through IEC103 protocol.
4800,9600,
23 Baud_Printer 19200,38400, 51600, Baud rate of printer port
115200 bps
0: disable
24 En_AutoPrint Enable/disable automatic printing function
1: enable
Conventional
SAS Select the mode of time synchronization of
25 Opt_TimeSyn
Advanced equipment.
NoTImeSyn
The address of the external SNTP clock

000.000.000.000~
26 IP_Server_SNTP synchronization server sending SNTP message to
255.255.255.255
the equipment.
The local time zone also refered to as the hour

27 OffsetHour_UTC -12~12hrs
offset hour from UTC .
28 OffsetMinute_UTC 0~60min The offset minute of local time from UTC.
Primary value/ Select display measurement values is primary value

29 Opt_Display_Status
Second value or secondary value
1. [En_LANx] (x= 2, 3, 4)
These setting are used to enable/disable IP addresses of Ethernet 2, 3 and 4 respectively. IP

address of Ethernet 1 is enabled fixedly.
“1”: enable the IP address of Ethernet port and the corresponding IP address setting is needed to
be set.
“0”: disable the IP address of Ethernet port and the corresponding IP address setting is not needed
to be set.

Date: 2011-08-26
7 Settings
2. [En_Broadcast]
This setting is only used only for IEC 103 protocol. If NR network IEC103 protocol is used, the
setting must be set as “1”.
0: the device does not send UDP messages through network;
1: the device sends UDP messages through network.
3. [Protocol_RS485x] (x=A, B)
The setting is used to select the communication protocol of rear RS-485 serial port X.
0: IEC 60870-5-103 protocol
1: Reserved
2: Modbus protocol
4. [Format_Measmt]
The setting is used to select the format of measurement data sent to SCADA through IEC103
protocol.
0: GDD data type through IEC103 protocol is 12;
1: GDD data type through IEC103 protocol is 7, i.e. 754 shorth real number of IEEE standard.
5. [En_AutoPrint]
If automatic print is required for disturbance report after protection operating, the setting should be
set as “1”.
6. [Opt_TimeSyn]
There are four selectons for clock synchronization of device, each selection includs different time
clock synchronization signals shown in following table.
Item Description
PPS(RS-485): Pulse per second (PPS) via RS-485 differential level.
IRIG-B(RS-485): IRIG-B via RS-485 differential level.
Conventional
PPM(DIN): Pulse per minute (PPM) via the binary input [BI_TimeSyn].
PPS(DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn].
SNTP(PTP): Unicast (point to point) SNTP mode via Ethernet network.
SAS SNTP(BC): Broadcast SNTP mode via Ethernet network.
Message (IEC103): Clock messages through IEC103 protocol.
IEEE1588: Clock message via IEEE1588.
Advanced IRIG-B(Fiber): IRIG-B via optical-fibre interface.
PPS(Fiber) PPS: Pulse per second (PPS) via optical-fibre interface.
When no time synchronization signal is connected to the equipment, please select
NoTimeSync
this option and the alarm message [Alm_TimeSync] will not be issued anymore.
“Conventional” mode and “SAS” mode are always be supported by device, but “Advanced” mdoe

Date: 2011-08-26
7 Settings
is only supported when NET-DSP module is equipped. The alarm signal [Alm_TimeSyn] may be
issued to remind user loss of time synchronization signals.
1) When “SAS” is selected, if there is no conventional clock synchronization signal, the device
will not send the alarm signal [Alm_TimeSyn]. When “Conventional”mode is slected, if there is
no conventional clock synchronization signal, “SAS”mode will be enabled automatically with
the alarm signal [Alm_TimeSyn] being issued simultaneously.
2) When “Advanced” mode is selected, if there is no conventional clock synchronization signal

connected to NET-DSP moduel，“SAS”mode is enabled automatically with the alarm signal
[Alm_TimeSyn] being issued simultaneously.
3) When “NoTimeSyn” mode is selected, the device will not send alarm signals without
NOTE! The clock message via IEC103 protocol is invalid when the device receives the
IRIG-B signal through RC-485 port.
7. [IP_Server_SNTP]
It is the address of the SNTP time synchronization server which sends SNTP timing messages to
the relay or BCU.
8. [OffsetHour_UTC], [OffsetMinute_UTC]
When the IEC61850 protocol is adopted in substations, if the time tags of communication
messages are required according to Universal Time Coordinated (UTC), the two settings are
used to set the local time of a country or area where the relay is installed. If there is no such a
requirement, the two settings must be set as “0”.
Example 1: In China where UTC offset is UTC +8:00, [OffsetHour_UTC] and [OffsetMinute_UTC]
should be set as “8hrs” and “0min” respectively.
Example 2: In Argentina where UTC offset is UTC-3:00, [OffsetHour_UTC] and

[OffsetMinute_UTC] should be set as “-3hrs” and “0min” respectively.
Example 3: In Nepal where UTC offset is UTC +5:45, [OffsetHour_UTC] and [OffsetMinute_UTC]
should be set as “+5hrs” and “45min” respectively.
Time zone GMT zone East 1st East 2nd East 3rd East 4th East 5th
Setting 0 1 2 3 4 5
th th th th th
Time zone East 6 East 7 East 8 East 9 East 10 East 11th
Setting 6 7 8 9 10 11
th st nd rd th
Time zone East/West 12 West 1 West 2 West 3 West 4 West 5th
Setting -12/12 -1 -2 -3 -4 -5
th th th th th
Time zone West 6 West 7 West 8 West 9 West 10 West 11th
Setting -6 -7 -8 -9 -10 -11
z Setting Path

Date: 2011-08-26
7 Settings
Main Menu -> Settings -> Device Setup -> Comm Settings
7.4 System Settings
z Setting list
Table 7.4-1 System settings
1 Active_Grp 1~10 1 Current setting group.
50Hz
2 Opt_SysFreq Select system working frequency.
60Hz
Max 20 Name of the protected primary equipment, such as

3 PrimaryEquip_Name
characters transformer, line, etc.
4 Sn 0.1~5000 0.001 MVA Transformer capacity
5 87R.Sn 0.1~5000 0.001 MVA Reactor capacity
6 87R.Un 0.1~2000 0.001 kV Primary rated phase-to-phase voltage of reactor
7 Un_HVS 0~2000 0.001 kV Primary rated voltage of HV side stated on nameplate.
8 Un_MVS 0~2000 0.001 kV Primary rated voltage of MV side stated on nameplate.
9 Un_LVS 0~2000 0.001 kV Primary rated voltage of LV side stated on nameplate.
Relative o’clock of MV side winding with respect to HV

10 Clk_MVS_WRT_HVS 0~11 1 Clk
side winding.
Relative o’clock of LV side winding with respect to HV

11 Clk_LVS_WRT_HVS 0~11 1 Clk
side winding.
The target o’clock each side current will be shift to for

12 Clk_PhComp 0~11 1 Clk
phase compensation
0: disable, Enable zero-sequence current elimination for phase

13 En_I0Elim_HVS
1: enable compensation of HV side.

14 En_I0Elim_MVS
1: enable compensation of MV side.

15 En_I0Elim_LVS
1: enable compensation of LV side.
16 x.U1n 0~2000 0.001 kV Primary rated voltage of VT.of x side
17 x.U2n 100~130 0.001 V Secondary rated voltage of VT of x side.
18 x.U1n_Delt 0~2000 0.001 kV Primary rated voltage of broken-delta VT of x side.
19 x.U2n_Delt 30~300 0.001 V Secondary rated voltage of broken-delta VT of x side.
20 x.I1n 0~60000 1 A Primary rated current of CT of x side.
21 x.I2n 1A or 5A A Secondary rated current of CT of x side.
22 x.I1n_Neu 0~60000 1 A Primary rated current of neutral CT at x side.

Date: 2011-08-26
7 Settings
23 x.I2n_Neu 1A or 5A A Secondary rated current of neutral CT at x side.
24 IntTurn.Z0 0~10000 1 ohm Impedance of neutral earthing reactor
25 f_High_FreqAlm 50~65 1 Hz High setting for frequency alarm.
26 f_Low_FreqAlm 40~60 1 Hz Low setting for frequency alarm.
NOTE! Symbol ”x” represents some side of transformer or VT/CT type only defined by
user through PCS-PC software, which may be “HVS”(HV side), “MVS”(MV side), etc.
1. [ Active_Grp]
The current protection setting group number, and total 10 group settings are provided. The device
settings, communication settings and system settings, are common for all protection groups.
2. [Sn], [Un_HVS], [Un_MVS], [Un_LVS], [x.U1n], [x.U2n], [x.I1n], [x.I2n]
During the calculation of current differential protection, in order to get current correction ratio of
each side of the transformer automatically, these basic parameters are needed, such as
transformer capacity, phase-to-phase primary voltages of each side and CT ratios of each side.
3. [Clk_MVS_WRT_HVS], [Clk_LVS_WRT_HVS], [Clk_LVS_WRT_HVS],

[Clk_PhComp], [En_IOElim_HVS], [En_I0Elim_MVS] [En_I0Elim_LVS]
[Clk_MVS_WRT_HVS],[Clk_LVS_WRT_HVS]: the wiring o’clock of MV/LV side with respect to HV

side, is the parameter shown on transformer nameplate with the range of 0~11, and need not
further calculation.
Clk_PhComp]: the target o’clock each side current will be shift to for phase compensation.
[En_I0Elim_HVS], [En_I0Elim_MVS] and [En_I0Elim_LVS]: logic settings to enable

zero-sequence current elimination for phase compensation of each side of transformer. The
setting is recommended to be set to “1” in general condition, and only if one side of transformer,
without eathing transformer being connected to, is no grounded, the setting of corresponding side
is recommended to be set to “0”.
For examples:
The vector group of a transformer is Y0/Δ11 and the target o’clock ([Clk_PhComp]) is set to “11”.
1) For HV side, the clock of HV side with reference to target o’clock is 1 (i.e. wiring o’clock
12-target o’clock 11) clock, so the matrix of relative o’clock 1 is adopted to compensate HV
side current. Zero-sequence current elimination has no effect on phase compensation in the
condition.
2) For LV side, the clock of LV side with reference to target o’clock is 0 (i.e. wiring o’clock 11-
target o’clock 11), so the matrix of relative o’clock 0 is adopted to compensate LV side current.
Then it is needed to decide whether zero-sequence current is eliminated and select the

Date: 2011-08-26
7 Settings
corresponding matrix.
If an earthing transformer is connected at LV side out the protection zone of differential

protection, then matrix of relative o’clock 0 without zero-sequence current elimination can be
selected.
If an earthing transformer is connected at LV side in the protection zone of differential

protection, then zero-sequence current must be eliminated and otherwise differential
protection may operate unexpectively during an external fault. Therefore the matrix of relative
o’clock 0 with zero-sequence current elimination should be selected.
Table 7.4-2 Matrix of phase compensation
Matrix Matrix
Relative
(without zero-sequence current (with zero-sequence current
o’clock
elimination) elimination)
⎡ 1 0 0⎤ ⎡ 2 − 1 − 1⎤
0
⎢0 1 0 ⎥ 1 ⎢
⋅ ⎢− 1 2 − 1⎥⎥
⎢ ⎥ 3
⎢⎣0 0 1⎥⎦ ⎢⎣− 1 − 1 2⎥⎦
⎡ 1 − 1 0⎤
1 ⎢
1 ⋅ ⎢ 0 1 − 1⎥⎥
3
⎢⎣− 1 0 1⎥⎦
⎡ 0 − 1 0⎤ ⎡ 1 − 2 1⎤
2
⎢ 0 0 −1 ⎥ 1 ⎢
⋅ ⎢ 1 1 − 2⎥⎥
⎢ ⎥ 3
⎢⎣− 1 0 0⎥⎦ ⎢⎣− 2 1 1⎥⎦
⎡ 0 − 1 1⎤
1 ⎢
3 ⋅ ⎢ 1 0 − 1⎥⎥
3
⎢⎣− 1 1 0⎥⎦
⎡0 0 1⎤ ⎡ − 1 − 1 2⎤
4
⎢ 1 0 0⎥ 1 ⎢
⋅ ⎢ 2 − 1 − 1⎥⎥
⎢ ⎥ 3
⎢⎣0 1 0⎥⎦ ⎢⎣− 1 2 − 1⎥⎦
⎡− 1 0 1⎤
1 ⎢
5 ⋅ ⎢ 1 − 1 0⎥⎥
3
⎢⎣ 0 1 − 1⎥⎦
⎡− 1 0 0⎤ ⎡− 2 1 1⎤
6
⎢ 0 − 1 0⎥ 1 ⎢
⋅ ⎢ 1 − 2 1⎥⎥
⎢ ⎥ 3
⎢⎣ 0 0 − 1⎥⎦ ⎢⎣ 1 1 − 2⎥⎦

Date: 2011-08-26
7 Settings
Matrix Matrix
Relative
(without zero-sequence current (with zero-sequence current
o’clock
elimination) elimination)
⎡ − 1 1 0⎤
1 ⎢
7 ⋅ ⎢ 0 − 1 1⎥⎥
3
⎢⎣ 1 0 − 1⎥⎦
⎡ 0 1 0⎤ ⎡ −1 2 − 1 ⎤
8
⎢0 0 1⎥⎥
1 ⎢
⋅ ⎢ −1 − 1 2 ⎥⎥
⎢ 3
⎢⎣ 1 0 0⎥⎦ ⎢⎣ 2 − 1 − 1⎥⎦
⎡ 0 1 − 1⎤
1 ⎢
9 ⋅ ⎢− 1 0 1⎥⎥
3
⎢⎣ 1 − 1 0⎥⎦
⎡ 0 0 − 1⎤ ⎡ 1 1 − 2⎤
10
⎢− 1 0 0⎥⎥
1 ⎢
⋅ ⎢− 2 1 1⎥⎥
⎢ 3
⎣⎢ 0 − 1 0⎥⎦ ⎣⎢ 1 − 2 1⎥⎦
⎡ 1 0 − 1⎤
1 ⎢
11 ⋅ ⎢− 1 1 0⎥⎥
3
⎢⎣ 0 − 1 1⎥⎦
4. [Un_HVS], [Un_MVS], [Un_LVS]
Setting principle of rated phase-to-phase voltages of each side is to take the primary rated
voltage marked on the nameplate of transformer as the primary rated voltage of corresponding
side. For an on-load tap changing transformer, the voltage of transformer with tap in middle
position can be taken as the value of this setting. As to other kind of transformers, actual
operation voltage (i.e. phase-to-phase voltage) shall be taken as this setting value, otherwise the
calculation of correction coefficient may be wrong
For example, if the voltage at 220kV side is 230kV for an on-load tap changing transformer with
tap in its middle position, and then the setting is set as 230kV.
NOTE! For one side not used in the relay, please set the primary rated voltage value of the
corresponding side as “0”.
5. [x.U1n], [x.U2n]
These settings are primary voltage and secondary voltage values of the three-phase VT of three
side of a transformer respectively, which are phase-to-phase voltage values.
For example, if the voltage ratio is 220kV/100V at HV side of a transformer, [HVS.U1n] shall be
set as “220kV” and [HVS.U2n] should be set as “100V”.

Date: 2011-08-26
7 Settings
6. [x.I1n], [x.I2n],[x.I1n_Neu], [x.I2n_Neu]
Set those settings respectively according to the actual primary value and secondary value of the
corresponding side CT.
7. [x.U1n], [x.U2n],[x.U1n_Delt], [x.U2n_Delt]
Set those settings respectively according to the actual primary value and secondary value of the
corresponding side VT.
z Setting path
Main Menu -> Settings -> System Settings

Date: 2011-08-26
Table of Contents
8.1 Overview........................................................................................................... 8-1

8.1.1 Keypad Operation ...............................................................................................................8-2
8.1.2 LED Indications ..................................................................................................................8-3
8.1.3 Front Communication Port ..................................................................................................8-4
8.1.4 Ethernet Pot Setup .............................................................................................................8-5
8.2 Understand the HMI Menu Tree ...................................................................... 8-6

8.2.1 Overview.............................................................................................................................8-6
8.2.2 Analog.................................................................................................................................8-9
8.2.3 Status................................................................................................................................8-10
8.2.4 Records ............................................................................................................................8-10
8.2.5 Settings............................................................................................................................. 8-11
8.2.6 Print ..................................................................................................................................8-12
8.2.7 Local Cmd ........................................................................................................................8-13
8.2.8 Information........................................................................................................................8-14
8.2.9 Test ...................................................................................................................................8-14
8.2.10 Clock...............................................................................................................................8-14
8.2.11 Language ........................................................................................................................8-14
8.3 Understand the LCD Display ........................................................................ 8-15

8.3.1 Overview...........................................................................................................................8-15
8.3.2 Display during Normal Operation ......................................................................................8-15
8.3.3 Display When Tripping ......................................................................................................8-16
8.3.4 Display under Abnormal Condition ...................................................................................8-17
8.3.5 Display When Binary State Changes ................................................................................8-18
8.3.6 Display Device Logs .........................................................................................................8-20
8.4 Keypad Operation .......................................................................................... 8-21

Date: 2011-11-04
8.4.1 View Device Analog ..........................................................................................................8-21
8.4.2 View Device Status ...........................................................................................................8-22
8.4.3 View Device Records........................................................................................................8-22
8.4.4 Print Device Records ........................................................................................................8-22
8.4.5 View Device Setting ..........................................................................................................8-23
8.4.6 Modify Device Setting .......................................................................................................8-24
8.4.7 Copy Device Setting .........................................................................................................8-27
8.4.8 Switch Setting Group ........................................................................................................8-27
8.4.9 Delete Records .................................................................................................................8-28
8.4.10 Modify Device Clock .......................................................................................................8-29
8.4.11 Check Software Version ..................................................................................................8-30
8.4.12 View Module Information ................................................................................................8-30
8.4.13 Communication Test .......................................................................................................8-31
8.4.14 Select Language .............................................................................................................8-32
List of Figures
Figure 8.1-1 Front panel of PCS-978 ........................................................................................8-1
Figure 8.1-2 Keypad mounted on the front panel ...................................................................8-2
Figure 8.1-3 the figure shows the LED indications .................................................................8-3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel..................................8-4
Figure 8.1-5 Rear view and terminal definition of NR1102C ..................................................8-6
Figure 8.2-1 Tree diagram of total command menu ................................................................8-8
Figure 8.3-1 LCD display of single line diagram ...................................................................8-15
Figure 8.3-2 LCD display 1 of trip report ...............................................................................8-16
Figure 8.3-3 LCD display 2 of trip report and alarm report ..................................................8-17
Figure 8.3-4 LCD display of alarm report...............................................................................8-18
Figure 8.3-5 Display of binary change report ........................................................................8-19
Figure 8.3-6 Display of control report ....................................................................................8-21
Figure 8.4-1 Display of inputting password ..........................................................................8-25
Figure 8.4-2 Display 1 of modifying settings.........................................................................8-26

Date: 2011-11-04
Figure 8.4-3 Display 2 of modifying settings.........................................................................8-26
Figure 8.4-4 Display of copy settings ....................................................................................8-27
Figure 8.4-5 Display of switching setting group ...................................................................8-28
Figure 8.4-6 Display of deleting report ..................................................................................8-29
Figure 8.4-7 Display of modifying clock ................................................................................8-30
Figure 8.4-8 Display of communication test..........................................................................8-31
Figure 8.4-9 Display of selecting language ...........................................................................8-32
List of Tables
Table 8.1-1 Definition of the 8-core cable ................................................................................8-4
Table 8.3-1 Tripping report messages ...................................................................................8-17
Table 8.3-2 Contact inputs list ................................................................................................8-19
Table 8.3-3 Contact oupputs list ............................................................................................8-20
Table 8.3-4 User Operating event list .....................................................................................8-21
PCS-978 Transformer Relay 8-c

Date: 2011-11-04
8-d PCS-978 Transformer Relay

Date: 2011-11-04
The operator can access the protective device from the front panel. Local communication with the
protective device is possible using a computer via a multiplex RJ45 port on the front panel.
Furthermore, remote communication is also possible using a PC with the substation automation
system via rear RS485 port or rear Ethernet port. The operator is able to check the protective
device status at any time.
This chapter describes human machine interface (HMI), and give operator an instruction about
how to display or print event report, setting and so on through HMI menu tree and display metering
value, including R.M.S. current, voltage and frequency etc. through LCD. Procedures to change
active setting group or a settable parameter value through keypad are also described in details.
NOTE！
About three measurements in menu “Measurements”, please refer to the following

description:
“Measurement1” is use to display measured values from protection calculation DSP

(displayed in secondary value)
“Measurement2” is used to display measured values from fault detector DSP (displayed
in secondary value)
“Measurement3” is used todisplay measured primary values and other calculated

quantities.
8.1 Overview
The human-machine interface consists of a human-machine interface (HMI) module which allows
a communication to be as simple as possible for the user. The HMI module helps to draw your
attention to something that has occurred which may activate a LED or a report displayed on the
LCD. Operator can locate the data of interest by navigating the keypad.
5
1
HEALTHY
11
PCS-978
2 12
ALARM TRANSFORMER RELAY
3 13
TRIP
4 14
5 15
6 16
ENT
7 17
8 18
1
9 19
3
10 20
4
2
Figure 8.1-1 Front panel of PCS-978

Date: 2011-11-04
The function of HMI module:
No. Item Description

A 320×240 dot matrix backlight LCD display is visible in dim lighting
1 LCD conditions. The corresponding messages are displayed when there is
operation implemented.
20 status indication LEDs, first three LEDs are fixed as the signals of
2 LED
“HEALTHY” , “ALARM” and “TRIP”, others are configurable.
3 Keypad Navigation keypad and command keys for full access to device
4 Communication port a multiplex RJ45 port for local communication with a PC
5 Logo Type and designation and manufacturer of device
8.1.1 Keypad Operation

P
GR
ESC
Figure 8.1-2 Keypad mounted on the front panel
1. “ESC”:
Cancel the operation
Quit the current menu
2. “ENT”:
Execute the operation
Confirm the interface
3. “GRP”
Activate the switching interface of setting group
4. leftward and rightward direction keys (“◄” and “►”):
Move the cursor horizontally
Enter the next menu or return to the previous menu
5. upward and downward direction keys (“▲” and “▼”)
Move the cursor vertically
Select command menu within the same level of menu

Date: 2011-11-04
6. plus and minus sign keys (“＋” and “－”)
Modify the value
Modify and display the message number
Page up/down
NOTE!
Any setting change shall be confirmed by simply pressing “+”, “3”, “5”, “-“, “ENT” in
sequence.
Any report deletion shall be executed by pressing “+”, “-“, “+”, “-“, “ENT” in sequence.
8.1.2 LED Indications
Figure 8.1-3 the figure shows the LED indications
A brief explanation has been made as bellow.
LED Display Description

When the equipment is out of service or any hardware error is
Off
HEALTHY detected during self-check.
Green Lit when the equipment is in service and ready for operation.
Off When equipment in normal operating condition.

ALARM Lit when VT circuit failure, CT circuit failure or other abnormal alarm
Yellow
is issued.
Off when the equipment is in normal operating condition

TRIP
Red Lit when any protection element trips.
NOTE! The “HEALTHY” LED can only be turned on by energizing the equipment again to
restart the relay.
“ALARM” LED is turned on when abnormalities of equipment occurs like above

mentioned and can be turned off after abnormalities are removed except alarm report
[Alm_CTS] which can only be reset only when the failure is removed and the equipment

Date: 2011-11-04
is rebooted or re-energized.
The “TRIP” LED is turned on and latched once any protection element operates and.
The “TRIP” LED can be turned off by pressing the signal RESET button on the front
panel.
Other LED indicators with no labels are configurable and user can configure them to be lit
by signals of operation element, alarm element and binary output contact according to
requirement through PCS-PC software, and there are three colors (green yellow and red)
for user selection.
8.1.3 Front Communication Port

There is a multiplex RJ45 port on the front panel. This port can be used as an RS-232 serial port
as well as a twisted-pair Ethernet port. As shown in the following figure, a customized cable is
applied for debugging via this multiplex RJ45 port.
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel
In the above figure and the following table:
P1: To connect the multiplex RJ45 port. An 8-core cable is applied here.
P2: To connect the twisted-pair Ethernet port of the computer.
P3: To connect the RS-232 serial port of the computer.
The definition of the 8-core cable in the above figure is introduced in the following table.
Table 8.1-1 Definition of the 8-core cable
Device side Computer side

Pin No. Core color Function
(Left) (Right)

Date: 2011-11-04
1 Orange TX+ of the Ethernet port P1-1 P2-1

2 Orange & white TX- of the Ethernet port P1-2 P2-2
3 Green & white RX+ of the Ethernet port P1-3 P2-3
4 Blue TXD of the RS-232 serial port P1-4 P3-2
5 Brown & white RXD of the RS-232 serial port P1-5 P3-3
6 Green RX- for the Ethernet port P1-6 P2-6
7 Blue & white The ground connection of the RS-232 port. P1-7 P3-5
8.1.4 Ethernet Pot Setup

MON plug-in module is equipped with two or four 100Base-TX Ethernet interface, take NR1102C
as an example, as shown in Figure 8.1-5.
The Ethernet port can be used to communication with PC via auxiliary software (PCS-PC) after
connecting the protection device with PC, so as to fulfill on-line function (please refer to the
instruction manual of PCS-PC). At first, the connection between the protection device and PC
must be established. Through setting the IP address and subnet mask of corresponding Ethernet
interface in the menu “Settings→Device Setup→Comm Settings”, it should be ensured that the
protection device and PC are in the same network segment. For example, setting the IP address
and subnet mask of network A. (using network A to connect with PC)
PC: IP address is set as “198.87.96.102”, subnet mask is set as “255.255.255.0”
The IP address and subnet mask of protection device should be [IP_LAN1]= 198.87.96.XXX,
[Mask_LAN1]=255.255.255.0, [En_LAN1]=1. (XXX can be any value from 0 to 255 except 102)
If the logic setting [En_LAN1] is non-available, it means that network A is always enabled.
NR1102C
ETHERNET
Network A
Network B
SYN+
SYN-
SGND
GND
RXD
TXD
SGND
GND

Date: 2011-11-04
Figure 8.1-5 Rear view and terminal definition of NR1102C
NOTE! If using other Ethernet port, for example, Ethernet B, the logic setting [En_LAN2]
must be set as “1”.
8.2 Understand the HMI Menu Tree
8.2.1 Overview
Press “▲” of any running interface and enter the main menu. Select different submenu by “▲” and
“▼”. Enter the selected submenu by pressing “ENT” or “►”. Press “◄” and return to the previous
menu. Press “ESC” and exit the main menu directly. For sake of executing the command menu
again, one command menu will be recorded in the quick menu after its first execution. Five latest
menu commands can be recorded in the quick menu. When the five menu commands are
recorded, the latest menu command will cover the earliest one, adopting the “first in first out”
principle. It is arranged from top to bottom and in accordance with the execution order of command
menus. Press “▲” to enter the main menu with the interface as shown in the following diagram:
Quick Menu
Language
Reset Target
Device Settings
Mainmenu
For the first powered protective device, there is no recorded shortcut menu. Press “▲” to enter the
main menu with the interface as shown in the following diagram:

Date: 2011-11-04
Measurements
Status
Records
Settings
Print
Local Cmd
Information
Test
Clock
Language

Date: 2011-11-04
Figure 8.2-1 Tree diagram of total command menu
Under the main interface, press “▲” to enter the main menu, and select submenu by pressing “▲”,
“▼” and “ENT”. The command menu adopts a tree shaped content structure. The above diagram
provides the integral structure and all the submenus under menu tree of the protection device.

Date: 2011-11-04
NOTE! The menu shown in above figure is not the specific-applicaton menu. For each
project, the menu varies with the protection configuration.
8.2.2 Analog
This menu is mainly used to display the real time sampling value of current, voltage and phase
angle. This menu and “Status” menu can fully reflects of the running environment of the protection
device. As long as the displayed values consist with the actual running situation, basically, the
protection device can work normally. This menu is set to greatly facilitate the debugging and
maintenance of people on site.
The menu “Measurements” has following submenus.

1 Measurement 1 Display sampled and calculated values on protection DSP module.
2 Measurement 2 Display sampled and calculated values on fault detector DSP module.
3 Measuement 3 Display measured primary values and other calculated quantities.
8.2.2.1 Measurements1
The menu “Measurement1” has following submenus.

Display measured values and corresponding phase angels of HV side
1 HVS Measurements
on protection DSP module.
Display measured values and corresponding phase angels of MV side
2 MVS Measurements
Display measured values and corresponding phase angels of LV side
3 LVS Measurements
Display currents for current differential protection and corresponding
4 Diff Measurements
phase angles on protection DSP module.
Display corrected currents for REF protection and corresponding
5 REF Measurements
phase angles on protection DSP module.
8.2.2.2 Measurements2
The menu “Measurements2” has following lower submenus.

Display measured values and corresponding phase angels of HV side
1 HVS Measurements
on fault detector DSP module.
Display measured values and corresponding phase angels of MV side
2 MVS Measurements
Display measured values and corresponding phase angels of LV side
3 LVS Measurements
Display currents for current differential protection and corresponding
4 Diff Measurements
phase angles on fault detector DSP module.

Date: 2011-11-04

Display corrected currents for REF protection and corresponding
5 REF Measurements
phase angles on fault detector DSP module.
8.2.3 Status
This menu is mainly used to display the state of binary inputs (including binary inputs via
opto-coupler and GOOSE binary inputs) and alarm signals in the protection device. This menu and
“Measurements” menu fully reflects the running environment of the protection device. As long as
the displayed values consist with the actual running situation, basically, the protection device can
work normally. This menu is set to greatly facilitate the debugging and maintenance of people on
site.
The submenu “Values” has following submenus.

1 Inputs Display all input signal states.
2 Outputs Display all output signal states.
3 Superv State Display supervision alarm states.
8.2.3.1 Inputs
The menu “Inputs” has following submenus.

1 Contact Inputs Display states of binary input derived from opto-isolated channels
8.2.3.2 Outputs
The menu “Outputs” has following submenus.

1 Contact Outputs Display states of binary output derived from opto-isolated channels
8.2.4 Records
This menu is used for displaying all kinds of records, so that the operator can load to view and use
as the reference of analyzing accidents and maintaining the device. All the records are stored in
non-volatile memory, and it can still record the reports even if it loses its power.
This menu includes the following command menus.
No. Item Function description

1 Disturb Records Display trip records.
Display self-check alarm and equipment operation abnormal alarm
2 Superv Events
reports.
3 IO Events Display binary events.
4 Device Logs Display running and operation reports of protective device.
5 Clear Records Clear all records.

Date: 2011-11-04
8.2.5 Settings
This menu is used for checking the setting of device equipment parameter, protection setting, logic
setting and system parameter, as well as modifying any of the above setting items. Moreover, it
can also execute the setting copy between different setting groups.
1 System Settings To display and modify the system settings.
2 Prot Settings To display and modify the protection settings
3 Logic Links To display and modify the logic links.
4 Device Setup To display and modify the settings related to device setup.
5 Copy Settings To copy settings from one group to another group.
(1) The submenu “Prot Settings” includes the following command menus.
1 Diff Prot Settings To display and modify the settings of current differential protection.
2 HVS REF Prot Settings To display and modify the settings of REF protection of HV side.
3 MVS REF Prot Settings To display and modify the settings of REF protection of MV side.
4 LVS REF Prot Settings To display and modify the settings of REF protection of LV side.
5 Overexcitation Prot Settings To display and modify the settings of overexcitation protection.
6 Mechanical Prot Settings To display and modify the settings of mechanical protection.
7 Frequency Prot Settings To display and modify the settings of frequency protection.
8 HVS Backup Prot Settings To display and modify the settings of backup protection of HV side.
9 MVS Backup Prot Settings To display and modify the settings of backup protection of MV side.
10 LVS Backup Prot Settings To display and modify the settings of backup protection of LV side.
11 Trip Logic Settings To display and modify the programmable tripping logic settings.
8.2.5.1 Logic Links
The submenu “Logic Links” includes the following command menus.
1 GOOSE Links To display and modify the GOOSE logic links。
8.2.5.2 Device Setup
(2) The menu “Device Setup” has following submenus.
1 Device Settings To display and modify the device settings.
2 Comm Settings To display and modify the communication settings.

Date: 2011-11-04
3 Label Settings To display and modify the label settings of protective device.
8.2.6 Print
This menu is used for printing device description, setting, all kinds of records, waveform and
information related with 103 Protocol.
This menu includes the following command menus and submenus.
To print the description information of protective device including

1 Device Info
software version.
To print settings, including communication parameter, protection

setting, logic links and device setup. It can print by different
2 Settings
classifications as well as printing all settings of the device. Besides, it
can also print out the latest modified setting item.
3 Disturb Records To print trip reports.
4 Superv Events To print status change of binary signal.
To print self-check alarm and equipment operation abnormal alarm

5 IO Events
reports.
To print present status of device, including measurement, signal

6 Device Status
status, settings, etc.
7 Waveforms To print recorded waveforms.
To print 103 Protocol information, including function type (FUN),

8 IEC103 Info information serial number (INF), general classification service group
number and channel number (ACC).
8.2.6.1 Settings
The menu “Settings” has following submenus.
1 System Settings To print the system settings.
2 Prot Settings To print the protection settings
3 Logic Links To print the logic links.
4 Device Setup To print the settings related to device setup.
5 All Settings To print all settings.
6 Latest Modified To print latest modified settings.
(1) The submenu “Prot Settings” includes the following command menus.
1 Diff Prot Settings To print the settings of current differential protection.

Date: 2011-11-04
2 HVS REF Prot Settings To print the settings of REF protection of HV side.
3 MVS REF Prot Settings To print the settings of REF protection of MV side.
4 LVS REF Prot Settings To print the settings of REF protection of LV side.
5 Overexcitation Prot Settings To print the settings of overexcitation protection.
6 Mechanical Prot Settings To print the settings of mechanical protection.
7 Frequency Prot Settings To print the settings of frequency protection.
8 HVS Backup Prot Settings To print the settings of backup protection of HV side.
9 MVS Backup Prot Settings To print the settings of backup protection of MV side.
10 LVS Backup Prot Settings To print the settings of backup protection of LV side.
11 Trip Logic Settings To display and modify the programmable tripping logic settings.
(2) The submenu “Logic Links” includes the following command menus.
1 Function Links To print the function logic links of protection element.
(3) The menu “Device Setup” has following submenus.
1 Device Settings To print the equipment settings including GOOSE module settings.
2 Comm Settings To print the communication settings.
3 Descron Settings To print the description settings of protective equipment.
To print the settings of configuring SLD display on LCD of protective

4 Display Settings
equipment.
8.2.6.2 Waveforms
The submenu “Waveforms” has following submenus.

1 Diff Wave To print differential current waveforms.
2 HVS Wave To print voltage and current waveforms of HV side.
3 MVS Wave To print voltage and current waveforms of MV side.
4 LVS Wave To print voltage and current waveforms of LV side.
8.2.7 Local Cmd

This menu is used for resetting the tripping relay with latch, protection device signal lamp, LCD
display, as the same as the resetting function of binary input. Record the currently acquired
waveform data of the protection device under normal condition for printing and uploading SAS.
Besides, it can send out the request of program download.

Date: 2011-11-04
1 Reset Target Reset the local signal, the signal indicator lamp and the LCD display.
2 Trig Oscillograph Trigger waveform recording.
3 Download Send out the download request.
8.2.8 Information
In this menu the LCD displays software information of DSP module, MON module and HMI module,
which consists of version, creating time of software, CRC codes and management sequence
number. Besides, hardware board information can also be viewed.
1 Version Info Display software version information of the equipment.
2 Board Info Monitor the current working state of each board of the equipment
8.2.9 Test
This menu is mainly used for developers to debug the program and for engineers to maintain
device. It can be used to check module information and item fault message, and fulfill the
communication test function. It’s also used to generate all kinds of report or event to transmit to the
SAS without any external input, so as to debug the communication on site.
1 Device Test Execute device tests.
2 Internal Signal Display internal signals of device.
The submenu “Device Test” has following submenus. Users can respectively execute the test
automatically or manually by selecting commands “All Test” or “Select Test”.
3 Protection Elements Generate messages of protection element to transmit to SCADA.
4 Superv Events Generate alarm messages to transmit to SCADA.
5 IO Events Generate binary events to transmit to SCADA.
8.2.10 Clock
The current time of internal clock can be viewed here. The time is displayed in the form
YY-MM-DD and hh:mm:ss. All values are presented with digits and can be modified.
8.2.11 Language
This menu is mainly used for set LCD display language.

Date: 2011-11-04
8.3 Understand the LCD Display
8.3.1 Overview
There are five kinds of LCD display, SLD (single line diagram) display, tripping reports, alarm
reports, binary input changing reports and control reports. Tripping reports and alarm reports will
not disappear until these reports are acknowledged by pressing the RESET button in the
protection panel (i.e. energizing the binary input [BI_RstTarg]). User can press both “ENT” and
“ESC” at the same time to switch the display among trip reports, alarm reports and the SLD display.
Binary change reports will be displayed for 5s and then it’ll return to the previous display interface
automatically. Control reports will not pop up and can only be viewed by navigating the
corresponding menu.
8.3.2 Display during Normal Operation

After the protection device is powered and turns into the initiating interface, it takes 30 seconds to
complete the initialization of protection device. During the initialization of protection device, the
“HEALTHY” indicator of the protection device goes out.
Under normal condition, the LCD will display the following interface. The LCD adopts white color
as its backlight that is activated if once there is any keyboard operation, and is extinguished
automatically after 60 seconds of no operation.
When the equipment is powered on, based on actual connection of the transformer, the LCD will
display single line diagram on its connection diagrams. If the transformer has three windings and 2
branches on LV side, the LCD will display by configuring the logic settings.
Figure 8.3-1 LCD display of single line diagram
breaker open. breaker closed.

Date: 2011-11-04
The displayed content of the interface contains: the current date and time of the protection device
(with a format of yy-mm-dd hh:mm:ss:), the currently valid setting group number, the three-phase
current and voltage sampled values of each side, differential current, residual differential current,
frequency etc.
8.3.3 Display When Tripping

This protection device can store 64 fault reports and 64 fault waveforms. When there is protection
element operating, the LCD will automatically display the latest fault report, and two kinds of LCD
display will be available depending on whether there is self-check report at present.
If the device has no self-check report, the display interface will only show the fault report.
Figure 8.3-2 LCD display 1 of trip report
Disturb Records NO.2 shows the title and SOE number of the report.
2008-11-28 07:10:00:200 shows the time when fault detector picks up, the format is
year–month-date and hour:minute:second:millisecond.
0ms TrigDFR shows fault detector of protection element and operation time of fault
detector is fixed as 0ms.
24ms AB 87.Op_Diff shows the relative operation time and operation element of protection
element
All the protection elements have been listed in Chapter “Operation Theory”, and please refer to
each protection element for details. Operation reports of fault detector and the reports related to
oscillography function are showed in the following table.

Date: 2011-11-04
Table 8.3-1 Tripping report messages
No. Message Description

1 ManTrigDFR Oscillography function is triggered manually.
2 RmtTrigDFR Oscillography function is triggered remotely.
3 TrigDFR Fault detector operates to trigger oscillography.
Oscillography function is triggered by alarm signals on
4 ProtBrd.AlmTrigDFR
protection board.
Oscillography function is triggered by failure signals on
5 ProtBrd.FailTrigDFR
protection board.
For the situation that the fault report and the self-check alarm report occur simultaneously in the
following figure, the upper half part is fault report, and the lower half part is self-check report. As to
the upper half part, it displays separately the record number of fault report, fault name, generating
time of fault report (with a format of yy-mm-dd hh:mm:ss:), protection element and tripping element.
If there is protection element, there is relative time on the basis of fault detector element and fault
phase. At the same time, if the total lines of protection element and tripping element are more than
3, a scroll bar will appear at the right. The height of the black part of the scroll bar basically
indicates the total lines of protection element and tripping element, and its position suggests the
position of the currently displayed line in the total lines. The scroll bar of protection element and
tripping element will roll up at the speed of one line per time. When it rolls to the last three lines, it’ll
roll from the earliest protection element and tripping element again. The displayed content of the
lower half part is similar to that of the upper half part.
NO.010 2008-11-28 10:10:00 Trip
0 ms TrigDFR
24 ms AB 87.Op_Diff
Alarm Infor
B12.Alm_OptoDC
Figure 8.3-3 LCD display 2 of trip report and alarm report
8.3.4 Display under Abnormal Condition

This protection device can store 1024 self-check reports. During the running of protection device,
the self-check report of hardware errors or system running abnormity will be displayed

Date: 2011-11-04
immediately.
Figure 8.3-4 LCD display of alarm report
Superv Events NO.4 shows the SOE number and title of the report
2008-11-28 09:18:47:500 shows the data and time of the report occured: year–month-date
and hour:minute:second:millisecond
Alm_Maintenance 0->1 shows the content of abnormality alarm
All the alarm elements have been listed in Chapter “Supervision”.
8.3.5 Display When Binary State Changes

When a binary input is energized or de-energized, output contacts operate, the corresponding IO
event report will be automatically displayed on LCD as follows. This protective equipment can
store 1024 events of binary signals. During the running of the equipment, the binary signals will be
displayed once the input signal state changes.

Date: 2011-11-04
IO_Events NO.4
2008-11-29 09:18:47:500ms
BI_RstTarg 0 1
Figure 8.3-5 Display of binary change report
No.004 Binary Events shows the number and title of the report
2008-11-28 09:18:47:500 shows the date and time of the report occurred, the format is
year–month-date and hour:minute:second:millisecond
BI_RstTarg 0->1 shows the state change of binary input, including binary input
name, original state and final state
Contact inputs and contact outputs are are listed in the following two tables, and user can define
undefined binary inputts as the specific binary inputs via PCS-PC software.
Table 8.3-2 Contact inputs list
No. Binary input Description

5 Bxx.BI_01 Binary input 01 of binary input module at slot xx position.

Date: 2011-11-04

NOTE! Bxx is the slot No. of module and please refer to Chapter “Hardware” for details.
The binary input number of different type module may be differential and signals list in
above table are just for reference.
Table 8.3-3 Contact oupputs list

1 TrpOut01 The 1st group of tripping outputs contats.
2 TrpOut02 The 2nd group of tripping outputs contats.
3 TrpOut03 The 3rd group of tripping outputs contats.
4 TrpOut04 The 4th group of tripping outputs contats.
11 TrpOut11 Binary input 11 of binary input module at slot xx position.
8.3.6 Display Device Logs

This protection device can store 1024 pieces of equipment logs. During the running of the
protection device, equipment logs will be displayed after user operations.

Date: 2011-11-04
Device Logs NO.4

2008-11-28 10:18:47:569ms
Device_Reboot
Figure 8.3-6 Display of control report
Device Logs NO. 4 shows the title and the number of the report
2008-11-28 10:18:47:569 shows the date and time when the report occurred, the format is
year–month-date and hour:minute:second:millisecond
Device_Reboot shows the state content of the user operation report.
User operating information listed below may be displayed.
Table 8.3-4 User Operating event list
No. Message Description

1 Device_Reboot The protective equipment has been rebooted.
2 Settings_Chgd The settings of protective equipment have been changed.
3 ActiveGrp_Chgd Active setting group has been changed.
4 Report_Cleared All reports have been deleted. (Device log events can not be deleted.)
5 Waveform_Cleared All waveforms have been deleted.
6 SubProcess_Exit A Subprocess has exited.
8.4 Keypad Operation

8.4.1 View Device Analog
The operation is as follows:
1. Press the key “▲” to enter the main menu.
2. Press the key “▲” or “▼” to move the cursor to the “Measurements” menu, and then
press the “ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu item, and then press

Date: 2011-11-04
the key “ENT” to enter the submenu.
4. Press the “▲” or “▼” to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most).
5. Press the key “◄” or “►” to select pervious or next command menu.
6. Press the key “ENT” or “ESC” to exit this menu (returning to the “Measurements” menu).
8.4.2 View Device Status

2. Press the key “▲” or “▼” to move the cursor to the “Status” menu, and then press the
“ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu item, and then press
the key “ENT” to enter the submenu.
4. Press the “▲” or “▼” to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most).
6. Press the key “ENT” or “ESC” to exit this menu (returning to the “Status” menu).
8.4.3 View Device Records

2. Press the key “▲” or “▼” to move the cursor to the “Records” menu, and then press the
key “ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu, and then press the
key “ENT” to enter the submenu.
4. Press the key “▲” or “▼” to page up/down.
5. Press the key “＋” or “－” to select pervious or next record.
7. Press the key “ENT” or “ESC” to exit this menu (returning to the “Records” menu).
8.4.4 Print Device Records

2. Press the key “▲” or “▼” to move the cursor to the “Print” menu, and then press the

Date: 2011-11-04
“ENT” to enter the menu.
Selecting the “Disturb Records”, and then
Press the “＋” or “－” to select pervious or next record. After pressing the key “ENT”,
the LCD will display “Start Printing... ”, and then automatically exit this menu
(returning to the menu “Print”). If the printer doesn’t complete its current print task
and re-start it for printing, and the LCD will display “Printer Busy…”. Press the key
“ESC” to exit this menu (returning to the menu “Print”).
Selecting the command menu “Superv Events” or “IO Events”, and then press the
key “▲” or “▼” to move the cursor. Press the “＋” or “－” to select the starting and
ending numbers of printing message. After pressing the key “ENT”, the LCD will
display “Start Printing…”, and then automatically exit this menu (returning to the
menu “Print”). Press the key “ESC” to exit this menu (returning to the menu “Print”).
4. If selecting the command menu “Device Info”, “Status“ or “IEC103_Info”, press the key
“ENT”, the LCD will display “Start printing..”, and then automatically exit this menu
(returning to the menu “Print”).
5. If selecting the “Settings”, “Logic Links”, press the key “ENT” or “►” to enter the next
level of menu.
6. After entering the submenu “Settings”, press the key “▲” or “▼” to move the cursor, and
then press the key “ENT” to print the corresponding default value. If selecting any item to
printing:
Press the key “＋” or “－” to select the setting group to be printed. After pressing the key
“ENT”, the LCD will display “Start Printing…”, and then automatically exit this menu
(returning to the menu “Settings”). Press the key “ESC” to exit this menu (returning to the
menu “Settings”).
7. After entering the submenu “Waveforms”, press the “＋” or “－” to select the waveform
item to be printed and press ”ENT” to enter. If there is no any waveform data, the LCD will
display “No Waveform Data!” (Before executing the command menu “HVS Wave”, it is
necessary to execute the command menu “Trig Oscillograph” in the menu “Local Cmd”,
otherwise the LCD will display “No Waveform Data!”). With waveform data existing:
Press the key “＋” or “－” to select pervious or next record. After pressing the key “ENT”,
the LCD will display “Start Printing…”, and then automatically exit this menu (returning to
the menu “Waveforms”). If the printer does not complete its current print task and
re-start it for printing, and the LCD will display “Printer Busy…”. Press the key “ESC” to
exit this menu (returning to the menu “Waveforms”).
8.4.5 View Device Setting


Date: 2011-11-04
2. Press the key “▲” or “▼” to move the cursor to the “Settings” menu, and then press the
key “ENT” or “►” to enter the menu.
key “ENT” to enter the menu.
4. Press the key “▲” or “▼” to move the cursor.
5. Press the key “+” or “-” to page up/down.
7. Press the key “ESC” to exit this menu (returning to the menu “Settings”).
NOTE! If the displayed information exceeds 14 lines, the scroll bar will appear on the right
side of the LCD to indicate the quantity of all displayed information of the command menu
and the relative location of information where the current cursor points at.
8.4.6 Modify Device Setting

2. Press the key “▲” or “▼” to move the cursor to the “Settings” menu, and then press
the key “ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to any command menu, and then press
the key “ENT” to enter the menu.
4. Press the key “▲” or “▼” to move the cursor.
5. Press the key “+” or “-” to page up/down.
7. Press the key “ESC” to exit this menu (returning to the menu “Settings” ).
8. If selecting the command menu “Device Settings” or “Comm Settings”, move the
cursor to the setting item to be modified, and then press the key “ENT”.
Press the key “＋” or “－” to modify the value (if the modified value is of multi-bit, press
the key “◄” or “►” to move the cursor to the digit bit, and then press the “＋” or “－” to
modify the value), press the key “ESC” to cancel the modification and return to the
displayed interface of the command menu “Device Settings”. Press the key “ENT” to
automatically exit this menu (returning to the displayed interface of the command menu
“Device Settings”).
Move the cursor to continue modifying other setting items. After all setting values are
modified, press the key “◄”, “►” or “ESC”, and the LCD will display “Save or Not?”.
Directly press the “ESC” or press the key “◄” or “►” to move the cursor. Select the
“Cancel”, and then press the key “ENT” to automatically exit this menu (returning to the

Date: 2011-11-04
displayed interface of the command menu “Device Settings”).
Press the key “◄” or “►” to move the cursor. Select “No” and press the key “ENT”, all
modified setting item will restore to its original value, exit this menu (returning to the
menu “Settings”).
Press the key “◄” or “►” to move the cursor to select “Yes”, and then press the key
“ENT”, the LCD will display password input interface.
Please Input Password:
－－－－
Figure 8.4-1 Display of inputting password
Input a 4-bit password (“＋”, “◄”, “▲” or “－”). If the password is incorrect, continue
inputting it, and then press the “ESC” to exit the password input interface and return to
the displayed interface of the command menu “Device Settings”. If the password is
correct, LCD will display “Save Settings…”, and then exit this menu (returning to the
displayed interface of the command menu “Device Settings”), with all modified setting
items as modified values.
NOTE! For different setting items, their displayed interfaces are different but their
modification methods are the same.
NOTE! After modifying the parameter settings of equipment i.e. settings in menu “Device
Settings” or “Comm Settings”, the “HEALTHY” indicator of the protection device will go
out, and the protection device will automatically restart and re-check the protection
setting. If the check doesn’t pass, the protection device will be blocked.
9. If selecting the command menu of protection element or tripping matrix such as “Diff
Prot Settings”, the LCD will display the following interface:

Date: 2011-11-04
2. Diff_Prot_Settings
Group NO select
Current Group NO: 01
Group NO To be Edited 02
Figure 8.4-2 Display 1 of modifying settings
Then move the cursor to the modified value and press “ENT” to enter. If the setting
[87.I_Biased] is selected to modify, then press the “ENT” to enter and the LCD will display
the following interface. is shown the “＋” or “－” to modify the value and then press the
“ENT” to enter.
87.I_Biased
Current Value 0.22
Modified Value 0.2 2
Min Value 0.05
Max Value 5.00
Figure 8.4-3 Display 2 of modifying settings
10. If selecting the other menus, move the cursor to the setting to be modified, and then
press the “ENT”.

Date: 2011-11-04
8.4.7 Copy Device Setting

1. Press the key “▲” to enter the main menu;
2. Press the key “▲” or “▼” to move the cursor to the “Settings” menu, and then press the
key “ENT” or “►” to enter the menu;
3. Press the key “▲” or “▼” to move the cursor to the command menu “Copy Settings”,
and then press the key “ENT” to enter the menu. The following display will be shown on
LCD.
Figure 8.4-4 Display of copy settings
Press the key “＋” or “－” to modify the value. Press the key “ESC”, and return to the
menu “Settings”. Press the “ENT”, the LCD will display the interface for password input,
if the password is incorrect, continue inputting it, press the key “ESC” to exit the
password input interface and return to the menu “Settings”. If the password is correct,
the LCD will display “Copy Settings Success!”, and exit this menu (returning to the menu
“Settings”).
8.4.8 Switch Setting Group

1. Exit the main menu.
2. Press the “GRP”.

Date: 2011-11-04
Figure 8.4-5 Display of switching setting group
Press the “＋” or “－” to modify the value, and then press the key “ESC” to exit this menu
(returning to the main menu). After pressing the key “ENT”, the LCD will display the password
input interface. If the password is incorrect, continue inputting it, and then press the key “ESC” to
exit the password input interface and return to its original state. If the password is correct, the
“HEALTHY” indicator of the protection device will go out, and the protection device will re-check
the protection setting. If the check doesn’t pass, the protection device will be blocked. If the check
is successful, the LCD will return to its original state.
8.4.9 Delete Records

1. Exit the main menu.
2. Press the “＋”, “－”, “＋”, “－” and key “ENT”; Press the key “ESC” to exit this menu
(returning to the original state). Press the key “ENT” to carry out the deletion.

Date: 2011-11-04
Figure 8.4-6 Display of deleting report
NOTE! The operation of deleting device records will delete all messages saved by the
protection device, including disturbance records, supervision events and binary events,
but the user operation reports (i.e. equipment logs) can not be deleted. Furthermore, all
deleted records are irrecoverable after deletion, so the function shall be used with great
cautious.
8.4.10 Modify Device Clock

2. Press the key “▲” or “▼” to move the cursor to the “Clock” menu, and then press the key
“ENT” to enter clock display.

Date: 2011-11-04
Figure 8.4-7 Display of modifying clock
3. Press the key “▲” or “▼” to move the cursor to the date or time to be modified.
4. Press the key ＋” or “－”, to modify value, and then press the key “ENT” to save the
modification and return to the main menu.
5. Press the key “ESC” to cancel the modification and return to the main menu.
8.4.11 Check Software Version

2. Press the key “▲” or “▼” to move the cursor to the “Information” menu, and then press
the “ENT” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to the command menu “Version Info”, and
then press the key “ENT” to display the software version.
4. Press the key “ESC” to return to the main menu.
8.4.12 View Module Information

2. Press the key “▲” or “▼” to move the cursor to the “Information” menu, and then press
the key “ENT” or “►” to enter the menu.
3. Press the key “▲” or “▼” to move the cursor to the command menu “Board Info”, and
then press the “ENT” to enter the menu.
4. Press the key “▲” or “▼” to move the scroll bar.

Date: 2011-11-04
5. Press the key “ENT” or “ESC” to exit this menu (returning to the “Information” menu).
8.4.13 Communication Test

2. Press the key “▲” or “▼” to move the cursor to the “Test” menu, and then press the key
3. Press the key “▲” or “▼” to move the cursor to the command menu “Comm Test”, and
then press the key “ENT” to enter the menu, to select test item. If “Prot Elements”
“Superv Events” or “IO Events” is selected, the LCD will display “Entering
Communication Test…”.
Figure 8.4-8 Display of communication test
4. Press the key “▲” or “▼” to move the cursor to select the corresponding command menu
“All Test” or “Select Test”. If selecting the “All Test”, press the “ENT”, and the device will
successively carry out all operation element message test one by one.
5. If selecting the “Select Test”, users will go to an interface, then select the ＋” or “－” to
page up/down to select each operation element and press the key “ENT” to execute the
test.
NOTE! If no input operation is carried out within 60s, exit the communication transmission
and return to the “Test” menu, at this moment, the LCD will display “Communication Test
Timeout and Exiting...”.
6. Press the key “ESC” to exit this menu (returning to the menu “TEST”, at this moment, the
LCD will display “Communication Test Exiting…”.

Date: 2011-11-04
8.4.14 Select Language

2. Press the key “▲” or “▼” to move the cursor to the command menu “Language”, and
then press the key “ENT” to enter the menu and the following display will be shown on
LCD.
Please Select Language:
1 中文
2 English
Figure 8.4-9 Display of selecting language
3. Press the key “▲” or “▼” to move the cursor to the language user preferred and press
the key “ENT” to execute language switching. After language switching is finished, LCD
will return to the menu “Language”, and the display language is changed. Otherwise,
press the key “ESC” to cancel language switching and return to the menu “Language”.
NOTE! The LCD interface provided in this chapter is only a reference and available for
explaining specific definition of LCD. The displayed interface of the actual protection
device may be some different from it, so you shall be subject to the actual protection
device.

Date: 2011-11-04
Table of Contents
9.1 General Description......................................................................................... 9-1

9.2 Introduction on PCS-PC software .................................................................. 9-1
9.3 Protective Equipment Configuration ............................................................. 9-1
9.3.1 Configuration of LED Indicators ..........................................................................................9-1
9.3.2 Configuration of Binary Input ..............................................................................................9-2
9.3.3 Configuration of Binary Output ...........................................................................................9-3
9.3.4 Setting configuration ...........................................................................................................9-4

Date: 2011-02-24

Date: 2011-02-24
By adoption of PCS-PC software, it is able to make system configuration, function configuration,

binary input and binary output configuration, LED indicator configuration and programming logic
for PCS-978 protection device.
9.2 Introduction on PCS-PC software
PCS-PC software, associated with UAPC platform device, is developed in order to meet
customer’s demand on functions of device such as device configuration and programmable design.
It selects substation as the core of data management and the device as fundamental unit,
supporting one substation joint to govern many ones of the devices. The software provides on-line
and off-line functions: on-line mode: Ethernet connected with the device to support IEC
60870-5-103 protocol and downloading of binary files through Ethernet net; off-line mode: off-line
setting configuration. In addition, it also supports programmable logic to meet customer’s
corresponding demand. For any detail, please refer to Instruction Manual of PCS-PC Auxiliary
Software.
Overall functions:
z Protective equipment Configuration (off-line function)
z Programmable logic (off-line function)
z Setting configuration (off-line & on-line function)
z Real-time display of analogue and digital quantity of device (on-line function)
z Display of sequence of report (SOE) (on-line function)
z Analysis of waveform (on-line function)
z Remote control (on-line function)
z File downloading/uploading (on-line function)
9.3 Protective Equipment Configuration
9.3.1 Configuration of LED Indicators
1. This equipment provides 20 LED indicators, among which the first three are “HEALTHY” LED,
“ALARM” LED and “TRIP” LED and the other 17 LEDs can be configured by users as
required.
2. The right tree structure in the software provides elements for lighting up, including protection
elements, alarm elements and binary input elements.
3. Use “KeepLight” to choose whether hold LED or not. In case of “Yes” selected, resetting must

Date: 2011-02-24
be performed by the resetting button once it is lit. In case of “No” selected, the signals will reset
automatically once the input signal returns.
4. If users hope the user-defined LED 1 (the fourth one) is lit and held when differential protection
operates; the user-defined LED 2 (the fifth one) is lit and not held when restricted earth fault
protection of HV side operates , configure it as per the following picture.
9.3.2 Configuration of Binary Input

1. Pin number of user-defined binary input on module is provided on the left of the interface.
2. The next step is to set debounce time (unit: ms) of the corresponding binary inputs. Debounce
time (i.e. time delay) of the step from 0 to 1 and from 1 to 0 can be set separately.
3. The “BinaryIn List” at the right is the corresponding function of the binary input, which needs
the user to configure. User can drag it from the right list to the assigned BI.
4. The available variables are: binary inputs of enabling protective function, binary input of
mechanical signal, output of programmable logic and GOOSE signal.
In case of binary inputs of enabling protective function, the binary input is enabled when it is “1”.
If some binary input of enabling protective function has no corresponding connection, it is fixed
enabled.

Date: 2011-02-24
If mechanical signal input is connected, the corresponding module must be mechanical module
NR1533. On condition that “Destination” is connected, no any operation is executed within the
program, and only directly transform input into output used as input of programmable logic.
9.3.3 Configuration of Binary Output

1. The function is applied for configuration of binary output terminals of NR1523 signal module of
equipment
2. There are total 7 groups of binary output, and each group includes one contact or two
contacts.
3. Users can drag the elements from the right list on the right hand side as the input/s to initiate
signal output.
4. The optional signals include: protection elements, alarm elements, binary inputs and fault
detector signal of protection element, etc.
5. In the event that user want to use the first group output contacts (i.e. contacts (pin1,pin2), (pin3,
pin4) on board 15) as alarm output contacts of thermal overload of HV side, find the
corresponding alarm element in the list on the right hand side and drag it to the corresponding
position of the “Board15_Pin1_2_Pint3_4” in the BO name column.

Date: 2011-02-24
9.3.4 Setting configuration

After function configuration is finished, disabled protective function is hidden in equipment and in
setting configuration list of PCS-PC software.
1. Users can configure the communication parameters, system settings, SLD settings and etc.
2. Each stage of protection can be configured. For example, the maximum configuration of
overcurrent protection of HV side is four stages, and characteristic of each stage can be
configured as definite time, standard inverse time, very inverse time, extremely inverse time,
long-time inverse time, user-defined inverse time, or disabled.
3. Users can select to show or hide some setting, and modify typical setting values.

Date: 2011-02-24
10 Communication
10 Communication
Table of Contents
10.1 General Description..................................................................................... 10-1

10.2 Rear Communication Port Information ...................................................... 10-1
10.2.1 RS-485 Interface ............................................................................................................10-1
10.2.2 Ethernet Interface ...........................................................................................................10-3
10.2.3 IEC60870-5-103 Communication ...................................................................................10-4
10.3 IEC60870-5-103 Interface over Serial Port ................................................. 10-4

10.3.1 Physical Connection and Link Layer ...............................................................................10-5
10.3.2 Initialization .....................................................................................................................10-5
10.3.3 Time Synchronization .....................................................................................................10-5
10.3.4 Spontaneous Events .......................................................................................................10-5
10.3.5 General Interrogation ......................................................................................................10-6
10.3.6 General Functions ..........................................................................................................10-6
10.3.7 Disturbance Records ......................................................................................................10-7
10.4 IEC60870-5-103 Interface over Ethernet .................................................... 10-8

10.5 Messages Description for IEC61850 Protocol ........................................... 10-8
10.5.1 Overview.........................................................................................................................10-8
10.5.2 Communication Profiles ..................................................................................................10-9
10.5.3 Server Data Organization .............................................................................................10-10
10.5.4 Server Features and Configuration ...............................................................................10-12
10.5.5 ACSI conformance ........................................................................................................10-14
10.5.6 Logical Nodes ...............................................................................................................10-18
10.6 DNP3.0 Interface ........................................................................................ 10-21

10.6.1 Overview.......................................................................................................................10-21
10.6.2 Link Layer Functions.....................................................................................................10-21
10.6.3 Transport Functions ......................................................................................................10-22

Date: 2011-09-05
10 Communication
10.6.4 Application Layer Functions ..........................................................................................10-22
List of Figures
Figure 10.2-1 EIA RS-485 bus connection arrangements ....................................................10-2
Figure 10.2-2 Ethernet communication cable .......................................................................10-3
Figure 10.2-3 Ethernet communication structure .................................................................10-4
List of Tables
Table 10.3-1 Generic service group numbers .......................................................................10-6
Table 10.3-2 Disturbance ACC numbers ...............................................................................10-7

Date: 2011-09-05
10 Communication

This section outlines the remote communications interfaces of NR equipment. The protective
device supports a choice of three protocols via the rear communication interface (RS-485 or
Ethernet), selected via the model number by setting. The protocol provided by the protective
device is indicated in the submenu in the “Comm_Settings” column. Using the keypad and LCD,
set the parameter [Protocol_RS485A] and [Protocol_RS485B], the corresponding protocol will be
selected.
The rear EIA RS-485 interface is isolated and is suitable for permanent connection of whichever
protocol is selected. The advantage of this type of connection is that up to 32 protective devices
can be “daisy chained” together using a simple twisted pair electrical connection.
It should be noted that the descriptions contained within this section do not aim to fully detail the
protocol itself. The relevant documentation for the protocol should be referred to for this
information. This section serves to describe the specific implementation of the protocol in the relay.
10.2 Rear Communication Port Information

10.2.1 RS-485 Interface
This protective device provides two rear RS-485 communication ports, and each port has three
terminals in the 12-terminal screw connector located on the back of the relay and each port has a
ground terminal for the earth shield of the communication cable. Please refer to the section of
“Communication Interface module” for details of the connection terminals. The rear ports provide
RS-485 serial data communication and are intended for use with a permanently wired connection
to a remote control center.
10.2.1.1 EIA RS-485 Standardized Bus
The EIA RS-485 two-wire connection provides a half-duplex fully isolated serial connection to the
product. The connection is polarized and whilst the product’s connection diagrams indicate the
polarization of the connection terminals it should be borne in mind that there is no agreed
definition of which terminal is which. If the master is unable to communicate with the product, and
the communication parameters match, then it is possible that the two-wire connection is reversed.
10.2.1.2 Bus Termination
The EIA RS-485 bus must have 120Ω (Ohm) ½ Watt terminating resistors fitted at either end
across the signal wires (refer to Figure 10.2-1). Some devices may be able to provide the bus
terminating resistors by different connection or configuration arrangements, in which case
separate external components will not be required. However, this product does not provide such a
facility, so if it is located at the bus terminus then an external termination resistor will be required.

Date: 2011-09-05
10 Communication
Figure 10.2-1 EIA RS-485 bus connection arrangements
10.2.1.3 Bus Connections & Topologies
The EIA RS-485 standard requires that each device is directly connected to the physical cable that
is the communications bus. Stubs and tees are expressly forbidden, such as star topologies. Loop
bus topologies are not part of the EIA RS-485 standard and are forbidden by it also.
Two-core screened cable is recommended. The specification of the cable will be dependent on the
application, although a multi-strand 0.5mm2 per core is normally adequate. Total cable length
must not exceed 500m. The screen must be continuous and connected to ground at one end,
normally at the master connection point; it is important to avoid circulating currents, especially
when the cable runs between buildings, for both safety and noise reasons.
This product does not provide a signal ground connection. If a signal ground connection is present
in the bus cable then it must be ignored, although it must have continuity for the benefit of other
devices connected to the bus. At no stage must the signal ground be connected to the cables
screen or to the product’s chassis. This is for both safety and noise reasons.
10.2.1.4 Biasing
It may also be necessary to bias the signal wires to prevent jabber. Jabber occurs when the signal
level has an indeterminate state because the bus is not being actively driven. This can occur when
all the slaves are in receive mode and the master is slow to turn from receive mode to transmit
mode. This may be because the master purposefully waits in receive mode, or even in a high
impedance state, until it has something to transmit. Jabber causes the receiving device(s) to miss
the first bits of the first character in the packet, which results in the slave rejecting the message
and consequentially not responding. Symptoms of these are poor response times (due to retries),
increasing message error counters, erratic communications, and even a complete failure to
communicate.
Biasing requires that the signal lines be weakly pulled to a defined voltage level of about 1V. There
should only be one bias point on the bus, which is best situated at the master connection point.
The DC source used for the bias must be clean; otherwise noise will be injected. Note that some
devices may (optionally) be able to provide the bus bias, in which case external components will
not be required.

Date: 2011-09-05
10 Communication
NOTE!
z It is extremely important that the 120Ω termination resistors are fitted. Failure to do so
will result in an excessive bias voltage that may damage the devices connected to the
bus.
z As the field voltage is much higher than that required, NR cannot assume
responsibility for any damage that may occur to a device connected to the network as
a result of incorrect application of this voltage.
z Ensure that the field voltage is not being used for other purposes (i.e. powering logic
inputs) as this may cause noise to be passed to the communication network.
10.2.2 Ethernet Interface

This protective device can provide four rear Ethernet interfaces (optional) and they are unattached
each other. Parameters of each Ethernet port can be configured in the submenu
“Comm_Settings”.
10.2.2.1 Ethernet Standardized Communication Cable
It is recommended to use twisted screened eight-core cable as the communication cable. A picture
is shown bellow.
Figure 10.2-2 Ethernet communication cable
10.2.2.2 Connections and Topologies
Each equipment is connected with an exchanger via communication cable, and thereby it forms a
star structure network. Dual-network is recommended in order to increase reliability. SCADA is
also connected to the exchanger and will play a role of master station, so the every equipment
which has been connected to the exchanger will play a role of slave unit.

Date: 2011-09-05
10 Communication
Figure 10.2-3 Ethernet communication structure
10.2.3 IEC60870-5-103 Communication

The IEC specification IEC60870-5-103: Telecontrol Equipment and Systems, Part 5: Transmission
Protocols Section 103 defines the use of standards IEC60870-5-1 to IEC60870-5-5 to perform
communication with protective device. The standard configuration for the IEC60870-5-103
protocol is to use a twisted pair EIA RS-485 connection over distances up to 500m. It also supports
to use an Ethernet connection. The relay operates as a slave in the system, responding to
commands from a master station.
To use the rear port with IEC60870-5-103 communication, the relevant settings of the protective
device must be configured. To do this use the keypad and LCD user interface. In the submenu
“Comm_Settings”, set the parameters [Protocol_RS485A], [Protocol_RS485B], [Baud_RS485A]
and [Baud_RS485B]. For using the Ethernet port with IEC60870-5-103 communication, the IP
address and submask of each Ethernet port can be set in the same submenu. Please refer to the
corresponding section in Chapter “Settings” for further details.
10.3 IEC60870-5-103 Interface over Serial Port

The IEC60870-5-103 interface over serial port (RS-485) is a master/slave interface with the
protective device as the slave device. It is properly developed by NR.
The protective device conforms to compatibility level 2; compatibility level 3 is not supported.
The following IEC60870-5-103 facilities are supported by this interface:
z Initialization (reset)
z Time synchronization
z Event record extraction
z General interrogation

Date: 2011-09-05
10 Communication
z General functions
z Disturbance records
10.3.1 Physical Connection and Link Layer

Two EIA RS-485 standardized ports are available for IEC60870-5-103 in this protective device.
The transmission speed is optional: 4800 bit/s, 9600 bit/s, 19200 bit/s or 38400 bit/s.
The link layer strictly abides by the rules defined in the IEC60870-5-103.
10.3.2 Initialization
Whenever the protective device has been powered up, or if the communication parameters have
been changed, a reset command is required to initialize the communications. The protective
device will respond to either of the two reset commands (Reset CU or Reset FCB), the difference
is that the Reset CU will clear any unsent messages in the transmit buffer.
The protective device will respond to the reset command with an identification message ASDU 5,
the COT (Cause Of Transmission) of this response will be either Reset CU or Reset FCB
depending on the nature of the reset command.
10.3.3 Time Synchronization

The protective device time and date can be set using the time synchronization feature of the
IEC60870-5-103 protocol. The protective device will correct for the transmission delay as specified
in IEC60870-5-103. If the time synchronization message is sent as a send/confirm message then
the protective device will respond with a confirmation. Whether the time-synchronization message
is sent as a send confirmation or a broadcast (send/no reply) message, a time synchronization
class 1 event will be generated/produced.
If the protective device clock is synchronized using the IRIG-B input then it will not be possible to
set the protective device time using the IEC60870-5-103 interface. An attempt to set the time via
the interface will cause the protective device to create an event with the current date and time
taken from the IRIG-B synchronized internal clock.
10.3.4 Spontaneous Events

Events are categorized using the following information:
z Type identification (TYP)
z Function type (FUN)
z Information number (INF)
Messages sent to substation automation system are grouped according to IEC60870-5-103

protocol. Operation elements are sent by ASDU2 (time-tagged message with relative time), and
status of binary Input and alarm element are sent by ASDU1 (time-tagged message). The cause of
transmission (COT) of these responses is 1.
1. Operation elements sent by ASDU2

Date: 2011-09-05
10 Communication
2. Alarm element sent by ASDU1
3. Binary input sent by ASDU1
Please print the IEC103 information by the menu “Print->I EC103_Info” for each specific project.
10.3.5 General Interrogation

The GI can be used to read the status of the relay, the function numbers, and information numbers
that will be returned during the GI cycle. The GI cycle strictly abides by the rules defined in the
IEC60870-5-103.
Refer the IEC60870-5-103 standard can get the enough details about general interrogation.
10.3.6 General Functions

The generic functions can be used to read the setting and protection measurement of the relay,
and modify the setting. Two supported type identifications are ASDU 21 and ASDU 10. For more
details about generic functions, see the IEC60870-5-103 standard.
Table 10.3-1 Generic service group numbers
Group Number Group Caption Description
01 Equip_Description
02 Trip_Element
03 Self-check_Alarm
04 Binary_Input
05 Control
06 System Settings
07 Diff Prot Settings
08 HVS REF Prot Settings
09 MVS REF Prot Settings
10 LVS REF Prot Settings
11 Overexcitation Prot Settings
12 HVS Backup Prot Settings
13 MVS Backup Prot Settings
14 LVS Backup Prot Settings
15 Trip Logic Settings
16 Function Links
17 Device Settings
18 Comm Settings
19 Setting_Group
20 HVS_Measurements$1

Date: 2011-09-05
10 Communication
Group Number Group Caption Description
21 MVS_Measurements$1
22 LVS_Measurements$1
23 OvExc_Measurements$1
24 Diff_Measurements$1
25 REF_Measurements$1
26 HVS_Measurements$2
27 MVS_Measurements$2
28 LVS_Measurements$2
29 OvExc_Measurements$2
30 Diff_Measurements$2
31 REF_Measurements$2
32 Disturb_Info_Analog
33 Disturb_Info_Binary00
34 Disturb_Info_Binary01
35 Fault_Data
36 Control_Report
NOTE! The above table is only an example and it will change with the differential
protection configurations.
10.3.7 Disturbance Records

This protective device can store up to 64 disturbance records in its memory. A pickup of the fault
detector or an operation of the relay can make the protective device store the disturbance records.
The disturbance records are stored in uncompressed format and can be extracted using the
standard mechanisms described in IEC60870-5-103.
Table 10.3-2 Disturbance ACC numbers
ACC No. Content ACC No. Content

1 HVS.Ia 18 HVS.Uc
2 HVS.Ib 19 MVS.Ua
3 HVS.Ic 20 MVS.Ub
4 MVS.Ia 21 MVS.Uc
5 MVS.Ib 22 LVS.Ua
6 MVS.Ic 23 LVS.Ub
7 LVS.Ia 24 LVS.Uc
8 LVS.Ib 25 87T.ida

Date: 2011-09-05
10 Communication
ACC No. Content ACC No. Content

9 LVS.Ic 26 87T.idb
10 HVS.3i0Ext 27 87T.idc
11 MVS.3i0Ext 28 87T.Ida_Hm2_Pct
12 LVS.3i0Ext 29 87T.Idb_Hm2_Pct
13 HVS.3u0Ext 30 87T.Idc_Hm2_Pct
14 MVS.3u0Ext 31 HVS.64REF.i0d
15 LVS.3u0Ext 32 MVS.64REF.i0d
16 HVS.Ua 33 LVS.64REF.i0d
17 HVS.Ub
10.4 IEC60870-5-103 Interface over Ethernet
The IEC60870-5-103 interface over Ethernet is a master/slave interface with the relay as the slave
device. It is properly developed by NR too. All the service of this relay is based on generic
functions of the IEC60870-5-103. The following table lists all the group number of this relay. And
this relay will send all the relevant information about group caption to the SAS or RTU after
establishing a successful communication link.
Please refer to Table 10.3-1 for detailed description of generic service group numbers.
10.5 Messages Description for IEC61850 Protocol

10.5.1 Overview
The IEC 61850 standard is the result of years of work by electric utilities and vendors of electronic
equipment to produce standardized communications systems. IEC 61850 is a series of standards
describing client/server and peer-to-peer communications, substation design and configuration,
testing, environmental and project standards. The complete set includes:
z IEC 61850-1: Introduction and overview
z IEC 61850-2: Glossary
z IEC 61850-3: General requirements
z IEC 61850-4: System and project management
z IEC 61850-5: Communications and requirements for functions and device models
z IEC 61850-6: Configuration description language for communication in electrical substations

related to IEDs
z IEC 61850-7-1: Basic communication structure for substation and feeder equipment -
Principles and models
z IEC 61850-7-2: Basic communication structure for substation and feeder equipment - Abstract
communication service interface (ACSI)

Date: 2011-09-05
10 Communication
z IEC 61850-7-3: Basic communication structure for substation and feeder equipment –
Common data classes
z IEC 61850-7-4: Basic communication structure for substation and feeder equipment –
Compatible logical node classes and data classes
z IEC 61850-8-1: Specific Communication Service Mapping (SCSM) – Mappings to MMS (ISO
9506-1 and ISO 9506-2) and to ISO/IEC 8802-3
z IEC 61850-9-1: Specific Communication Service Mapping (SCSM) – Sampled values over
serial unidirectional multidrop point to point link
z IEC 61850-9-2: Specific Communication Service Mapping (SCSM) – Sampled values over
ISO/IEC 8802-3
z IEC 61850-10: Conformance testing
These documents can be obtained from the IEC (http://www.iec.ch). It is strongly recommended
that all those involved with any IEC 61850 implementation obtain this document set.
10.5.2 Communication Profiles

The PCS-978 series relay supports IEC 61850 server services over TCP/IP communication
protocol stacks. The TCP/IP profile requires the PCS-978 series to have an IP address to establish
communications.
1. MMS protocol
IEC 61850 specifies the use of the Manufacturing Message Specification (MMS) at the upper
(application) layer for transfer of real-time data. This protocol has been in existence for a number
of years and provides a set of services suitable for the transfer of data within a substation LAN
environment. Actual MMS protocol services are mapped to IEC 61850 abstract services in
IEC61850-8-1.
2. Client/server
This is a connection-oriented type of communication. The connection and communication activity

is initiated and controlled by the client. Substation computers running HMI programs or SOE
logging software are considered as IEC61850 clients. Substation equipment such as protection
relays, meters, RTUs, transformer, tap changers, or bay control units are considered as servers.
Please note that RTUs can also be considered as clients.
3. Peer-to-peer
This is a non-connection-oriented, high speed type of communication usually between substation

equipment, such as protection relays. GOOSE is the method of peer-to-peer communication.
4. Substation configuration language (SCL)
A substation configuration language is a number of files used to describe the configuration of

substation equipment. Each configured device has an IEC Capability Description (ICD) file and a
Configured IED Description (CID) file. The substation single line information is stored in a System

Date: 2011-09-05
10 Communication
Specification Description (SSD) file. The entire substation configuration is stored in a Substation
Configuration Description (SCD) file. The SCD file is the combination of the individual ICD files
and the SSD file.
10.5.3 Server Data Organization

IEC61850 defines an object-oriented approach to data and services. An IEC61850 physical device
can contain one or more logical device(s) (for proxy). Each logical device can contain many logical
nodes. Each logical node can contain many data objects. Each data object is composed of data
attributes and data attribute components. Services are available at each level for performing
various functions, such as reading, writing, control commands, and reporting.
Each IED represents one IEC61850 physical device. The logical node LPHD contains information
about the IED physical device. The logical node LLN0 contains information about the IED logical
device.
10.5.3.1 Digital Status Values
The GGIO logical node is available in the PCS-978 series relays to provide access to digital status
points (including general I/O inputs and warnings) and associated timestamps and quality flags.
The data content must be configured before the data can be used. GGIO provides digital status
points for access by clients. It is intended that clients use GGIO in order to access digital status
values from the PCS-978 series relays. Clients can utilize the IEC61850 buffered reporting
features available from GGIO in order to build sequence of events (SOE) logs and HMI display
screens. Buffered reporting should generally be used for SOE logs since the buffering capability
reduces the chances of missing data state changes. All needed status data objects are transmitted
to HMI clients via buffered reporting, and the corresponding buffered reporting control block
(BRCB) is defined in LLN0.
10.5.3.2 Analog Values
Most of analog measured values are available through the MMXU logical nodes, and metering
values in MMTR, the else in MMXN, MSQI and so on. Each MMXU logical node provides data
from a IED current/voltage “source”. There is one MMXU available for each configurable source.
MMXU1 provides data from CT/VT source 1(usually for protection purpose), and MMXU2 provides
data from CT/VT source 2 (usually for monitor and display purpose). All these analog data objects
are transmitted to HMI clients via unbuffered reporting periodically, and the corresponding
unbuffered reporting control block (URCB) is defined in LLN0. MMXUx logical nodes provide the
following data for each source:
z MMXU.MX.Hz: frequency
z MMXU. MX.PPV.phsAB: phase AB voltage magnitude and angle
z MMXU.MX.PPV.phsBC: phase BC voltage magnitude and angle
z MMXU.MX.PPV.phsCA: Phase CA voltage magnitude and angle
z MMXU.MX.PhV.phsA: phase AG voltage magnitude and angle
z MMXU.MX.PhV.phsB: phase BG voltage magnitude and angle

Date: 2011-09-05
10 Communication
z MMXU.MX.PhV.phsC: phase CG voltage magnitude and angle
z MMXU.MX.A.phsA: phase A current magnitude and angle
z MMXU.MX.A.phsB: phase B current magnitude and angle
z MMXU.MX.A.phsC: phase C current magnitude and angle
10.5.3.3 Protection Logical Nodes
The following list describes the protection elements for all PCS-978 series relays. The specified
relay will contain a subset of protection elements from this list.
z PDIF: current differential and transfer trip
z PDIS: phase-to-phase distance, phase-to-ground distance and SOTF distance
z PTUC: undercurrent
z PTOC: phase overcurrent, zero sequence overcurrent and overcurrent when CTS
z PTUV: undervoltage
z PTUF: underfrequency
z PTOV: overvoltage and auxiliary overvoltage
z RREC: automatic reclosing
The protection elements listed above contain start (pickup) and operate flags, instead of any
element has its own start (pickup) flag separately, all the elements share a common start (pickup)
flags “PTRC.ST.Str.general”. The operate flag for PTOC1 is “PTOC1.ST.Op.general”. For the
PCS-978 series relay protection elements, these flags take their values from related module for
the corresponding element. Similar to digital status values, the protection trip information is
reported via BRCB, and it also locates in LLN0.
10.5.3.4 LLN0 and Other Logical Nodes
Logical node LLN0 is essential for an IEC61850 based IED. This LN shall be used to address
common issues for Logical Devices. Most of the public services, the common settings, control
values and some device oriented data objects are available here. The public services may be
BRCB, URCB and GSE control blocks and similar global defines for the whole device; the
common settings include all the setting items of communication settings. System settings and
some of the protection setting items, which can be configured to two or more protection elements
(logical nodes). In LLN0, the item Loc is a device control object, this Do item indicates the local
operation for complete logical device, when it is true, all the remote control commands to the IED
will be blocked and those commands make effective until the item Loc is changed to false. In
PCS-978 series relays, besides the logical nodes we describe above, there are some other logical
nodes below in the IEDs:
z MMXU: This LN shall be used to acquire values from CTs and VTs and calculate measurands
such as r.m.s. values for current and voltage or power flows out of the acquired voltage and
current samples. These values are normally used for operational purposes such as power flow

Date: 2011-09-05
10 Communication
supervision and management, screen displays, state estimation, etc. The requested accuracy for
these functions has to be provided.
z LPHD: Physical device information, the logical node to model common issues for physical
device.
z PTRC: Protection trip conditioning, it shall be used to connect the “operate” outputs of one or
more protection functions to a common “trip” to be transmitted to XCBR. In addition or alternatively,
any combination of “operate” outputs of protection functions may be combined to a new “operate”
of PTRC.
z RDRE: Disturbance recorder function. It triggers the fault wave recorder and its output refers
to the “IEEE Standard Format for Transient Data Exchange (COMTRADE) for Power System” (IEC
60255-24). All enabled channels are included in the recording, independently of the trigger mode.
10.5.4 Server Features and Configuration
10.5.4.1 Buffered/unbuffered Reporting
IEC61850 buffered and unbuffered reporting control blocks locate in LLN0, they can be configured
to transmit information of protection trip information (in the Protection logical nodes), binary status
values (in GGIO) and analog measured/calculated values (in MMXU, MMTR and MSQI). The
reporting control blocks can be configured in CID files, and then be sent to the IED via an
IEC61850 client. The following items can be configured.
z TrgOps: Trigger options. The following bits are supported by the PCS-978 series
relays:
－ Bit 1: Data-change
－ Bit 4: Integrity
－ Bit 5: General interrogation
z OptFlds: Option Fields. The following bits are supported by the PCS-978 series relays:
－ Bit 1: Sequence-number
－ Bit 2: Report-time-stamp
－ Bit 3: Reason-for-inclusion
－ Bit 4: Data-set-name
－ Bit 5: Data-reference
－ Bit 6: Buffer-overflow (for buffered reports only)
－ Bit 7: EntryID (for buffered reports only)
－ Bit 8: Conf-revision
－ Bit 9: Segmentation
z IntgPd: Integrity period.

Date: 2011-09-05
10 Communication
z BufTm: Buffer time.
10.5.4.2 File Transfer
MMS file services are supported to allow transfer of oscillography, event record or other files from
a PCS-978 series relay.
10.5.4.3 Timestamps
The Universal Time Coordinated(UTC for short) timestamp associated with all IEC61850 data
items represents the lastest change time of either the value or quality flags of the data item
10.5.4.4 Logical Node Name Prefixes
IEC61850 specifies that each logical node can have a name with a total length of 11 characters.
The name is composed of:
z A five or six-character name prefix.
z A four-character standard name (for example, MMXU, GGIO, PIOC, etc.).
z A one or two-character instantiation index.
Complete names are of the form xxxxxxPTOC1, where the xxxxxx character string is configurable.
Details regarding the logical node naming rules are given in IEC61850 parts 6 and 7-2. It is
recommended that a consistent naming convention be used for an entire substation project.
10.5.4.5 GOOSE Services
IEC61850 specifies the type of broadcast data transfer services: Generic Object Oriented
Substation Events (GOOSE). IEC61850 GOOSE services provide virtual LAN (VLAN) support,
Ethernet priority tagging, and Ether-type Application ID configuration. The support for VLANs and
priority tagging allows for the optimization of Ethernet network traffic. GOOSE messages can be
given a higher priority than standard Ethernet traffic, and they can be separated onto specific
VLANs. Devices that transmit GOOSE messages also function as servers. Each GOOSE
publisher contains a “GOOSE control block” to configure and control the transmission.
The GOOSE transmission (including subscribing and publishing) is controlled by GOOSE VEBI
settings in device.
The PCS-978 series relays support IEC61850 Generic Object Oriented Substation Event (GOOSE)
communication. All GOOSE messages contain IEC61850 data collected into a dataset. It is this
dataset that is transferred using GOOSE message services. The GOOSE related dataset is
configured in the CID file and it is recommended that the fixed GOOSE be used for
implementations that require GOOSE data transfer between PCS-978 series relays.
IEC61850 GOOSE messaging contains a number of configurable parameters, all of which must be
correct to achieve the successful transfer of data. It is critical that the configured datasets at the
transmission and reception devices are an exact match in terms of data structure, and that the
GOOSE addresses and name strings match exactly.
The general steps required for transmission configuration are:

Date: 2011-09-05
10 Communication
1. Configure the data.
2. Configure the transmission dataset.
3. Configure the GOOSE service settings.
The general steps required for reception configuration are:
1. Configure the data.
2. Configure the reception dataset.
3. Configure the GOOSE service settings.
10.5.5 ACSI conformance
10.5.5.1 ACSI Basic Conformance Statement
Services Client Server PCS-978
Client-Server Roles
B11 Server side (of Two-party Application-Association) － C1 Y
B12 Client side (of Two-party Application-Association) C1 － N
SCSMS Supported
B21 SCSM: IEC 61850-8-1 used Y Y Y
B22 SCSM: IEC 61850-9-1 used N N N
B23 SCSM: IEC 61850-9-2 used Y N Y
B24 SCSM: other N N N
Generic Substation Event Model (GSE)
B31 Publisher side － O Y
B32 Subscriber side O － Y
Transmission Of Sampled Value Model (SVC)
B41 Publisher side － O N
B42 Subscriber side O － N
Where:
C1: Shall be "M" if support for LOGICAL-DEVICE model has been declared
O: Optional
M: Mandatory
Y: Supported by PCS-978 relay
N: Currently not supported by PCS-978 relay
10.5.5.2 ACSI Models Conformance Statement

Date: 2011-09-05
10 Communication
M1 Logical device C2 C2 Y
M2 Logical node C3 C3 Y
M3 Data C4 C4 Y
M4 Data set C5 C5 Y
M5 Substitution O O Y
M6 Setting group control O O Y
Reporting
M7 Buffered report control O O Y
M7-1 sequence-number Y Y Y
M7-2 report-time-stamp Y Y Y
M7-3 reason-for-inclusion Y Y Y
M7-4 data-set-name Y Y Y
M7-5 data-reference Y Y Y
M7-6 buffer-overflow Y Y Y
M7-7 entryID Y Y Y
M7-8 BufTm N N N
M7-9 IntgPd Y Y Y
M7-10 GI Y Y Y
M8 Unbuffered report control M M Y
M8-1 sequence-number Y Y Y
M8-2 report-time-stamp Y Y Y
M8-3 reason-for-inclusion Y Y Y
M8-4 data-set-name Y Y Y
M8-5 data-reference Y Y Y
M8-6 BufTm N N N
M8-7 IntgPd N Y Y
Logging
M9 Log control O O N
M9-1 IntgPd N N N
M10 Log O O N
GSE
M12 GOOSE O O Y
M13 GSSE O O N
M14 Multicast SVC O O N
M15 Unicast SVC O O N

Date: 2011-09-05
10 Communication
M16 Time M M Y
M17 File transfer O O Y
Where:
C2: Shall be "M" if support for LOGICAL-NODE model has been declared
C3: Shall be "M" if support for DATA model has been declared
C4: Shall be "M" if support for DATA-SET, Substitution, Report, Log Control, or Time models has
been declared
C5: Shall be "M" if support for Report, GSE, or SMV models has been declared
M: Mandatory
Y: Supported by PCS-978 relay
N: Currently not supported by PCS-978 relay
10.5.5.3 ACSI Services Conformance Statement
Service Server/Publisher PCS-978
Server
S1 ServerDirectory M Y
Application association
S2 Associate M Y
S3 Abort M Y
S4 Release M Y
Logical device
S5 LogicalDeviceDirectory M Y
Logical node
S6 LogicalNodeDirectory M Y
S7 GetAllDataValues M Y
Data
S8 GetDataValues M Y
S9 SetDataValues M Y
S10 GetDataDirectory M Y
S11 GetDataDefinition M Y
Data set
S12 GetDataSetValues M Y
S13 SetDataSetValues O
S14 CreateDataSet O

Date: 2011-09-05
10 Communication
S15 DeleteDataSet O
S16 GetDataSetDirectory M Y
Substitution
S17 SetDataValues M Y
Setting group control
S18 SelectActiveSG M/O Y
S19 SelectEditSG M/O Y
S20 SetSGValuess M/O Y
S21 ConfirmEditSGValues M/O Y
S22 GetSGValues M/O Y
S23 GetSGCBValues M/O Y
Reporting
Buffered report control block
S24 Report M Y
S24-1 data-change M Y
S24-2 qchg-change M Y
S24-3 data-update M Y
S25 GetBRCBValues M Y
S26 SetBRCBValues M Y
Unbuffered report control block
S27 Report M Y
S27-1 data-change M Y
S27-2 qchg-change M Y
S27-3 data-update M Y
S28 GetURCBValues M Y
S29 SetURCBValues M Y
Logging
Log control block
S30 GetLCBValues O
S31 SetLCBValues O
Log
S32 QueryLogByTime O
S33 QueryLogAfter O
S34 GetLogStatusValues O
Generic substation event model (GSE)

Date: 2011-09-05
10 Communication
GOOSE control block
S35 SendGOOSEMessage M Y
S36 GetGoReference O
S37 GetGOOSEElementNumber O Y
S38 GetGoCBValues M Y
S39 SetGoCBValuess M Y
Control
S51 Select O
S52 SelectWithValue M Y
S53 Cancel M Y
S54 Operate M Y
S55 Command-Termination O Y
S56 TimeActivated-Operate O
File transfer
S57 GetFile M/O Y
S58 SetFile O Y
S59 DeleteFile O
S60 GetFileAttributeValues M/O Y
Time
SNTP M Y
10.5.6 Logical Nodes
10.5.6.1 Logical Nodes Table
The PCS-978relays support IEC61850 logical nodes as indicated in the following table. Note that
the actual instantiation of each logical node is determined by the product order code.
Nodes PCS-978
L: System Logical Nodes
LPHD: Physical device information YES
LLN0: Logical node zero YES
P: Logical Nodes For Protection Functions
PDIF: Differential YES
PDIR: Direction comparison －
PDIS: Distance －
PDOP: Directional overpower －
PDUP: Directional underpower －

Date: 2011-09-05
10 Communication
Nodes PCS-978
PFRC: Rate of change of frequency －
PHAR: Harmonic restraint YES
PHIZ: Ground detector －
PIOC: Instantaneous overcurrent YES
PMRI: Motor restart inhibition －
PMSS: Motor starting time supervision －
POPF: Over power factor －
PPAM: Phase angle measuring －
PSCH: Protection scheme －
PSDE: Sensitive directional earth fault YES
PTEF: Transient earth fault －
PTOC: Time overcurrent YES
PTOF: Overfrequency YES
PTOV: Overvoltage YES
PTRC: Protection trip conditioning YES
PTTR: Thermal overload YES
PTUC: Undercurrent －
PTUV: Undervoltage YES
PUPF: Underpower factor －
PTUF: Underfrequency YES
PVOC: Voltage controlled time overcurrent YES
PVPH: Volts per Hz YES
PZSU: Zero speed or underspeed －
R: Logical Nodes For Protection Related Functions
RDRE: Disturbance recorder function YES
RADR: Disturbance recorder channel analogue －
RBDR: Disturbance recorder channel binary －
RDRS: Disturbance record handling －
RBRF: Breaker failure YES
RDIR: Directional element YES
RFLO: Fault locator －
RPSB: Power swing detection/blocking －
RREC: Autoreclosing －
RSYN: Synchronism-check or synchronizing －
C: Logical Nodes For Control

Date: 2011-09-05
10 Communication
Nodes PCS-978
CALH: Alarm handling －
CCGR: Cooling group control －
CILO: Interlocking －
CPOW: Point-on-wave switching －
CSWI: Switch controller －
G: Logical Nodes For Generic References
GAPC: Generic automatic process control －
GGIO: Generic process I/O YES
GSAL: Generic security application －
I: Logical Nodes For Interfacing And Archiving
IARC: Archiving －
IHMI: Human machine interface －
ITCI: Telecontrol interface －
ITMI: Telemonitoring interface －
A: Logical Nodes For Automatic Control
ANCR: Neutral current regulator －
ARCO: Reactive power control －
ATCC: Automatic tap changer controller －
AVCO: Voltage control －
M: Logical Nodes For Metering And Measurement
MDIF: Differential measurements －
MHAI: Harmonics or interharmonics －
MHAN: Non phase related harmonics or interharmonic －
MMTR: Metering －
MMXN: Non phase related measurement －
MMXU: Measurement YES
MSQI: Sequence and imbalance －
MSTA: Metering statistics －
S: Logical Nodes For Sensors And Monitoring
SARC: Monitoring and diagnostics for arcs －
SIMG: Insulation medium supervision (gas) －
SIML: Insulation medium supervision (liquid) －
SPDC: Monitoring and diagnostics for partial discharges －
X: Logical Nodes For Switchgear
TCTR: Current transformer YES

Date: 2011-09-05
10 Communication
Nodes PCS-978
TVTR: Voltage transformer YES
Y: Logical Nodes For Power Transformers
YEFN: Earth fault neutralizer (Peterson coil) －
YLTC: Tap changer －
YPSH: Power shunt －
YPTR: Power transformer YES
Z: Logical Nodes For Further Power System Equipment
ZAXN: Auxiliary network －
ZBAT: Battery －
ZBSH: Bushing －
ZCAB: Power cable －
ZCAP: Capacitor bank －
ZCON: Converter －
ZGEN: Generator －
ZGIL: Gas insulated line －
ZLIN: Power overhead line －
ZMOT: Motor －
ZREA: Reactor YES
ZRRC: Rotating reactive component －
ZSAR: Surge arrestor －
ZTCF: Thyristor controlled frequency converter －
ZTRC: Thyristor controlled reactive component －
10.6 DNP3.0 Interface
10.6.1 Overview
The descriptions given here are intended to accompany this relay. The DNP3.0 protocol is not
described here; please refer to the DNP3.0 protocol standard for the details about the DNP3.0
implementation. This manual only specifies which objects, variations and qualifiers are supported
in this relay, and also specifies what data is available from this relay via DNP3.0.
The relay operates as a DNP3.0 slave and supports subset level 2 of the protocol, plus some of
the features from level 3. The DNP3.0 communication uses the EIA RS-485 at the rear of this relay.
The data format is 1 start bit, 8 data bits, no parity bit and 1 stop bit.
10.6.2 Link Layer Functions

Please see the DNP3.0 protocol standard for the details about the linker layer functions.

Date: 2011-09-05
10 Communication
10.6.3 Transport Functions

Please see the DNP3.0 protocol standard for the details about the transport functions.
10.6.4 Application Layer Functions
10.6.4.1 Time Synchronization
1. Time delay measurement
Master/Slave Function Code Object Variation Qualifier

Master 0x17 －－－
Slave 0x81 0x34 0x02 0x07
2. Read time of device

Master 0x01 0x34 0x00, 0x01 0x07
Slave 0x81 0x32 0x01 0x07
3. Write time of device

Master 0x02 0x32 0x01 0x00,0x01,0x07,0x08
Slave 0x81 －－－
10.6.4.2 Supported Writing Functions
1. Write time of device
See Section 10.6.4.1 for the details.
2. Reset the CU (Reset IIN bit7)

Master 0x02 0x50 0x01 0x00, 0x01
Slave 0x81 －－－
10.6.4.3 Supported Reading Functions
1. Supported qualifiers
Master Qualifier 0x00 0x01 0x06 0x07 0x08

Slave Qualifier 0x00 0x01 0x01 0x07 0x08
2. Supported objects and variations
z Object 1, Binary inputs
Master Variation 0x00 0x01 0x02

Slave Variation 0x02 0x01 0x02
The protection operation signals, alarm signals and binary input state change signals are
transported respectively according to the variation sequence in above table.

Date: 2011-09-05
10 Communication
z Object 2, SOE
Master Variation 0x00 0x01 0x02 0x03

Slave Variation 0x02 0x01 0x02 0x03
If the master qualifier is “0x07”, the slave responsive qualifier is “0x27”; and if the master
qualifier is “0x01”, “0x06” or “0x08”, the slave responsive qualifier is “0x28”.
z Object 30, Analog inputs
Master Variation 0x00 0x01 0x02 0x03 0x04

Slave Variation 0x01 0x01 0x02 0x03 0x04
The measurement values are transported firstly, and then the relay measurement values are
transported.
z Object 40, Analog outputs
Master Variation 0x00 0x01 0x02

Slave Variation 0x01 0x01 0x02
The protection settings are transported in this object.
z Object 50, Time Synchronization
See Section 10.6.4.1 for the details.
3. Class 0 data request
The master adopts the “Object 60” for the Class 0 data request and the variation is “0x01”.
The slave responds with the above mentioned “Object 1”, “Object 30” and “Object 40” (see
“Supported objects and variations” in Section 10.6.4.3).
4. Class 1 data request
The master adopts the “Object 60” for the Class 1 data request and the variation is “0x02”.
The slave responds with the above mentioned “Object 2” (see “Supported objects and
variations” in Section 10.6.4.3).
5. Multiple object request
The master adopts the “Object 60” for the multiple object request and the variation is “0x01”,
“0x02”, “0x03” and “0x04”.
The slave responds with the above mentioned “Object 1”, “Object 2”, “Object 30” and “Object
40” (see “Supported objects and variations” in Section 10.6.4.3).

Date: 2011-09-05
10 Communication

Date: 2011-09-05
11 Installation
11 Installation
Table of Contents
11.1 General .......................................................................................................... 11-1

11.2 Safety Instructions ....................................................................................... 11-1
11.3 Checking the Shipment ................................................................................ 11-2
11.4 Material and Tools Required ........................................................................ 11-2
11.5 Device Location and Ambient Conditions .................................................. 11-2
11.6 Mechanical Installation ................................................................................ 11-3
11.7 Electrical Installation and Wiring ................................................................ 11-4
11.7.1 Grounding Guidelines ..................................................................................................... 11-4
11.7.2 Cubicle Grounding .......................................................................................................... 11-4
11.7.3 Ground Connection on the Device .................................................................................. 11-5
11.7.4 Grounding Strips and their Installation ............................................................................ 11-6
11.7.5 Guidelines for Wiring ....................................................................................................... 11-6
11.7.6 Wiring for Electrical Cables ............................................................................................. 11-7
Table of Figures
Figure 11.6-1 Dimensions of PCS-978 ....................................................................................11-3
Figure 11.6-2 Panel cut-out dimensions of PCS-978 ..........................................................11-3
Figure 11.6-3 Demonstration of plugging a board into its corresponding slot ..................11-4
Figure 11.7-1 Cubicle grounding system ...............................................................................11-5
Figure 11.7-2 Ground terminal of this relay ...........................................................................11-6
Figure 11.7-3 Ground strip and termination ..........................................................................11-6
Figure 11.7-4 Glancing demo about the wiring for electrical cables ...................................11-7
Date: 2011-11-21
11 Installation

Date: 2011-11-21
11 Installation
11.1 General
The equipment must be shipped, stored and installed with the greatest care.
Choose the place of installation such that the communication interface and the controls on the
front of the device are easily accessible.
Air must circulate freely around the equipment. Observe all the requirements regarding place of
installation and ambient conditions given in this instruction manual.
Take care that the external wiring is properly brought into the equipment and terminated correctly
and pay special attention to grounding. Strictly observe the corresponding guidelines contained in
this section.
11.2 Safety Instructions
Modules and units may only be replaced by correspondingly trained personnel. Always observe
the basic precautions to avoid damage due to electrostatic discharge when handling the
equipment.
In certain cases, the settings have to be configured according to the demands of the engineering
configuration after replacement. It is therefore assumed that the personnel who replace modules
and units are familiar with the use of the operator program on the service PC.
DANGER! Only insert or withdraw the PWR module while the power supply is switched
off. To this end, disconnect the power supply cable that connects with the PWR module.
WARNING! Only insert or withdraw other modules while the power supply is switched off.
WARNING! The modules may only be inserted in the slots designated in Section 6.2.
Components can be damaged or destroyed by inserting boards in the wrong slots.
DANGER! Improper handling of the equipment can cause damage or an incorrect
response of the equipment itself or the primary plant.
WARNING! Industry packs and ribbon cables may only be replaced or the positions of
jumpers be changed on a workbench appropriately designed for working on electronic

equipment. The modules, bus backplanes are sensitive to electrostatic discharge when
not in the unit's housing.
The basic precautions to guard against electrostatic discharge are as follows:
z Should boards have to be removed from this relay installed in a grounded cubicle in an HV
Date: 2011-11-21
11 Installation
switchgear installation, please discharge yourself by touching station ground (the cubicle)
beforehand.
z Only hold electronic boards at the edges, taking care not to touch the components.
z Only works on boards that have been removed from the cubicle on a workbench designed for
electronic equipment and wear a grounded wristband. Do not wear a grounded wristband,
however, while inserting or withdrawing units.
z Always store and ship the electronic boards in their original packing. Place electronic parts in
electrostatic screened packing materials.
11.3 Checking the Shipment
Check that the consignment is complete immediately upon receipt. Notify the nearest NR
Company or agent, should departures from the delivery note, the shipping papers or the order be
found.
Visually inspect all the material when unpacking it. When there is evidence of transport damage,
lodge a claim immediately in writing with the last carrier and notify the nearest NR Company or
agent.
If the equipment is not going to be installed immediately, store all the parts in their original packing
in a clean dry place at a moderate temperature. The humidity at a maximum temperature and the
permissible storage temperature range in dry air are listed in Section 2.1.3.
11.4 Material and Tools Required
The necessary mounting kits will be provided, including screws, pincers and assembly
instructions.
A suitable drill and spanners are required to secure the cubicles to the floor using the plugs
provided (if this relay is mounted in cubicles).
11.5 Device Location and Ambient Conditions
The place of installation should permit easy access especially to front of the device, i.e. to the
human machine interface of the equipment.
There should also be free access at the rear of the equipment for additions and replacement of
electronic boards.
Since every piece of technical equipment can be damaged or destroyed by inadmissible ambient
conditions, such as:
1. The location should not be exposed to excessive air pollution (dust, aggressive substances).
2. Severe vibration, extreme changes of temperature, high levels of humidity, surge voltages of

Date: 2011-11-21
11 Installation
high amplitude and short rise time and strong induced magnetic fields should be avoided as
far as possible.
3. Air must not be allowed to circulate freely around the equipment.
The equipment can in principle be mounted in any attitude, but it is normally mounted vertically
(visibility of markings).
WARNING! Excessively high temperature can appreciably reduce the operating life of
this relay.
11.6 Mechanical Installation
This relay is made of a single layer 4U height 19" chassis with 8 connectors on its rear panel.
Following two figures show the dimensions of this relay for reference in mounting.
101.6
177.0
Figure 11.6-1 Dimensions of PCS-978
465.0
101.6
179.0
4-Ф6.8
450.0
Figure 11.6-2 Panel cut-out dimensions of PCS-978
NOTE! It is necessary to leave enough space top and bottom of the cut-out in the cubicle
for heat emission of this relay.
Date: 2011-11-21
11 Installation
The safety instructions must be abided by when installing the boards, please see Section 11.2 for
the details.
Following figure shows the installation way of a module being plugged into a corresponding slot.
Figure 11.6-3 Demonstration of plugging a board into its corresponding slot
In the case of equipment supplied in cubicles, place the cubicles on the foundations that have
been prepared. Take care while doing so not to jam or otherwise damage any of the cables that
have already been installed. Secure the cubicles to the foundations.
11.7 Electrical Installation and Wiring
11.7.1 Grounding Guidelines

Switching operations in HV installations generate transient over voltages on control signal cables.
There is also a background of electromagnetic RF fields in electrical installations that can induce
spurious currents in the devices themselves or the leads connected to them.
All these influences can influence the operation of electronic apparatus.
On the other hand, electronic apparatus can transmit interference that can disrupt the operation of
other apparatus.
In order to minimize these influences as far as possible, certain standards have to be observed
with respect to grounding, wiring and screening.
NOTE! All these precautions can only be effective if the station ground is of good quality.
11.7.2 Cubicle Grounding

The cubicle must be designed and fitted out such that the impedance for RF interference of the
ground path from the electronic device to the cubicle ground terminal is as low as possible.
Metal accessories such as side plates, blanking plates etc., must be effectively connected
surface-to-surface to the grounded frame to ensure a low-impedance path to ground for RF
interference. The contact surfaces must not only conduct well, they must also be non-corroding.

Date: 2011-11-21
11 Installation
NOTE! If the above conditions are not fulfilled, there is a possibility of the cubicle or parts
of it forming a resonant circuit at certain frequencies that would amplify the transmission
of interference by the devices installed and also reduce their immunity to induced
interference.
Movable parts of the cubicle such as doors (front and back) or hinged equipment frames must be
effectively grounded to the frame by three braided copper strips (see Figure 11.7-1).
The metal parts of the cubicle housing and the ground rail are interconnected electrically
conducting and corrosion proof. The contact surfaces shall be as large as possible.
NOTE! For metallic connections please observe the voltage difference of both materials
according to the electrochemical code.
The cubicle ground rail must be effectively connected to the station ground rail by a grounding strip
(braided copper).
Figure 11.7-1 Cubicle grounding system
11.7.3 Ground Connection on the Device

There is a ground terminal on the rear panel, and the ground braided copper strip can be
connected with it. Take care that the grounding strip is always as short as possible. The main thing
is that the device is only grounded at one point. Grounding loops from unit to unit are not allowed.
There are some ground terminals on some connectors of this relay, and the sign is “GND”. All the
ground terminals are connected in the cabinet of this relay. So, the ground terminal on the rear
panel (see Figure 11.7-2) is the only ground terminal of this device.
Date: 2011-11-21
11 Installation
Figure 11.7-2 Ground terminal of this relay
11.7.4 Grounding Strips and their Installation

High frequency currents are produced by interference in the ground connections and because of
skin effect at these frequencies, only the surface region of the grounding strips is of consequence.
The grounding strips must therefore be of (preferably tinned) braided copper and not round copper
conductors, as the cross-section of round copper would have to be too large.
Proper terminations must be fitted to both ends (press/pinch fit and tinned) with a hole for bolting
them firmly to the items to be connected.
The surfaces to which the grounding strips are bolted must be electrically conducting and
non-corroding.
The following figure shows the ground strip and termination.
Figure 11.7-3 Ground strip and termination
11.7.5 Guidelines for Wiring

There are several types of cables that are used in the connection of this relay: braided copper
cable, serial communication cable etc. Recommendation of each cable:
z Grounding: braided copper cable, 2.5mm2 ~ 6.0mm2
z Power supply, binary inputs & outputs: brained copper cable, 1.5mm2 ~ 2.5mm2
z AC voltage inputs: brained copper cable, 1.5mm2 ~ 2.5mm2
z AC current inputs: brained copper cable, 2.5mm2 ~ 6.0mm2
z Serial communication: 4-core shielded braided cable
z Ethernet communication: 4-pair screened twisted category 5E cable

Date: 2011-11-21
11 Installation
11.7.6 Wiring for Electrical Cables

A female connector is used for connecting the wires with it, and then a female connector plugs into
a corresponding male connector that is in the front of one board. See Chapter “Hardware” for
further details about the pin defines of these connectors.
The following figure shows the glancing demo about the wiring for the electrical cables.
Figure 11.7-4 Glancing demo about the wiring for electrical cables
DANGER! Never allow the current transformer (CT) secondary circuit connected to this
equipment to be opened while the primary system is live. Opening the CT circuit will
produce a dangerously high voltage.
Date: 2011-11-21
11 Installation

Date: 2011-11-21
12 Commissioning
12 Commissioning
Table of Contents
12.1 General ..........................................................................................................12-1

12.2 Safety Instructions .......................................................................................12-1
12.3 Commission Tools........................................................................................12-2
12.4 Setting Familiarization .................................................................................12-2
12.5 Product Checks ............................................................................................12-3
12.5.1 With the Relay De-energized ......................................................................................... 12-3
12.5.2 With the Relay Energized .............................................................................................. 12-5
12.5.3 Print Fault Report ........................................................................................................... 12-8
12.5.4 On-load Checks ............................................................................................................. 12-9

Date: 2011-11-21
12 Commissioning

Date: 2011-11-21
12 Commissioning
12.1 General
This relay is fully numerical in their design, implementing all protection and non-protection
functions in software. The relay employs a high degree of self-checking and in the unlikely event of
a failure, will give an alarm. As a result of this, the commissioning test does not need to be as
extensive as with non-numeric electronic or electro-mechanical relays.
To commission numerical relays, it is only necessary to verify that the hardware is functioning
correctly and the application-specific software settings have been applied to the relay.
Blank commissioning test and setting records are provided at the end of this manual for
completion as required.
Before carrying out any work on the equipment, the user should be familiar with the contents of the
safety and technical data sections and the ratings on the equipment’s rating label.
12.2 Safety Instructions
WARNING! Hazardous voltages are present in this electrical equipment during operation.
Non-observance of the safety rules can result in severe personal injury or property
damage.
WARNING! Only the qualified personnel shall work on and around this equipment after
becoming thoroughly familiar with all warnings and safety notices of this manual as well
as with the applicable safety regulations.
Particular attention must be drawn to the following:
z The earthing screw of the device must be connected solidly to the protective earth conductor
before any other electrical connection is made.
z Hazardous voltages can be present on all circuits and components connected to the supply
voltage or to the measuring and test quantities.
z Hazardous voltages can be present in the device even after disconnection of the supply
voltage (storage capacitors!)
z The limit values stated in the Chapter “Technical Data” must not be exceeded at all, not even
during testing and commissioning.
z When testing the device with secondary test equipment, make sure that no other
measurement quantities are connected. Take also into consideration that the trip circuits and
maybe also close commands to the circuit breakers and other primary switches are
disconnected from the device unless expressly stated.

Date: 2011-11-21
12 Commissioning
DANGER! Current transformer secondary circuits must have been short-circuited before
the current leads to the device are disconnected.
WARNING! Primary test may only be carried out by qualified personnel, who are familiar
with the commissioning of protection system, the operation of the plant and safety rules
and regulations (switching, earthing, etc.).
12.3 Commission Tools
Minimum equipment required:
z Multifunctional dynamic current and voltage injection test set with interval timer.
z Multimeter with suitable AC current range and AC/DC voltage ranges of 0~440V and 0~250V
respectively.
z Continuity tester (if not included in the multimeter).
z Phase angle meter.
z Phase rotation meter.
NOTE! Modern test set may contain many of the above features in one unit.
Optional equipment:
z An electronic or brushless insulation tester with a DC output not exceeding 500V (for
insulation resistance test when required).
z A portable PC, with appropriate software (this enables the rear communications port to be
tested, if this is to be used, and will also save considerable time during commissioning).
z EIA RS-485 to EIA RS-232 converter (if EIA RS-485 IEC60870-5-103 port is being tested).
z PCS-9780 serials dedicated protection tester HELP-2000.
12.4 Setting Familiarization
When commissioning this device for the first time, sufficient time should be allowed to become
familiar with the method by which the settings are applied. A detailed description of the menu
structure of this relay is contained in Chapter “Operation Theory” and Chapter “Settings”.
With the front cover in place all keys are accessible. All menu cells can be read. The LED
indicators and alarms can be reset. Protection or configuration settings can be changed, or fault
and event records cleared. However, menu cells will require the appropriate password to be
entered before changes can be made.

Date: 2011-11-21
12 Commissioning
Alternatively, if a portable PC is available together with suitable setting software (such as

PCS-9700 SAS software), the menu can be viewed one page at a time to display a full column of
data and text. This PC software also allows settings to be entered more easily, saved to a file on
disk for future reference or printed to produce a setting record. Refer to the PC software user
manual for details. If the software is being used for the first time, allow sufficient time to become
familiar with its operation.
12.5 Product Checks
These product checks cover all aspects of the relay which should be checked to ensure that it has
not been physically damaged prior to commissioning, is functioning correctly and all input quantity
measurements are within the stated tolerances.
If the application-specific settings have been applied to the relay prior to commissioning, it is
advisable to make a copy of the settings so as to allow them restoration later. This could be done
by extracting the settings from the relay itself via printer or manually creating a setting record.
12.5.1 With the Relay De-energized

This relay is fully numerical and the hardware is continuously monitored. Commissioning tests can
be kept to a minimum and need only include hardware tests and conjunctive tests. The function
tests are carried out according to user’s correlative regulations.
The following tests are necessary to ensure the normal operation of the equipment before it is first
put into service.
z Hardware tests
These tests are performed for the following hardware to ensure that there is no hardware
defect. Defects of hardware circuits other than the following can be detected by
self-monitoring when the DC power is supplied.
z User interfaces test
z Binary input circuits and output circuits test
z AC input circuits test
z Function tests
These tests are performed for the following functions that are fully software-based. Tests of
the protection schemes and fault locator require a dynamic test set.
z Measuring elements test
z Timers test
z Metering and recording test
z Conjunctive tests
The tests are performed after the relay is connected with the primary equipment and other

Date: 2011-11-21
12 Commissioning
external equipment.
z On load test.
z Phase sequence check and polarity check.
12.5.1.1 Visual Inspection
After unpacking the product, check for any damage to the relay case. If there is any damage, the
internal module might also have been affected, contact the vendor. The following items listed is
necessary.
z Protection panel
Carefully examine the protection panel, protection equipment inside and other parts inside to
see that no physical damage has occurred since installation.
The rated information of other auxiliary protections should be checked to ensure it is correct
for the particular installation.
z Panel wiring
Check the conducting wire which is used in the panel to assure that their cross section
meeting the requirement.
Carefully examine the wiring to see that they are no connection failure exists.
z Label
Check all the isolator binary inputs, terminal blocks, indicators, switches and push buttons to
make sure that their labels meet the requirements of this project.
z Equipment plug-in modules
Check each plug-in module of the equipments on the panel to make sure that they are well
installed into the equipment without any screw loosened.
z Earthing cable
Check whether the earthing cable from the panel terminal block is safely screwed to the panel
steel sheet.
z Switch, keypad, isolator binary inputs and push button
Check whether all the switches, equipment keypad, isolator binary inputs and push buttons
work normally and smoothly.
12.5.1.2 Insulation Test (if required)
Insulation resistance tests are only necessary during commissioning if it is required for them to be
done and they have not been performed during installation.
Isolate all wiring from the earth and test the isolation with an electronic or brushless insulation
tester at a DC voltage not exceeding 500V, The circuits need to be tested should include:

Date: 2011-11-21
12 Commissioning
z Voltage transformer circuits
z Current transformer circuits
z DC power supply
z Optic-isolated control inputs
z Output contacts
z Communication ports
The insulation resistance should be greater than 100MΩ at 500V.
Test method:
To unplug all the terminals sockets of this relay, and do the Insulation resistance test for each
circuit above with an electronic or brushless insulation tester.
On completion of the insulation resistance tests, ensure all external wiring is correctly reconnected
to the protection.
12.5.1.3 External Wiring
Check that the external wiring is correct to the relevant relay diagram and scheme diagram.
Ensure as far as practical that phasing/phase rotation appears to be as expected.
Check the wiring against the schematic diagram for the installation to ensure compliance with the
customer’s normal practice.
12.5.1.4 Auxiliary Power Supply
The relay only can be operated under the auxiliary power supply depending on the relay’s nominal
power supply rating.
The incoming voltage must be within the operating range specified in Section 2.1.2, before
energizing the relay, measure the auxiliary supply to ensure it within the operating range.
Other requirements to the auxiliary power supply are specified in Section 2.1.2. See this section
for further details about the parameters of the power supply.
WARNING! Energize this relay only if the power supply is within the specified operating
ranges in Section 2.1.2.
12.5.2 With the Relay Energized

The following groups of checks verify that the relay hardware and software is functioning correctly
and should be carried out with the auxiliary supply applied to the relay.
The current and voltage transformer connections must remain isolated from the relay for these
checks. The trip circuit should also remain isolated to prevent accidental operation of the
associated circuit breaker.

Date: 2011-11-21
12 Commissioning
12.5.2.1 Front Panel LCD Display
Connect the relay to DC power supply correctly and turn the relay on. Check program version and
forming time displayed in command menu to ensure that are corresponding to what ordered.
12.5.2.2 Date and Time
If the time and date is not being maintained by substation automation system, the date and time
should be set manually.
Set the date and time to the correct local time and date using menu item “CLOCK”.
In the event of the auxiliary supply failing, with a battery fitted on CPU board, the time and date will
be maintained. Therefore when the auxiliary supply is restored the time and date will be correct
and not need to set again.
To test this, remove the auxiliary supply from the relay for approximately 30s. After being
re-energized, the time and date should be correct.
12.5.2.3 Light Emitting Diodes (LEDs)
On power up, the green LED “HEALTHY” should have illuminated and stayed on indicating that
the relay is healthy.
The relay has latched signal relays which remember the state of the trip, auto-reclose when the
relay was last energized from an auxiliary supply. Therefore these indicators may also illuminate
when the auxiliary supply is applied. If any of these LEDs are on then they should be reset before
proceeding with further testing. If the LED successfully reset, the LED goes out. There is no testing
required for that that LED because it is known to be operational.
It is likely that alarms related to voltage transformer supervision will not reset at this stage.
12.5.2.4 Testing the HEALTHY and ALARM LEDs
Apply the rated DC power supply and check that the “HEALTHY” LED is lighting in green. We
need to emphasize that the “HEALTHY” LED is always lighting in operation course except that the
equipment find serious errors in it.
Produce one of the abnormal conditions listed in Chapter “Supervision”, the “ALARM” LED will
light in yellow. When abnormal condition reset, the “ALARM” LED extinguishes.
12.5.2.5 Testing the TRIP LED
The “TRIP” LED can be tested by initiating a manual circuit breaker trip from the relay. However
the “TRIP” LED will operate during the setting checks. Therefore no further testing of the “TRIP”
LED is required at this stage.
12.5.2.6 Testing the AC Current Inputs
This test verified that the accuracy of current measurement is within the acceptable tolerances.
Apply rated current to each current transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the relays menu.

Date: 2011-11-21
12 Commissioning
The measurement accuracy of the protection is 2.5% or 0.02In. However, an additional allowance
must be made for the accuracy of the test equipment being used.
NOTE! The closing circuit should remain isolated during these checks to prevent
accidental operation of the associated circuit breaker.
Input Measurement (on LCD)

Group No. Item
Value Angle Value Angle
Ia
Three-phase current 1 Ib
Ic
Ia
Ic
Ia
Ic
Ia
Three-phase current …. Ib
Ic
Neutral current 1 3I0
Neutral current … 3I0
12.5.2.7 Testing the AC Voltage Inputs
This test verified that the accuracy of voltage measurement is within the acceptable tolerances.
Apply rated voltage to each voltage transformer input in turn; checking its magnitude using a
multimeter/test set readout. The corresponding reading can then be checked in the relays menu.
The measurement accuracy of the relay is 2.5% or 0.1V. However an additional allowance must be
made for the accuracy of the test equipment being used.
NOTE! The closing circuit should remain isolated during these checks to prevent
accidental operation of the associated circuit breaker.
Linearity and precision checkout

Items
Three-phase voltage 1 Ua

Date: 2011-11-21
12 Commissioning

Items
Ub
Uc
Ua
Three-phase voltage 2 Ub
Uc
Ua
Ub
Three-phase voltage 3
Uc
Uc
Residual voltage 1 3U0
12.5.2.8 Testing the Binary Inputs
This test checks that all the binary inputs on the equipment are functioning correctly.
The binary inputs should be energized one at a time, see external connection diagrams for
terminal numbers.
Ensure that the voltage applied on the binary input must be within the operating range.
The status of each binary input can be viewed using relay menu. Sign “1” denotes an energized
input and sign “0” denotes a de-energized input.
Binary Inputs testing checkout
Terminal No. Signal Name BI Status on LCD Correct?
Test method:
To unplug all the terminals sockets of this protective device, and do the Insulation resistance test
for each circuit above with an electronic or brushless insulation tester.
On completion of the insulation resistance tests, ensure all external wiring is correctly reconnected
to the protection.
12.5.3 Print Fault Report

In order to acquire the details of protection operation, it is convenient to print the fault report of
protection device. The printing work can be easily finished when operator presses the print button
on panel of protection device to energize binary input [BI_Print] or operate control menu. What
should be noticed is that only the latest fault report can be printed if operator presses the print

Date: 2011-11-21
12 Commissioning
button. A complete fault report includes the content shown as follows.
1) Trip event report
2) Binary input when protection devices start
3) Self-check and the transition of binary input in the process of devices start
4) Fault wave forms compatible with COMTRADE
5) The setting value when the protection device trips
12.5.4 On-load Checks

The objectives of the on-load checks are:
z Confirm the external wiring to the current and voltage inputs is correct.
z Measure the magnitude of on-load current and voltage (if applicable).
z Check the polarity of each current transformer.
However, these checks can only be carried out if there are no restrictions preventing the
tenderization of the plant being protected.
Remove all test leads, temporary shorting leads, etc. and replace any external wiring that has
been removed to allow testing.
If it has been necessary to disconnect any of the external wiring from the protection in order to
perform any of the foregoing tests, it should be ensured that all connections are replaced in
accordance with the relevant external connection or scheme diagram. Confirm current and voltage
transformer wiring.
12.5.4.1 Final Checks
After the above tests are completed, remove all test or temporary shorting leads, etc. If it has been
necessary to disconnect any of the external wiring from the protection in order to perform the
wiring verification tests, it should be ensured that all connections are replaced in accordance with
the relevant external connection or scheme diagram.
Ensure that the protection has been restored to service.
If the protection is in a new installation or the circuit breaker has just been maintained, the circuit
breaker maintenance and current counters should be zero. If a test block is installed, remove the
test plug and replace the cover so that the protection is put into service.
Ensure that all event records, fault records, disturbance records and alarms have been cleared
and LED’s has been reset before leaving the protection.

Date: 2011-11-21
12 Commissioning

Date: 2011-11-21
13 Maintenance
13 Maintenance
Table of Contents
13.1 Appearance Check ...................................................................................... 13-1

13.2 Failure Tracing and Repair .......................................................................... 13-1
13.3 Replace Failed Modules .............................................................................. 13-1
13.4 Replace Button Battery ............................................................................... 13-3
13.5 Cleaning ....................................................................................................... 13-3
13.6 Storage ......................................................................................................... 13-3
PCS-978 Transformer Relay 13-i

Date: 2011-11-21
13 Maintenance
13-ii PCS-978 Transformer Relay

Date: 2011-11-21
13 Maintenance
NR numerical relay PCS-978 is designed to require no special maintenance. All measurement and
signal processing circuit are fully solid state. All input modules are also fully solid state. The output
relays are hermetically sealed.
Since the device is almost completely self-monitored, from the measuring inputs to the output
relays, hardware and software defects are automatically detected and reported. The
self-monitoring ensures the high availability of the device and generally allows for a corrective
rather than preventive maintenance strategy. Therefore, maintenance checks in short intervals are
not required.
Operation of the device is automatically blocked when a hardware failure is detected. If a problem
is detected in the external measuring circuits, the device normally only provides alarm messages.
13.1 Appearance Check

The relay case should be clean without any dust stratification. Case cover should be sealed well.
No component has any mechanical damage and distortion, and they should be firmly fixed in the
case. Relay terminals should be in good condition. The keys on the front panel with very good
feeling can be operated flexibly.
It is only allowed to plug or withdraw relay board when the supply is reliably switched off. Never
allow the CT secondary circuit connected to this equipment to be opened while the primary system
is live when withdrawing an AC module. Never try to insert or withdraw the relay board when it is
unnecessary.
Check weld spots on PCB whether they are well soldered without any rosin joint. All dual inline
components must be well plugged.
13.2 Failure Tracing and Repair

Failures will be detected by automatic supervision or regular testing.
When a failure is detected by supervision, a remote alarm is issued and the failure is indicated on
the front panel with LED indicators and LCD display. It is also recorded in the event record.
Failures detected by supervision are traced by checking the “Superv_Events” screen on the LCD.
When a failure is detected during regular testing, confirm the following:
z Test circuit connections are correct
z Modules are securely inserted in position
z Correct power supply voltage is applied
z Correct analog inputs are applied
z Test procedures comply with those stated in the manual
13.3 Replace Failed Modules

If the failure is identified to be in the relay module and the user has spare modules, the user can

Date: 2011-11-21
13 Maintenance
recover the protection by replacing the failed modules.
Repair at the site should be limited to module replacement. Maintenance at the component level is
not recommended.
Check that the replacement module has an identical module name (AI, PWR, CPU, SIG, BI, BO,
etc.) and hardware type-form as the removed module. Furthermore, the CPU module replaced
should have the same software version. In addition, the AI module, PWR module, BI module, IO
module and RLY module replaced should have the same ratings.
The module name is indicated on the top front of the module. The software version is indicated in
LCD menu “Version_Info”.
CAUTION: When handling a module, take anti-static measures such as wearing an
earthed wrist band and placing modules on an earthed conductive mat. Otherwise, many
of the electronic components could suffer damage. After replacing the CPU module, check
the settings.
1) Replacing a module
z Switch off the power supply
z Disconnect the trip outputs
z Short circuit all AC current inputs and disconnect all AC voltage inputs
z Unscrew the module.
WARNING: Hazardous voltage can be present in the DC circuit just after switching off the
DC power supply. It takes approximately 30 seconds for the voltage to discharge.
2) Replacing the Human Machine Interface Module (front panel)
z Open the relay front panel
z Unplug the ribbon cable on the front panel by pushing the catch outside.
z Detach the HMI module from the relay
z Attach the replacement module in the reverse procedure.
3) Replacing the AI, PWR, CPU, BI, IO, BO module
z Unscrew the module connector
z Unplug the connector from the target module.
z Unscrew the module.
z Pull out the module
z Inset the replacement module in the reverser procedure.

Date: 2011-11-21
13 Maintenance
z After replacing the CPU module, input the application-specific setting values again.
WARNING: Units and modules may only be replaced while the supply is switched off
and only by appropriately trained and qualified personnel. Strictly observe the basic
precautions to guard against electrostatic discharge.
WARNING: When handling a module, take anti-static measures such as wearing an
earthed wrist band and placing modules on an earthed conductive mat. Otherwise,
many of the electronic components could suffer damage. After replacing the CPU
module, check the settings.
DANGER: After replacing modules, be sure to check that the same configuration is set
as before the replacement. If this is not the case, there is a danger of the unintended
operation of switchgear taking place or of protections not functioning correctly. Persons
may also be put in danger.
13.4 Replace Button Battery

When the voltage of button Battery on CPU board is below 2.5 volts (nominal voltage is 3 volts),
please replace the button battery to ensure internal clock of CPU board running correctly.
13.5 Cleaning
Before cleaning the relay, ensure that all AC/DC supplies, current transformer connections are
isolated to prevent any chance of an electric shock whilst cleaning. Use a smooth cloth to clean
the front panel. Do not use abrasive material or detergent chemicals.
13.6 Storage
The spare relay or module should be stored in a dry and clean room. Based on IEC standard
60255-6 the storage temperature should be from-40°C to 70°C, but the temperature of from -10°C
to 40°C is recommended for long-term storage.

Date: 2011-11-21
13 Maintenance

Date: 2011-11-21
Table of Contents
14.1 Decommissioning ........................................................................................ 14-1

14.1.1 Switching off ...................................................................................................................14-1
14.1.2 Disconnecting Cables .....................................................................................................14-1
14.1.3 Dismantling .....................................................................................................................14-1
14.2 Disposal........................................................................................................ 14-1

Date: 2011-11-21

Date: 2011-11-21
14.1 Decommissioning
14.1.1 Switching off

To switch off the PCS-978, switch off the external miniature circuit breaker of the power supply.
14.1.2 Disconnecting Cables

Disconnect the cables in accordance with the rules and recommendations made by relational
department.
DANGER! Before disconnecting the power supply cables that connected with the PWR
module of the PCS-978 make sure that the external miniature circuit breaker of the power
supply is switched off.
DANGER! Before disconnecting the cables that are used to connect analog input module
with the primary CTs, make sure that the primary CTs aren’t in service.
14.1.3 Dismantling
The PCS-978 rack may now be removed from the system cubicle, after which the cubicles may
also be removed.
DANGER! When the station is in operation, make sure that there is an adequate safety
distance to live parts, especially as dismantling is often performed by unskilled personnel.
14.2 Disposal
In every country there are companies specialized in the proper disposal of electronic waste.
NOTE! Strictly observe all local and national regulations when disposing of the device.

Date: 2011-11-21

Date: 2011-11-21

In the latest version of the instruction manual, several descriptions on existing features have been
modified.
Manual version and modification history records
Manual Version Software

Date Description of change
Source New Version
1． Protection modularization
1.02 2.00 2011-04-22 2． New terminology rules adopting ANSI function code
3． Loos-leaf format
1． Add breaker failure protection
2.00 2.01 2.00 2011-08-18
2． Add pole disagreement protection
1． Mechanical IO module NR1533 is replaced by NR1536
2.01 2.02 2.00 2011-11-21
2． Add description of inrush current bocking

Date: 2011-11-21

Date: 2011-11-21

PCS-978 Transformer and Reactor Relay PDF

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

PCS-978 Transformer and Reactor Relay PDF

Caricato da

Copyright:

Formati disponibili

PCS-978

NR Electric Co., Ltd.

Health and Safety

Qualified personnel are individuals who:

 Are trained in emergency procedures (first aid).

PCS-978 Transformer Relay I

Instructions and Warnings

The following indicators and standard definitions are used:

II PCS-978 Transformer Relay

The earthing terminal of the equipment must be securely earthed

 Printed circuit board

Carefully handle the connection cable without applying excessive force.

Version: 2.02 NR ELECTRIC CO., LTD.

69 Suyuan Avenue. Jiangning, Nanjing 211102, China

P/N: EN_YJBH5100.0086.0203 Tel: +86-25-87178185, Fax: +86-25-87178208

Website: www.nrelect.com, www.nari-relays.com

Copyright © NR 2011. All rights reserved Email: nr_techsupport@nari-relays.com

We reserve the rights to make technical improvements without notice.

PCS-978 Transformer Relay III

IV PCS-978 Transformer Relay

The chapter contents are summarized as below:

5 Meaurement and Recording

8 Human Machine Interface

PCS-978 Transformer Relay V

14 Decommissioning and Disposal

15 Manual Version History

Typographic and Graphical Conventions

The following symbols are used in drawings:

BI Binary signal via opto-coupler

SET I> Input signal from comparator with setting

EN Input signal of logic setting for function enabling

Input of binary signal except those signals via opto-coupler

VI PCS-978 Transformer Relay

Input of other signal

XXX Output signal

IDMT Timer (inverse-time characteristic)

Instrument current transformer

Instrument voltage transformer

PCS-978 Transformer Relay VII

VIII PCS-978 Transformer Relay

1.1 Application ....................................................................................................... 1-1

1.3.2 Transformer Current Differential Protection ........................................................................1-9

1.3.3 Restricted Earth Fault Protection ......................................................................................1-10

1.3.4 Winding Differential Protection .........................................................................................1-10

1.3.5 Reactor Current Differential Protection ............................................................................. 1-11

1.3.6 Reactor Inter-Turn Fault Protection .................................................................................. 1-11

1.3.7 Overexcitation Protection.................................................................................................. 1-11

1.3.8 Mechanical Protection ......................................................................................................1-12

1.3.9 Phase Overcurrent Protection ..........................................................................................1-12

1.3.10 Ground Overcurrent Protection .......................................................................................1-12

1.3.11 Phase Overvoltage Protection ........................................................................................1-12

1.3.12 Residual Overvoltage Protection ....................................................................................1-13

1.3.13 Undervoltage Protection .................................................................................................1-13

1.3.14 Thermal Overload Protection ..........................................................................................1-13

Figure 1.1-1 2-winding and 3-winding applications ................................................................1-2

Figure 1.1-2 Autotransformer applications .............................................................................1-3

Figure 1.2-1 Function diagram 1 for a three-winding transformer ........................................1-5

Figure 1.2-2 Function diagram 2 for an auto-transformer ......................................................1-6

Figure 1.2-3 Function diagram 3 for reactor............................................................................1-6

PCS-978 Transformer Relay 1-a

Table 1.2-1 Protective functions in PCS-978 ...........................................................................1-4

Table 1.2-2 Miscellaneous functions in PCS-978 ....................................................................1-7

1-b PCS-978 Transformer Relay