Electrical Characterizations of Bonded Wafers

Team: Crazy 4
Sager Ayyoub
Moises Bahena
Punya Koirala
Laith Ayyoub

Project Mentor: Dr. Rafiqul Islam

Email: rafiqul.islam@cactusmaterials.com
11/28/19
Executive Summary

The modern era of science and technology is getting more and more sophisticated. Every
day new inventions are emerging with better ideas and more complicated applications. Looking
at the advancement of technology in IC designs today, it is unbelievable that there are billions of
transistors in a cm2 of a microchip. In this fantastic world of technology, Crazy 4 is trying to
make some significant impact through their research on the characterization of bonded wafers.
The research allows the team to find how to design a circuitry inside any computer modules. The
goal is to shrink the area of space taken by different components inside an IC. By studying the I-
V and C-V characteristics under different physical and environmental conditions, it allows
designing optimal IC design which can withstand various adverse effects on the IC like
overheating, slowing the speed. Final goal of the project is the make low gain avalanche
detectors which will revolutionize medical, and defense industries.

The tentative duration of the project is to complete by April of 2020. During the first
phase of the project, thorough investigation and research are done. During this research phase,
various materials from the library, internet, research papers will be reviewed, and experts in the
area will be consulted. The main motive of the research phase is to come up with better ideas and
understanding of how the process will be done

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Introduction

The big picture: Low to moderate gain (x10-50) reach-through silicon avalanche diodes
(LGADs) are a proposed sensor type to achieve ~10 ps time resolution for collider experiments
1. A timing resolution of 26 ps per single LGAD layer was achieved recently [2], which made
thin LGADs (~50 um) a baseline option for timing detectors of both CMS and ATLAS at the
high luminosity upgrade of the LHC (HL-LHC) around 2026 3, 4. Devices as Silicon
Photomultipliers (SiPM) and Avalanche Photo-Diodes (APD) have a higher gain than LGADs
but these detectors also exhibit a higher noise than LGADs. The high multiplication spoils the
time resolution. Furthermore, SiPM and APDs have crosstalk, which increases with the
multiplication. A total segmentation of the pixels is required. The improvement of timing
resolution on tracking detectors allows collecting only the data of time-compatible events and
rejecting those events that cannot be associated to a track due to an excessive time difference.
Therefore, more data can be taken and pile-up effect is avoided, making LGADs good candidates
for the upgrade of the HGTD, ATLAS Forward Proton detector (AFP), Endcap Timing Layer,
and CMS-Totem Proton Precision Spectroscopy detector (CT-PPS) projects. The current
generation of reach-through diodes suffers from large fractional dead area at the edges of the
pixel (>50 micron) and only moderate radiation hardness. Efforts by scientists are underway
to solve edges problem by introducing “AC coupled buried layer design”. In the AC coupled
LGAD, the prompt signal is coupled through a thin oxide layer to the pickup electrode. The sheet
resistance of the anode implant and coupling capacitance must be tuned to provide the proper
output pulse shape, neighbor signal, and DC coupling to ground. The main obstacle for their
successful use at future experiments in high energy physics is the degradation of gain with
fluence. LGADs will be exposed at the HL-LHC to equivalent fluences of up to ∅eq = 6 ⋅ 1015
cm −2. At these fluences the gain due to the p+ layer completely disappears 6. In this process,
radiation removes donors and creates acceptors, which modifies the field in the reach-through
region, ultimately
eliminating gain.

The internal structures of microelectronics are sensitive to various conditions. These

conditions range from the characteristic properties of the device such as heat dissipation, the
integration of internal elements and stability, to the outside environmental influences such as
temperature, oxidation, and high pressure. In this matter, wafer bonding serves as a packaging
technology that is used on wafer-level for the fabrication of different types of electronics to
minimize the effects of the environmental conditions as well as enhancing the performance of the
device [3].

The purpose of this project is to find out what is needed to characterize bonded wafers
and how these wafers are affected by using various materials while creating certain types of
integrated circuits. The team would like to brainstorm and discover more information about how

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electrical characteristics behave in certain conditions and with different types of materials when
in use with bonded wafers. At present, many companies build their integrated circuits side by
side, taking a broader area that could be used by other additional features or improvements. The
results in this project can further push the boundaries of microelectronic design. If the results of
this project holds any value, future engineers can start building integrated circuits stacked on top
of each other, making more room in everyday electronics. Cactus materials have already looked
further into this, and with the project in mind, we hope to advance this research for a brighter
future.

Wafer bonding offers an alternative approach to develop an engineering substrate

which can replace currently epitaxially grown thick layers. The layer is proposed to be
epitaxial to finely control the thickness and dopants. A high resistivity wafers with a low
resistivity handle wafers will be bonded to develop an “engineering substrate” which can
be tuned for many applications from high energy physics to x-rays detectors. This
architecture will enable new sciences and a key advancement in R&D of next generation
LAGD detectors. The substrate construction will be based on oxide free silicon direct
bonding techniques developed by Cactus Materials, Inc. and a standard CVD epitaxy
process. The dopant concentration will be varied along with bonding interface
characterization to optimize the performance of the of the substrates (i.e. charge
collection).

The purpose of this project is to find out what is needed to characterize bonded wafers
and how these wafers are affected by using various materials while creating certain types of
integrated circuits. The team would like to brainstorm and discover more information about how
electrical characteristics behave in certain conditions and with different types of materials when
in use with bonded wafers. At present, many companies build their integrated circuits side by
side, taking a broader area that could be used by other additional features or improvements. The
results in this project can further push the boundaries of microelectronic design. If the results of
this project hold any value, future engineers can start building integrated circuits stacked on top
of each other, making more room in everyday electronics. Cactus materials have already looked
further into this, and with the project in mind, we hope to advance this research for a brighter
future.

Previous work done

A journal "Electrical properties of wafer-bonded GaAs/Si heterojunctions" was published

in Applied Physics Letters, Vol.73(16) in 1998 authored by Y. C. Zhou, Z. H. Zhu, D. Crouse,
and Y. H. Lo. They started with a provided bonded wafer. They used both the samples of n-
GaAs/n-Si and p-GaAs/p-Si wafer for their research. Their study was related to how the wafer
reacts electrically to temperature from 77K to 259K basically, below the room temperature [1].

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But the article did not provide enough information about how the materials were prepared and
made ready for the test. The result they got is shown in the figure below:
This figure is imported from the journal directly.

Figure. 1. Temperature dependent current–voltage characteristics for (a) p-GaAs/p-Si and (b) n-
GaAs/n-Si. Both samples were hydrophobically bonded. [2].

Another research was done on the subject by a group of students, namely O Salehzadeh,
B Cawston-Grant, S P Watkins, and P M Mooney from the department of physics at Simon
Fraser University, Canada. It was published in Semiconductor Science and Technology vol 29 in
2014. The article explains the procedure used to bond two GaAs wafers without any intermediate
layers, or they used a direct bonding process. They studied the I-V characteristics of bonded
wafers in different parameters like length and thickness. Their work schematics and results are
shown below [2].:

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Figure 2. (a) Schematic drawing of the electrical measurement inside an SEM and (b) SEM image of a probe
contacting a feature [1].

Figure 3. I–V characteristics of square bonded GaAs/GaAs features of different sizes [1].

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Project scope

At present, the most prominent applications of wafer bonding are in the Silicon-on-
insulator and Silicon-based devices. The purpose of the project is to brainstorm, research, and
innovate new design and characterization techniques and waveguide structures for bonded
wafers and apply these techniques on different types of wafers. Also, this project will help
reduce the area needed on an IC as it will stack the components on top of each other. The end
product we are looking for is to implement it in a LGAD which provides a low gain and less
noise compared to APD which will detect high energy photon and give us a faster time resolution
and clearer data to analyze.

Target specifications:

● Get trained and gain experience in the Nanofab lab.

● Learn to measure I-V, C-V, and other characterizations of different types of bonded
wafers.

Final project

Documentation will be created on how to characterize the electrical properties of bonded

wafers with a waveguide. This documentation will explain the methodology on how to prototype
bonded wafers with metal contacts and measure I-V and C-V, design waveguide structures,
characterization techniques for waveguide loss, and develop a prototype of bonded wafers with
waveguide structure.

How is it unique?

The project will be more like a research letter. Extensive research has been done on
various resources, and no documentation that explains the characterization of electrical
properties of bonded wafers was found. The project will represent the outcome of the gained
experience of working in the Nanofab.

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Technical Work Done This Semester

This semester has been solely focused on research side of the project with the team
members doing extensive research about what exactly the goal is for the project. At the
beginning of the semester the task was to find basic ideas on how the process for measuring
bonded wafers characteristics but only one research document was found to support the project.
Not satisfied with what was found the team felt there was a need for more information and with
the help of Dr. Islam a more direct path was given, and more resources were found. A great book
for the project called Semiconductor Wafer Bonding was recommended to our team and in
chapter 7 specifically which talks about the properties of the bonded interfaces [6]. Also, in the
information provided above under previous work done, it is shown how and what was found in
the research that was done.

The team also developed some new skills needed to measure contact angles on wafers.
The training was done at ASU’s Nanofab by Wey Lynn a Cactus Material employee provided by
Dr. Islam. A measurement tool called contact measurement goniometer by Ramé-Hart and a
software application named DROPimage Advanced are the primary tools that are going to be
used for the contact measurement. The measurements have not been conducted yet because the
wafers from cactus have not been provided at least not until January. Towards the end of the
semester the team was given a task to design a diode in cadence. Initially the instructions where
given to create a layout from scratch to learn the skills needed on the creation of the diode on the
wafer, this was only to see how the process of it comes to life and what is wrong and what was
right. The figure below displays the initial layout in cadence.

Figure 4. Diode Design Layout

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 The initial design for it will be provided by Cactus Materials since the company has done
previous work on creating wafers there will be no setbacks for the next semester. With the help
of the team and other TA’s we developed a design for the diode but the modeling for the diode
could not be completed as we had issues with paths on cadence.

What needs to be done next

For the next semester, Crazy 4 will be working on a prototype of bonded wafers with
integrated wave-guide. The plan is to design two wafers of different types and bond them
together using the techniques that were researched and found during the first semester. The team
has already designed the first silicon prototype and the next prototype will be designed in
collaboration with Cactus materials in the first stages of the next semester. Later on, using the
different bonding techniques, the different types of wafers will be bonded together and studied
thoroughly to finish the characterization project and publish it. The team will also do the
practical work to design a waveguide structure connected with bonded wafers as well as
implementing the needed characterization techniques. I-V, C-V, gain and loss characteristics will
be studied and noted down. Waveguides will be introduced between the bonded surfaces and the
team will observe how it will affect electrons behavior. Below is a comprehensive schedule for
the whole project:

Schedule for the second semester

Budget: Wafer bonding cost: $0 (CactusMaterials.Inc is developing the wafers bonding for us)
Characterization cost(hourly): $200(estimated).
Materials/thin film including cleanroom timing and wafer cost: $200(estimated).
Total cost: $400(estimated).

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Milestones:
• Research and design appropriate characterization techniques for bonded wafers: ✓
• Design a prototype of a silicon wafer: ✓
• Design a prototype of Si-(GaAs, LiNbO3) bonded wafers: Yet to be done.
• Measure I-V, C-V and other characterization for bonded wafers: Yet to be done.
Publish characterization results and finish up: Yet to be done.

Capabilities and Facilities

The facilities needed to bring forth our project are all located at ASU. Dr. Islam called it
the Nanofab, which stands for Nanofabrication. Nanofabrication is the manufacture and design
of relatively small objects that need to be measured in nanometers. Engineers mostly use this in
circuits design because when creating wafer or integrated circuits. Everything is tiny that needs
to fit in everyday electronics such as smartphones, computers, tv's, cars, airplanes, and many
more things we use daily. The use of a Nanofab technology has been a standard since the 1970s
with building sophisticated objects by scaling them down or building them up one atom at a
time. Many people compare things that get created in a Nanofab lab to a plant that was grown
from seed [4] [5].
ASU has an actual Nanofab lab on campus that is available to students where the team
can conduct testing and the design of the project. Training will be done in the Nanofab first on
how to measure contact angles and hydrophilic and hydrophobic types of wafers. Cactus
Materials will already make the wafers themselves. With the Nanofab as a facility available for
this project, many things can be done, and the focus of the projects will include thermal
processing tools and process and device characterization tools for the team to use.

The team has not had any experience with the software and equipment provided.
However, Dr. Islam, head of Cactus Materials, has done previous related work that is going to
significantly benefit the team and get the necessary capabilities that the team lacks. Schedules for
team training have been initiated and await further information to know what the next step would
be to develop the project further.

At this time, each team member has been working independently to get a better
understanding of the high-level picture of the project. Using the different resources that ASU

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provided to students, our team was able to have a better understanding of the project. Microwave
101, and the IEEE website helped the team determine the correct way of finding the
measurement of the Electrical Characterization of Bonded Wafer. Moreover, Cactus Material's
company provided other resources to support and direct the team to approach the project in the
right way.

Cactus Material will direct the team to conduct the project. Dr. Islam met with the group
members and described in detail the overall project, furthermore, held a weekly training session
on how to use the equipment for measuring the electrical characterization of different types of
wafers. The team has been given access to check the Nanofab lab at ASU for additional
information regarding the project to accomplish the goals at the end. The team member has the
necessary capabilities for the project through cooperation with Cactus material company and
conducts all requirements of measurements and procedures, besides, the level of education and
previous experience that exist in a team member. Team communication plays an essential role in
the success of the project through a weekly meeting with the team mentor that guides each
member of the team to the correct way for conducting the project, plus the basic understanding
of using the electrical equipment such as ammeter, voltmeter, and oscilloscope. Simulating the
circuit and identify the electrical measurement needs special skills and experience to master it
properly. Identifying the current behavior over the voltage, the relationship between the current
and the capacitor inside the bonded wafer, and what's the difference between the electrical
characterization of the different types of bonded wafers. Luckily, one team member has had
experience working in a lab that knows the necessary skills and the basic capabilities of testing,
measuring, and determine what it needs to accomplish the project. From now till spring 2020,
our mentor provided a weekly schedule to help the team and organize the time needed to bring
our design to real life by using the facilities provided by Cactus Material's.

Considerations

One of the considerations the project can effect is the health field. Since LGAD’s involve
high energy systems it is a very useful system in gathering data such as images. Once again,
because of the low noise it provides it is assumed a clearer picture for xrays, and other imaging
tools that use photons. This will benefit the population on developing better detections in
abnormalities in the body which can result in a greater chance of treatments or and lower risks
for early detections.
The second consideration that the project effects is a political stance. Since in the final
stage when the LGAD is made it can be used for detectors for the military such as incoming
missles or radars. Anything with a high frequency will be spotted by the device and because of
the time resolution decrease it will be very beneficial to select when a threat is prominent.

Conclusion

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 Nowadays, most devices of IC applications are spread horizontally over the wafer.
Bonded wafers provided a solution to reduce the area of an IC by stacking different layers of
Silicon on top of each other. The electrical properties of different bonded wafers are to be
characterized, and documentation will be created navigating through the whole project. This will
also be done to enhance the performance of the IC by looking at characteristic properties of the
device such as heat dissipation, the integration of internal elements and stability, and modifying
the IC to fulfill requirements. The outside environmental influences such as temperature,
oxidation, and high pressure will be taken into consideration as well, and different materials will
be used. Different strategies are going to be implemented according to what is required. The
project is an effort collaboration between team members and their mentor as well as the Nanofab
facility, who will provide real-life training for the students. This project will give students the
experience of working with bonded wafers and waveguides in the Nanofab lab, which is vital for
the future career of anyone interested in working in the fabrication of semiconductors. The team
will try to research new techniques for characterizing the electrical properties of these wafers.

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References:

[1] O. Salehzadeh. (2014). “Electrical Characterization on in-place bonded interfaces.” ASU

Library (Online Article). https://iopscience.iop.org/article/10.1088/0268-1242/29/8/085002/pdf

[2] C. Zhou, Z. H. Zhu, D. Crouse, and Y. H. Lo. (1998). “Electrical properties of wafer-bonded
GaAs/Si heterojunctions.” ASU Library (Online Article).
https://aip.scitation.org/doi/pdf/10.1063/1.122454

[3] S.-H. Choa. (2005). "Reliability of MEMS packaging: vacuum maintenance and packaging
induced stress". Microsystem. Technol. 11 (11). pp. 1187–1196.

[4] M. Rouse. (2005). “Nanofabrication” Whatis.com (Online Article)

https://whatis.techtarget.com/definition/nanofabrication

[5] K -B. Kim. “Nanofabrication process using electron beam lithography” School of Materials
Science and Engineering Seoul National University (Online Article).
https://www.cmu.edu/nanotechnology-forum/Forum_2/Korea_talks/Ki-
Bum%20Kim%20Talk.pdf

[6] Q.-Y. Tong and U. Gösele. (1999). “Semiconductor Wafer Bonding”. New York: John &
Wiley & Sons, Inc. pp175-185.

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