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FinFET Modelling Using TCAD

Chapter · January 2018

DOI: 10.1007/978-981-10-4280-5_21

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FinFET Modelling Using TCAD

Sreenivasa Rao Ijjada, Chaithanya Mannepalli

and Md. Hameed Pasha

Abstract Digital device are playing a crucial role in everyone’s life, hence, they
are seeking for compact and high-performance devices which can be handled easily.
For this researchers made drastic changes to the technology by scaling down the
device for lesser area and high performance, but beyond some limit the CMOS
device turned in opposite by showing short-channel effects. To subdue them, we
design FinFET using TCAD tools, which has superior control over the channel and
displays higher performance even after scaling to lower dimensions.

Keywords Short-channel effects ⋅ MOSFET ⋅ TCAD ⋅ FinFET

1 Introduction

MOSFET is the fundamental building block of CMOS integrated circuits [1]. It

produces many disadvantages while it is being scaled, the most of which are the
short-channel effects and leakage currents [2]. While dealing with short-channel
effects in bulk MOSFET, body doping concentration increases and consequently
there is a trade-off between the carrier mobility and tunnelling effect, eventually
increasing the off-state currents. This leads to increase of parasitic capacitances.
In order to have a control on the DIBL effect, high halo doping can be used but it
degrades on current and increases the BTB Tunnelling. High-K dielectrics can
support to reduce serious gate leakages in short-channel devices. To utilize the

S.R. Ijjada ⋅ C. Mannepalli (✉)

Electronics and Communication Engineering,
GITAM University, Visakhapatnam, India
e-mail: chaithanya15992@gmail.com
S.R. Ijjada
e-mail: isnaidu2003@gmail.com
Md. Hameed Pasha
Jayamukhi Institute of Technological Sciences, Narsampet, India
e-mail: hameedjits@gmail.com

© Springer Nature Singapore Pte Ltd. 2018 201

S.C. Satapathy et al. (eds.), Proceedings of 2nd International Conference
on Micro-Electronics, Electromagnetics and Telecommunications,
Lecture Notes in Electrical Engineering 434, DOI 10.1007/978-981-10-4280-5_21
202 S.R. Ijjada et al.

Fig. 1 Geometric description

of FinFET

Fig. 2 Planar view of MOSFET and FinFET

advantages of device scaling with minimized SCEs beyond 20 nm technology node

the device structures are continuously trying to modify, results FINFET.
FinFET results due to the relentless increase in levels of integration. Based on
the earlier depleted lean-channel transistor design [3], FinFET is built on an SOI
substrate making it a non-planar and double gate device [4]. FinFET gate is bent up
and narrowed down and the FET structure so obtained looks like set of fins when
viewed as shown in the Fig. 1 [5]. FinFET have three modes; single gate, double
gate and trigate. Double gate reduces DIBL and improves threshold swing.
The dimensional parameters of a FinFET are the height and thickness of the fin
and the “critical design dimension” is defined by the drawn gate length that sep-
arates the nodes of source and drain. A vertical fin protrudes above the substrate as
it traverses from one side of the fin to the other enabling to interface with three sides
of the fin or channel as shown in the Fig. 2. It provides a better electrical control
over the channel and helps in reducing leakage current and SCEs, thereby achieving
high on-current. Thickness of the fin determines the effective channel length of the
device.
FinFET Modelling Using TCAD 203

Effective gate length,

Leff = Lgate + 2Lext ð1Þ

Effective gate Width,

Weff = Tfin + 2Hfin ð2Þ

Channel Width,

nfin * hfin ð3Þ

where, ‘n’ is the number of fins used. More number of fins is preferred to achieve
the constraint of the device performance. FinFET has near ideal sub-threshold
behaviour, which is nearly impossible with planar technology.

2 Modelling

Substrate with Undoped/doped Boron–Silicon Nitride hard mask with photo-resist

material is patterned over a lightly doped p-substrate with the process of film
deposition and photolithography. Fin channel patterning–Fins are formed with
highly anisotropic etch process in a specific time limit as there is no stop layer on a
bulk wafer as in the SOI. Oxide deposition and planarization—Here, the aspect
ratio is kept high and then the oxide is planarized by chemical–mechanical pol-
ishing by making hard mask layer as the stop layer. Gate oxidation, patterning and
deposition—On top of the fins the gate oxide is deposited through thermal oxi-
dation to separate the channel from the gate electrode. Dopant activation—Since
underneath the oxide the fins are still connected, a dopant junction is created due to
a high-dose implant at the base of the fin which completes the isolation.
TCAD has certain design flow to design and test the designed device. The flow
of TCAD is shown in Fig. 3.
Before, we go for device characterization we need to model the device in TCAD.
Device modelling can be done with the following steps at first we need to define the
regions and select the materials to be used for designing. Next, we need to place the
nitride spacers to avoid lateral diffusion and define the contacts of the modelled
device. After, the first two steps we need to define the doping concentration of the
source and drain regions, when the doping and the device modelling is done we
need to mesh the device there are two meshing global and local meshing. Where
global is used to cover entire device and local is used to cover the junctions.
204 S.R. Ijjada et al.

Fig. 3 Tool flow in synopsys TCAD

Fig. 4 Three-dimensional FinFET device

For meshing we use command (sde:build-mesh “snmesh” “” “device_name”).

Meshing is the final step before device characterization after meshing is successful
we go for inspect command for analyzing the modelled device.
The modelled device can be viewed in mesh viewer or tecplot as shown in
Fig. 4.
FinFET Modelling Using TCAD 205

Mathematical Modelling for FinFET

The mobilities of medium- or short-channel devices, however, are not readily
extractable from raw capacitance and drain current data due to non-negligible
parasitic effects as in the long channel devices.
The different regions of operation of FinFET according to the Ids and Vds
Equations is given as follows
The current equation in saturation region goes as follows
 
W Vg − Vt 2
Ids = μCox , ð4Þ
L 2m

where

tox
m=1+3 , ð5Þ
xd

xd is the depletion layer thickness.

In cut- off region, Vg < Vt, and the current equation changes to

W qðVg − ΔϕÞ  − qVds


Ids = μ kTni tsi s kT 1e kT . ð6Þ
L

And in the linear region where Vg > Vt, Ids increases linearly with Vds.
 
W Vds
Ids = 2μCox Vg − VT − Vds ð7Þ
L 2

The threshold voltage of FinFET is given by the Eq. 8

 
kT 2Cox kT h2 π 2
Vth = ϕ + n ln 2 + ð8Þ
q q ni tsi 2mds Wsi2

3 Simulation

By using Tecplot environment FinFET structures are obtained are shown in the
Figs. 5 and 6. Tecplot 360 is an integrated post-processing environment that allows
analyzing the detailed flow-field data while producing exceptional visual output. It
is a computational fluid dynamics (CFD) and numerical simulation software
package.
Contour lines/contour—It joins points of equal elevation (height) above a par-
ticular given level. Basically, it is used to calculate pressure or temperature.
206 S.R. Ijjada et al.

Fig. 5 Three-dimensional FinFET with mesh and contours

Fig. 6 Three-dimensional FinFET with different contour levels

FinFET Modelling Using TCAD 207

Fig. 7 Integration results for FinFET designed structure

Integration method—It is a trapezoidal method, i.e., second-order accurate. For

each cell, the cell-centred value of the quantity being integrated is multiplied by the
volume of the cell, and is summed over all cells.
• When the integrand is node-centred, the nodal value of the face nodes is
averaged.
• When the integrand is cell-centred, the values of the cells to either side of the
face are averaged.
After the integration method the Fig. 7 shows the integration results of FinFET.

4 Results and Analysis

After structure of FinFET is designed, the study of characteristics of FinFET

structure is important via transfer characteristics, output characteristics and
trans-conductance. The drain currents versus gate voltage at the low drain bias of
selected medium channel n-channel FinFETs are obtained with the extracted
mobility. The calibrated Ids versus Vgs data is shown in Fig. 8 for Vd = 0.1 V and
Vd = 1.5 V.
208 S.R. Ijjada et al.

Fig. 8 FinFET transfer characteristics

Fig. 9 Transconductance versus drain current of FinFET

In order to model Ids versus Vds graph at high drain bias, the inclusion of high
field effects is necessary. The experimental FinFETs does not suffer from excessive
channel length modulation, due to the superior gate-controllability over the channel
region.
With high gate overdrives, degradation of transconductance gm is observed with
the Fig. 9. The drain current does not increase linearly proportional to 1 = L
because the parasitic resistance effects in addition to the mobility degradation due to
the relaxed tensile strain. In other words, the normalized drain current degrades
towards shorter gate lengths.
The Fig. 10 shows the output characteristics of FinFET from which we can infer
that at a positive Vd, a horizontal electric field is formed which is smaller than the
thin oxide field which gives rise to the channel formation. Keeping Vg same, if Vd
increases, pinched-off portion forms depletion region with high electric field and
then it enters into saturation region (Id remains same).
FinFET Modelling Using TCAD 209

Fig. 10 Output
characteristics of FinFET

The drain current plots are in an excellent agreement with the experimental data
in all bias regimes. Channel length modulation effects are not excessive in the
experimental data due to the excellent control of gate over the channel region.
In the transfer characteristics, since the gate terminal is electrically isolated from
the remaining terminals, the Vg is almost equal to 0, this is why, Ig is not the part of
the transfer characteristics. From the transfer characteristics graph, we infer that as
Vgs increases for nFET (for Vgs between 0 and 0.5 V, Id is almost equal to 0). This
means that equivalent resistance between drain and source terminals are extremely
high. Once Vg reaches 0.4 V, the current increases rapidly with Vg indicating that
the equivalent resistance at the drain decreases with the increase in Vg. Therefore,
nFET has the threshold voltage of 0.4 V. By analyzing the output characteristics of
FinFET, we find that at a positive Vd, a horizontal electric field is formed which is
smaller than the thin oxide field which gives rise to the channel formation. If Vd
increases (when Vg is same), pinched-off portion forms depletion region with high
electric field while entering into the saturation region.

5 Conclusions and Future Scope

The usage of FinFET’s in the nanodevices has improved results than the MOS-
FETs. FinFET’s overcome the short-channel effects faced by scaled down MOS-
FET’s to operate successfully at lesser channel length. The FinFET developed can
be used for suppressing the leakage current and performance enhancement in other
circuits like Adder, Schmitt Trigger circuits, and so on. The FinFET-based appli-
cations can be extended to various fields, such as nano robots, bio sensing, analog,
and RF circuits. The device performance may be also improved by using alternate
materials like carbon nano tubes or graphene. This could increase the speed of
operation and provides better control over the channel and reduces power con-
sumption. The FinFETs finds suitable in the integration of Si-ULSIs.
 210 S.R. Ijjada et al.

References

1. SUNG MO (STEVE) ANG and Yusuf Leblebigi.: CMOS Digital Integrated Circuits Analysis
and Design.
2. Vaidy Subramanian, Bertrand Parvais, Jonathan Borremans, Abdelkarim Mercha, Dimitri
Linten, Piet Wambacq.: Planar Bulk MOSFETs Versus FinFETs: An Analog/RF Perspective,
IEEE Transactions on Electron Devices.
3. Xiaoxia Wu Feng Wang Yuan.: Analysis Of Subthreshold Finfet Circuits For Ultra-Low Power
Design, The Pennylvania State University, USA.
4. http://www.inst.eecs.berkeley.edu/∼ee130/sp06/chp7full.pdf: MOSFET Technology Scaling,
Leakage Current, and Other Topics.
5. http://www.radio-electronics.com/info/data/semicond/fet-field-effecttransistor/finfet-technology-
basics.php.

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